WO2024036626A1 - 阵列基板、显示面板及显示装置 - Google Patents

阵列基板、显示面板及显示装置 Download PDF

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Publication number
WO2024036626A1
WO2024036626A1 PCT/CN2022/113717 CN2022113717W WO2024036626A1 WO 2024036626 A1 WO2024036626 A1 WO 2024036626A1 CN 2022113717 W CN2022113717 W CN 2022113717W WO 2024036626 A1 WO2024036626 A1 WO 2024036626A1
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WIPO (PCT)
Prior art keywords
signal line
clock signal
group
line
shift register
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PCT/CN2022/113717
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English (en)
French (fr)
Inventor
邱鑫茂
涂婷婷
徐姗姗
刘耀
刘祖文
李宗祥
程浩
黄雅雯
林剑涛
朱敬光
王进
石常洪
吕耀朝
陶文昌
Original Assignee
京东方科技集团股份有限公司
福州京东方光电科技有限公司
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Priority to PCT/CN2022/113717 priority Critical patent/WO2024036626A1/zh
Publication of WO2024036626A1 publication Critical patent/WO2024036626A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes

Definitions

  • the present application relates to the field of display technology, and in particular, to an array substrate, a display panel and a display device.
  • embodiments of the present application provide an array substrate, including: a display area and a peripheral area located on one side of the display area;
  • the peripheral area includes a plurality of first signal line groups, and each of the first signal line groups includes two clock signal lines extending in the same direction;
  • the signal transmitted in the clock signal line is a square wave signal
  • the phase of the clock signal transmitted by one of the clock signal lines in the same group of the first signal line is different from the phase of the clock transmitted by the other clock signal line.
  • the phases of the signals are opposite, and the two clock signal lines in the same first signal line group are arranged adjacently.
  • the peripheral area further includes at least one second signal line, the second signal line extends in the same direction as the clock signal line, and the signal transmitted in the second signal line is a constant voltage signal;
  • the minimum distance between the second signal line and the clock signal line is less than or equal to a preset value, and the range of the preset value includes 1 ⁇ m-5cm.
  • the second signal line includes a common signal line, a first power signal line, a second power signal line, a first level signal line, a second level signal line and a ground line. At least one.
  • the common signal line includes a common electrode signal line, a common electrode feedback signal line and a common electrode compensation signal line, and the common electrode signal line, the common electrode feedback signal line and the common electrode signal line are The electrode compensation signal lines are electrically connected together.
  • the second signal line is located on a side of each first signal line group away from the display area
  • the second signal line is located on a side of each first signal line group close to the display area.
  • the peripheral area includes multiple groups of shift register unit groups, and each group of the shift register unit group includes the same number of shift register units; the same group of shift register units The number of the shift register units in the unit group is the same as the number of each of the clock signal lines; each of the shift register units is located on the side of each of the first signal line groups close to the display area;
  • one of the shift register unit groups includes N shift register units arranged in cascade
  • one of the clock signal lines in the same group of the first signal line group is connected to the nth stage of the shift register unit group.
  • the shift register unit is electrically connected, and the other clock signal line in the same group of the first signal line group is electrically connected to the n+N/2th level shift register unit; n is less than or equal to N/2, And n is an odd number and N is an even number.
  • the peripheral area includes M groups of the first signal line group, and the first signal line group includes the m-th clock signal line and the m+M-th clock signal line, where M is at least Including one of 3, 4, 5, 6, 8 or 10, m is less than or equal to M, and m is a positive integer;
  • Each group of the first signal line groups is arranged sequentially along a first direction; wherein the first direction is the direction in which the peripheral area points to the display area, or the first direction is the direction in which the display area Point in the direction of the peripheral area.
  • the peripheral area includes three groups of the first signal line groups, the first group of the first signal line groups includes a first clock signal line and a fourth clock signal line, and the second group of the first signal line group includes a first clock signal line and a fourth clock signal line.
  • the first signal line group includes a second clock signal line and a fifth clock signal line, and the third group of the first signal line group includes a third clock signal line and a sixth clock signal line;
  • the first group of the first signal line group, the second group of the first signal line group, and the third group of the first signal line group are respectively arranged in sequence along the first direction.
  • the first clock signal line, the fourth clock signal line, the second clock signal line, the fifth clock signal line, the third clock signal line and the The sixth clock signal lines are arranged sequentially along the first direction.
  • the array substrate includes a substrate and a first conductive layer and a second conductive layer located on the substrate, and the second conductive layer is located away from the first conductive layer. one side of the substrate;
  • the first conductive layer includes the first signal line group, and the second conductive layer includes a plurality of clock signal auxiliary lines; the extension direction of at least some line segments of the clock signal auxiliary lines is consistent with the first signal line group. intersect;
  • the clock signal line includes a plurality of first openings and a plurality of second openings, and the number of the first openings is greater than the number of the second openings; at least part of the clock signal auxiliary line is on the substrate.
  • the projection overlaps with an area enclosed by an orthographic projection of the outer contour of the second opening on the substrate.
  • the peripheral area includes a first gap, the first gap is located between the shift register unit group and the first signal line group, and an extension of the first gap The direction is the same as the extension direction of the clock signal line;
  • Some of the clock signal auxiliary lines respectively include a bending structure, and the orthographic projection pattern of the bending structure of each clock signal auxiliary line on the substrate has different sizes, and each of the bending structures is located at the corresponding position. in the first gap.
  • part of the clock signal auxiliary lines includes a first line segment, the bending structure and a second line segment; the first line segment and the second line segment pass through the bending structure connect;
  • the orthographic projection of the first line segment on the substrate overlaps the orthographic projection of the clock signal line on the substrate, and the first line segment of each clock signal auxiliary line extends along it
  • the length in the direction, the length in the extension direction of the second line segment and the length of the bending structure in the extension direction are all equal to each other.
  • part of the second signal lines is located between each of the first signal line groups and the shift register unit group, and the first gap is located between each of the first signal line groups. and the second signal line;
  • the size of the first gap in the direction from the first signal line group to the second signal line is greater than twice the minimum distance between two adjacent clock signal lines.
  • embodiments of the present application provide a display panel, including the array substrate as described in the first aspect.
  • embodiments of the present application provide a display device, including the display panel as described in the second aspect, and further comprising a timing controller configured to provide each clock signal of the display panel with lines input different clock signals.
  • Figure 1 is a schematic diagram illustrating the principle of clock signal coupling in a related technology provided by an embodiment of the present application
  • Figure 2 is a schematic diagram of a horizontal stripe phenomenon provided by an embodiment of the present application.
  • Figure 3 is a schematic structural diagram of an array substrate provided by an embodiment of the present application.
  • Figure 4 is a schematic structural diagram of an array substrate driven by eight clock signals in a related technology provided by an embodiment of the present application;
  • Figure 5 is a timing diagram of the array substrate shown in Figure 4.
  • Figure 6 is a bar chart of voltage transitions generated by each clock signal line in Figure 4.
  • Figure 7(1) is a diagram illustrating the clock signal input of each clock signal line of the array substrate in Figure 4.
  • Figure 7(2) is a diagram illustrating the clock signal input of each clock signal line of the array substrate in Figure 8;
  • Figure 8 is a schematic structural diagram of an array substrate provided by an embodiment of the present application.
  • Figure 9(1) is a schematic diagram of the coupling effect of the clock signals in each clock signal line of the array substrate in Figure 4 to the common electrode signal;
  • Figure 9(2) is a schematic diagram of the coupling effect of the clock signals in each clock signal line of the array substrate in Figure 8 to the common electrode signal;
  • Figure 10 is a comparison diagram of the voltage jump of the common electrode signal in the array substrate shown in Figure 4 and Figure 8;
  • Figure 11 is a timing diagram of the array substrate shown in Figures 12 and 13;
  • Figure 12 is a schematic structural diagram of an array substrate driven by six clock signals in a related technology provided by an embodiment of the present application;
  • Figure 13 is a schematic structural diagram of another array substrate provided by an embodiment of the present application.
  • Figure 14 is a schematic structural diagram of an array substrate driven by 16 clock signals in a related technology provided by an embodiment of the present application;
  • Figure 15 is a timing diagram of the array substrate shown in Figures 14 and 16;
  • Figure 16 is a schematic structural diagram of another array substrate provided by an embodiment of the present application.
  • Figure 17 is a comparison diagram of the voltage jump of the common electrode signal of the array substrate shown in Figure 14 and Figure 16;
  • Figure 18 is a design layout of a partial area of the peripheral area of an array substrate provided by an embodiment of the present application.
  • the upper edge transition and the lower edge transition of the clock signal of the display panel will be coupled with the signal with a constant voltage.
  • the upper edge transition and the lower edge transition of the clock signal are coupled with the common electrode line.
  • the signal (Vcom signal) is coupled, or the upper and lower edge transitions of the clock signal are coupled with the signal (Vcom signal) in the common electrode feedback line, causing interference to the Vcom signal, causing the originally constant voltage signal to A voltage jump occurs, causing abnormal display on the display panel and reducing the display effect.
  • the liquid crystal display panel includes a color filter substrate and an array substrate.
  • the color filter substrate is provided with a black matrix layer (BM), and the array substrate (Array) is provided with a common electrode line (Vcom Line) and a clock signal line (CLK Line). Since the LCD
  • the black matrix layer in the display panel has a certain degree of conductivity.
  • the black matrix layer (BM) and the common electrode line (Vcom Line) form the first equivalent capacitance C1, and its dielectric layer can be air (Air ), sealant (Seal) or liquid crystal (LC);
  • the black matrix layer (BM) and the clock signal line (CLK Line) form a second equivalent capacitance C2, and its dielectric layer can be liquid crystal (LC).
  • the black matrix layer (BM) on the color filter substrate has an integrated structure, which is equivalent to the upper electrodes of the first equivalent capacitance C1 and the second equivalent capacitance C2 being electrically connected together.
  • the display brightness of each pixel unit is controlled and adjusted by controlling the voltage difference between the common electrode voltage and the pixel voltage.
  • the signal (Vcom) on the common electrode line generates a signal as shown in Figure 1
  • the voltage difference between the voltage of the common electrode and the pixel voltage changes accordingly, causing uneven brightness of the display screen.
  • alternating light and dark ripples are produced as shown in Figure 2.
  • the period of the ripple is eight rows of pixel units, of which four rows of pixel units are dark and four rows of pixel units are bright.
  • the embodiments of the present application adopt the following technical solution, by loading clock signals with the same upper and lower edge transition times and opposite directions (that is, the same frequency and opposite phases) on adjacent clock signal lines. , through the mechanism that the clock signal coupling effects in two adjacent clock signal lines cancel each other out, the impact of the clock signal on the signal with constant voltage is effectively reduced, thereby improving the display caused by signal jumps in the clock signal line interfering with other signals. Fix bad problems and improve display effect.
  • Embodiments of the present application provide an array substrate, including: a display area AA and a peripheral area BB located on one side of the display area AA;
  • the peripheral area BB includes multiple first signal line groups (for example, G1, G2, G3, G4 shown in Figure 8), and each first signal line group includes two clock signal lines CLK lines extending in the same direction;
  • the signal transmitted in the clock signal line CLK is a square wave signal as shown in Figure 5.
  • the phase of the clock signal transmitted by one clock signal line in the same first signal line group is different from the phase of the clock transmitted by the other clock signal line.
  • the phases of the signals are opposite, and the two clock signal lines in the same first signal line group are arranged adjacently.
  • the peripheral area BB includes four groups of first signal line groups, for example, a first group of first signal line groups G1 and a second group of first signal line groups G2 , the third group of first signal line group G3, and the fourth group of first signal line group G4.
  • the first group of first signal line group G1 includes two clock signal lines, and one of the clock signal lines transmits
  • the clock signal is the first clock signal CLK1 as shown in Figure 5
  • the signal transmitted in the other clock signal line is the fifth clock signal CLK5 as shown in Figure 5.
  • the first The falling edge of the square wave of the clock signal CLK1 is aligned with the rising edge of the square wave of the fifth clock signal CLK5, indicating that both are transmitted at the same time.
  • the number of the first signal line groups included in the peripheral area BB is not limited here.
  • the peripheral area BB includes two groups of first signal lines. At this time, the array substrate includes four circuits driven by the clock signal CLK. In other embodiments, the peripheral area BB includes three groups of first signal lines. line group, at this time, the array substrate includes 6 circuits driven by the clock signal CLK; in some embodiments, the peripheral area BB includes four groups of first signal line groups, at this time, the array substrate includes 8 clock signals CLK driven circuit; in other embodiments, the peripheral area BB includes five groups of first signal lines.
  • the array substrate includes 10 circuits driven by the clock signal CLK; of course, the peripheral area BB includes the first signal lines
  • the number of groups can also be six groups, eight groups, or ten groups, which can be determined according to the actual circuit design of the surrounding area.
  • the arrangement order of the two adjacent first signal line groups is not limited here.
  • the arrangement sequence can be determined according to the design space and the circuit arrangement requirements of the surrounding area.
  • Figure 3 shows a structural diagram of an array substrate.
  • the peripheral area BB is located on one side of the display area AA.
  • the peripheral area BB includes multiple groups of first signal line groups 1.
  • the common electrode signal line Vcom line extends from the display area AA.
  • the peripheral area BB is also provided with a common electrode feedback signal line Feed line and a common electrode compensation signal line (for example, Vom-b1 and Vom-b2).
  • the common electrode signal line Vcom line and the common electrode feedback signal line Feed line can be respectively provided in the areas on both sides of the plurality of first signal line groups 1; in other embodiments, The common electrode signal line Vcom line and the common electrode feedback signal line Feed line may both be located on the side of the plurality of first signal line groups 1 away from the display area AA.
  • FIG. 4 shows a schematic structural diagram of an array substrate in the related art, as shown in combination with Figures 4 and 5.
  • any two adjacent clock signal lines such as the clock signal line marked 1 and the mark 1 2
  • the rising edges of the clock signals (such as CLK1 and CLK2) transmitted in the clock signal line) differ by 1/4 of the time it takes for a square wave.
  • FIG. 12 and FIG. 14 show schematic structural diagrams of two other array substrates in the related art.
  • the rising edges of the clock signals (such as CLK1 and CLK2) transmitted in any two adjacent clock signal lines are different from each other. 1/3 of the time it takes for a square wave.
  • the rising edges of the clock signals (such as CLK1 and CLK2) transmitted in any two adjacent clock signal lines (such as the clock signal line marked 1 and the clock signal line marked 2) are different from each other. 1/8 of the time it takes for a square wave.
  • Figure 8 shows a schematic structural diagram of an array substrate provided by an embodiment of the present application.
  • the same group for example, the first group G1, second group G2, third group G3, fourth group G4.
  • the two clock signal lines in the same first signal line group are arranged adjacently.
  • the first group of first signal lines G1 includes the first clock signal line CLK1 and the fifth clock signal line CLK5. Combined with the timing of the clock signal in Figure 5, it can be seen that the clock signal CLK1 and the clock signal The polarity of the level of CLK5 is opposite, and the falling edge of the clock signal CLK1 is aligned with the rising edge of the clock signal CLK5.
  • the situation of the first signal line group of the second group G2, the third group G3, and the fourth group G4 is the same as that of the first group. G1 is similar, so I won’t go into details here.
  • the first group G1, the second group G2, the third group G3, and the fourth group G4 are arranged in sequence; in other embodiments, the fourth group G4, the first group G1, the second group G2, and the third group G3 are arranged in sequence; in other embodiments, the third group G3, the fourth group G4, the first group G1, and the second group G2 are arranged in sequence; Of course, there are other arrangements possible, and I will not list them all here.
  • CLK, CLK1, CLK2, etc. all represent clock signals
  • CLK lines, CLK1 lines, CLK2 lines, etc. all represent clock signal lines that transmit specific clock signals.
  • the clock provided in the embodiment of the present application
  • the names of the signal lines are all named based on the clock signals they transmit.
  • related marks such as 1, 2, 3 all represent the location of the clock signal lines.
  • Table 1 Voltage jumps caused by coupling of clock signal lines at different locations
  • ⁇ represents the rising edge of the clock signal
  • ⁇ represents the falling edge of the clock signal
  • the voltage jump value of each clock signal line in the related art can be obtained as shown in Table 2
  • the voltage jump value corresponding to the comprehensive coupling and the voltage jump value corresponding to the comprehensive coupling of each clock signal line of the present application as shown in Figure 3.
  • the trend diagram of voltage jump within one cycle can be obtained as shown in Figure 10. From the voltage jump trend diagram in Figure 10, it can be seen that the implementation of this application
  • the absolute value of the voltage jump value generated by the array substrate provided in the example within one signal period is significantly smaller than the absolute value of the voltage jump value generated by the array substrate in the related art within one signal period.
  • Figure 17 respectively provides voltage jump trend diagrams generated within one signal period corresponding to the array substrate of the related art in Figure 14 and another array substrate of the present application in Figure 16. From the voltage jump in Figure 17 It can be seen from the trend chart that the absolute value of the voltage jump value generated by the array substrate as shown in Figure 16 provided by the embodiment of the present application within one signal period is significantly smaller than that generated by the array substrate in the related art within one signal period. The absolute value of the voltage jump value.
  • the clock signals in the two adjacent clock signal lines are The mechanism of mutual cancellation of coupling effects effectively reduces the impact of the clock signal on signals with constant voltage, such as the Vcom signal, thus improving the display problems caused by signal jumps in the clock signal line interfering with other signals and improving the display effect.
  • the signal lines marked 1-7 in the related art respectively input the clock signal CLK1 (CLK Signal 1) - the clock signal CLK8 (CLK Signal 8) in sequence, as shown in (2) of Figure 7 ) figure, in some embodiments provided by this application, the signal lines at positions marked 1-7 respectively input clock signal CLK1 (CLK Signal 1), clock signal CLK5 (CLK Signal 5), clock signal CLK3 (CLK Signal 3), clock signal CLK7 (CLK Signal 7) clock signal CLK2 (CLK Signal 2), clock signal CLK6 (CLK Signal 6), clock signal CLK4 (CLK Signal 4), clock signal CLK8 (CLK Signal 8), that is, mark
  • the signal lines at positions 1-7 are respectively the first clock signal line, the fifth clock signal line, the third clock signal line, the seventh clock signal line, the second clock signal line, the sixth clock signal line, and the fourth clock. signal line and the eighth clock signal line.
  • the peripheral area BB also includes at least one second signal line (for example, the common electrode signal line Vcom line).
  • the extension direction of the second signal line and the clock signal line The same, and the signal transmitted in the second signal line is a constant voltage signal; wherein the minimum distance between the second signal line and the clock signal line is less than or equal to the preset value, and the range of the preset value includes 1 ⁇ m-5cm.
  • the above preset value may be 1 ⁇ m, 2 ⁇ m, 3 ⁇ m, 4 ⁇ m, 5 ⁇ m, 6 ⁇ m, 7 ⁇ m, 100 ⁇ m, 200 ⁇ m, 500 ⁇ m, 800 ⁇ m, 1 cm, 2 cm, 3 cm or 4 cm.
  • the second signal line includes a common signal line, a first power signal line VDD1 line, a second power signal line VDD2 line, a first level signal line VSS1 line, and a second level signal line VSS2 line and at least one of the ground line GND line.
  • the common signal lines include a common electrode signal line Vcom line, a common electrode feedback signal line Feed line, and a common electrode compensation signal line Vcom-b1 line or Vcom-b2 line.
  • the common electrode signal line Vcom line is common
  • the electrode feedback signal line Feed line and the common electrode compensation signal line Vcom-b1 line or Vcom-b2 line are electrically connected together.
  • the common electrode signal line Vcom line, the common electrode feedback signal line Feed line, and the common electrode compensation signal line Vcom-b1 line or Vcom-b2 line are also electrically connected to the driving chip of the display panel respectively.
  • the array substrate includes a plurality of common electrode signal lines Vcom lines arranged in an array, and the common electrode signal lines Vcom lines extend from the display area AA to the peripheral area BB; the common electrode feedback signal line Feed line and the common electrode signal line Vcom line extend from the display area AA to the peripheral area BB.
  • the electrode compensation signal line Vcom-b1 line or Vcom-b2 line is located in the peripheral area BB.
  • the problem of uneven brightness includes but is not limited to bright lines, dark lines, horizontal lines, vertical lines, flickering, etc.
  • the OLED display panel For the OLED display panel, at least one of the first power signal line VDD1 line, the second power signal line VDD2 line, the first level signal line VSS1 line, the second level signal line VSS2 line and the ground line GND line
  • circuits such as the GateGOA drive circuit and the EM GOA drive circuit become unstable due to the signal jump, which makes the anode voltage that controls the light emission of the pixel unit unstable and causes uneven brightness of the display panel.
  • the principle of uneven brightness in other types of display panels is similar to the above and will not be described again.
  • the phase of the clock signal transmitted through one clock signal line in the same first signal line group is opposite to the phase of the clock signal transmitted through another clock signal line, and the phase of the clock signal transmitted through the same first signal line group is Two clock signal lines are arranged adjacently.
  • the minimum distance between the second signal line and the clock signal line is less than or equal to the preset value, transmission is carried out through two adjacent clock signal lines in the same first signal line group.
  • the mechanism of the clock signal coupling effect canceling each other out improves the voltage jump of each second signal line, greatly reducing the problem of jumps in the constant voltage signal, thereby improving the display effect.
  • the second signal line is located on a side of each first signal line group away from the display area AA; and/or the second signal line is located on a side of each first signal line group close to the display area AA.
  • each second signal line is located on a side of each first signal line group away from the display area AA;
  • each second signal line is located on the side of each first signal line group close to the display area AA.
  • some of the second signal lines are located on the side of each first signal line group away from the display area, and some of the second signal lines are located on the side of each first signal line group close to the display area. one side.
  • the peripheral area BB includes multiple groups of shift register unit groups, and each group of shift register unit groups includes the same number of shift register units GOA. ;
  • the number of shift register units GOA in the same shift register unit group is the same as the number of clock signal lines; each shift register unit is located on the side of each first signal line group close to the display area AA;
  • the array substrate includes 8 clock signal lines, a shift register unit group includes 8 shift register units GOA, and the 8 shift register units GOA are respectively connected with 8 clock signal lines.
  • the clock signal lines are electrically connected.
  • the array substrate includes 6 clock signal lines, a shift register unit group includes 6 shift register units GOA, and the 6 shift register units GOA are respectively connected with 6 clock signal lines.
  • the clock signal lines are electrically connected.
  • the array substrate includes 16 clock signal lines, a shift register unit group includes 16 shift register units GOA, and the 16 shift register units GOA are respectively connected with 16 clock signal lines.
  • the clock signal lines are electrically connected.
  • a clock signal line in the same first signal line group is electrically connected to the nth stage shift register unit, Another clock signal line in the same first signal line group is electrically connected to the n+N/2th stage shift register unit; n is less than or equal to N/2, and n is an odd number and N is an even number.
  • N may include 4, 6, 8, 10, 12, 16, and 20.
  • the array substrate includes 8 clock signal lines, and a group of shift register unit groups includes 8 shift register units GOA.
  • the first clock signal line CLK1 line is electrically connected to the first pole shift register unit GOA1
  • the fifth clock signal line CLK5 line is electrically connected to the fifth stage shift register unit GOA5
  • the third clock signal line CLK3 line is electrically connected to the third pole shift register unit GOA3
  • the seventh clock signal line CLK7 line is electrically connected to the seventh-level shift register unit GOA7
  • the fourth clock signal line CLK4 is electrically connected to the fourth pole shift register unit GOA4
  • the sixth clock signal line CLK6 is electrically connected to the sixth stage shift register unit GOA6
  • the second clock signal line CLK2 is electrically connected to the second-level shift register unit GOA2
  • the array substrate includes 6 clock signal lines, and a group of shift register unit groups includes 6 shift register units GOA.
  • the first clock signal line CLK1 is electrically connected to the first-pole shift register unit GOA1
  • the fourth clock signal line CLK4 is electrically connected to the fourth-level shift register unit GOA4
  • the second first signal line group G2 the second clock signal line CLK2 line is electrically connected to the second pole shift register unit GOA2
  • the fifth clock signal line CLK5 line is electrically connected to the fifth stage shift register unit GOA5
  • the third clock signal line CLK3 is electrically connected to the third pole shift register unit GOA3
  • the sixth clock signal line CLK6 is electrically connected to the sixth pole shift register unit GOA6.
  • the array substrate includes 16 clock signal lines, and a group of shift register unit groups includes 16 shift register units GOA.
  • the first clock signal line CLK1 line is electrically connected to the first pole shift register unit GOA1
  • the ninth clock signal line CLK9 line is electrically connected to the ninth level shift register unit GOA9
  • the second clock signal line CLK2 is electrically connected to the second pole shift register unit GOA2
  • the tenth clock signal line CLK10 is electrically connected to the tenth stage shift register unit GOA10
  • the third clock signal line CLK3 line is electrically connected to the third pole shift register unit GOA3
  • the eleventh clock signal line CLK11 line is electrically connected to the eleventh pole shift register unit GOA11
  • the fourth clock signal line CLK4 is electrically connected to the fourth pole shift register unit GOA
  • the STV signals transmitted in the STV signal line are used as the first-level shift register unit GOA1, the second-level shift register unit GOA2 and the third-level shift respectively.
  • the enable signal input of the register unit GOA3; the output signal of the first-level shift register unit GOA1 is input into the display area AA on the one hand, and on the other hand serves as the input signal of the fourth-level shift register unit GOA4; the second-level shift register
  • the output signal of unit GOA2 is input into the display area AA on the one hand, and serves as the input signal of the fifth-level shift register unit GOA5 on the other hand;
  • the output signal of the third-level shift register unit GOA3 is input into the display area AA on the one hand, and on the other hand, it is input into the display area AA on the other hand.
  • On the one hand it serves as the input signal of the sixth-stage shift register unit GOA6.
  • the cascading method of GOA units in Figures 8 and 16 is similar to that here. For details, please refer to related technologies and will not be described again here.
  • the peripheral area includes M groups of first signal line groups, and the first signal line group includes the m-th clock signal line and the m+M-th clock signal line, where M at least includes 3, 4, and 5 One of , 6, 8 or 10, m is less than or equal to M, and m is a positive integer;
  • the first signal line group includes the third clock signal line CLK3 and the sixth clock signal line CLK5.
  • the clock signal lines included in the first signal line group are the same as The above is similar and will not be repeated here.
  • the first group of first signal lines includes a first clock signal line CLK1 line and a fourth clock signal line CLK4 line
  • the second group of first signal line groups Including the second clock signal line CLK2 line and the fifth clock signal line CLK5 line
  • the third group of first signal line groups includes the third clock signal line CLK3 line and the sixth clock signal line CLK5 line; only the same group of clock signal lines are adjacent Settings, the setting positions between the two groups can be transformed and adjusted.
  • first clock signal line in the same group when the same group of clock signal lines are arranged adjacently, you can set the first clock signal line in the same group to be on the left and the second clock signal line on the right; or you can also set the first clock signal line in the same group to be on the right.
  • the first clock signal line is on the right and the second clock signal line is on the left.
  • each group of first signal line groups is arranged sequentially along a first direction; wherein, the first direction is the direction in which the peripheral area BB points to the display area AA, or the first direction is the direction in which the display area AA points.
  • the direction of the surrounding area BB is the direction of the surrounding area BB.
  • Table 4 provides the arrangement of each clock signal line when driving the two 6CLK lines in the related art and the 48 types of clock signal lines when driving the 6CLK line provided by the embodiment of the present application along the peripheral area BB and pointing to the display area AA. Arrangement method. For the 8CLK line driver, 10CLK line driver, 12CLK line driver, 16CLK line driver, and 20CLK line driver, the arrangement of each clock signal line can also be set by referring to the arrangement in Table 4.
  • each clock signal line includes 24 ⁇ 4 ⁇ 3 ⁇ 2 ⁇ 1, 25 ⁇ 5 ⁇ 4 ⁇ 3 ⁇ 2 ⁇ 1, 26 ⁇ 6 ⁇ 5 ⁇ 4 ⁇ 3 ⁇ 2 ⁇ 1, 28 ⁇ 8 ⁇ 7 ⁇ 6 ⁇ 5 ⁇ 4 ⁇ 3 ⁇ 2 ⁇ 1, 210 ⁇ 10 ⁇ 9 ⁇ 8 ⁇ 7 ⁇ 6 ⁇ 5 ⁇ 4 ⁇ 3 ⁇ 2 ⁇ 1 solutions.
  • the peripheral area BB includes three groups of first signal line groups, and the first group G1 of the first signal line group includes a first clock signal line CLK1 line and a fourth clock signal line CLK4 line, the second group G2 first signal line group includes the second clock signal line CLK2 line and the fifth clock signal line CLK5 line, the third group G3 first signal line group includes the third clock signal line CLK3 line and the sixth clock The signal line CLK6; the first group of first signal lines G1, the second group of first signal lines G2, and the third group of first signal lines G3 are respectively arranged in sequence along the first direction.
  • the first direction is the direction in which the peripheral area BB points to the display area AA, or, in some other embodiments, the first direction is the direction in which the display area AA points to the peripheral area BB.
  • the signal line CLK3 and the sixth clock signal line CLK6 are respectively arranged in sequence along the first direction.
  • the signal lines CLK3 are arranged sequentially along the first direction.
  • the array substrate includes a substrate and a first conductive layer and a second conductive layer located on the substrate, and the second conductive layer is located on a side of the first conductive layer away from the substrate;
  • the first conductive layer may be a gate layer (Gate), and the second conductive layer may be a source-drain metal layer (SD);
  • the first conductive layer includes a first signal line group
  • the second conductive layer includes a plurality of clock signal auxiliary lines (such as lines marked f1, f2...); the extension of at least part of the line segments of the clock signal auxiliary lines The direction intersects with the first signal line group; wherein, the portions of each clock signal line in the first signal line group shown in Figure 18 all extend in the vertical direction; the portions of the clock signal auxiliary lines that overlap with each clock signal line are all Extend horizontally;
  • the clock signal line includes a plurality of first openings K1 and a plurality of second openings K2.
  • the number of the first openings K1 is greater than the number of the second openings K2; at least part of the clock signal line
  • the orthographic projection of the auxiliary lines (such as the traces marked f1, f2...) on the substrate overlaps with the area delineated by the orthographic projection of the outer contour of the second opening K2 on the substrate.
  • first opening K1 and the second opening K2 are not provided at the position where the clock signal line and the clock signal auxiliary line are electrically connected (the circled area in FIG. 18 ), but via holes are provided to electrically connect the two.
  • the area of the area delineated by the orthographic projection of the outer contour of the second opening K2 on the substrate is larger than the area of the area delineated by the orthographic projection of the outer contour of the first opening K1 on the substrate.
  • each signal line located on the side of each clock signal line away from the display area AA includes a plurality of first openings K1.
  • setting the first openings K1 can increase the light transmittance of this area, so that the frame glue can
  • the curing stage increases the transmittance of ultraviolet light and increases the curing rate of the frame glue; on the other hand, the opening can improve the heat dissipation efficiency of the BB wiring in the peripheral area, thereby improving the stability of the circuit in the peripheral area BB.
  • the orthographic projection of each at least part of the clock signal auxiliary line (such as the traces marked f1, f2...) on the substrate is aligned with the outer contour of the second opening K2 on the substrate. There is overlap in the area circled by the orthographic projection on the bottom. In this way, the overlapping area between the clock signal auxiliary line located on the second conductive layer and the clock signal line located on the first conductive layer can be reduced, thereby greatly reducing the Reduce the parasitic capacitance generated between the two, thus improving the stability of the circuit.
  • the orthographic projection of some of the minute signal auxiliary lines (such as the traces marked f1, f2%) on the substrate overlaps with the area delineated by the orthographic projection of the outer contour of the second opening K2 on the substrate;
  • each clock signal auxiliary line (such as the traces marked f1, f2...) on the substrate overlaps with the area delineated by the orthographic projection of the outer contour of the second opening K2 on the substrate.
  • the number of the second openings K2 is not limited here, and can be specifically determined according to the actual circuit design.
  • the types of clock signal auxiliary lines are the same as the number of clock signal lines; for a set of shift register groups, the corresponding number of clock signal auxiliary lines is the same as the number of clock signal lines.
  • the first clock signal line CLK1 is electrically connected to the first pole shift register GOA1 through the first clock signal auxiliary line f1
  • the second clock signal line CLK2 is electrically connected to the first pole shift register GOA1 through the second clock signal auxiliary line f2.
  • the second-pole shift register GOA2 is electrically connected to the third-pole shift register GOA2.
  • the third clock signal line CLK3 is electrically connected to the third-pole shift register GOA3 through the third clock signal auxiliary line f3.
  • the fourth clock signal line CLK4 is electrically connected to the fourth clock signal auxiliary line f3.
  • the auxiliary line f6 is electrically connected to the sixth pole shift register GOA6, the seventh clock signal line CLK7 is electrically connected to the seventh pole shift register GOA7 through the seventh clock signal auxiliary line f7, and the eighth clock signal line CLK8 is electrically connected through the eighth The clock signal auxiliary line f8 is electrically connected to the eighth pole shift register GOA8.
  • the peripheral area BB includes a first gap X1, the first gap X1 is located between the shift register unit group and the first signal line group, and the extension of the first gap X1 The direction is the same as the extension direction of the clock signal line;
  • Some of the clock signal auxiliary lines (such as the traces marked f1, f2...) respectively include bending structures, and the orthographic projection patterns of the bending structures of each clock signal auxiliary line on the substrate have different sizes, and each bending structure is located in the first gap X1.
  • each clock signal auxiliary line except the first clock signal auxiliary line f1 includes a bending structure, and according to each clock signal auxiliary line, it points in the direction of the display area AA along the peripheral area BB to the direction of the display area AA.
  • the minimum distance between the transistors in direct contact (the transistors in the GOA unit) is different, and the size of each bending structure is different to compensate for the resistance difference caused by the length difference, thereby improving the accurate transmission of electrical signals in the circuit and improving the circuit stability, thereby improving the display effect.
  • some clock signal auxiliary lines include a first line segment, a bending structure and a second line segment; the first line segment and the second line segment are connected by a bending structure; the first The line segment and the second line segment extend in the same direction;
  • each clock signal auxiliary line except the first clock signal auxiliary line f1 includes a bending structure
  • the orthographic projection of the first line segment on the substrate overlaps with the orthographic projection of the clock signal line on the substrate.
  • the length is equal to the sum of the lengths of the bent structure along its extending direction. In this way, the resistance difference caused by the length difference can be compensated, thereby improving the accurate transmission of electrical signals in the circuit, improving the stability of the circuit, and thereby improving the display effect.
  • some second signal lines are located between each first signal line group and the shift register unit group, and the first gap X1 Located between each first signal line group (clock signal line CLK) and the second signal line (such as VDD1, VDD2, VSS1, VSS2); the first gap X1 points in the direction of the second signal line along the first signal line group The minimum distance between two adjacent clock signal lines CLK that is greater than twice the size.
  • the array substrate also includes a second gap X2, and the second gap X2 is located between the STV signal line and the shift register group.
  • the width of the second gap X2 is smaller than the width of the first gap X1, where the width here refers to the size of the first signal line group in the direction toward the second signal line.
  • An embodiment of the present application provides a display panel, including the array substrate as described above.
  • the above-mentioned display panel is a liquid crystal display panel (Liquid Crystal Display, LCD).
  • the liquid crystal display panel may include a twisted nematic (TN) type, a vertical alignment (Vertical Alignment, VA) ) type, In Plane Switching (IPS) type and Advanced Super Dimension Switch (ADS, Advanced Super Dimension Switch) type.
  • TN twisted nematic
  • VA vertical alignment
  • IPS In Plane Switching
  • ADS Advanced Super Dimension Switch
  • the above-mentioned display panel may be an OLED (Organic Light Emitting Diode, organic light emitting diode) display panel.
  • the OLED display panel includes an OLED display panel with a silicon substrate (Si Substrate) and an OLED with a glass substrate. display panel.
  • the display panel may be a Micro-LED (Micro-Light Emitting Diode, micro organic light-emitting diode).
  • the above display panel may be Mini-LED (Mini-Light Emitting Diode, sub-millimeter organic light-emitting diode).
  • Micro-LED display panels and Mini-LED display panels also include glass substrates and silicon substrates respectively.
  • An embodiment of the present application provides a display device, including the display panel as described above, and further including a timing controller (TCON) configured to input different clock signals to each clock signal line of the display panel.
  • TCON timing controller
  • the input of the clock signal CLK signal corresponding to the GOA or Gate IC on the array substrate of the display device is output by a driver chip (such as a Level shifter or an all-in-one PMIC chip).
  • the CLK signal timing corresponding to the driver chip output terminal (Pin) can be adjusted through Code.
  • the output terminal 1 (Pin1) that originally outputs the CLK1 signal can output the CLK5 signal after being adjusted by the Code.
  • the output terminal 5 (Pin5) that originally outputs the CLK5 signal After adjusting the Code the CLK1 signal can be output.
  • the output signal of the driver chip can be adjusted to correspond to the distribution of the clock signal line while the driver chip remains unchanged, so that under the original process preparation conditions, the application
  • the array substrate of the display device provided by the embodiment can still be produced normally, that is to say, even if the clock signal line layout design is changed, it can still be produced using the original process, thus minimizing the production cost.
  • the display device may be an LCD display, an OLED display, a Micro-LED display, a Mini-LED display and other display devices, as well as any product or component with a display function such as a television, a digital camera, a mobile phone, a tablet computer, etc. including these display devices.

Abstract

一种阵列基板、显示面板、显示装置，涉及显示技术领域，阵列基板包括显示区(AA)以及位于显示区(AA)一侧的周边区(BB)；周边区(BB)包括多组第一信号线组，每组第一信号线组包括延伸方向相同的两条时钟信号线(CLK)；其中，时钟信号线(CLK)中传输的信号为方形波信号，同一组第一信号线组中的一条时钟信号线(CLK1)传输的时钟信号的相位与另一条时钟信号线(CLK5)传输的时钟信号的相位相反,且同一组第一信号线组中的两条时钟信号线(CLK)相邻设置。阵列基板的显示效果好，制备成本低。

Description

阵列基板、显示面板及显示装置 技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板、显示面板及显示装置。
背景技术
显示屏内存在传输恒定电压的信号线，例如公共电极线，公共电极线传输的电压称为公共电压(Vcom)，公共电压的波动将会引起显示屏出现横纹、显示亮度不均(Mura)、残像、闪烁、残像等显示不良问题。以液晶显示屏(Liquid Crystal Display，LCD)为例，它的发光是一种保持形式，在持续电场作用下液晶保持一定的透过亮度，电场强度与像素电极和公共电极之间的电压差成正比。故而，公共电压(Vcom)信号的波动严重降低显示效果。
发明内容
本申请的实施例采用如下技术方案：
第一方面，本申请的实施例提供了一种阵列基板，包括：显示区以及位于所述显示区一侧的周边区；
所述周边区包括多组第一信号线组，每组所述第一信号线组包括延伸方向相同的两条时钟信号线；
其中，所述时钟信号线中传输的信号为方形波信号，同一组所述第一信号线组中的一条所述时钟信号线传输的时钟信号的相位与另一条所述时钟信号线传输的时钟信号的相位相反，且同一组所述第一信号线组中的两条所述时钟信号线相邻设置。
在本申请的一些实施例中，所述周边区还包括至少一条第二信号线，所述第二信号线与所述时钟信号线的延伸方向相同，且所述第二信号线中传输的信号为恒定的电压信号；
其中，所述第二信号线到所述时钟信号线之间的最小距离小于或等于预设值，所述预设值的范围包括1μm-5cm。
在本申请的一些实施例中，所述第二信号线包括公共信号线、第一电源信号线、第二电源信号线、第一电平信号线、第二电平信号线和接 地线中的至少一条。
在本申请的一些实施例中，所述公共信号线包括公共电极信号线、公共电极反馈信号线和公共电极补偿信号线，所述公共电极信号线、所述公共电极反馈信号线和所述公共电极补偿信号线电连接在一起。
在本申请的一些实施例中，所述第二信号线位于各所述第一信号线组远离所述显示区的一侧；
和/或，所述第二信号线位于各所述第一信号线组靠近所述显示区的一侧。
在本申请的一些实施例中，所述周边区包括多组移位寄存器单元组，各组所述移位寄存器单元组包括的所述移位寄存器单元的数量相同；同一组所述移位寄存器单元组中的所述移位寄存器单元的数量与各所述时钟信号线的数量相同；各所述移位寄存器单元均位于各所述第一信号线组靠近所述显示区的一侧；
在一组所述移位寄存器单元组包括N个级联设置的所述移位寄存器单元的情况下，同一组所述第一信号线组中的一条所述时钟信号线与第n级所述移位寄存器单元电连接，同一组所述第一信号线组中的另一条所述时钟信号线与第n+N/2级所述移位寄存器单元电连接；n小于或等于N/2，且n为奇数，N为偶数。
在本申请的一些实施例中，所述周边区包括M组所述第一信号线组，所述第一信号线组包括第m时钟信号线和第m+M时钟信号线，其中，M至少包括3、4、5、6、8或10中的一个，m小于或等于M，且m为正整数；
各组所述第一信号线组分别沿第一方向依次排布；其中，所述第一方向为所述周边区指向所述显示区的方向，或者，所述第一方向为所述显示区指向所述周边区的方向。
在本申请的一些实施例中，所述周边区包括三组所述第一信号线组，第一组所述第一信号线组包括第一时钟信号线和第四时钟信号线，第二组所述第一信号线组包括第二时钟信号线和第五时钟信号线，第三组所述第一信号线组包括第三时钟信号线和第六时钟信号线；
第一组所述第一信号线组、第二组所述第一信号线组、第三组所述第一信号线组分别沿所述第一方向依次排布。
在本申请的一些实施例中，所述第一时钟信号线、所述第四时钟信 号线、所述第二时钟信号线、所述第五时钟信号线、所述第三时钟信号线和所述第六时钟信号线分别沿所述第一方向依次排布。
在本申请的一些实施例中，所述阵列基板包括衬底以及位于所述衬底上的第一导电层和第二导电层，所述第二导电层位于所述第一导电层远离所述衬底的一侧；
所述第一导电层包括所述第一信号线组，所述第二导电层包括多条时钟信号辅助线；所述时钟信号辅助线的至少部分线段的延伸方向与所述第一信号线组相交；
所述时钟信号线包括多个第一开口和多个第二开口，所述第一开口的数量大于所述第二开口的数量；至少部分所述时钟信号辅助线在所述衬底上的正投影与所述第二开口的外轮廓在所述衬底上的正投影圈定的区域存在交叠。
在本申请的一些实施例中，所述周边区包括第一间隙，所述第一间隙位于所述移位寄存器单元组与所述第一信号线组之间，且所述第一间隙的延伸方向与所述时钟信号线的延伸方向相同；
部分所述时钟信号辅助线分别包括弯折结构，且各所述时钟信号辅助线的所述弯折结构在所述衬底上的正投影图形的尺寸不同，各所述弯折结构均位于所述第一间隙中。
在本申请的一些实施例中，部分所述时钟信号辅助线包括第一线段、所述弯折结构和第二线段；所述第一线段和所述第二线段通过所述弯折结构连接；
所述第一线段在所述衬底上的正投影与所述时钟信号线在所述衬底上的正投影交叠，各所述时钟信号辅助线的所述第一线段沿其延伸方向上长度、所述第二线段沿其延伸方向上长度与所述弯折结构沿其延伸方向上长度之和均相等。
在本申请的一些实施例中，部分所述第二信号线位于各所述第一信号线组与所述移位寄存器单元组之间，所述第一间隙位于各所述第一信号线组与所述第二信号线之间；
所述第一间隙沿所述第一信号线组指向所述第二信号线的方向上的尺寸大于两倍的相邻两条所述时钟信号线之间的最小距离。
第二方面，本申请的实施例提供了一种显示面板，包括如第一方面 所述的阵列基板。
第三方面，本申请的实施例提供了一种显示装置，包括如第二方面所述的显示面板，还包括时序控制器，所述时序控制器被配置为向所述显示面板的各时钟信号线输入不同的时钟信号。
上述说明仅是本申请技术方案的概述，为了能够更清楚了解本申请的技术手段，而可依照说明书的内容予以实施，并且为了让本申请的上述和其它目的、特征和优点能够更明显易懂，以下特举本申请的具体实施方式。
附图说明
为了更清楚地说明本申请实施例或相关技术中的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1为本申请实施例提供的一种相关技术中时钟信号耦合作用的原理说明图；
图2为本申请的实施例提供的一种横纹现象示意图；
图3为本申请的实施例提供的一种阵列基板的结构示意图；
图4为本申请的实施例提供的一种相关技术中的8个时钟信号驱动的阵列基板的结构示意图；
图5为图4中所示的阵列基板的时序图；
图6为图4中各时钟信号线产生的电压跳变条形图；
图7(1)为图4中阵列基板的各时钟信号线的时钟信号输入说明图；
图7(2)为图8中阵列基板的各时钟信号线的时钟信号输入说明图；
图8为本申请的实施例提供的一种阵列基板的结构示意图；
图9(1)为图4中阵列基板的各时钟信号线中的时钟信号对公共电极信号的耦合作用示意图；
图9(2)为图8中阵列基板的各时钟信号线中的时钟信号对公共电极信号的耦合作用示意图；
图10为图4与图8所示的阵列基板中公共电极信号的电压跳变对比图；
图11为图12和图13中所示的阵列基板的时序图；
图12为本申请的实施例提供的一种相关技术中的6个时钟信号驱动的阵列基板的结构示意图；
图13为本申请的实施例提供的另一种阵列基板的结构示意图；
图14为本申请的实施例提供的一种相关技术中的16个时钟信号驱动的阵列基板的结构示意图；
图15为图14和图16中所示的阵列基板的时序图；
图16为本申请的实施例提供的又一种阵列基板的结构示意图；
图17为图14和图16中所示的阵列基板的公共电极信号的电压跳变对比图；
图18为本申请的实施例提供的一种阵列基板的周边区局部区域的设计版图。
具体实施例
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在图中，为了清晰，可能夸大了区域和层的厚度。在图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
在本申请的实施例中，除非另有说明，“多个”的含义是两个或两个以上；术语“上”等指示的方位或位置关系为基于附图所述的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的结构或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例”、“一些实施例”、“示例性实施例”、“示例”、“特定示例”或“一些示例”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本申请的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
在本申请的实施例中，采用“第一”、“第二”等字样对功能和作用基本相同的相同项或相似项进行区分，仅为了清楚描述本申请实施例的技术方案，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。
相关技术中，显示面板的时钟信号的上沿跳变和下沿跳变会与电压恒定的信号之间产生耦合，例如，时钟信号的上沿跳变和下沿跳变与公共电极线中的信号(Vcom信号)产生耦合，或者时钟信号的上沿跳变和下沿跳变与公共电极反馈线中的信号(Vcom信号)产生耦合，从而对Vcom信号造成干扰，使得原本电压恒定的信号上出现电压跳变，从而造成显示面板显示异常，降低显示效果。
以显示面板为液晶显示面板(Liquid Crystal Display，LCD)为例，说明时钟信号的上沿跳变和下沿跳变对电压恒定的信号产生的影响。液晶显示面板包括彩膜基板和阵列基板，彩膜基板上设置有黑色矩阵层(BM)，阵列基板(Array)上设置有公共电极线(Vcom Line)和时钟信号线(CLK Line)，由于LCD显示面板中的黑色矩阵层具有一定程度的导电能力，如图1所示，黑色矩阵层(BM)与公共电极线(Vcom Line)形成第一等效电容C1，其介质层可以为空气(Air)、框胶(Seal)或液晶(LC)中的至少一种；黑色矩阵层(BM)与时钟信号线(CLK Line)形成第二等效电容C2，其介质层可以为液晶(LC)。彩膜基板上的黑色矩阵层(BM)为一体化结构，相当于第一等效电容C1和第二等效电容C2的上极电连接在一起，这样，在时钟信号线中产生如图1中所示的方形波信号时，由于第一等效电容C1和第二等效电容C2 的上极电连接在一起，时钟信号线中的方形波信号会耦合到第一等效电容C1上，从而对公共电极线上的信号产生影响，使得公共电极线上的信号(Vcom)产生如图1中所示的电压跳变(Ripple)。
在液晶显示面板中，通过控制公共电极的电压和像素电压之间的压差，来控制和调节各像素单元的显示亮度，在公共电极线上的信号(Vcom)产生如图1中所示的电压跳变(Ripple)的情况下，公共电极的电压和像素电压之间的压差随之发生变化，进而造成显示画面的亮度不均，例如，产生如图2中所示的明暗交替的波纹现象。在图2中，波纹的周期为8行像素单元，其中，四行像素单元偏暗(Dark)，四行像素单元偏亮(Bright)。
基于此，本申请的实施例采用如下技术方案，通过将上沿跳变和下沿跳变时刻相同、且方向相反的时钟信号(即频率相同、相位相反)加载在相邻的时钟信号线上，通过相邻两条时钟信号线中的时钟信号耦合作用相互抵消的机理，有效降低时钟信号对电压恒定的信号产生的影响，从而改善时钟信号线中信号跳变对其它信号的干扰造成的显示不良问题，提高显示效果。
本申请的实施例提供了一种阵列基板，包括：显示区AA以及位于显示区AA一侧的周边区BB；
周边区BB包括多组第一信号线组(例如，图8中所示的G1、G2、G3、G4)，每组第一信号线组包括延伸方向相同的两条时钟信号线CLK线；
其中，时钟信号线CLK线中传输的信号为如图5所示的方形波信号，同一组第一信号线组中的一条时钟信号线传输的时钟信号的相位与另一条时钟信号线传输的时钟信号的相位相反，且同一组第一信号线组中的两条时钟信号线相邻设置。
在示例性的实施例中，结合图5和图8所示，周边区BB包括四组第一信号线组，例如，第一组第一信号线组G1、第二组第一信号线组G2、第三组第一信号线组G3、第四组第一信号线组G4，以第一组第一信号线组G1为例，其包括两条时钟信号线，且其中一条时钟信号线 中传输的时钟信号为如图5中所示的第一时钟信号CLK1，另一条时钟信号线中传输的信号为如图5中所示的第五时钟信号CLK5，从图5中可以看到，第一时钟信号CLK1的方形波的下降沿与第五时钟信号CLK5的方形波的上升沿对齐，说明两者在同一时刻传输。
需要说明的是，在本说明书中，一个时钟信号的方形波的上升沿与另一个时钟信号的方形波的下降沿位于同一时刻，说明两个时钟信号的频率相同，相位相反，后文不再赘述。
这里对于周边区BB包括的第一信号线组的数量不进行限定。
在一些实施例中，周边区BB包括两组第一信号线组，此时，该阵列基板包括4个时钟信号CLK驱动的电路；在另一些实施例中，周边区BB包括三组第一信号线组，此时，该阵列基板包括6个时钟信号CLK驱动的电路；在又一些实施例中，周边区BB包括四组第一信号线组，此时，该阵列基板包括8个时钟信号CLK驱动的电路；在另一些实施例中，周边区BB包括五组第一信号线组，此时，该阵列基板包括10个时钟信号CLK驱动的电路；当然，周边区BB包括的第一信号线组的数量还可以为六组、八组、十组，具体可以根据实际周边区的电路设计确定。
这里对于相邻两组第一信号线组的排布顺序不进行限定，在同一组第一信号线组中的两条时钟信号线相邻设置的情况下，相邻两组第一信号线组的排布顺序可以根据设计空间以及周边区的电路排布需求确定。
图3中示出了一种阵列基板的结构图，周边区BB位于显示区AA的一侧，其中，周边区BB包括多组第一信号线组1，公共电极信号线Vcom线从显示区AA延伸至周边区BB，周边区BB还设置有公共电极反馈信号线Feed线和公共电极补偿信号线(例如Vom-b1和Vom-b2)。在一些实施例中，如图3所示，公共电极信号线Vcom线和公共电极反馈信号线Feed线可以分别设置在多组第一信号线组1两侧的区域；在另一些实施例中，公共电极信号线Vcom线和公共电极反馈信号线Feed线可以均位于多组第一信号线组1远离显示区AA的一侧。
图4示出了相关技术中的一种阵列基板的结构示意图，结合图4 和图5所示，在图4中，任意相邻的两条时钟信号线(例如标记①的时钟信号线和标记②的时钟信号线)中传输的时钟信号(例如CLK1和CLK2)的上升沿均相差一个方形波所耗时间的1/4。另外，图12和图14示出了相关技术中的另外两种阵列基板的结构示意图。结合图11和图12所示，任意相邻的两条时钟信号线(例如标记①的时钟信号线和标记②的时钟信号线)中传输的时钟信号(例如CLK1和CLK2)的上升沿均相差一个方形波所耗时间的1/3。结合图14和图15所示，任意相邻的两条时钟信号线(例如标记①的时钟信号线和标记②的时钟信号线)中传输的时钟信号(例如CLK1和CLK2)的上升沿均相差一个方形波所耗时间的1/8。
图8示出了本申请的实施例提供的一种阵列基板的结构示意图，结合图5中时钟信号的时序和图8所示的电连接方式，在图8中，同一组(例如第一组G1、第二组G2、第三组G3、第四组G4)第一信号线组中的一条时钟信号线传输的时钟信号CLK的上升沿与另一条时钟信号线传输的时钟信号CLK的下降沿在同一时刻，且同一组第一信号线组中的两条时钟信号线相邻设置。
在图8中，第一组第一信号线组G1包括第一时钟信号线CLK1线和第五时钟信号线CLK5线，结合图5中时钟信号的时序，可以看到，时钟信号CLK1和时钟信号CLK5的电平的极性相反，且时钟信号CLK1的下降沿和时钟信号CLK5的上升沿对齐，第二组G2、第三组G3、第四组G4第一信号线组的情况与第一组G1类似，这里不再赘述。
在一些实施例中，如图8所示，第一组G1、第二组G2、第三组G3、第四组G4第一信号线组依次排布；在另一些实施例中，第四组G4、第一组G1、第二组G2、第三组G3依次排布；在另一些实施例中，第三组G3、第四组G4、第一组G1、第二组G2依次排布；当然，还可以有其它的排布方式，这里不再一一列举。
需要说明的是，在本说明书中，CLK、CLK1、CLK2等均代表时钟信号，CLK线、CLK1线、CLK2线等均代表传输特定时钟信号的时钟信号线，本申请的实施例中提供的时钟信号线的名称均以其传输的时 钟信号为区分进行命名，另外，在附图中，①、②、③等相关标记均代表时钟信号线所处的位置。
表1：不同位置时钟信号线的耦合作用产生的电压跳变
Figure PCTCN2022113717-appb-000001
在相关技术中，例如在如图4所示的阵列基板中，由于第一时钟信号线CLK1线、第二时钟信号线CLK2线、第三时钟信号线CLK3线、第四时钟信号线CLK4线、第五时钟信号线CLK5线、第六时钟信号线CLK6线、第七时钟信号线CLK7线、第八时钟信号线CLK8线依次排布，对于如图4中所示的公共电极信号线Vcom线，各时钟信号线对其产生耦合作用，使得公共电极信号线中传输的Vcom信号发生如图5中所示的Vcom信号跳变。经过测试，图4中标记①、②、③等不同位置的时钟信号线的耦合作用产生的电压跳变如图6以及表1所示。
表2：相关技术中各时钟信号线的综合耦合
Figure PCTCN2022113717-appb-000002
表3：本申请中各时钟信号线的综合耦合
Figure PCTCN2022113717-appb-000003
其中，在上述表2和表3中，↑代表时钟信号的上升沿，↓代表时钟 信号的下降沿。
对于如图4所示的相关技术中的阵列基板，根据表1中不同位置处的各时钟信号线的耦合作用产生的电压跳变值，可以得到如表2中相关技术中各时钟信号线的综合耦合对应的电压跳变值以及如图3中本申请的各时钟信号线的综合耦合对应的电压跳变值。根据图2和图3中的电压跳变数值，可以得到如图10中所示的一个周期内电压跳变的趋势图，从图10中的电压跳变趋势图可以看到，本申请的实施例提供的阵列基板在一个信号周期内产生的电压跳变值的绝对值明显小于相关技术中的阵列基板在一个信号周期内产生的电压跳变值的绝对值。
另外，图17中分别提供了图14中相关技术的阵列基板和图16中本申请的另一种阵列基板对应的一个信号周期内产生的电压跳变趋势图，从图17中的电压跳变趋势图可以看到，本申请的实施例提供的如图16所示的阵列基板在一个信号周期内产生的电压跳变值的绝对值明显小于相关技术中的阵列基板在一个信号周期内产生的电压跳变值的绝对值。
在本申请的实施例中，通过将上沿跳变和下沿跳变时刻相同、且方向相反的时钟信号加载在相邻的时钟信号线上，通过相邻两条时钟信号线中的时钟信号耦合作用相互抵消的机理，有效降低时钟信号对电压恒定的信号，例如Vcom信号产生的影响，从而改善时钟信号线中信号跳变对其它信号的干扰造成的显示不良问题，提高显示效果。
如图7中(1)图所示，相关技术中标记①-⑦位置处的信号线分别依次输入时钟信号CLK1(CLK Signal 1)-时钟信号CLK8(CLK Signal 8)，如图7中(2)图所示，本申请提供的一些实施例中，标记①-⑦位置处的信号线分别依次输入时钟信号CLK1(CLK Signal 1)、时钟信号CLK5(CLK Signal 5)、时钟信号CLK3(CLK Signal 3)、时钟信号CLK7(CLK Signal 7)时钟信号CLK2(CLK Signal 2)、时钟信号CLK6(CLK Signal 6)、时钟信号CLK4(CLK Signal 4)、时钟信号CLK8(CLK Signal 8)，也即标记①-⑦位置处的信号线分别依次为第一时钟信号线、第五时钟信号线、第三时钟信号线、第七时钟信号线、 第二时钟信号线、第六时钟信号线、第四时钟信号线和第八时钟信号线。
下面结合图9中(1)图和图9中(2)图，具体说明表2和表3中各信号线的耦合方式。根据图9中(1)图和图9中(2)图可知，无论时钟信号线的位置如何，均为时钟信号CLK1与时钟信号CLK5进行耦合，时钟信号CLK2与时钟信号CLK6进行耦合，时钟信号CLK3与时钟信号CLK7进行耦合，时钟信号CLK4与时钟信号CLK8进行耦合；由于如图4中所示的相关技术中的时钟信号线的排布方式与本申请的实施例提供的如图8所示的时钟信号线的排布方式不同，故而表2中的综合耦合方式一栏与表3的综合耦合方式一栏有所不同。另外，根据图9中(1)图和图9中(2)图中所示的综合Vcom Ripple(Vcom电压跳变)趋势可以看出，本申请的实施例提供的阵列基板，通过相邻两条时钟信号线中的时钟信号耦合作用相互抵消的机理，能够有效降低时钟信号对电压恒定的信号产生的干扰，提高电压恒定的信号的稳定性，从而提高阵列基板的电路稳定性，提高显示效果。
在本申请的一些实施例中，如图4、图8所示，周边区BB还包括至少一条第二信号线(例如公共电极信号线Vcom线)，第二信号线与时钟信号线的延伸方向相同，且第二信号线中传输的信号为恒定的电压信号；其中，第二信号线到时钟信号线之间的最小距离小于或等于预设值，预设值的范围包括1μm-5cm。
示例性的，上述预设值可以为1μm、2μm、3μm、4μm、5μm、6μm、7μm、100μm、200μm、500μm、800μm、1cm、2cm、3cm或4cm。
需要说明的是，在第二信号线包括多条的情况下，由于每条第二信号线到时钟信号线之间的最小距离不同，时钟信号线对各第二信号线产生的耦合作用的大小不同，从而对各第二信号线产生的电压跳变的大小不同，通过本申请的实施例提供的同一组第一信号线组中相邻两条时钟信号线传输的时钟信号耦合作用相互抵消的机理，对各第二信号线的电压跳变改善的程度不同。
在本申请的一些实施例中，第二信号线包括公共信号线、第一电源信号线VDD1线、第二电源信号线VDD2线、第一电平信号线VSS1 线、第二电平信号线VSS2线和接地线GND线中的至少一条。
在本申请的一些实施例中，公共信号线包括公共电极信号线Vcom线、公共电极反馈信号线Feed线和公共电极补偿信号线Vcom-b1线或Vcom-b2线，共电极信号线Vcom线公共电极反馈信号线Feed线和公共电极补偿信号线Vcom-b1线或Vcom-b2线电连接在一起。另外，公共电极信号线Vcom线、公共电极反馈信号线Feed线和公共电极补偿信号线Vcom-b1线或Vcom-b2线还分别与显示面板的驱动芯片电连接。
在示例性的实施例中，阵列基板包括阵列排布的多条公共电极信号线Vcom线，且公共电极信号线Vcom线从显示区AA延伸至周边区BB；公共电极反馈信号线Feed线和公共电极补偿信号线Vcom-b1线或Vcom-b2线均位于周边区BB。
在实际应用中，对于位于时钟信号线附近的任意一条第二信号线，由于时钟信号线中传输的信号为方形波信号，而第二信号线中传输的均为电压恒定的信号，第二信号线中电压恒定的电信号极易受到时钟信号线中信号的干扰，从而产生电压跳变，使得原本电压恒定的电信号变得不稳定，从而减低阵列基板中电路的稳定性，使得显示出现异常。
对于液晶显示面板，在公共信号线中传输的信号出现跳变时，公共电压信号Vcom与像素电极的电压信号之间的差值发生波动，从而使得局部区域液晶的偏转出现异常，发生显示面板亮度不均的问题，其中，亮度不均的问题包括但不限于亮纹、暗纹、横纹、竖纹、闪烁等。
对于OLED显示面板，在第一电源信号线VDD1线、第二电源信号线VDD2线、第一电平信号线VSS1线、第二电平信号线VSS2线和接地线GND线中的至少一条中的信号出现跳变时，诸如GateGOA驱动电路、EM GOA驱动电路等电路由于信号的跳变出现不稳定，从而使得控制像素单元发光的阳极电压不稳定，也会出现显示面板亮度不均的问题。其它类型显示面板发生亮度不均的原理与上述类似，不再赘述。
本申请的实施例，通过同一组第一信号线组中的一条时钟信号线传输的时钟信号的相位与另一条时钟信号线传输的时钟信号的相位相反，且同一组第一信号线组中的两条时钟信号线相邻设置，在第二信号线与 时钟信号线之间的最小距离小于或等于预设值的情况下，通过同一组第一信号线组中相邻两条时钟信号线传输的时钟信号耦合作用相互抵消的机理，对各第二信号线的电压跳变进行改善，很大程度上降低恒定电压信号出现跳变的问题，从而改善显示效果。
其中，第二信号线位于各第一信号线组远离显示区AA的一侧；和/或，第二信号线位于各第一信号线组靠近显示区AA的一侧。
在一些实施例中，各第二信号线均位于各第一信号线组远离显示区AA的一侧；
在一些实施例中，如图12、图13所示，各第二信号线位于各第一信号线组靠近显示区AA的一侧。
在一些实施例中，如图4、图8所示，部分第二信号线位于各第一信号线组远离显示区的一侧，部分第二信号线位于各第一信号线组靠近显示区的一侧。
在本申请的一些实施例中，如图8、图13、图16所示，周边区BB包括多组移位寄存器单元组，各组移位寄存器单元组包括的移位寄存器单元GOA的数量相同；同一组移位寄存器单元组中的移位寄存器单元GOA的数量与各时钟信号线的数量相同；各移位寄存器单元均位于各第一信号线组靠近显示区AA的一侧；
在示例性的实施例中，如图8所示，阵列基板包括8条时钟信号线，一组移位寄存器单元组包括8个移位寄存器单元GOA，8个移位寄存器单元GOA分别与8条时钟信号线电连接。在示例性的实施例中，如图13所示，阵列基板包括6条时钟信号线，一组移位寄存器单元组包括6个移位寄存器单元GOA，6个移位寄存器单元GOA分别与6条时钟信号线电连接。在示例性的实施例中，如图16所示，阵列基板包括16条时钟信号线，一组移位寄存器单元组包括16个移位寄存器单元GOA，16个移位寄存器单元GOA分别与16条时钟信号线电连接。其中，在一组移位寄存器单元组包括N个级联设置的移位寄存器单元GOA的情况下，同一组第一信号线组中的一条时钟信号线与第n级移位寄存器单元电连接，同一组第一信号线组中的另一条时钟信号线与第 n+N/2级移位寄存器单元电连接；n小于或等于N/2，且n为奇数，N为偶数。示例性的，N可以包括4、6、8、10、12、16、20。
在示例性的实施例中，如图8所示，阵列基板包括8条时钟信号线，一组移位寄存器单元组包括8个移位寄存器单元GOA，在第一组第一信号线组G1中，第一时钟信号线CLK1线与第一极移位寄存器单元GOA1电连接，第五时钟信号线CLK5线与第五级移位寄存器单元GOA5电连接；在第二组第一信号线组G2中，第三时钟信号线CLK3线与第三极移位寄存器单元GOA3电连接，第七时钟信号线CLK7线与第七级移位寄存器单元GOA7电连接；在第三组第一信号线组G3中，第四时钟信号线CLK4线与第四极移位寄存器单元GOA4电连接，第六时钟信号线CLK6线与第六级移位寄存器单元GOA6电连接；在第四组第一信号线组G4中，第二时钟信号线CLK2线与第二级移位寄存器单元GOA2电连接，第八时钟信号线CLK8线与第八级移位寄存器单元GOA8电连接。且同一组第一信号线组中的两条时钟信号线的信号频率相同。
在示例性的实施例中，如图13所示，阵列基板包括6条时钟信号线，一组移位寄存器单元组包括6个移位寄存器单元GOA，在第一组第一信号线组G1中，第一时钟信号线CLK1线与第一极移位寄存器单元GOA1电连接，第四时钟信号线CLK4线与第四级移位寄存器单元GOA4电连接；在第二组第一信号线组G2中，第二时钟信号线CLK2线与第二极移位寄存器单元GOA2电连接，第五时钟信号线CLK5线与第五级移位寄存器单元GOA5电连接；在第三组第一信号线组G3中，第三时钟信号线CLK3线与第三极移位寄存器单元GOA3电连接，第六时钟信号线CLK6线与第六极移位寄存器单元GOA6电连接。
在示例性的实施例中，如图16所示，阵列基板包括16条时钟信号线，一组移位寄存器单元组包括16个移位寄存器单元GOA，在第一组第一信号线组G1中，第一时钟信号线CLK1线与第一极移位寄存器单元GOA1电连接，第九时钟信号线CLK9线与第九级移位寄存器单元GOA9电连接；在第二组第一信号线组G2中，第二时钟信号线CLK2 线与第二极移位寄存器单元GOA2电连接，第十时钟信号线CLK10线与第十级移位寄存器单元GOA10电连接；在第三组第一信号线组G3中，第三时钟信号线CLK3线与第三极移位寄存器单元GOA3电连接，第十一时钟信号线CLK11线与第十一极移位寄存器单元GOA11电连接；在第四组第一信号线组G4中，第四时钟信号线CLK4线与第四极移位寄存器单元GOA4电连接，第十二时钟信号线CLK12线与第十二极移位寄存器单元GOA12电连接；在第五组第一信号线组G5中，第五时钟信号线CLK5线与第五极移位寄存器单元GOA5电连接，第十三时钟信号线CLK13线与第十三极移位寄存器单元GOA13电连接；在第六组第一信号线组G6中，第六时钟信号线CLK6线与第六极移位寄存器单元GOA6电连接，第十四时钟信号线CLK14线与第十四极移位寄存器单元GOA14电连接；在第七组第一信号线组G7中，第七时钟信号线CLK7线与第七极移位寄存器单元GOA7电连接，第十五时钟信号线CLK15线与第十五极移位寄存器单元GOA15电连接；在第八组第一信号线组G8中，第八时钟信号线CLK8线与第八极移位寄存器单元GOA8电连接，第十六时钟信号线CLK16线与第十六极移位寄存器单元GOA16电连接。
下面说明各级GOA单元的级联方式，以图13为例，STV信号线中传输的STV信号分别作为第一级移位寄存器单元GOA1、第二级移位寄存器单元GOA2和第三级移位寄存器单元GOA3的使能信号输入；第一级移位寄存器单元GOA1的输出信号一方面输入显示区AA中，另一方面作为第四级移位寄存器单元GOA4的输入信号；第二级移位寄存器单元GOA2的输出信号一方面输入显示区AA中，另一方面作为第五级移位寄存器单元GOA5的输入信号,；第三级移位寄存器单元GOA3的输出信号一方面输入显示区AA中，另一方面作为第六级移位寄存器单元GOA6的输入信号。图8和图16中GOA单元的级联方式与此处类似，具体可以参考相关技术，这里不再赘述。
在本申请的一些实施例中，周边区包括M组第一信号线组，第一信号线组包括第m时钟信号线和第m+M时钟信号线，其中，M至少包 括3、4、5、6、8或10中的一个，m小于或等于M，且m为正整数；
示例性的，周边区包括3组第一信号线组(M＝3)，m＝1时，第一信号线组包括第一时钟信号线CLK1线和第四时钟信号线CLK4线；m＝2时，第一信号线组包括第二时钟信号线CLK2线和第五时钟信号线CLK5线；m＝3时，第一信号线组包括第三时钟信号线CLK3线和第六时钟信号线CLK5线。另外，周边区包括4、5、6、8或10组第一信号线组(M＝4、5、6、8或10)的情况下，第一信号线组包括的时钟信号线的情况与上述类似，这里不再赘述。
这里对于上述各组第一信号线组排布的方式不进行限定。示例性的，以图12中所示的6CLK线驱动为例，第一组第一信号线组包括第一时钟信号线CLK1线和第四时钟信号线CLK4线，第二组第一信号线组包括第二时钟信号线CLK2线和第五时钟信号线CLK5线，第三组第一信号线组包括第三时钟信号线CLK3线和第六时钟信号线CLK5线；只有同一组时钟信号线相邻设置，两组之间的设置位置可以变换和调整。需要说明的是，同一组时钟信号线相邻设置时，可以设置同一组中第一条时钟信号线位于左侧，第二条时钟信号线位于右侧；或者，也可以设置同一组中第一条时钟信号线位于右侧，第二条时钟信号线位于左侧。
在示例性的实施例中，各组第一信号线组分别沿第一方向依次排布；其中，第一方向为周边区BB指向显示区AA的方向，或者，第一方向为显示区AA指向周边区BB的方向。
表4中提供了相关技术中的两种6CLK线驱动时各时钟信号线以及本申请的实施例提供的48种6CLK线驱动时各时钟信号线沿周边区BB指向显示区AA的排布方式的排布方式。对于8CLK线驱动、10CLK线驱动、12CLK线驱动、16CLK线驱动、20CLK线驱动时各时钟信号线的排布方式也可以参照如表4中的排布方式设置。需要说明的是，对于8CLK线驱动、10CLK线驱动、12CLK线驱动、16CLK线驱动、20CLK线驱动时各时钟信号线的排布方式依次包括24×4×3×2×1、25×5×4×3×2×1、26×6×5×4×3×2×1、28×8×7×6×5×4×3×2×1、210×10×9×8×7×6×5×4×3×2×1种方案。
表4：6CLK信号驱动时各时钟信号线的排布方式
Figure PCTCN2022113717-appb-000004
在本申请的一些实施例中，如图13所示，周边区BB包括三组第一信号线组，第一组G1第一信号线组包括第一时钟信号线CLK1线和第四时钟信号线CLK4线，第二组G2第一信号线组包括第二时钟信号线CLK2线和第五时钟信号线CLK5线，第三组G3第一信号线组包括第三时钟信号线CLK3线和第六时钟信号线CLK6线；第一组第一信号线组G1、第二组第一信号线组G2、第三组第一信号线组G3分别沿第一方向依次排布。其中，在图13中，第一方向为周边区BB指向显示区AA的方向，或者，在另外一些实施例中，第一方向为显示区AA指向周边区BB的方向。
在本申请的一些实施例中，如图13所示，第一时钟信号线CLK1线、第四时钟信号线CLK4线、第二时钟信号线CLK2线、第五时钟信号线CLK5线、第三时钟信号线CLK3线和第六时钟信号线CLK6线分别沿第一方向依次排布。
在另一些实施例中，第四时钟信号线CLK4线、第一时钟信号线CLK1线、第五时钟信号线CLK5线、第二时钟信号线CLK2线、第六时钟信号线CLK6线、第三时钟信号线CLK3线分别沿第一方向依次排布。
在本申请的一些实施例中，阵列基板包括衬底以及位于衬底上的第一导电层和第二导电层，第二导电层位于第一导电层远离衬底的一侧；
在示例性的实施例中，第一导电层可以为栅极层(Gate)，第二导电层可以为源漏金属层(SD)；
如图18所示，第一导电层包括第一信号线组，第二导电层包括多条时钟信号辅助线(例如标记f1、f2…的走线)；时钟信号辅助线的至少部分线段的延伸方向与第一信号线组相交；其中，图18中示出的第一信号线组中各时钟信号线的部分均沿竖直方向延伸；时钟信号辅助线与各时钟信号线交叠的部分均沿水平方向延伸；
在示例性的实施例中，如图18所示，时钟信号线包括多个第一开口K1和多个第二开口K2，第一开口K1的数量大于第二开口K2的数量；至少部分时钟信号辅助线(例如标记f1、f2…的走线)在衬底上的 正投影与第二开口K2的外轮廓在衬底上的正投影圈定的区域存在交叠。
其中，在时钟信号线与时钟信号辅助线电连接的位置处(如图18中标记圆圈的区域)未设置第一开口K1和第二开口K2，而是设置过孔使得两者电连接。
示例性的，第二开口K2的外轮廓在衬底上的正投影圈定的区域的面积大于第一开口K1的外轮廓在衬底上的正投影圈定的区域的面积。
示例性的，位于各时钟信号线远离显示区AA一侧的各信号线均包括多个第一开口K1，一方面，设置第一开口K1能够提高该区域的光线透过率，以在框胶固化阶段提高紫外光线的透过率，提高框胶固化速率；另一方面，该开口能够提高周边区BB走线的散热效率，从而提高周边区BB的电路的稳定性。
另外，通过在时钟信号线上设置第二开口K2，使得各至少部分时钟信号辅助线(例如标记f1、f2…的走线)在衬底上的正投影与第二开口K2的外轮廓在衬底上的正投影圈定的区域存在交叠，这样，能够减小位于第二导电层的时钟信号辅助线与位于第一导电层的时钟信号线之间的交叠面积，从而很大程度上减小两者之间产生的寄生电容，从而提高电路的稳定性。
至少部分时钟信号辅助线(例如标记f1、f2…的走线)在衬底上的正投影与第二开口K2的外轮廓在衬底上的正投影圈定的区域存在交叠包括但不限于如下情况：
第一、部分钟信号辅助线(例如标记f1、f2…的走线)在衬底上的正投影与第二开口K2的外轮廓在衬底上的正投影圈定的区域存在交叠；
第二、每一条钟信号辅助线(例如标记f1、f2…的走线)在衬底上的正投影均与第二开口K2的外轮廓在衬底上的正投影圈定的区域存在交叠。
需要说明的是，这里对于第二开口K2的数量不进行限定，具体可以根据实际的电路设计确定。
示例性的，时钟信号辅助线的种类与时钟信号线的数量相同；对于一组移位寄存器组对应的时钟信号辅助线的数量与时钟信号线的数量 相同。
例如，如图18所示，第一时钟信号线CLK1线通过第一时钟信号辅助线f1与第一极移位寄存器GOA1电连接，第二时钟信号线CLK2线通过第二时钟信号辅助线f2与第二极移位寄存器GOA2电连接，第三时钟信号线CLK3线通过第三时钟信号辅助线f3与第三极移位寄存器GOA3电连接，第四时钟信号线CLK4线通过第四时钟信号辅助线f4与第四极移位寄存器GOA4电连接，第五时钟信号线CLK5线通过第五时钟信号辅助线f5与第五极移位寄存器GOA5电连接，第六时钟信号线CLK6线通过第六时钟信号辅助线f6与第六极移位寄存器GOA6电连接，第七时钟信号线CLK7线通过第七时钟信号辅助线f7与第七极移位寄存器GOA7电连接，第八时钟信号线CLK8线通过第八时钟信号辅助线f8与第八极移位寄存器GOA8电连接。
在本申请的一些实施例中，如图18所示，周边区BB包括第一间隙X1，第一间隙X1位于移位寄存器单元组与第一信号线组之间，且第一间隙X1的延伸方向与时钟信号线的延伸方向相同；
部分时钟信号辅助线(例如标记f1、f2…的走线)分别包括弯折结构，且各时钟信号辅助线的弯折结构在衬底上的正投影图形的尺寸不同，各弯折结构均位于第一间隙X1中。
示例性的，在图18中，除第一时钟信号辅助线f1之外的其它各时钟信号辅助线均包括弯折结构，根据各时钟信号辅助线沿周边区BB指向显示区AA的方向到与之直接接触的晶体管(GOA单元中的晶体管)之间的最小距离的不同，各弯折结构的尺寸不同，以弥补由于长度差异造成的电阻差异，从而提高电路中电信号的准确传输，提高电路的稳定性，进而提高显示效果。
在本申请的一些实施例中，如图18所示，部分时钟信号辅助线包括第一线段、弯折结构和第二线段；第一线段和第二线段通过弯折结构连接；第一线段和第二线段的延伸方向相同；
示例性的，除第一时钟信号辅助线f1之外的其它各时钟信号辅助线均包括弯折结构；
第一线段在衬底上的正投影与时钟信号线在衬底上的正投影交叠，各时钟信号辅助线的第一线段沿其延伸方向上长度、第二线段沿其延伸方向上长度与弯折结构沿其延伸方向上长度之和均相等。这样，能够弥补由于长度差异造成的电阻差异，从而提高电路中电信号的准确传输，提高电路的稳定性，进而提高显示效果。
在本申请的一些实施例中，如图18所示，部分第二信号线(例如VDD1、VDD2、VSS1、VSS2)位于各第一信号线组与移位寄存器单元组之间，第一间隙X1位于各第一信号线组(时钟信号线CLK)与第二信号线(例如VDD1、VDD2、VSS1、VSS2)之间；第一间隙X1沿第一信号线组指向第二信号线的方向上的尺寸大于两倍的相邻两条时钟信号线CLK之间的最小距离。
另外，阵列基板还包括第二间隙X2，第二间隙X2位于STV信号线与移位寄存器组之间。第二间隙X2的宽度小于第一间隙X1的宽度，其中，这里的宽度指的是第一信号线组指向第二信号线的方向上的尺寸。
本申请的实施例提供了一种显示面板，包括如前文所述的阵列基板。
这里对于上述显示面板包括的阵列基板的结构不再赘述，具体可以参考前文的说明。
在示例性的实施例中，上述显示面板为液晶显示面板(Liquid Crystal Display，LCD)，示例性的，液晶显示面板可以包括扭曲向列(Twisted Nematic，TN)型、垂直配向(Vertical Alignment，VA)型、平面转换(In Plane Switching，IPS)型和高级超维场开关(ADS，Advanced Super Dimension Switch)型。
在示例性的实施例中，上述显示面板可以为OLED(Organic Light Emitting Diode，有机发光二极管)显示面板，OLED显示面板包括具有硅衬底(Si Substrate)的OLED显示面板以及具有玻璃衬底的OLED显示面板。
在示例性的实施例中，上述显示面板可以为Micro-LED(Micro-Light Emitting Diode，微型有机发光二极管)。或者，上述显示面板可 以为Mini-LED(Mini-Light Emitting Diode，次毫米有机发光二极管)。Micro-LED显示面板和Mini-LED显示面板也分别包括玻璃衬底和硅衬底两种类型。
本申请的实施例提供了一种显示装置，包括如前文所述的显示面板，还包括时序控制器(TCON)，时序控制器被配置为向显示面板的各时钟信号线输入不同的时钟信号。
在示例性的实施例中，显示装置的阵列基板上的GOA或者Gate IC对应的时钟信号CLK信号的输入由驱动芯片(例如Level shifter或多合一的PMIC芯片)输出。驱动芯片输出端子(Pin)对应的CLK信号时序可以通过Code调整，例如，原先输出CLK1信号的输出端子1(Pin1)通过Code调整之后可以输出CLK5信号，原先输出CLK5信号的输出端子5(Pin5)通过Code调整之后可以输出CLK1信号，这样，可以在驱动芯片不变的情况下，通过Code调整使得驱动芯片的输出信号与时钟信号线的分布向对应，从而使得在原有工艺制备条件下，本申请的实施例提供的显示装置的阵列基板仍能够正常生产，也就是说，在时钟信号线排布设计变动的情况下仍能够使用原有工艺生产，最大限度的降低了生产成本。
该显示装置可以是LCD显示器、OLED显示器、Micro-LED显示器、Mini-LED显示器等显示器件以及包括这些显示器件的电视、数码相机、手机、平板电脑等任何具有显示功能的产品或者部件。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (15)

  1. 一种阵列基板，其中，包括：显示区以及位于所述显示区一侧的周边区；
    所述周边区包括多组第一信号线组，每组所述第一信号线组包括延伸方向相同的两条时钟信号线；
    其中，所述时钟信号线中传输的信号为方形波信号，同一组所述第一信号线组中的一条所述时钟信号线传输的时钟信号的相位与另一条所述时钟信号线传输的时钟信号的相位相反，且同一组所述第一信号线组中的两条所述时钟信号线相邻设置。
  2. 根据权利要求1所述的阵列基板，其中，所述周边区还包括至少一条第二信号线，所述第二信号线与所述时钟信号线的延伸方向相同，且所述第二信号线中传输的信号为恒定的电压信号；
    其中，所述第二信号线到所述时钟信号线之间的最小距离小于或等于预设值，所述预设值的范围包括1μm-5cm。
  3. 根据权利要求2所述的阵列基板，其中，所述第二信号线包括公共信号线、第一电源信号线、第二电源信号线、第一电平信号线、第二电平信号线和接地线中的至少一条。
  4. 根据权利要求3所述的阵列基板，其中，所述公共信号线包括公共电极信号线、公共电极反馈信号线和公共电极补偿信号线，所述公共电极信号线、所述公共电极反馈信号线和所述公共电极补偿信号线电连接在一起。
  5. 根据权利要求3所述的阵列基板，其中，所述第二信号线位于各所述第一信号线组远离所述显示区的一侧；
    和/或，所述第二信号线位于各所述第一信号线组靠近所述显示区的一侧。
  6. 根据权利要求3所述的阵列基板，其中，所述周边区包括多组移位寄存器单元组，各组所述移位寄存器单元组包括的所述移位寄存器单元的数量相同；同一组所述移位寄存器单元组中的所述移位寄存器单元的数量与各所述时钟信号线的数量相同；各所述移位寄存器单元均位 于各所述第一信号线组靠近所述显示区的一侧；
    在一组所述移位寄存器单元组包括N个级联设置的所述移位寄存器单元的情况下，同一组所述第一信号线组中的一条所述时钟信号线与第n级所述移位寄存器单元电连接，同一组所述第一信号线组中的另一条所述时钟信号线与第n+N/2级所述移位寄存器单元电连接；n小于或等于N/2，且n为奇数，N为偶数。
  7. 根据权利要求6所述的阵列基板，其中，所述周边区包括M组所述第一信号线组，所述第一信号线组包括第m时钟信号线和第m+M时钟信号线，其中，M至少包括3、4、5、6、8或10中的一个，m小于或等于M，且m为正整数；
    各组所述第一信号线组分别沿第一方向依次排布；其中，所述第一方向为所述周边区指向所述显示区的方向，或者，所述第一方向为所述显示区指向所述周边区的方向。
  8. 根据权利要求7所述的阵列基板，其中，所述周边区包括三组所述第一信号线组，第一组所述第一信号线组包括第一时钟信号线和第四时钟信号线，第二组所述第一信号线组包括第二时钟信号线和第五时钟信号线，第三组所述第一信号线组包括第三时钟信号线和第六时钟信号线；
    第一组所述第一信号线组、第二组所述第一信号线组、第三组所述第一信号线组分别沿所述第一方向依次排布。
  9. 根据权利要求8所述的阵列基板，其中，所述第一时钟信号线、所述第四时钟信号线、所述第二时钟信号线、所述第五时钟信号线、所述第三时钟信号线和所述第六时钟信号线分别沿所述第一方向依次排布。
  10. 根据权利要求6-9中任一项所述的阵列基板，其中，所述阵列基板包括衬底以及位于所述衬底上的第一导电层和第二导电层，所述第二导电层位于所述第一导电层远离所述衬底的一侧；
    所述第一导电层包括所述第一信号线组，所述第二导电层包括多条时钟信号辅助线；所述时钟信号辅助线的至少部分线段的延伸方向与所 述第一信号线组相交；
    所述时钟信号线包括多个第一开口和多个第二开口，所述第一开口的数量大于所述第二开口的数量；至少部分所述时钟信号辅助线在所述衬底上的正投影与所述第二开口的外轮廓在所述衬底上的正投影圈定的区域存在交叠。
  11. 根据权利要求10所述的阵列基板，其中，所述周边区包括第一间隙，所述第一间隙位于所述移位寄存器单元组与所述第一信号线组之间，且所述第一间隙的延伸方向与所述时钟信号线的延伸方向相同；
    部分所述时钟信号辅助线分别包括弯折结构，且各所述时钟信号辅助线的所述弯折结构在所述衬底上的正投影图形的尺寸不同，各所述弯折结构均位于所述第一间隙中。
  12. 根据权利要求11所述的阵列基板，其中，部分所述时钟信号辅助线包括第一线段、所述弯折结构和第二线段；所述第一线段和所述第二线段通过所述弯折结构连接；
    所述第一线段在所述衬底上的正投影与所述时钟信号线在所述衬底上的正投影交叠，各所述时钟信号辅助线的所述第一线段沿其延伸方向上长度、所述第二线段沿其延伸方向上长度与所述弯折结构沿其延伸方向上长度之和均相等。
  13. 根据权利要求11所述的阵列基板，其中，部分所述第二信号线位于各所述第一信号线组与所述移位寄存器单元组之间，所述第一间隙位于各所述第一信号线组与所述第二信号线之间；
    所述第一间隙沿所述第一信号线组指向所述第二信号线的方向上的尺寸大于两倍的相邻两条所述时钟信号线之间的最小距离。
  14. 一种显示面板，其中，包括如权利要求1-13中任一项所述的阵列基板。
  15. 一种显示装置，其中，包括如权利要求14所述的显示面板，还包括时序控制器，所述时序控制器被配置为向所述显示面板的各时钟信号线输入不同的时钟信号。
PCT/CN2022/113717 2022-08-19 2022-08-19 阵列基板、显示面板及显示装置 WO2024036626A1 (zh)

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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070195215A1 (en) * 2006-02-22 2007-08-23 Seiko Epson Corporation Electro-optical device and electronic apparatus including electro-optical device
CN110751929A (zh) * 2019-11-29 2020-02-04 厦门天马微电子有限公司 一种显示面板及显示装置
CN110930927A (zh) * 2019-12-09 2020-03-27 厦门天马微电子有限公司 显示面板和显示装置
CN111429856A (zh) * 2020-04-09 2020-07-17 深圳市华星光电半导体显示技术有限公司 显示面板和电子设备
CN113594186A (zh) * 2021-07-30 2021-11-02 武汉天马微电子有限公司 阵列基板及显示面板
CN113853642A (zh) * 2020-04-28 2021-12-28 京东方科技集团股份有限公司 显示面板、驱动方法及显示装置
CN215494431U (zh) * 2021-06-09 2022-01-11 合肥京东方显示技术有限公司 一种阵列基板、显示面板及显示设备

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070195215A1 (en) * 2006-02-22 2007-08-23 Seiko Epson Corporation Electro-optical device and electronic apparatus including electro-optical device
CN110751929A (zh) * 2019-11-29 2020-02-04 厦门天马微电子有限公司 一种显示面板及显示装置
CN110930927A (zh) * 2019-12-09 2020-03-27 厦门天马微电子有限公司 显示面板和显示装置
CN111429856A (zh) * 2020-04-09 2020-07-17 深圳市华星光电半导体显示技术有限公司 显示面板和电子设备
CN113853642A (zh) * 2020-04-28 2021-12-28 京东方科技集团股份有限公司 显示面板、驱动方法及显示装置
CN215494431U (zh) * 2021-06-09 2022-01-11 合肥京东方显示技术有限公司 一种阵列基板、显示面板及显示设备
CN113594186A (zh) * 2021-07-30 2021-11-02 武汉天马微电子有限公司 阵列基板及显示面板

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