WO2016149994A1 - Pmos栅极驱动电路 - Google Patents

Pmos栅极驱动电路 Download PDF

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Publication number
WO2016149994A1
WO2016149994A1 PCT/CN2015/078825 CN2015078825W WO2016149994A1 WO 2016149994 A1 WO2016149994 A1 WO 2016149994A1 CN 2015078825 W CN2015078825 W CN 2015078825W WO 2016149994 A1 WO2016149994 A1 WO 2016149994A1
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Prior art keywords
electrically connected
thin film
film transistor
type thin
node
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PCT/CN2015/078825
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English (en)
French (fr)
Inventor
戴超
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深圳市华星光电技术有限公司
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Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US14/761,301 priority Critical patent/US9570028B2/en
Priority to KR1020177022688A priority patent/KR101943249B1/ko
Priority to GB1711831.6A priority patent/GB2550306B/en
Priority to JP2017545370A priority patent/JP6405056B2/ja
Publication of WO2016149994A1 publication Critical patent/WO2016149994A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/3406—Control of illumination source
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention relates to the field of liquid crystal display driving, and in particular to a PMOS gate driving circuit.
  • LCD Liquid crystal display
  • PDAs personal digital assistants
  • digital cameras computer screens or laptop screens, etc.
  • liquid crystal displays which include a liquid crystal display panel and a backlight module.
  • the working principle of the liquid crystal display panel is to fill liquid crystal molecules between a Thin Film Transistor Array Substrate (TFT Array Substrate) and a Color Filter (CF), and apply driving on the two substrates.
  • TFT Array Substrate Thin Film Transistor Array Substrate
  • CF Color Filter
  • each pixel is electrically connected to a thin film transistor (TFT), a gate of a thin film transistor is connected to a horizontal scanning line, and a drain is connected to a vertical data line, and a source (Source) ) is connected to the pixel electrode.
  • TFT thin film transistor
  • Source Source
  • the driving of the horizontal scanning line of the active liquid crystal display panel is mainly completed by an external integrated circuit (IC), and the external IC can control the stepwise charging and discharging of the horizontal scanning lines of each level.
  • the GOA technology (Gate Driver on Array) is an array substrate row driving technology, which is a driving method in which a gate driving circuit can be fabricated on a TFT array substrate by using an array process of a liquid crystal display panel to realize a gate-by-row scanning.
  • GOA technology can reduce the bonding process of external ICs, have the opportunity to increase production capacity and reduce product cost, and can make LCD panels more suitable for making narrow-frame or borderless display products.
  • CMOS complementary metal-oxide-semiconductor
  • CMOS complementary metal-oxide-semiconductor
  • the gate drive circuit improves the performance of the gate drive circuit, improve the integration of the liquid crystal display panel, and further reduce the frame width of the liquid crystal display panel.
  • the present invention provides a PMOS gate driving circuit, including a plurality of cascaded GOA unit circuits, each stage of the GOA unit circuit includes: a pull-up control module, a pull-up module, a downlink module, and a first Pull-down module, bootstrap capacitor, and pull-down maintenance module;
  • the pull-up control module is electrically connected to the first node and the pull-down maintenance module; the pull-up control module includes at least one P-type thin film transistor, and at least accesses the level of the first-stage N-1th GOA unit circuit Signal, and constant voltage negative potential;
  • the pull-up module includes: a 22nd P-type thin film transistor, a gate of the 22nd P-type thin film transistor is electrically connected to the first node, and a source is electrically connected to the Mth clock signal, and the drain a pole output scan drive signal;
  • the first pull-down module is electrically connected to the first node and the scan driving signal, and includes a fortieth P-type thin film transistor and a forty-first P-type thin film transistor connected in series, for using the first node during the inactive period The potential is pulled to the potential of the scan driving signal;
  • One end of the bootstrap capacitor is electrically connected to the first node, and the other end is electrically connected to the scan driving signal;
  • the pull-down maintaining module includes: an inverter composed of a plurality of P-type thin film transistors, an input end of the inverter is electrically connected to the first node, and an output end is electrically connected to the second node; a second P-type thin film transistor, the gate of the thirty-second P-type thin film transistor is electrically connected to the second node, and the source is electrically connected to the drain of the forty-first P-type thin film transistor, and the drain is electrically connected a first constant voltage positive potential; a forty-second P-type thin film transistor, the gate of the forty-second P-type thin film transistor is electrically connected to the second node, and the drain is electrically connected to the first node, the source Electrically connected to the drain of the 82nd P-type thin film transistor; the 82nd P-type thin film transistor, the gate of the 82nd P-type thin film transistor is electrically connected to the first node, and the source is electrically Connected to a constant voltage negative potential, the drain is electrically connected
  • the pull-up control module includes a P-type thin film transistor: an eleventh P-type thin film transistor, and a gate of the eleventh P-type thin film transistor is connected to a level-transmitted signal of a first-stage N-1th GOA unit circuit
  • the source is connected to a constant voltage negative potential, and the drain is electrically connected to the first node.
  • the gate of the fortieth P-type thin film transistor is electrically connected to the M+2 clock signal, the source is electrically connected to the first node, and the drain is electrically connected to the gate of the forty-first P-type thin film transistor.
  • the gate and the source of the forty-first P-type thin film transistor are electrically connected to the drain of the fortieth P-type thin film transistor, and the drain is electrically connected to the scan driving signal.
  • the inverter includes a fifty-second P-type thin film transistor, and the fifty-second P-type thin film crystal
  • the gate of the body tube is electrically connected to the first node, the source is electrically connected to the second constant voltage positive potential, and the drain is electrically connected to the third node;
  • the fifty-first P-type thin film crystal, the fiftyth a gate and a source of a P-type thin film transistor are electrically connected to a constant voltage negative potential, and a drain is electrically connected to the third node;
  • the gate is electrically connected to the first node, the source is electrically connected to the second constant voltage positive potential, the drain is electrically connected to the second node;
  • the gate of the thin film transistor is electrically connected to the third node, the source is electrically connected to the negative potential of the constant voltage, and the drain is electrically connected
  • the inverter is a dual inverter comprising a main inverter and an auxiliary inverter;
  • the main inverter includes: a fifty-second P-type thin film transistor, a gate of the fifty-two P-type thin film transistor is electrically connected to the first node, and a source is electrically connected to the first constant voltage positive potential The drain is electrically connected to the third node; the fifty-first P-type thin film crystal, the gate and the source of the fifty-first P-type thin film transistor are electrically connected to the constant voltage negative potential, and the drain electrical property Connected to the third node; a fifty-fourth P-type thin film transistor, the gate of the fifty-fourth P-type thin film transistor is electrically connected to the first node, the source is electrically connected to the fourth node, and the drain is electrically connected Connected to the second node; the 53rd P-type thin film transistor, the gate of the 53rd P-type thin film transistor is electrically connected to the third node, and the source is electrically connected to the constant voltage negative potential, and the drain is electrically connected Sexually connected to the second node;
  • the auxiliary inverter includes: a sixty-second P-type thin film transistor, a gate of the sixty-two P-type thin film transistor is electrically connected to the first node, and a source is electrically connected to the second constant voltage positive potential
  • the drain is electrically connected to the fifth node; the sixty-first P-type thin film crystal, the gate and the source of the sixty-first P-type thin film transistor are electrically connected to the constant voltage negative potential, and the drain electrical property Connected to the fifth node; a 64th P-type thin film transistor, the gate of the 64th P-type thin film transistor is electrically connected to the first node, and the source is electrically connected to the second constant voltage positive potential, and is drained Electrode is electrically connected to the fourth node; a 63rd P-type thin film transistor, the gate of the 63rd P-type thin film transistor is electrically connected to the fifth node, and the source is electrically connected to the constant voltage negative potential, The drain is electrically connected to the fourth node.
  • the inverter is a dual inverter comprising a main inverter and an auxiliary inverter;
  • the main inverter includes: a fifty-second P-type thin film transistor, a gate of the fifty-two P-type thin film transistor is electrically connected to the first node, and a source is electrically connected to the first constant voltage positive potential The drain is electrically connected to the third node; the fifty-first P-type thin film crystal, the gate and the source of the fifty-first P-type thin film transistor are electrically connected to the constant voltage negative potential, and the drain electrical property Connected to the third node; a fifty-fourth P-type thin film transistor, the gate of the fifty-fourth P-type thin film transistor is electrically connected to the first node, the source is electrically connected to the fourth node, and the drain is electrically connected Connected to the second node; a fifty-third P-type thin film transistor, the gate of the fifty-third P-type thin film transistor is electrically connected In the third node, the source is electrically connected to the constant voltage negative potential, and the drain is electrically connected to the second node;
  • the auxiliary inverter includes: a 64th P-type thin film transistor, a gate of the 64th P-type thin film transistor is electrically connected to the first node, and a source is electrically connected to the second constant voltage positive potential The drain is electrically connected to the fourth node; the 63rd P-type thin film transistor, the gate of the 63rd P-type thin film transistor is electrically connected to the third node, and the source is electrically connected to the constant voltage negative The potential and the drain are electrically connected to the fourth node.
  • the invention also provides a PMOS gate driving circuit, comprising a plurality of cascaded GOA unit circuits, each stage GOA unit circuit comprises: a pull-up control module, a pull-up module, a downlink module, a first pull-down module, Bootstrap capacitor, and pull-down maintenance module;
  • N be a positive integer in the Nth stage GOA unit circuit:
  • the pull-up control module is electrically connected to the first node and the pull-down maintenance module; the pull-up control module includes at least one P-type thin film transistor, and at least accesses the level of the first-stage N-1th GOA unit circuit Signal, and constant voltage negative potential;
  • the pull-up module includes: a 22nd P-type thin film transistor, a gate of the 22nd P-type thin film transistor is electrically connected to the first node, and a source is electrically connected to the Mth clock signal, and the drain a pole output scan drive signal;
  • the down-transmission module includes: a 21st P-type thin film transistor, a gate of the 21st P-type thin film transistor is electrically connected to the first node, and a source is electrically connected to the Mth clock signal, and the drain Extreme output stage signal;
  • One end of the bootstrap capacitor is electrically connected to the first node, and the other end is electrically connected to the scan driving signal;
  • the pull-down maintaining module includes: an inverter composed of a plurality of P-type thin film transistors, an input end of the inverter is electrically connected to the first node, and an output end is electrically connected to the second node; a second P-type thin film transistor, the gate of the thirty-second P-type thin film transistor is electrically connected to the second node, and the source is electrically connected to the drain of the forty-first P-type thin film transistor, and the drain is electrically connected a first constant voltage positive potential; a forty-second P-type thin film transistor, the gate of the forty-second P-type thin film transistor is electrically connected to the second node, and the drain is electrically connected to the first node, the source Electrically connected to the drain of the 82nd P-type thin film transistor; the 82nd P-type thin film transistor, the gate of the 82nd P-type thin film transistor is electrically connected to the first node, and the source is electrically Connected to a constant voltage negative potential, the drain is electrically connected
  • the first constant voltage positive potential is lower than the second constant voltage positive potential
  • the pull-up control module includes a P-type thin film transistor: an eleventh P-type thin film transistor, and a gate of the eleventh P-type thin film transistor is connected to a level of the first-stage N-1th GOA unit circuit. Transmitting the signal, the source is connected to the constant voltage negative potential, and the drain is electrically connected to the first node;
  • the gate of the fortieth P-type thin film transistor is electrically connected to the level-transmitting signal of the next two-stage N+2-level GOA unit or the scan driving signal of the next two-stage N+2-level GOA unit, and the source Electrically connected to the first node, the drain is electrically connected to the source of the forty-first P-type thin film transistor; the gate of the forty-first P-type thin film transistor is electrically connected to the M+2 clock signal
  • the source is electrically connected to the drain of the fortieth P-type thin film transistor, and the drain is electrically connected to the scan driving signal.
  • the invention provides a PMOS gate driving circuit, wherein the pull-up control module is connected to a constant voltage negative potential, which can reduce the influence of leakage of the PMOS device on the first node; and the pull-down maintenance module is set by P
  • a dual inverter composed of a thin film transistor and a special anti-leakage design can reduce the leakage of the first node, avoid the influence of the electrical properties of the depletion-type P-type thin film transistor on the output of the inverter, and improve the gate driving circuit.
  • the stability and the integration of the panel further reduce the width of the frame of the liquid crystal display panel, and are particularly suitable for small-sized panels having high requirements on the width of the frame.
  • FIG. 1 is a circuit diagram of a first embodiment of a PMOS gate driving circuit of the present invention
  • FIG. 2 is a circuit diagram of a first stage GOA unit circuit of a first embodiment of a PMOS gate driving circuit of the present invention
  • FIG. 3 is a circuit diagram of a penultimate stage GOA unit circuit of the first embodiment of the PMOS gate driving circuit of the present invention
  • FIG. 4 is a circuit diagram of a final stage GOA unit circuit of the first embodiment of the PMOS gate driving circuit of the present invention
  • FIG. 5 is a timing diagram of a PMOS gate driving circuit of the present invention.
  • FIG. 6 is a circuit diagram of a second embodiment of a PMOS gate driving circuit of the present invention.
  • FIG. 7 is a circuit diagram of a third embodiment of a PMOS gate driving circuit of the present invention.
  • FIG. 8 is a circuit diagram of a fourth embodiment of a PMOS gate driving circuit of the present invention.
  • FIG. 9 is a circuit diagram of a fifth embodiment of a PMOS gate driving circuit of the present invention.
  • FIG. 10 is a circuit diagram of a sixth embodiment of a PMOS gate driving circuit of the present invention.
  • FIG. 11 is a circuit diagram of a seventh embodiment of a PMOS gate driving circuit of the present invention.
  • FIG. 12 is a circuit diagram of an eighth embodiment of a PMOS gate driving circuit of the present invention.
  • FIG. 13 is a schematic diagram showing the structure of a first circuit of an inverter in a PMOS gate driving circuit of the present invention
  • FIG. 14 is a schematic diagram showing a second circuit structure of an inverter in a PMOS gate driving circuit of the present invention.
  • FIG. 15 is a schematic diagram showing a third circuit structure of an inverter in a PMOS gate driving circuit of the present invention.
  • the present invention provides a PMOS gate drive circuit.
  • the PMOS gate driving circuit includes a plurality of cascaded GOA unit circuits, each stage of the GOA unit circuit includes: a pull-up control module 100, a pull-up module 200, The downlink module 300, the first pull-down module 400, the bootstrap capacitor 500, and the pull-down maintenance module 600.
  • N be a positive integer in the Nth stage GOA unit circuit:
  • the pull-up control module 100 includes a P-type thin film transistor: an eleventh P-type thin film transistor T11, and a gate of the eleventh P-type thin film transistor T11 is connected to a first-stage N-1th GOA unit circuit.
  • the signal ST (N-1) is transmitted, the source is connected to the constant voltage negative potential VSS1, and the drain is electrically connected to the first node Q(N).
  • the pull-up module 200 includes: a 222th P-type thin film transistor T22, the gate of the 22nd P-type thin film transistor T22 is electrically connected to the first node Q(N), and the source is electrically connected to The Mth clock signal CK(M) and the drain output scan drive signal G(N).
  • the down-going module 300 includes: a 21st P-type thin film transistor T21, the gate of the 21st P-type thin film transistor T21 is electrically connected to the first node Q(N), and the source is electrically connected to The Mth clock signal CK(M) and the drain output stage pass signal ST(N).
  • the first pull-down module 400 includes: a fortieth P-type thin film transistor T40 and a forty-first P-type thin film transistor T41 connected in series; a gate of the forty-th P-type thin film transistor T40
  • the gate drive signal ST(N+2) electrically connected to the next two stages of the N+2th GOA unit or the scan drive signal G(N+2) of the next two stages of the N+2th GOA unit, source electrical Connected to the first node Q(N), the drain is electrically connected to the source of the forty-first P-type thin film transistor T41; the gate of the forty-first P-type thin film transistor T41 is electrically connected to the M+
  • the two clock signals CK (M+2) are electrically connected to the drain of the fortieth P-type thin film transistor T40, and the drain is electrically connected to the scan driving signal G(N).
  • One end of the bootstrap capacitor 500 is electrically connected to the first node Q(N), and the other end is electrically connected to the scan driving signal G(N).
  • the pull-down maintaining module 600 includes: an inverter F1 composed of a plurality of P-type thin film transistors, an input end of the inverter F1 is electrically connected to the first node Q(N), and an output terminal is electrically connected to the output terminal a second node P(N); a thirty-second P-type thin film transistor T32, a gate of the thirty-second P-type thin film transistor T32 is electrically connected to the second node P(N), and the source is electrically connected to
  • the drain of the forty-first P-type thin film transistor T41 is electrically connected to the first constant voltage positive potential VDD1;
  • the gate of the forty-second P-type thin film transistor T42 of the forty-second P-type thin film transistor T42 Electrically connected to the second node P(N), the drain is electrically connected to the first node Q(N), and the source is electrically connected to the drain of the 82nd P-type thin film transistor T82; the 82nd P The thin film transistor T82, the gate of the
  • the eleventh P-type thin film transistor The gate of T11 is electrically connected to the enable signal STV; as shown in FIG. 3 and FIG. 4, in the second-to-last stage and the last-level connection relationship of the first embodiment of the PMOS gate drive circuit of the present invention, the The gate of the forty P-type thin film transistor T40 is electrically connected to the enable signal STV.
  • FIG. 5 is a timing diagram of the PMOS gate driving circuit of the present invention, wherein STV represents a start signal of the circuit; CK(1), CK(2), CK(3), and CK(4) are clock signals CK ( The four sets of clock signals included in M) are high frequency clock signals.
  • the M+2 group clock signal CK (M+) 2) is the first clock signal CK(1)
  • the clock signal CK(M) is the fourth clock signal CK(4)
  • the M+2 group clock signal CK(M+2) is the second
  • VSS1 is a constant-voltage negative potential;
  • VDD1 VDD is the first and second constant voltage positive potentials, respectively, and the first constant voltage positive potential VDD1 is lower than the second constant voltage positive potential VDD2.
  • the working process of the first embodiment of the PMOS gate driving circuit is:
  • the eleventh P-type thin film transistor T11 When the level signal ST(N-1) of the upper N-1th GOA unit circuit is low, the eleventh P-type thin film transistor T11 is turned on, and the constant voltage negative potential VSS1 enters the circuit, and the bootstrap capacitor 500 charging, so that the first node Q (N) gets a negative potential, and then the level signal ST (N-1) of the upper N-1 stage GOA unit circuit is converted to a high potential, the first node Q (N) The negative potential is maintained by the bootstrap capacitor 500 while the twenty-first P-type thin film transistor T21 and the twenty-second P-type thin film transistor T22 are turned on by the control of the first node Q(N).
  • the Mth group clock signal CK(M) is at a low potential, and continues to charge the bootstrap capacitor 500 through the twenty-second P-type thin film transistor T22, so that the first node Q(N) reaches a lower potential,
  • the drain of the twenty-second P-type thin film transistor T22 outputs the scan driving signal G(N)
  • the drain of the twenty-first P-type thin film transistor T21 outputs the signal ST(N)
  • the scan driving signal G Both (N) and the graded signal ST(N) are low.
  • the time slot in which the scan drive signal G(N) is low is generally referred to as the active period.
  • the inverter F1 is inverted.
  • the 82nd P-type thin film transistor T82 in the pull-down maintaining module 600 is turned on, and the 81st P-type thin film transistor T81 and the forty-second P-type thin film transistor are turned on.
  • T42 and the 32nd P-type thin film transistor T32 are both turned off, and the source potential of the forty-second P-type thin film transistor T42 is pulled down to the constant voltage negative potential VSS1, which can reduce the first node Q(N) after the fourth
  • the leakage of the twelve P-type thin film transistor T42 and the constant voltage negative potential VSS1 are used to perform signal transmission of the eleventh thin film transistor T11, and the leakage of the first node Q(N) can also be reduced.
  • the Mth group clock signal CK(M) becomes a high potential, corresponding to the scan driving signal G(N) outputted from the drain of the 22nd P-type thin film transistor T22, and the 21st P-type thin film transistor
  • the pass signal ST(N) of the drain output of T21 also transitions to a high potential, and the circuit enters the inactive period, when the M+2 clock signal CK(M+2), and the next two stages of the N+2 level GOA
  • the fortieth P-type thin film transistor T40 and the fortieth A P-type thin film transistor T41 is turned on, the potential of the first node Q(N) is pulled to a high potential of the scan driving signal G(N), and the twenty-first P-type thin film transistor T21 and the twenty-second P-type film are Transistor T22 is turned off;
  • the inverter F1 may be three structures as shown in FIG. 13, FIG. 14, and FIG. 15, respectively:
  • the structure of the first inverter F1 is as shown in FIG. 13, and includes a fifty-second P-type thin film transistor T52.
  • the gate of the fifty-second P-type thin film transistor T52 is electrically connected to the first node Q (N).
  • the source is electrically connected to the second constant voltage positive potential VDD2, the drain is electrically connected to the third node S(N); the fifty-first P-type thin film crystal T51, the fifty-first P-type thin film transistor
  • the gate and the source of the T51 are electrically connected to the constant voltage negative potential VSS1, the drain is electrically connected to the third node S(N), and the fifty-fourth P-type thin film transistor T54, the fifty-fourth P-type
  • the gate of the thin film transistor T54 is electrically connected to the first node Q(N), the source is electrically connected to the second constant voltage positive potential VDD2, and the drain is electrically connected to the second node P(N); a P-type thin film transistor T53, the gate of the 53r
  • the fifty-second P-type thin film transistor T52 and the fifty-fourth P-type thin film transistor T54 are both turned on, and the fifty-first P-type thin film transistor T51 is The fifty-third P-type thin film transistor T53 is turned off, the potential of the second node P(N) is the second constant voltage positive potential VDD2; when the first node Q(N) is high during the non-active period, the fiftyth The second P-type thin film transistor T52 and the fifty-fourth P-type thin film transistor T54 are both turned off, and the fifty-first P-type thin film transistor T51 and the fifty-third P-type thin film transistor T53 are both turned on, and the second node P(N) The potential is a constant voltage negative potential VSS1.
  • the structure of the second inverter F1 is as shown in FIG. 14.
  • the inverter F1 is a dual inverter, and includes a main inverter F11 and an auxiliary inverter F13.
  • the main inverter F11 includes: a fifty-second P-type thin film transistor T52, the gate of the fifty-second P-type thin film transistor T52 is electrically connected to the first node Q(N), and the source is electrically connected.
  • the first constant voltage positive potential VDD1 the drain is electrically connected to the third node S(N); the fifty-first P-type thin film crystal T51, the gate and the source of the fifty-first P-type thin film transistor T51
  • the current is electrically connected to the constant voltage negative potential VSS1, the drain is electrically connected to the third node S(N); the fifty-fourth P-type thin film transistor T54, the gate of the fifty-fourth P-type thin film transistor T54 is electrically connected Connected to the first node Q(N), the source is electrically connected to the fourth node K(N), the drain is electrically connected to the second node P(N), and the fifty-third P-type thin film transistor T53 is The gate of the 53rd P-type thin film transistor T53 is
  • the auxiliary inverter F13 includes: a sixty-second P-type thin film transistor T62, the gate of the sixty-two P-type thin film transistor T62 is electrically connected to the first node Q(N), the source is electrically connected to the second constant voltage positive potential VDD2, and the drain is electrically connected to the fifth a node T(N); a sixty-first P-type thin film transistor T61, the gate and the source of the sixty-first P-type thin film transistor T61 are electrically connected to the constant voltage negative potential VSS1, and the drain is electrically connected to a fifth node T(N); a 64th P-type thin film transistor T64, the gate of the 64th P-type thin film transistor T64 is electrically connected to the first node Q(N), and the source is electrically connected to a second constant voltage positive potential VDD2, a drain electrically connected to the fourth node K(N); a 63rd P-type thin film transistor T63, the gate of the 63rd P-type thin film transistor T63 is electrical
  • the fifty-second P-type thin film transistor T52 and the fifty-fourth P-type thin film transistor T54 in the main inverter F11 are both turned on, the fiftyth a P-type thin film transistor T51 and a fifty-third P-type thin film transistor T53 are turned off, and the sixty-second P-type thin film transistor T62 and the sixty-fourth P-type thin film transistor T64 in the auxiliary main inverter F13 are both turned on,
  • the potential of the two nodes P(N) is raised to a second constant voltage positive potential VDD2 higher than the first constant voltage positive potential VDD1; when the first node Q(N) is high during the inactive period, the main inversion
  • the fifty-second P-type thin film transistor T52 and the fifty-fourth P-type thin film transistor T54 in the device F11 are both turned off, and the fifty-first P-type thin film transistor T51 and the fifty-third P-type thin film transistor T53 are both turned on, the first The
  • the structure of the third inverter F1 is as shown in FIG. 15, and the inverter F1 is a dual inverter including a main inverter F11 and an auxiliary inverter F13.
  • the main inverter F11 includes: a fifty-second P-type thin film transistor T52, the gate of the fifty-second P-type thin film transistor T52 is electrically connected to the first node Q(N), and the source is electrically connected.
  • the first constant voltage positive potential VDD1 the drain is electrically connected to the third node S(N); the fifty-first P-type thin film crystal T51, the gate and the source of the fifty-first P-type thin film transistor T51
  • the current is electrically connected to the constant voltage negative potential VSS1, the drain is electrically connected to the third node S(N); the fifty-fourth P-type thin film transistor T54, the gate of the fifty-fourth P-type thin film transistor T54 is electrically connected Connected to the first node Q(N), the source is electrically connected to the fourth node K(N), the drain is electrically connected to the second node P(N), and the fifty-third P-type thin film transistor T53 is The gate of the 53rd P-type thin film transistor T53 is
  • the auxiliary inverter F13 includes: a 64th P-type thin film transistor T64, the gate of the 64th P-type thin film transistor T64 is electrically connected to the first node Q(N), and the source is electrically Connected to the second constant voltage The positive potential VDD2, the drain is electrically connected to the fourth node K(N); the 63rd P-type thin film transistor T63, the gate of the 63rd P-type thin film transistor T63 is electrically connected to the third node S (N), the source is electrically connected to the constant voltage negative potential VSS1, and the drain is electrically connected. Connected to the fourth node K(N).
  • the structure of the third inverter F1 reduces the effect of the dual inverter while reducing two P-type thin film transistors, simplifying the circuit.
  • the fifty-second P-type thin film transistor T52 and the fifty-fourth P-type thin film transistor T54 in the main inverter F11 are both turned on, the fiftyth A P-type thin film transistor T51 and a 53rd P-type thin film transistor T53 are turned off, a 64th P-type thin film transistor T64 in the auxiliary main inverter F13 is turned on, and a 63rd P-type thin film transistor T63 is turned off,
  • the potential of the two nodes P(N) is raised to a second constant voltage positive potential VDD2 higher than the first constant voltage positive potential VDD1; when the first node Q(N) is high during the inactive period, the main inversion
  • the fifty-second P-type thin film transistor T52 and the fifty-fourth P-type thin film transistor T54 in the device F11 are both turned off, and the fifty-first P-type thin film transistor T51 and the fifty-third P-type thin film transistor T53 are both turned on, the
  • the auxiliary inverter F13 can supply a higher potential to the main inverter F11 during the operation, thereby ensuring that the leakage of the first node Q(N) is reduced and avoiding The effect of the electrical properties of the depletion mode P-type thin film transistor on the output of the inverter.
  • FIG. 6 is a circuit diagram of a second embodiment of the present invention.
  • the second embodiment differs from the first embodiment only in that the fourth P-type thin film transistor T40 and the fortieth in the first pull-down module 400 are used.
  • the gate access signal of a P-type thin film transistor T41 is interchanged, that is, the gate of the fortieth P-type thin film transistor T40 is electrically connected to the M+2 clock signal CK(M+2), and the fourth The gate of the eleven P-type thin film transistor T41 is electrically connected to the level-transmitting signal ST(N+2) of the next two-stage N+2-stage GOA unit or the scan driving signal G of the lower two-stage N+2-th order GOA unit (N+2), correspondingly, in the first-stage connection relationship of the second embodiment of the PMOS gate driving circuit of the present invention, the gate of the eleventh P-type thin film transistor T11 is electrically connected to the enable signal STV, and the reciprocal In the second-stage and last-level connection relationship, the gate of the forty-first P-type thin film transistor T41 is electrically connected to the enable signal STV, and other circuit structures and working processes are the same as in the first embodiment, where No longer.
  • FIG. 7 is a circuit diagram of a third embodiment of the present invention.
  • the third embodiment is different from the first embodiment only in that the fourth P-type thin film transistor T40 in the first pull-down module 400 is diode-shaped.
  • the body connection method is used to reduce leakage current, that is, the gate and the source of the fortieth P-type thin film transistor T40 are electrically connected to the first node Q(N), and the drain level is electrically connected to the forty-first P-type thin film transistor T41.
  • the gate of the forty-first P-type thin film transistor T41 is electrically connected to the M+2 clock signal CK(M+2), and the source is electrically connected to the fortieth P-type thin film transistor T40
  • the drain and the drain are electrically connected to the scan driving signal G(N).
  • the gate of the eleventh P-type thin film transistor T11 is electrically connected to the start signal STV, and other circuit structures and working processes are Same as the first embodiment, I will not repeat them here.
  • FIG. 8 is a circuit diagram of a fourth embodiment of the present invention.
  • the fourth embodiment is different from the first embodiment only in that the forty-first P-type thin film transistor T41 in the first pull-down module 400 is used.
  • the pole body is connected to reduce the leakage current, that is, the gate and the source of the forty-first P-type thin film transistor T41 are electrically connected to the drain of the fortieth P-type thin film transistor T40, and the drain is electrically connected to the scan driving signal.
  • the gate of the fortieth P-type thin film transistor T40 is electrically connected to the M+2th clock signal CK(M+2), and the source is electrically connected to the first node Q(N), the drain level Electrically connected to the gate and the source of the forty-first P-type thin film transistor T41; correspondingly, in the first-stage connection relationship of the third embodiment of the PMOS gate driving circuit of the present invention, the eleventh P-type film
  • the gate of the transistor T11 is electrically connected to the start signal STV.
  • Other circuit configurations and operation processes are the same as those in the first embodiment, and are not described herein again.
  • FIG. 9 is a circuit diagram of a fifth embodiment of the present invention.
  • the fifth embodiment is different from the first embodiment in that the pull-up control module 100 includes three P-type thin film transistors: an eleventh P-type film.
  • the transistor T11, the twelfth P-type thin film transistor T12, and the thirteenth P-type thin film transistor T13; the gate and the source of the eleventh P-type thin film transistor T11 are connected to the upper level N-1th GOA a step signal ST(N-1) of the unit circuit, a drain electrically connected to the source of the twelfth P-type thin film transistor T12, and a drain of the thirteenth P-type thin film transistor T13; the twelfth P
  • the gate of the thin film transistor T12 is connected to the pass signal ST(N-1) of the upper N-1th GOA unit circuit, and the source is electrically connected to the drain of the eleventh P-type thin film transistor T11, and the drain Electrode is electrically connected to the first node Q(
  • the gate and the source of the eleventh P-type thin film transistor T11 and the gate of the twelfth P-type thin film transistor T12 The gate of the fortieth P-type thin film transistor T40 is electrically connected to the enable signal STV.
  • the gate of the fortieth P-type thin film transistor T40 is electrically connected to the start signal STV.
  • Other circuit configurations are the same as those of the first embodiment, and are not described herein again.
  • the working process of the fifth embodiment is slightly different from the working process of the first embodiment, and is characterized in that when the level signal ST(N-1) of the upper N-1th GOA unit circuit is low, the scan driving The signal G(N) is at a high potential, the eleventh P-type thin film transistor T11 is turned on and the twelfth P-type thin film transistor T12 is turned on, and the thirteenth P-type thin film transistor T13 is turned off, and the upper-stage N-1th stage GOA unit circuit is turned on.
  • the level transfer signal ST(N-1) enters the circuit; and when the level transfer signal ST(N-1) of the upper N-1th stage GOA unit circuit becomes high, the scan drive signal G(N) is low At the potential, the eleventh P-type thin film transistor T11 and the twelfth P-type thin film transistor T12 are turned off, the thirteenth P-type thin film transistor T13 is turned on, and the constant-voltage negative potential VSS1 enters the drain of the eleventh P-type thin film transistor T11. versus The source of the twelfth P-type thin film transistor T12 makes the eleventh P-type thin film transistor T11 and the twelfth P-type thin film transistor T12 more effective to prevent leakage. The rest of the working process is the same as that of the first embodiment, and details are not described herein again.
  • the gate of the eleventh P-type thin film transistor T11 and the source and the gate of the twelfth P-type thin film transistor T12 are electrically connected to the enable signal STV
  • the last In the second-level and last-level connection relationship, the gate of the forty-first P-type thin film transistor T41 is electrically connected to the start signal STV, and other circuit structures and working processes are the same as those in the fifth embodiment. Let me repeat.
  • FIG. 11 is a circuit diagram of a seventh embodiment of the present invention.
  • the seventh embodiment is different from the fifth embodiment in that the twentieth P-type thin film transistor T40 in the first pull-down module 400 is diode-shaped.
  • the body connection method is used to reduce leakage current, that is, the gate and the source of the fortieth P-type thin film transistor T40 are electrically connected to the first node Q(N), and the drain level is electrically connected to the forty-first P-type thin film transistor T41.
  • the gate of the forty-first P-type thin film transistor T41 is electrically connected to the M+2 clock signal CK(M+2), and the source is electrically connected to the fortieth P-type thin film transistor T40
  • the drain and the drain are electrically connected to the scan driving signal G(N).
  • the gate and the source of the eleventh P-type thin film transistor T11 and the gate of the twelfth P-type thin film transistor T12 It is electrically connected to the start signal STV.
  • Other circuit configurations and working processes are the same as those in the fifth embodiment, and are not described herein again.
  • FIG. 12 it is a circuit diagram of an eighth embodiment of the present invention.
  • the eighth embodiment is different from the fifth embodiment in that the fourth eleventh P-type thin film transistor T41 in the first pull-down module 400 is used.
  • the pole body is connected to reduce the leakage current, that is, the gate and the source of the forty-first P-type thin film transistor T41 are electrically connected to the drain of the fortieth P-type thin film transistor T40, and the drain is electrically connected to the scan driving signal.
  • the gate of the fortieth P-type thin film transistor T40 is electrically connected to the M+2th clock signal CK(M+2), and the source is electrically connected to the first node Q(N), the drain level Electrically connected to the gate and the source of the forty-first P-type thin film transistor T41; correspondingly, in the first-stage connection relationship of the eighth embodiment of the PMOS gate driving circuit of the present invention, the eleventh P-type film
  • the gate and the source of the transistor T11 and the gate of the twelfth P-type thin film transistor T12 are electrically connected to the enable signal STV.
  • Other circuit configurations and operation processes are the same as those of the fifth embodiment, and are not described herein again.

Abstract

一种PMOS栅极驱动电路，包括级联的多个GOA单元电路，每一级GOA单元电路均包括：上拉控制模块（100）、上拉模块（200）、下传模块（300）、第一下拉模块（400）、自举电容（500）、及下拉维持模块（600）；所述上拉控制模块（100）接入一恒压负电位（VSS1），能够降低PMOS器件漏电对第一节点（Q(N) ）的影响；所述下拉维持模块（600）包括由P型薄膜晶体管构成的双重反相器（F1），并采用特殊的防漏电设计，能够减少第一节点（Q(N) ）的漏电，避免耗尽型P型薄膜晶体管的电性对反相器输出的影响，提高栅极驱动电路的稳定性，并提高面板的集成度，进一步减小液晶显示面板的边框宽度，适用于对边框宽度有较高要求的小尺寸面板。

Description

PMOS栅极驱动电路 技术领域
本发明涉及液晶显示器驱动领域，尤其涉及一种PMOS栅极驱动电路。
背景技术
液晶显示器(Liquid Crystal Display，LCD)具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。如：液晶电视、移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本电脑屏幕等，在平板显示领域中占主导地位。
现有市场上的液晶显示器大部分为背光型液晶显示器，其包括液晶显示面板及背光模组(backlight module)。液晶显示面板的工作原理是在薄膜晶体管阵列基板(Thin Film Transistor Array Substrate，TFT Array Substrate)与彩色滤光片基板(Color Filter，CF)之间灌入液晶分子，并在两片基板上施加驱动电压来控制液晶分子的旋转方向，以将背光模组的光线折射出来产生画面。
主动式液晶显示器中，每个像素电性连接一个薄膜晶体管(TFT)，薄膜晶体管的栅极(Gate)连接至水平扫描线，漏极(Drain)连接至垂直方向的数据线，源极(Source)则连接至像素电极。在水平扫描线上施加足够的电压，会使得电性连接至该条水平扫描线上的所有TFT打开，从而数据线上的信号电压能够写入像素，控制不同液晶的透光度进而达到控制色彩与亮度的效果。目前主动式液晶显示面板水平扫描线的驱动主要由外接的集成电路板(Integrated Circuit，IC)来完成，外接的IC可以控制各级水平扫描线的逐级充电和放电。而GOA技术(Gate Driver on Array)即阵列基板行驱动技术，是可以运用液晶显示面板的阵列制程将栅极驱动电路制作在TFT阵列基板上，实现对栅极逐行扫描的驱动方式。GOA技术能减少外接IC的焊接(bonding)工序，有机会提升产能并降低产品成本，而且可以使液晶显示面板更适合制作窄边框或无边框的显示产品。
通常，低温多晶硅(LTPS)半导体薄膜晶体管有两种类型的器件：一种是以电子导电为主的N型器件(NMOS)，一种是以空穴导电为主的P型器件(PMOS)。一般CMOS是指将NMOS和PMOS一起使用的互补型器件。在一些特殊的应用场合和制程条件限制的情况下，液晶显示器需要选择PMOS单型器件作为栅极驱动电路的薄膜晶体管。因此，有必要对PMOS 单型器件设计集成的栅极驱动电路，以改善栅极驱动电路的性能，提高液晶显示面板的集成度，进一步减小液晶显示面板的边框宽度。
发明内容
本发明的目的在于提供一种PMOS栅极驱动电路，能够减少漏电，提高栅极驱动电路的稳定性，并提高面板的集成度，进一步减小液晶显示面板的边框宽度，尤其适用于对边框宽度有较高要求的小尺寸面板。
为实现上述目的，本发明提供一种PMOS栅极驱动电路，包括级联的多个GOA单元电路，每一级GOA单元电路均包括：上拉控制模块、上拉模块、下传模块、第一下拉模块、自举电容、及下拉维持模块；
设N为正整数，在第N级GOA单元电路中：
所述上拉控制模块电性连接于第一节点、及下拉维持模块；所述上拉控制模块至少包括一个P型薄膜晶体管，至少接入上一级第N-1级GOA单元电路的级传信号、及恒压负电位；
所述上拉模块包括：第二十二P型薄膜晶体管，所述第二十二P型薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第M条时钟信号，漏极输出扫描驱动信号；
所述下传模块包括：第二十一P型薄膜晶体管，所述第二十一P型薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第M条时钟信号，漏极输出级传信号；
所述第一下拉模块电性连接于第一节点与扫描驱动信号，包括相互串联的第四十P型薄膜晶体管与第四十一P型薄膜晶体管，用于在非作用期间将第一节点的电位拉到扫描驱动信号的电位；
所述自举电容的一端电性连接于第一节点，另一端电性连接于扫描驱动信号；
所述下拉维持模块包括：一由多个P型薄膜晶体管构成的反相器，所述反相器的输入端电性连接于第一节点，输出端电性连接于第二节点；第三十二P型薄膜晶体管，所述第三十二P型薄膜晶体管的栅极电性连接于第二节点，源极电性连接于第四十一P型薄膜晶体管的漏极，漏极电性连接于第一恒压正电位；第四十二P型薄膜晶体管，所述第四十二P型薄膜晶体管的栅极电性连接于第二节点，漏极电性连接于第一节点，源极电性连接于第八十二P型薄膜晶体管的漏极；第八十二P型薄膜晶体管，所述第八十二P型薄膜晶体管的栅极电性连接于第一节点，源极电性连接于恒压负电位，漏极电性连接于第八十一P型薄膜晶体管的漏极；第八十一P 型薄膜晶体管，所述第八十一P型薄膜晶体管的栅极电性连接于第二节点，源极电性连接于第二恒压正电位，漏极电性连接于第八十二P型薄膜晶体管的漏极；
所述第一恒压正电位低于第二恒压正电位。
所述上拉控制模块包括一个P型薄膜晶体管：第十一P型薄膜晶体管，所述第十一P型薄膜晶体管的栅极接入上一级第N-1级GOA单元电路的级传信号，源极接入恒压负电位，漏极电性连接于第一节点。
所述上拉控制模块包括三个P型薄膜晶体管：第十一P型薄膜晶体管、第十二P型薄膜晶体管、及第十三P型薄膜晶体管；所述第十一P型薄膜晶体管的栅极与源极均接入上一级第N-1级GOA单元电路的级传信号，漏极电性连接于第十二P型薄膜晶体管的源极、及第十三P型薄膜晶体管的漏极；所述第十二P型薄膜晶体管的栅极接入上一级第N-1级GOA单元电路的级传信号，源极电性连接于第十一P型薄膜晶体管的漏极，漏极电性连接于第一节点；所述第十三P型薄膜晶体管的栅极接入扫描驱动信号，源极接入恒压负电位，漏极电性连接于第十一P型薄膜晶体管的漏极。
所述第四十P型薄膜晶体管的栅极电性连接于下两级第N+2级GOA单元的级传信号或下两级第N+2级GOA单元的扫描驱动信号，源极电性连接于第一节点，漏级电性连接于第四十一P型薄膜晶体管的源极；所述第四十一P型薄膜晶体管的栅极电性连接于第M+2条时钟信号，源极电性连接于第四十P型薄膜晶体管的漏极，漏极电性连接于扫描驱动信号。
所述第四十P型薄膜晶体管的栅极电性连接于第M+2条时钟信号，源极电性连接于第一节点，漏级电性连接于第四十一P型薄膜晶体管的源极；所述第四十一P型薄膜晶体管的栅极电性连接于下两级第N+2级GOA单元的级传信号或下两级第N+2级GOA单元的扫描驱动信号，源极电性连接于第四十P型薄膜晶体管的漏极，漏极电性连接于扫描驱动信号。
所述第四十P型薄膜晶体管的栅极与源极均电性连接于第一节点，漏级电性连接于第四十一P型薄膜晶体管的源极；所述第四十一P型薄膜晶体管的栅极电性连接于第M+2条时钟信号，源极电性连接于第四十P型薄膜晶体管的漏极，漏极电性连接于扫描驱动信号。
所述第四十P型薄膜晶体管的栅极电性连接于第M+2条时钟信号，源极电性连接于第一节点，漏级电性连接于第四十一P型薄膜晶体管的栅极与源极；所述第四十一P型薄膜晶体管的栅极与源极均电性连接于第四十P型薄膜晶体管的漏极，漏极电性连接于扫描驱动信号。
所述反相器包括第五十二P型薄膜晶体管，所述第五十二P型薄膜晶 体管的栅极电性连接于第一节点，源极电性连接于第二恒压正电位，漏极电性连接于第三节点；第五十一P型薄膜晶体，所述第五十一P型薄膜晶体管的栅极及源极均电性连接于恒压负电位，漏极电性连接于第三节点；第五十四P型薄膜晶体管，所述第五十四P型薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第二恒压正电位，漏极电性连接于第二节点；第五十三P型薄膜晶体管，所述第五十三P型薄膜晶体管的栅极电性连接于第三节点，源极电性连接于电性连接于恒压负电位，漏极电性连接于第二节点。
所述反相器为双重反相器，包括主反相器、及辅助反相器；
所述主反相器包括：第五十二P型薄膜晶体管，所述第五十二P型薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第一恒压正电位，漏极电性连接于第三节点；第五十一P型薄膜晶体，所述第五十一P型薄膜晶体管的栅极及源极均电性连接于恒压负电位，漏极电性连接于第三节点；第五十四P型薄膜晶体管，所述第五十四P型薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第四节点，漏极电性连接于第二节点；第五十三P型薄膜晶体管，所述第五十三P型薄膜晶体管的栅极电性连接于第三节点，源极电性连接于恒压负电位，漏极电性连接于第二节点；
所述辅助反相器包括：第六十二P型薄膜晶体管，所述第六十二P型薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第二恒压正电位，漏极电性连接于第五节点；第六十一P型薄膜晶体，所述第六十一P型薄膜晶体管的栅极及源极均电性连接于恒压负电位，漏极电性连接于第五节点；第六十四P型薄膜晶体管，所述第六十四P型薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第二恒压正电位，漏极电性连接于第四节点；第六十三P型薄膜晶体管，所述第六十三P型薄膜晶体管的栅极电性连接于第五节点，源极电性连接于恒压负电位，漏极电性连接于第四节点。
所述反相器为双重反相器，包括主反相器、及辅助反相器；
所述主反相器包括：第五十二P型薄膜晶体管，所述第五十二P型薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第一恒压正电位，漏极电性连接于第三节点；第五十一P型薄膜晶体，所述第五十一P型薄膜晶体管的栅极及源极均电性连接于恒压负电位，漏极电性连接于第三节点；第五十四P型薄膜晶体管，所述第五十四P型薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第四节点，漏极电性连接于第二节点；第五十三P型薄膜晶体管，所述第五十三P型薄膜晶体管的栅极电性连接 于第三节点，源极电性连接于恒压负电位，漏极电性连接于第二节点；
所述辅助反相器包括：第六十四P型薄膜晶体管，所述第六十四P型薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第二恒压正电位，漏极电性连接于第四节点；第六十三P型薄膜晶体管，所述第六十三P型薄膜晶体管的栅极电性连接于第三节点，源极电性连接于恒压负电位，漏极电性连接于第四节点。
本发明还提供一种PMOS栅极驱动电路，包括级联的多个GOA单元电路，每一级GOA单元电路均包括：上拉控制模块、上拉模块、下传模块、第一下拉模块、自举电容、及下拉维持模块；
设N为正整数，在第N级GOA单元电路中：
所述上拉控制模块电性连接于第一节点、及下拉维持模块；所述上拉控制模块至少包括一个P型薄膜晶体管，至少接入上一级第N-1级GOA单元电路的级传信号、及恒压负电位；
所述上拉模块包括：第二十二P型薄膜晶体管，所述第二十二P型薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第M条时钟信号，漏极输出扫描驱动信号；
所述下传模块包括：第二十一P型薄膜晶体管，所述第二十一P型薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第M条时钟信号，漏极输出级传信号；
所述第一下拉模块电性连接于第一节点与扫描驱动信号，包括相互串联的第四十P型薄膜晶体管与第四十一P型薄膜晶体管，用于在非作用期间将第一节点的电位拉到扫描驱动信号的电位；
所述自举电容的一端电性连接于第一节点，另一端电性连接于扫描驱动信号；
所述下拉维持模块包括：一由多个P型薄膜晶体管构成的反相器，所述反相器的输入端电性连接于第一节点，输出端电性连接于第二节点；第三十二P型薄膜晶体管，所述第三十二P型薄膜晶体管的栅极电性连接于第二节点，源极电性连接于第四十一P型薄膜晶体管的漏极，漏极电性连接于第一恒压正电位；第四十二P型薄膜晶体管，所述第四十二P型薄膜晶体管的栅极电性连接于第二节点，漏极电性连接于第一节点，源极电性连接于第八十二P型薄膜晶体管的漏极；第八十二P型薄膜晶体管，所述第八十二P型薄膜晶体管的栅极电性连接于第一节点，源极电性连接于恒压负电位，漏极电性连接于第八十一P型薄膜晶体管的漏极；第八十一P型薄膜晶体管，所述第八十一P型薄膜晶体管的栅极电性连接于第二节点， 源极电性连接于第二恒压正电位，漏极电性连接于第八十二P型薄膜晶体管的漏极；
所述第一恒压正电位低于第二恒压正电位；
其中，所述上拉控制模块包括一个P型薄膜晶体管：第十一P型薄膜晶体管，所述第十一P型薄膜晶体管的栅极接入上一级第N-1级GOA单元电路的级传信号，源极接入恒压负电位，漏极电性连接于第一节点；
其中，所述第四十P型薄膜晶体管的栅极电性连接于下两级第N+2级GOA单元的级传信号或下两级第N+2级GOA单元的扫描驱动信号，源极电性连接于第一节点，漏级电性连接于第四十一P型薄膜晶体管的源极；所述第四十一P型薄膜晶体管的栅极电性连接于第M+2条时钟信号，源极电性连接于第四十P型薄膜晶体管的漏极，漏极电性连接于扫描驱动信号。
本发明的有益效果：本发明提供的一种PMOS栅极驱动电路，其上拉控制模块接入一恒压负电位，能够降低PMOS器件漏电对第一节点的影响；其下拉维持模块设置由P型薄膜晶体管构成的双重反相器，并采用特殊的防漏电设计，能够减少第一节点的漏电，避免耗尽型P型薄膜晶体管的电性对反相器输出的影响，提高栅极驱动电路的稳定性，并提高面板的集成度，进一步减小液晶显示面板的边框宽度，尤其适用于对边框宽度有较高要求的小尺寸面板。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为本发明的PMOS栅极驱动电路的第一实施例的电路图；
图2为本发明的PMOS栅极驱动电路第一实施例的第一级GOA单元电路的电路图；
图3为本发明的PMOS栅极驱动电路第一实施例的倒数第二级GOA单元电路的电路图；
图4为本发明的PMOS栅极驱动电路第一实施例的最后一级GOA单元电路的电路图；
图5为本发明的PMOS栅极驱动电路的时序图；
图6为本发明的PMOS栅极驱动电路的第二实施例的电路图；
图7为本发明的PMOS栅极驱动电路的第三实施例的电路图；
图8为本发明的PMOS栅极驱动电路的第四实施例的电路图；
图9为本发明的PMOS栅极驱动电路的第五实施例的电路图；
图10为本发明的PMOS栅极驱动电路的第六实施例的电路图；
图11为本发明的PMOS栅极驱动电路的第七实施例的电路图；
图12为本发明的PMOS栅极驱动电路的第八实施例的电路图；
图13为本发明的PMOS栅极驱动电路中反相器的第一种电路结构示意图；
图14为本发明的PMOS栅极驱动电路中反相器的第二种电路结构示意图；
图15为本发明的PMOS栅极驱动电路中反相器的第三种电路结构示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
本发明提供了一种PMOS栅极驱动电路。图1所示为本发明第一实施例的电路图，该PMOS栅极驱动电路包括级联的多个GOA单元电路，每一级GOA单元电路均包括：上拉控制模块100、上拉模块200、下传模块300、第一下拉模块400、自举电容500、及下拉维持模块600。
设N为正整数，在第N级GOA单元电路中：
所述上拉控制模块100包括一个P型薄膜晶体管：第十一P型薄膜晶体管T11，所述第十一P型薄膜晶体管T11的栅极接入上一级第N-1级GOA单元电路的级传信号ST(N-1)，源极接入恒压负电位VSS1，漏极电性连接于第一节点Q(N)。
所述上拉模块200包括：第二十二P型薄膜晶体管T22，所述第二十二P型薄膜晶体管T22的栅极电性连接于第一节点Q(N)，源极电性连接于第M条时钟信号CK(M)，漏极输出扫描驱动信号G(N)。
所述下传模块300包括：第二十一P型薄膜晶体管T21，所述第二十一P型薄膜晶体管T21的栅极电性连接于第一节点Q(N)，源极电性连接于第M条时钟信号CK(M)，漏极输出级传信号ST(N)。
所述第一下拉模块400包括：相互串联的第四十P型薄膜晶体管T40与第四十一P型薄膜晶体管T41；所述第四十P型薄膜晶体管T40的栅极 电性连接于下两级第N+2级GOA单元的级传信号ST(N+2)或下两级第N+2级GOA单元的扫描驱动信号G(N+2)，源极电性连接于第一节点Q(N)，漏级电性连接于第四十一P型薄膜晶体管T41的源极；所述第四十一P型薄膜晶体管T41的栅极电性连接于第M+2条时钟信号CK(M+2)，源极电性连接于第四十P型薄膜晶体管T40的漏极，漏极电性连接于扫描驱动信号G(N)。
所述自举电容500的一端电性连接于第一节点Q(N)，另一端电性连接于扫描驱动信号G(N)。
所述下拉维持模块600包括：一由多个P型薄膜晶体管构成的反相器F1，所述反相器F1的输入端电性连接于第一节点Q(N)，输出端电性连接于第二节点P(N)；第三十二P型薄膜晶体管T32，所述第三十二P型薄膜晶体管T32的栅极电性连接于第二节点P(N)，源极电性连接于第四十一P型薄膜晶体管T41的漏极，漏极电性连接于第一恒压正电位VDD1；第四十二P型薄膜晶体管T42所述第四十二P型薄膜晶体管T42的栅极电性连接于第二节点P(N)，漏极电性连接于第一节点Q(N)，源极电性连接于第八十二P型薄膜晶体管T82的漏极；第八十二P型薄膜晶体管T82，所述第八十二P型薄膜晶体管T82的栅极电性连接于第一节点Q(N)，源极电性连接于恒压负电位VSS1，漏极电性连接于第八十一P型薄膜晶体管T81的漏极；第八十一P型薄膜晶体管T81，所述第八十一P型薄膜晶体管T81的栅极电性连接于第二节点P(N)，源极电性连接于第二恒压正电位VDD2，漏极电性连接于第八十二P型薄膜晶体管T82的漏极。
特别的，请参阅图2、图3、及图4，如图2所示，在本发明PMOS栅极驱动电路第一实施例的第一级连接关系中，所述第十一P型薄膜晶体管T11的栅极电性连接于启动信号STV；如图3、图4所示，在本发明PMOS栅极驱动电路第一实施例的倒数第二级、及最后一级连接关系中，所述第四十P型薄膜晶体管T40的栅极电性连接于启动信号STV。
图5所示为本发明PMOS栅极驱动电路的时序图，其中，STV表示电路的启动信号；CK(1)、CK(2)、CK(3)、及CK(4)为时钟信号CK(M)所包含的四组时钟信号，均为高频时钟信号，当所述时钟信号CK(M)为第三时钟信号CK(3)时，所述第M+2组时钟信号CK(M+2)为第一时钟信号CK(1)，当所述时钟信号CK(M)为第四时钟信号CK(4)时，所述第M+2组时钟信号CK(M+2)为第二时钟信号CK(2)；Q(1)、Q(2)分别为第一级、第二级GOA单元电路中第一节点Q(N)的波形；G(1)、G(2)分别为第一级、第二级GOA单元电路输出的扫描驱动信号G(N)的波形；VSS1为恒压负电位；VDD1、 VDD分别为第一、第二恒压正电位，且第一恒压正电位VDD1低于于第二恒压正电位VDD2。
具体地，结合图1、图5，该PMOS栅极驱动电路的第一实施例的工作过程为：
当上一级第N-1级GOA单元电路的级传信号ST(N-1)为低电位时，第十一P型薄膜晶体管T11导通，恒压负电位VSS1进入电路，对自举电容500充电，使第一节点Q(N)得到一负电位，随后上一级第N-1级GOA单元电路的级传信号ST(N-1)转变为高电位，第一节点Q(N)通过自举电容500维持负电位，同时第二十一P型薄膜晶体管T21与第二十二P型薄膜晶体管T22受第一节点Q(N)的控制而导通。
随后，第M组时钟信号CK(M)为低电位，并通过第二十二P型薄膜晶体管T22继续向自举电容500充电，使得第一节点Q(N)达到一更低的电位，与此同时，第二十二P型薄膜晶体管T22的漏极输出扫描驱动信号G(N)，第二十一P型薄膜晶体管T21的漏极输出级传信号ST(N)，且扫描驱动信号G(N)与级传信号ST(N)均为低电位。对于PMOS栅极驱动电路，一般将扫描驱动信号G(N)为低电位的时隙称为作用期间，在作用期间，由于第一节点Q(N)为低电位，经反相器F1反相后得到第二节点P(N)为高电位，下拉维持模块600中的第八十二P型薄膜晶体管T82导通，而第八十一P型薄膜晶体管T81、第四十二P型薄膜晶体管T42、及第三十二P型薄膜晶体管T32均关闭，第四十二P型薄膜晶体管T42的源极电位被拉低到恒压负电位VSS1，能够减少第一节点Q(N)经过第四十二P型薄膜晶体管T42的漏电，另外采用所述恒压负电位VSS1来进行第十一薄膜晶体管T11的信号传递，也可以减少第一节点Q(N)的漏电。
接着，第M组时钟信号CK(M)变为高电位，相应由第二十二P型薄膜晶体管T22的漏极输出的扫描驱动信号G(N)、及由第二十一P型薄膜晶体管T21的漏极输出的级传信号ST(N)也转变为高电位，电路进入非作用期间，当第M+2条时钟信号CK(M+2)、及下两级第N+2级GOA单元的级传信号ST(N+2)或下两级第N+2级GOA单元的扫描驱动信号G(N+2)为低电位到来时，第四十P型薄膜晶体管T40及第四十一P型薄膜晶体管T41均导通，第一节点Q(N)的电位被拉到扫描驱动信号G(N)的高电位，第二十一P型薄膜晶体管T21与第二十二P型薄膜晶体管T22均关闭；在非作用期间，由于第一节点Q(N)为高电位，经反相器F1反相后得到第二节点P(N)为低电位，下拉维持模块600中的第八十二P型薄膜晶体管T82关闭，而第八十一P型薄膜晶体管T81、第四十二P型薄膜晶体管T42、及第三十二 P型薄膜晶体管T32均导通，第一节点Q(N)的电位被第四十二P型薄膜晶体管T42及第八十一P型薄膜晶体管T81抬升并保持在第二恒压正电位VDD2。
进一步的，所述反相器F1可为分别如图13、图14、图15所示的三种结构：
第一种反相器F1的结构如图13所示，包括第五十二P型薄膜晶体管T52，所述第五十二P型薄膜晶体管T52的栅极电性连接于第一节点Q(N)，源极电性连接于第二恒压正电位VDD2，漏极电性连接于第三节点S(N)；第五十一P型薄膜晶体T51，所述第五十一P型薄膜晶体管T51的栅极及源极均电性连接于恒压负电位VSS1，漏极电性连接于第三节点S(N)；第五十四P型薄膜晶体管T54，所述第五十四P型薄膜晶体管T54的栅极电性连接于第一节点Q(N)，源极电性连接于第二恒压正电位VDD2，漏极电性连接于第二节点P(N)；第五十三P型薄膜晶体管T53，所述第五十三P型薄膜晶体管T53的栅极电性连接于第三节点S(N)，源极电性连接于电性连接于恒压负电位VSS1，漏极电性连接于第二节点P(N)。
当作用期间第一节点Q(N)为低电位时，所述第五十二P型薄膜晶体管T52与第五十四P型薄膜晶体管T54均导通，第五十一P型薄膜晶体管T51与第五十三P型薄膜晶体管T53关闭，第二节点P(N)的电位为第二恒压正电位VDD2；当非作用期间第一节点Q(N)为高电位时，所述第五十二P型薄膜晶体管T52与第五十四P型薄膜晶体管T54均关闭，第五十一P型薄膜晶体管T51与第五十三P型薄膜晶体管T53均导通，第二节点P(N)的电位为恒压负电位VSS1。
第二种反相器F1的结构如图14所示，所述反相器F1为双重反相器，包括主反相器F11、及辅助反相器F13。
所述主反相器F11包括：第五十二P型薄膜晶体管T52，所述第五十二P型薄膜晶体管T52的栅极电性连接于第一节点Q(N)，源极电性连接于第一恒压正电位VDD1，漏极电性连接于第三节点S(N)；第五十一P型薄膜晶体T51，所述第五十一P型薄膜晶体管T51的栅极及源极均电性连接于恒压负电位VSS1，漏极电性连接于第三节点S(N)；第五十四P型薄膜晶体管T54，所述第五十四P型薄膜晶体管T54的栅极电性连接于第一节点Q(N)，源极电性连接于第四节点K(N)，漏极电性连接于第二节点P(N)；第五十三P型薄膜晶体管T53，所述第五十三P型薄膜晶体管T53的栅极电性连接于第三节点S(N)，源极电性连接于恒压负电位VSS1，漏极电性连接于第二节点P(N)；所述辅助反相器F13包括：第六十二P型薄膜晶体管 T62，所述第六十二P型薄膜晶体管T62的栅极电性连接于第一节点Q(N)，源极电性连接于第二恒压正电位VDD2，漏极电性连接于第五节点T(N)；第六十一P型薄膜晶体T61，所述第六十一P型薄膜晶体管T61的栅极及源极均电性连接于恒压负电位VSS1，漏极电性连接于第五节点T(N)；第六十四P型薄膜晶体管T64，所述第六十四P型薄膜晶体管T64的栅极电性连接于第一节点Q(N)，源极电性连接于第二恒压正电位VDD2，漏极电性连接于第四节点K(N)；第六十三P型薄膜晶体管T63，所述第六十三P型薄膜晶体管T63的栅极电性连接于第五节点T(N)，源极电性连接于恒压负电位VSS1，漏极电性连接于第四节点K(N)。
当作用期间第一节点Q(N)为低电位时，所述主反相器F11中的第五十二P型薄膜晶体管T52与第五十四P型薄膜晶体管T54均导通，第五十一P型薄膜晶体管T51与第五十三P型薄膜晶体管T53关闭，辅助主反相器F13中的第六十二P型薄膜晶体管T62与第六十四P型薄膜晶体管T64均导通，第二节点P(N)的电位被抬升为高于第一恒压正电位VDD1的第二恒压正电位VDD2；当非作用期间第一节点Q(N)为高电位时，所述主反相器F11中的第五十二P型薄膜晶体管T52与第五十四P型薄膜晶体管T54均关闭，第五十一P型薄膜晶体管T51与第五十三P型薄膜晶体管T53均导通，第二节点P(N)的电位为恒压负电位VSS1。
第三种反相器F1的结构如图15所示，所述反相器F1为双重反相器，包括主反相器F11、及辅助反相器F13。
所述主反相器F11包括：第五十二P型薄膜晶体管T52，所述第五十二P型薄膜晶体管T52的栅极电性连接于第一节点Q(N)，源极电性连接于第一恒压正电位VDD1，漏极电性连接于第三节点S(N)；第五十一P型薄膜晶体T51，所述第五十一P型薄膜晶体管T51的栅极及源极均电性连接于恒压负电位VSS1，漏极电性连接于第三节点S(N)；第五十四P型薄膜晶体管T54，所述第五十四P型薄膜晶体管T54的栅极电性连接于第一节点Q(N)，源极电性连接于第四节点K(N)，漏极电性连接于第二节点P(N)；第五十三P型薄膜晶体管T53，所述第五十三P型薄膜晶体管T53的栅极电性连接于第三节点S(N)，源极电性连接于恒压负电位VSS1，漏极电性连接于第二节点P(N)；所述辅助反相器F13包括：第六十四P型薄膜晶体管T64，所述第六十四P型薄膜晶体管T64的栅极电性连接于第一节点Q(N)，源极电性连接于第二恒压正电位VDD2，漏极电性连接于第四节点K(N)；第六十三P型薄膜晶体管T63，所述第六十三P型薄膜晶体管T63的栅极电性连接于第三节点S(N)，源极电性连接于恒压负电位VSS1，漏极电性连 接于第四节点K(N)。该第三种反相器F1的结构在达到双重反相器效果的同时，减少了两个P型薄膜晶体管，简化了电路。
当作用期间第一节点Q(N)为低电位时，所述主反相器F11中的第五十二P型薄膜晶体管T52与第五十四P型薄膜晶体管T54均导通，第五十一P型薄膜晶体管T51与第五十三P型薄膜晶体管T53关闭，辅助主反相器F13中的第六十四P型薄膜晶体管T64导通，第六十三P型薄膜晶体管T63关闭，第二节点P(N)的电位被抬升为高于第一恒压正电位VDD1的第二恒压正电位VDD2；当非作用期间第一节点Q(N)为高电位时，所述主反相器F11中的第五十二P型薄膜晶体管T52与第五十四P型薄膜晶体管T54均关闭，第五十一P型薄膜晶体管T51与第五十三P型薄膜晶体管T53均导通，第二节点P(N)的电位为恒压负电位VSS1。
上述如图14、图15所示的双重反相器，辅助反相器F13能够在作用期间给主反相器F11提供一个更高的电位，确保减少第一节点Q(N)的漏电，避免耗尽型P型薄膜晶体管的电性对反相器输出的影响。
请参阅图6，为本发明第二实施例的电路图，该第二实施例与第一实施例的区别仅在于，将第一下拉模块400中第四十P型薄膜晶体管T40与第四十一P型薄膜晶体管T41的栅极接入信号进行互换，即将第四十P型薄膜晶体管T40的栅极电性连接于第M+2条时钟信号CK(M+2)，而将第四十一P型薄膜晶体管T41的栅极电性连接于下两级第N+2级GOA单元的级传信号ST(N+2)或下两级第N+2级GOA单元的扫描驱动信号G(N+2)，相应的，本发明PMOS栅极驱动电路第二实施例的第一级连接关系中，所述第十一P型薄膜晶体管T11的栅极电性连接于启动信号STV，倒数第二级、及最后一级连接关系中，所述第四十一P型薄膜晶体管T41的栅极电性连接于启动信号STV，其它电路结构及工作过程均与第一实施例相同，此处不再赘述。
请参阅图7，为本发明第三实施例的电路图，该第三实施例与第一实施例的区别仅在于，将第一下拉模块400中的第四十P型薄膜晶体管T40采用二极体接法来减少漏电，即将第四十P型薄膜晶体管T40的栅极与源极均电性连接于第一节点Q(N)，漏级电性连接于第四十一P型薄膜晶体管T41的源极；所述第四十一P型薄膜晶体管T41的栅极电性连接于第M+2条时钟信号CK(M+2)，源极电性连接于第四十P型薄膜晶体管T40的漏极，漏极电性连接于扫描驱动信号G(N)。相应的，本发明PMOS栅极驱动电路第三实施例的第一级连接关系中，所述第十一P型薄膜晶体管T11的栅极电性连接于启动信号STV，其它电路结构及工作过程均与第一实施例相同， 此处不再赘述。
请参阅图8，为本发明第四实施例的电路图，该第四实施例与第一实施例的区别仅在于，将第一下拉模块400中的第四十一P型薄膜晶体管T41采用二极体接法来减少漏电，即将第四十一P型薄膜晶体管T41的栅极与源极均电性连接于第四十P型薄膜晶体管T40的漏极，漏极电性连接于扫描驱动信号G(N)；第四十P型薄膜晶体管T40的栅极电性连接于第M+2条时钟信号CK(M+2)，源极电性连接于第一节点Q(N)，漏级电性连接于第四十一P型薄膜晶体管T41的栅极与源极；相应的，本发明PMOS栅极驱动电路第三实施例的第一级连接关系中，所述第十一P型薄膜晶体管T11的栅极电性连接于启动信号STV，其它电路结构及工作过程均与第一实施例相同，此处不再赘述。
请参阅图9，为本发明第五实施例的电路图，该第五实施例与第一实施例的区别在于，所述上拉控制模块100包括三个P型薄膜晶体管：第十一P型薄膜晶体管T11、第十二P型薄膜晶体管T12、及第十三P型薄膜晶体管T13；所述第十一P型薄膜晶体管T11的栅极与源极均接入上一级第N-1级GOA单元电路的级传信号ST(N-1)，漏极电性连接于第十二P型薄膜晶体管T12的源极、及第十三P型薄膜晶体管T13的漏极；所述第十二P型薄膜晶体管T12的栅极接入上一级第N-1级GOA单元电路的级传信号ST(N-1)，源极电性连接于第十一P型薄膜晶体管T11的漏极，漏极电性连接于第一节点Q(N)；所述第十三P型薄膜晶体管T13的栅极接入扫描驱动信号G(N)，源极接入恒压负电位VSS1，漏极电性连接于第十一P型薄膜晶体管T11的漏极。相应的，本发明PMOS栅极驱动电路第五实施例的第一级连接关系中，所述第十一P型薄膜晶体管T11的栅极与源极、第十二P型薄膜晶体管T12的栅极电性连接于启动信号STV；倒数第二级、及最后一级连接关系中，所述第四十P型薄膜晶体管T40的栅极电性连接于启动信号STV。其它电路结构与第一实施例相同，此处不再赘述。
该第五实施例的工作过程与第一实施例的工作过程略有差别，表现在当上一级第N-1级GOA单元电路的级传信号ST(N-1)为低电位，扫描驱动信号G(N)为高电位，第十一P型薄膜晶体管T11与第十二P型薄膜晶体管T12导通，第十三P型薄膜晶体管T13关闭，上一级第N-1级GOA单元电路的级传信号ST(N-1)进入电路；而当上一级第N-1级GOA单元电路的级传信号ST(N-1)变为高电位，扫描驱动信号G(N)为低电位时，第十一P型薄膜晶体管T11与第十二P型薄膜晶体管T12关闭，第十三P型薄膜晶体管T13导通，恒压负电位VSS1进入第十一P型薄膜晶体管T11的漏极与 第十二P型薄膜晶体管T12的源极，使得第十一P型薄膜晶体管T11与第十二P型薄膜晶体管T12关闭的更加有效，防止漏电。其余工作过程与第一实施例相同，此处不再赘述。
请参阅图10，为本发明第六实施例的电路图，该第六实施例与第五实施例的区别在于，将第一下拉模块400中第四十P型薄膜晶体管T40与第四十一P型薄膜晶体管T41的栅极接入信号进行互换。即将第四十P型薄膜晶体管T40的栅极电性连接于第M+2条时钟信号CK(M+2)，而将第四十一P型薄膜晶体管T41的栅极电性连接于下两级第N+2级GOA单元的级传信号ST(N+2)或下两级第N+2级GOA单元的扫描驱动信号G(N+2)，相应的，本发明PMOS栅极驱动电路第六实施例的第一级连接关系中，所述第十一P型薄膜晶体管T11的栅极与源极、第十二P型薄膜晶体管T12的栅极电性连接于启动信号STV，倒数第二级、及最后一级连接关系中，所述第四十一P型薄膜晶体管T41的栅极电性连接于启动信号STV，其它电路结构及工作过程均与第五实施例相同，此处不再赘述。
请参阅图11，为本发明第七实施例的电路图，该第七实施例与第五实施例的区别仅在于，将第一下拉模块400中的第四十P型薄膜晶体管T40采用二极体接法来减少漏电，即将第四十P型薄膜晶体管T40的栅极与源极均电性连接于第一节点Q(N)，漏级电性连接于第四十一P型薄膜晶体管T41的源极；所述第四十一P型薄膜晶体管T41的栅极电性连接于第M+2条时钟信号CK(M+2)，源极电性连接于第四十P型薄膜晶体管T40的漏极，漏极电性连接于扫描驱动信号G(N)。相应的，本发明PMOS栅极驱动电路第七实施例的第一级连接关系中，所述第十一P型薄膜晶体管T11的栅极与源极、第十二P型薄膜晶体管T12的栅极电性连接于启动信号STV，其它电路结构及工作过程均与第五实施例相同，此处不再赘述。
请参阅图12，为本发明第八实施例的电路图，该第八实施例与第五实施例的区别仅在于，将第一下拉模块400中的第四十一P型薄膜晶体管T41采用二极体接法来减少漏电，即将第四十一P型薄膜晶体管T41的栅极与源极均电性连接于第四十P型薄膜晶体管T40的漏极，漏极电性连接于扫描驱动信号G(N)；第四十P型薄膜晶体管T40的栅极电性连接于第M+2条时钟信号CK(M+2)，源极电性连接于第一节点Q(N)，漏级电性连接于第四十一P型薄膜晶体管T41的栅极与源极；相应的，本发明PMOS栅极驱动电路第八实施例的第一级连接关系中，所述第十一P型薄膜晶体管T11的栅极与源极、第十二P型薄膜晶体管T12的栅极电性连接于启动信号STV，其它电路结构及工作过程均与第五实施例相同，此处不再赘述。
综上所述，本发明的PMOS栅极驱动电路，其上拉控制模块接入一恒压负电位，能够降低PMOS器件漏电对第一节点的影响；其下拉维持模块设置由P型薄膜晶体管构成的双重反相器，并采用特殊的防漏电设计，能够减少第一节点的漏电，避免耗尽型P型薄膜晶体管的电性对反相器输出的影响，提高栅极驱动电路的稳定性，并提高面板的集成度，进一步减小液晶显示面板的边框宽度，尤其适用于对边框宽度有较高要求的小尺寸面板。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (14)

  1. 一种PMOS栅极驱动电路，包括级联的多个GOA单元电路，每一级GOA单元电路均包括：上拉控制模块、上拉模块、下传模块、第一下拉模块、自举电容、及下拉维持模块；
    设N为正整数，在第N级GOA单元电路中：
    所述上拉控制模块电性连接于第一节点、及下拉维持模块；所述上拉控制模块至少包括一个P型薄膜晶体管，至少接入上一级第N-1级GOA单元电路的级传信号、及恒压负电位；
    所述上拉模块包括：第二十二P型薄膜晶体管，所述第二十二P型薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第M条时钟信号，漏极输出扫描驱动信号；
    所述下传模块包括：第二十一P型薄膜晶体管，所述第二十一P型薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第M条时钟信号，漏极输出级传信号；
    所述第一下拉模块电性连接于第一节点与扫描驱动信号，包括相互串联的第四十P型薄膜晶体管与第四十一P型薄膜晶体管，用于在非作用期间将第一节点的电位拉到扫描驱动信号的电位；
    所述自举电容的一端电性连接于第一节点，另一端电性连接于扫描驱动信号；
    所述下拉维持模块包括：一由多个P型薄膜晶体管构成的反相器，所述反相器的输入端电性连接于第一节点，输出端电性连接于第二节点；第三十二P型薄膜晶体管，所述第三十二P型薄膜晶体管的栅极电性连接于第二节点，源极电性连接于第四十一P型薄膜晶体管的漏极，漏极电性连接于第一恒压正电位；第四十二P型薄膜晶体管，所述第四十二P型薄膜晶体管的栅极电性连接于第二节点，漏极电性连接于第一节点，源极电性连接于第八十二P型薄膜晶体管的漏极；第八十二P型薄膜晶体管，所述第八十二P型薄膜晶体管的栅极电性连接于第一节点，源极电性连接于恒压负电位，漏极电性连接于第八十一P型薄膜晶体管的漏极；第八十一P型薄膜晶体管，所述第八十一P型薄膜晶体管的栅极电性连接于第二节点，源极电性连接于第二恒压正电位，漏极电性连接于第八十二P型薄膜晶体管的漏极；
    所述第一恒压正电位低于第二恒压正电位。
  2. 如权利要求1所述的PMOS栅极驱动电路，其中，所述上拉控制模块包括一个P型薄膜晶体管：第十一P型薄膜晶体管，所述第十一P型薄膜晶体管的栅极接入上一级第N-1级GOA单元电路的级传信号，源极接入恒压负电位，漏极电性连接于第一节点。
  3. 如权利要求1所述的PMOS栅极驱动电路，其中，所述上拉控制模块包括三个P型薄膜晶体管：第十一P型薄膜晶体管、第十二P型薄膜晶体管、及第十三P型薄膜晶体管；所述第十一P型薄膜晶体管的栅极与源极均接入上一级第N-1级GOA单元电路的级传信号，漏极电性连接于第十二P型薄膜晶体管的源极、及第十三P型薄膜晶体管的漏极；所述第十二P型薄膜晶体管的栅极接入上一级第N-1级GOA单元电路的级传信号，源极电性连接于第十一P型薄膜晶体管的漏极，漏极电性连接于第一节点；所述第十三P型薄膜晶体管的栅极接入扫描驱动信号，源极接入恒压负电位，漏极电性连接于第十一P型薄膜晶体管的漏极。
  4. 如权利要求1所述的PMOS栅极驱动电路，其中，所述第四十P型薄膜晶体管的栅极电性连接于下两级第N+2级GOA单元的级传信号或下两级第N+2级GOA单元的扫描驱动信号，源极电性连接于第一节点，漏级电性连接于第四十一P型薄膜晶体管的源极；所述第四十一P型薄膜晶体管的栅极电性连接于第M+2条时钟信号，源极电性连接于第四十P型薄膜晶体管的漏极，漏极电性连接于扫描驱动信号。
  5. 如权利要求1所述的PMOS栅极驱动电路，其中，所述第四十P型薄膜晶体管的栅极电性连接于第M+2条时钟信号，源极电性连接于第一节点，漏级电性连接于第四十一P型薄膜晶体管的源极；所述第四十一P型薄膜晶体管的栅极电性连接于下两级第N+2级GOA单元的级传信号或下两级第N+2级GOA单元的扫描驱动信号，源极电性连接于第四十P型薄膜晶体管的漏极，漏极电性连接于扫描驱动信号。
  6. 如权利要求1所述的PMOS栅极驱动电路，其中，所述第四十P型薄膜晶体管的栅极与源极均电性连接于第一节点，漏级电性连接于第四十一P型薄膜晶体管的源极；所述第四十一P型薄膜晶体管的栅极电性连接于第M+2条时钟信号，源极电性连接于第四十P型薄膜晶体管的漏极，漏极电性连接于扫描驱动信号。
  7. 如权利要求1所述的PMOS栅极驱动电路，其中，所述第四十P型薄膜晶体管的栅极电性连接于第M+2条时钟信号，源极电性连接于第一节点，漏级电性连接于第四十一P型薄膜晶体管的栅极与源极；所述第四十一P型薄膜晶体管的栅极与源极均电性连接于第四十P型薄膜晶体管的漏 极，漏极电性连接于扫描驱动信号。
  8. 如权利要求1所述的PMOS栅极驱动电路，其中，所述反相器包括第五十二P型薄膜晶体管，所述第五十二P型薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第二恒压正电位，漏极电性连接于第三节点；第五十一P型薄膜晶体，所述第五十一P型薄膜晶体管的栅极及源极均电性连接于恒压负电位，漏极电性连接于第三节点；第五十四P型薄膜晶体管，所述第五十四P型薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第二恒压正电位，漏极电性连接于第二节点；第五十三P型薄膜晶体管，所述第五十三P型薄膜晶体管的栅极电性连接于第三节点，源极电性连接于电性连接于恒压负电位，漏极电性连接于第二节点。
  9. 如权利要求1所述的PMOS栅极驱动电路，其中，所述反相器为双重反相器，包括主反相器、及辅助反相器；
    所述主反相器包括：第五十二P型薄膜晶体管，所述第五十二P型薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第一恒压正电位，漏极电性连接于第三节点；第五十一P型薄膜晶体，所述第五十一P型薄膜晶体管的栅极及源极均电性连接于恒压负电位，漏极电性连接于第三节点；第五十四P型薄膜晶体管，所述第五十四P型薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第四节点，漏极电性连接于第二节点；第五十三P型薄膜晶体管，所述第五十三P型薄膜晶体管的栅极电性连接于第三节点，源极电性连接于恒压负电位，漏极电性连接于第二节点；
    所述辅助反相器包括：第六十二P型薄膜晶体管，所述第六十二P型薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第二恒压正电位，漏极电性连接于第五节点；第六十一P型薄膜晶体，所述第六十一P型薄膜晶体管的栅极及源极均电性连接于恒压负电位，漏极电性连接于第五节点；第六十四P型薄膜晶体管，所述第六十四P型薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第二恒压正电位，漏极电性连接于第四节点；第六十三P型薄膜晶体管，所述第六十三P型薄膜晶体管的栅极电性连接于第五节点，源极电性连接于恒压负电位，漏极电性连接于第四节点。
  10. 如权利要求1所述的PMOS栅极驱动电路，其中，所述反相器为双重反相器，包括主反相器、及辅助反相器；
    所述主反相器包括：第五十二P型薄膜晶体管，所述第五十二P型薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第一恒压正电位，漏极电性连接于第三节点；第五十一P型薄膜晶体，所述第五十一P型薄 膜晶体管的栅极及源极均电性连接于恒压负电位，漏极电性连接于第三节点；第五十四P型薄膜晶体管，所述第五十四P型薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第四节点，漏极电性连接于第二节点；第五十三P型薄膜晶体管，所述第五十三P型薄膜晶体管的栅极电性连接于第三节点，源极电性连接于恒压负电位，漏极电性连接于第二节点；
    所述辅助反相器包括：第六十四P型薄膜晶体管，所述第六十四P型薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第二恒压正电位，漏极电性连接于第四节点；第六十三P型薄膜晶体管，所述第六十三P型薄膜晶体管的栅极电性连接于第三节点，源极电性连接于恒压负电位，漏极电性连接于第四节点。
  11. 一种PMOS栅极驱动电路，包括级联的多个GOA单元电路，每一级GOA单元电路均包括：上拉控制模块、上拉模块、下传模块、第一下拉模块、自举电容、及下拉维持模块；
    设N为正整数，在第N级GOA单元电路中：
    所述上拉控制模块电性连接于第一节点、及下拉维持模块；所述上拉控制模块至少包括一个P型薄膜晶体管，至少接入上一级第N-1级GOA单元电路的级传信号、及恒压负电位；
    所述上拉模块包括：第二十二P型薄膜晶体管，所述第二十二P型薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第M条时钟信号，漏极输出扫描驱动信号；
    所述下传模块包括：第二十一P型薄膜晶体管，所述第二十一P型薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第M条时钟信号，漏极输出级传信号；
    所述第一下拉模块电性连接于第一节点与扫描驱动信号，包括相互串联的第四十P型薄膜晶体管与第四十一P型薄膜晶体管，用于在非作用期间将第一节点的电位拉到扫描驱动信号的电位；
    所述自举电容的一端电性连接于第一节点，另一端电性连接于扫描驱动信号；
    所述下拉维持模块包括：一由多个P型薄膜晶体管构成的反相器，所述反相器的输入端电性连接于第一节点，输出端电性连接于第二节点；第三十二P型薄膜晶体管，所述第三十二P型薄膜晶体管的栅极电性连接于第二节点，源极电性连接于第四十一P型薄膜晶体管的漏极，漏极电性连接于第一恒压正电位；第四十二P型薄膜晶体管，所述第四十二P型薄膜晶体管的栅极电性连接于第二节点，漏极电性连接于第一节点，源极电性 连接于第八十二P型薄膜晶体管的漏极；第八十二P型薄膜晶体管，所述第八十二P型薄膜晶体管的栅极电性连接于第一节点，源极电性连接于恒压负电位，漏极电性连接于第八十一P型薄膜晶体管的漏极；第八十一P型薄膜晶体管，所述第八十一P型薄膜晶体管的栅极电性连接于第二节点，源极电性连接于第二恒压正电位，漏极电性连接于第八十二P型薄膜晶体管的漏极；
    所述第一恒压正电位低于第二恒压正电位；
    其中，所述上拉控制模块包括一个P型薄膜晶体管：第十一P型薄膜晶体管，所述第十一P型薄膜晶体管的栅极接入上一级第N-1级GOA单元电路的级传信号，源极接入恒压负电位，漏极电性连接于第一节点；
    其中，所述第四十P型薄膜晶体管的栅极电性连接于下两级第N+2级GOA单元的级传信号或下两级第N+2级GOA单元的扫描驱动信号，源极电性连接于第一节点，漏级电性连接于第四十一P型薄膜晶体管的源极；所述第四十一P型薄膜晶体管的栅极电性连接于第M+2条时钟信号，源极电性连接于第四十P型薄膜晶体管的漏极，漏极电性连接于扫描驱动信号。
  12. 如权利要求11所述的PMOS栅极驱动电路，其中，所述反相器包括第五十二P型薄膜晶体管，所述第五十二P型薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第二恒压正电位，漏极电性连接于第三节点；第五十一P型薄膜晶体，所述第五十一P型薄膜晶体管的栅极及源极均电性连接于恒压负电位，漏极电性连接于第三节点；第五十四P型薄膜晶体管，所述第五十四P型薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第二恒压正电位，漏极电性连接于第二节点；第五十三P型薄膜晶体管，所述第五十三P型薄膜晶体管的栅极电性连接于第三节点，源极电性连接于电性连接于恒压负电位，漏极电性连接于第二节点。
  13. 如权利要求11所述的PMOS栅极驱动电路，其中，所述反相器为双重反相器，包括主反相器、及辅助反相器；
    所述主反相器包括：第五十二P型薄膜晶体管，所述第五十二P型薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第一恒压正电位，漏极电性连接于第三节点；第五十一P型薄膜晶体，所述第五十一P型薄膜晶体管的栅极及源极均电性连接于恒压负电位，漏极电性连接于第三节点；第五十四P型薄膜晶体管，所述第五十四P型薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第四节点，漏极电性连接于第二节点；第五十三P型薄膜晶体管，所述第五十三P型薄膜晶体管的栅极电性连接于第三节点，源极电性连接于恒压负电位，漏极电性连接于第二节点；
    所述辅助反相器包括：第六十二P型薄膜晶体管，所述第六十二P型薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第二恒压正电位，漏极电性连接于第五节点；第六十一P型薄膜晶体，所述第六十一P型薄膜晶体管的栅极及源极均电性连接于恒压负电位，漏极电性连接于第五节点；第六十四P型薄膜晶体管，所述第六十四P型薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第二恒压正电位，漏极电性连接于第四节点；第六十三P型薄膜晶体管，所述第六十三P型薄膜晶体管的栅极电性连接于第五节点，源极电性连接于恒压负电位，漏极电性连接于第四节点。
  14. 如权利要求11所述的PMOS栅极驱动电路，其中，所述反相器为双重反相器，包括主反相器、及辅助反相器；
    所述主反相器包括：第五十二P型薄膜晶体管，所述第五十二P型薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第一恒压正电位，漏极电性连接于第三节点；第五十一P型薄膜晶体，所述第五十一P型薄膜晶体管的栅极及源极均电性连接于恒压负电位，漏极电性连接于第三节点；第五十四P型薄膜晶体管，所述第五十四P型薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第四节点，漏极电性连接于第二节点；第五十三P型薄膜晶体管，所述第五十三P型薄膜晶体管的栅极电性连接于第三节点，源极电性连接于恒压负电位，漏极电性连接于第二节点；
    所述辅助反相器包括：第六十四P型薄膜晶体管，所述第六十四P型薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第二恒压正电位，漏极电性连接于第四节点；第六十三P型薄膜晶体管，所述第六十三P型薄膜晶体管的栅极电性连接于第三节点，源极电性连接于恒压负电位，漏极电性连接于第四节点。
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