WO2023065388A1 - 栅极驱动电路及显示面板 - Google Patents
栅极驱动电路及显示面板 Download PDFInfo
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- WO2023065388A1 WO2023065388A1 PCT/CN2021/127378 CN2021127378W WO2023065388A1 WO 2023065388 A1 WO2023065388 A1 WO 2023065388A1 CN 2021127378 W CN2021127378 W CN 2021127378W WO 2023065388 A1 WO2023065388 A1 WO 2023065388A1
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- Prior art keywords
- thin film
- film transistor
- gate
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- output terminal
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- 239000010409 thin film Substances 0.000 claims abstract description 450
- 239000003990 capacitor Substances 0.000 claims description 35
- 230000000087 stabilizing effect Effects 0.000 claims description 6
- 238000005516 engineering process Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 229920005591 polysilicon Polymers 0.000 description 8
- 102100036685 Growth arrest-specific protein 2 Human genes 0.000 description 4
- 101001072710 Homo sapiens Growth arrest-specific protein 2 Proteins 0.000 description 4
- 239000000969 carrier Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 230000002159 abnormal effect Effects 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 238000001514 detection method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 102100036683 Growth arrest-specific protein 1 Human genes 0.000 description 1
- 101001072723 Homo sapiens Growth arrest-specific protein 1 Proteins 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000008447 perception Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0404—Matrix technologies
- G09G2300/0408—Integration of the drivers onto the display substrate
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/08—Details of timing specific for flat panels, other than clock recovery
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
- G09G2330/021—Power management, e.g. power saving
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2354/00—Aspects of interface with display user
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
Definitions
- the embodiments of the present application relate to the field of display technology, and in particular to a gate driving circuit and a display panel.
- GOA Gate Driver On Array
- GOA technology is a gate drive technology that integrates the gate drive circuit of the display panel on the glass substrate. Because GOA technology can reduce the bonding process of external ICs, it can reduce product costs. , and is more suitable for making display products with narrow borders or no borders.
- the existing GOA circuit includes a plurality of cascaded gate driving units, and each level of gate driving units corresponds to driving one level of horizontal scanning lines.
- Each level of gate driving unit mainly includes a pull-up circuit, a pull-up control circuit and a pull-down circuit.
- the pull-up circuit is mainly responsible for outputting the clock signal as a gate drive signal; the pull-up control circuit controls the opening time of the pull-up circuit by raising the pull-up node, and the pull-up control circuit is generally connected to the gate passed by the front-stage gate drive unit Driving signal; the pull-down circuit is responsible for pulling down the pull-up node and the gate driving signal to a low potential at the first time.
- the pull-up node of the gate drive circuit needs to maintain a high potential during the pull-up phase and the touch-stop phase.
- the touch-stop phase refers to the touch screen
- the gate drive circuit needs to detect the touch signal during the normal display phase. Therefore, the gate drive signal is not output at this stage, and the gate drive signal is output only after the touch signal detection and collection are completed.
- the pull-up node needs to maintain a high potential, that is, compared to The shorter the pull-up period, the longer the touch stop period, and the longer the pull-up node needs to maintain the high potential. It can be seen that the potential stability of the pull-up node plays a vital role in the stable operation of the GOA circuit.
- thin-film transistors are the basic components of gate drive circuits. According to the classification of thin-film transistors, thin-film transistors can be divided into amorphous silicon (A-Si) thin-film transistors, low-temperature polysilicon (LTPS) thin-film transistors, and oxide (IGZO) thin-film transistors.
- A-Si amorphous silicon
- LTPS low-temperature polysilicon
- IGZO oxide
- the potential of the pull-up node of the gate drive circuit cannot maintain a stable high potential due to the leakage of the thin-film transistor connected to it during the pull-up phase and the touch stop phase, resulting in touch
- the gate drive unit of the intermediate stop stage fails, causing the display panel to appear split screen.
- an embodiment of the present application provides a gate drive circuit and a display panel.
- the embodiment of the present application provides a gate drive circuit
- the gate drive circuit includes a plurality of cascaded gate drive units, each stage of the gate drive unit includes: a pull-up control module 100 and a pull-down control module 100 Module 300, of which:
- the pull-up control module 100 is connected to the first node Q, and connected to the output terminal of the forward scanning signal, the output terminal of the reverse scanning signal, the output terminal of the n-mth gate driving signal, and the output terminal of the n+mth gate driving signal , for the signal output from the forward scan signal output end, the signal output from the reverse scan signal output end, the signal output from the n-mth stage gate drive signal output end, and the n+mth stage Under the control of the signal output from the gate drive signal output terminal, increase the potential of the first node; both n and m are positive integers, and n>m;
- the pull-down module is connected to the first node, and connected to the constant voltage low potential, the n+mth clock signal output terminal, and the n-mth clock signal output terminal, and is used for the constant voltage low potential, the nth Pulling down the potential of the first node under the control of +m clock signals and the n-mth clock signal;
- the thin film transistors in the pull-up control module and/or in the pull-down module respectively connected to the first node Q are oxide thin film transistors.
- the pull-up control module includes a first thin film transistor and a second thin film transistor, the gate of the first thin film transistor is connected to the n-mth stage gate drive signal output end, and the gate of the second thin film transistor is The gate is connected to the output terminal of the n+mth stage gate drive signal, the source of the first thin film transistor is connected to the output terminal of the forward scanning signal, and the source of the second thin film transistor is connected to the output terminal of the reverse scanning signal.
- the drain of the first thin film transistor and the drain of the second thin film transistor are both connected to the first node; wherein, the first thin film transistor and the second thin film transistor are oxide thin film transistors.
- the pull-down module includes a fifth thin film transistor and a sixth thin film transistor, the gate of the fifth thin film transistor is connected to the n+mth clock signal output end or the n-mth clock signal output end, so The source of the fifth thin film transistor is connected to the first node, the drain of the fifth thin film transistor is connected to the source of the sixth thin film transistor, and the drain of the sixth thin film transistor is connected to a constant voltage low potential;
- the fifth thin film transistor is an oxide thin film transistor.
- the gate driving unit at the nth stage further includes a pull-up module
- the pull-up module includes a third thin film transistor and a fourth thin film transistor
- the gate of the third thin film transistor is connected to a constant voltage high potential
- the source of the third thin film transistor is connected to the first node
- the drain of the third thin film transistor and the gate of the fourth thin film transistor are both connected to the fourth node
- the fourth thin film transistor The source is connected to the nth clock signal output end
- the drain of the fourth thin film transistor is connected to the nth stage gate drive signal output end.
- the pull-down module further includes an eleventh thin film transistor, the gate of the eleventh thin film transistor is connected to the second node, and the source of the eleventh thin film transistor is connected to the gate of the nth stage
- the electrode driving signal output terminal, the drain of the eleventh thin film transistor is connected to a constant voltage low potential.
- the gate drive unit at the nth stage further includes a voltage stabilizing module, and the voltage stabilizing module includes a first capacitor and a second capacitor, wherein one end of the first capacitor is connected to the first node One end of the second capacitor is connected to the second node, and the other end of the first capacitor and the other end of the second capacitor are both connected to the constant voltage low potential output end.
- the voltage stabilizing module includes a first capacitor and a second capacitor, wherein one end of the first capacitor is connected to the first node One end of the second capacitor is connected to the second node, and the other end of the first capacitor and the other end of the second capacitor are both connected to the constant voltage low potential output end.
- the gate driving unit at the nth stage further includes a gate signal turn-on module
- the gate signal turn-on module includes a twelfth thin film transistor, a thirteenth thin film transistor, and a fourteenth thin film transistor, so
- the gate and drain of the twelfth thin film transistor, the gate of the thirteenth thin film transistor, and the gate of the fourteenth thin film transistor are all connected to the first global control signal output terminal, and the twelfth thin film transistor
- the source of the thin film transistor is connected to the fourth node, the source of the thirteenth thin film transistor and the source of the fourteenth thin film transistor are both connected to the second node, and the drain of the thirteenth thin film transistor is connected to the The drains of the fourteenth thin film transistors are all connected to the constant-voltage low-potential output terminals.
- the gate driving unit at the nth stage further includes a gate signal closing module, the gate signal closing module includes a fifteenth thin film transistor, the gate of the fifteenth thin film transistor is connected to the second The global control signal output terminal, the source of the fifteenth thin film transistor is connected to the gate signal output terminal of the nth stage, and the drain of the fifteenth thin film transistor is connected to the constant voltage low potential output terminal.
- the gate signal closing module includes a fifteenth thin film transistor, the gate of the fifteenth thin film transistor is connected to the second The global control signal output terminal, the source of the fifteenth thin film transistor is connected to the gate signal output terminal of the nth stage, and the drain of the fifteenth thin film transistor is connected to the constant voltage low potential output terminal.
- the embodiment of the present application further provides a gate drive circuit
- the gate drive includes a plurality of cascaded gate drive units
- the gate drive unit at the nth stage includes: a first thin film transistor, a second a thin film transistor and a fifth thin film transistor
- the gate of the first thin film transistor is connected to the output terminal of the n-mth gate drive signal
- the gate of the second thin film transistor is connected to the output terminal of the n+mth gate drive signal
- the source of the first thin film transistor is connected to the output terminal of the forward scanning signal
- the source of the second thin film transistor is connected to the output terminal of the reverse scanning signal
- the drains of the fifth thin film transistor are connected to the first node
- the gate of the fifth thin film transistor is connected to the n+mth clock signal output end or the n-mth clock signal output end
- the source of the fifth thin film transistor is connected to the first A node, wherein at least
- the gate driving unit at the nth stage further includes: the gate driving unit at the nth stage further includes: a sixth thin film transistor, the gate of the sixth thin film transistor is connected to the second node, so The drain of the fifth thin film transistor is connected to the source of the sixth thin film transistor, and the drain of the sixth thin film transistor is connected to a constant low potential.
- the gate driving unit of the nth stage further includes: a third thin film transistor and a fourth thin film transistor, the gate of the third thin film transistor is connected to a constant voltage high potential, and the gate of the third thin film transistor is The source is connected to the first node, the drain of the third thin film transistor and the gate of the fourth thin film transistor are both connected to the fourth node, and the source of the fourth thin film transistor is connected to the nth clock A signal output terminal, the drain of the fourth thin film transistor is connected to the n-th stage gate drive signal output terminal.
- the gate driving unit at the nth stage further includes: an eleventh thin film transistor, the gate of the eleventh thin film transistor is connected to the second node, and the source of the eleventh thin film transistor is connected to The nth stage gate drive signal output terminal, the drain of the eleventh thin film transistor is connected to a constant low potential.
- the gate driving unit at the nth stage further includes: a first capacitor and a second capacitor, wherein one end of the first capacitor is connected to the first node, and one end of the second capacitor is connected to The second node, the other end of the first capacitor and the other end of the second capacitor are all connected to the constant voltage low potential output end.
- the twelfth thin film transistor, the thirteenth thin film transistor, and the fourteenth thin film transistor, the gate and drain of the twelfth thin film transistor, the gate of the thirteenth thin film transistor, and The gate of the fourteenth thin film transistor is connected to the first global control signal output terminal, the source of the twelfth thin film transistor is connected to the fourth node, the source of the thirteenth thin film transistor is connected to the tenth thin film transistor The sources of the four thin film transistors are all connected to the second node, and the drains of the thirteenth thin film transistor and the fourteenth thin film transistor are connected to the constant voltage low potential output terminal.
- the gate of the fifteenth thin film transistor is connected to the second global control signal output terminal, and the source of the fifteenth thin film transistor is connected to the nth stage gate signal output terminal , the drain of the fifteenth thin film transistor is connected to the constant voltage low potential output terminal.
- the embodiment of the present application further provides a display panel, which includes the gate driving circuit as described in any one of the above embodiments.
- the gate driving circuit includes a plurality of cascaded gate driving units, and the gate driving unit at the nth stage includes: a first thin film transistor, a second thin film transistor and a fifth thin film transistor, so The gate of the first thin film transistor is connected to the output end of the gate driving signal of the n-mth stage, the gate of the second thin film transistor is connected to the output end of the gate driving signal of the n+mth stage, and the source of the first thin film transistor connected to the output terminal of the forward scan signal, the source of the second thin film transistor is connected to the output terminal of the reverse scan signal, and the drain of the first thin film transistor and the drain of the second thin film transistor are both connected to the first node;
- the gate of the fifth thin film transistor is connected to the n+mth clock signal output end or the n-mth clock signal output end, and the source of the fifth thin film transistor is connected to the first node, wherein the first At least one of the thin film transistor, the second thin film transistor and the fifth thin film transistor is
- the gate driving unit at the nth stage further includes: a sixth thin film transistor, the gate of the sixth thin film transistor is connected to the second node, and the drain of the fifth thin film transistor is connected to the first The sources of the six thin film transistors, and the drain of the sixth thin film transistor are connected to a constant low potential.
- the gate driving unit of the nth stage further includes: a third thin film transistor and a fourth thin film transistor, the gate of the third thin film transistor is connected to a constant voltage high potential, and the gate of the third thin film transistor is The source is connected to the first node, the drain of the third thin film transistor and the gate of the fourth thin film transistor are both connected to the fourth node, and the source of the fourth thin film transistor is connected to the nth clock signal output terminal, and the drain of the fourth thin film transistor is connected to the output terminal of the gate driving signal of the nth stage.
- the gate driving unit at the nth stage further includes: an eleventh thin film transistor, the gate of the eleventh thin film transistor is connected to the second node, and the source of the eleventh thin film transistor is connected to The nth stage gate drive signal output terminal, the drain of the eleventh thin film transistor is connected to a constant low potential.
- the pull-up control module and the pull-down module of each stage of the gate drive unit are respectively connected to the first node, wherein the pull-up control module and/or the pull-down module are connected to
- the thin film transistor connected to the first node adopts an oxide thin film transistor, so that the leakage current of the first node is reduced by utilizing the characteristics of the small off-state leakage current of the oxide thin film transistor, so that the potential of the first node is in the pull-up phase and the touch stop phase It is kept stable to prevent abnormal picture of the display panel due to the unstable potential of the first node.
- FIG. 1 is a schematic circuit diagram of a gate drive circuit provided in an embodiment of the present application
- FIG. 2 is a schematic diagram of the first timing sequence of the gate drive circuit provided by the embodiment of the present application.
- FIG. 3 is a second timing diagram of the gate drive circuit provided by the embodiment of the present application.
- FIG. 4 is a third timing diagram of the gate drive circuit provided by the embodiment of the present application.
- FIG. 5 is a first structural schematic diagram of a display panel provided by an embodiment of the present application.
- FIG. 6 is a schematic diagram of a second structure of a display panel provided by an embodiment of the present application.
- FIG. 1 is a schematic circuit diagram of a gate drive circuit provided by an embodiment of the present application.
- the embodiment of the present application provides a gate drive circuit.
- the gate drive circuit includes a plurality of cascaded gate drive units, each The primary gate driving unit includes: a pull-up control module 100 and a pull-down module 300 .
- the pull-up control module 100 is connected to the first node Q, and connected to the output terminal of the forward scanning signal U2D, the output terminal of the reverse scanning signal D2U, the output terminal of the n-mth gate driving signal G(n-m) and the n+mth gate
- the output terminal of the driving signal G(n+m) which is used for the forward scanning signal U2D, the reverse scanning signal D2U, the n-mth level gate driving signal G(n-m), and the n+mth level gate driving signal G( Under the control of n+m), increase the potential of the first node Q; both n and m are positive integers; both n and m are positive integers, and n>m;
- the pull-up control module 100 is connected to the first node Q, and connected to the output terminal of the forward scanning signal U2D and the output terminal of the n-mth gate driving signal G(n-m), or connected to the output terminal of the reverse scanning signal D2U and the output terminal of the nth stage
- the +m-level gate drive signal G(n+m) output terminal is used to increase the potential of the first node Q through the forward scanning signal U2D under the control of the n-mth level gate drive signal G(n-m), or in Under the control of the gate driving signal G(n+m) of the n+mth stage, the potential of the first node Q is increased by the reverse scanning signal D2U.
- the pull-down module 300 is connected to the first node Q and the constant voltage low potential VGL, and the output end of the n+m clock signal CK (n+m) or the output end of the n-m clock signal CK (n-m), for Under the control of the n+m clock signal CK (n+m) or the n-m clock signal CK (n-m), the potential of the first node Q is pulled down by the constant voltage low potential VGL;
- the thin film transistors in the pull-up control module 100 and/or in the pull-down module 300 respectively connected to the first node Q are oxide thin film transistors.
- the pull-up control module 100 and the pull-down module 300 of each stage of the gate drive unit are respectively connected to the first node Q, wherein the pull-up control module 100 and/or the pull-down module 300
- the thin film transistor connected to the first node Q adopts an oxide thin film transistor, so that the leakage current of the first node Q is reduced by utilizing the characteristics of the small off-state leakage current of the oxide thin film transistor, so that the potential of the first node Q is in the pull-up phase and
- the touch-stop stage is kept stable to prevent abnormal picture of the display panel due to the unstable potential of the first node Q.
- the pull-up control module 100 includes a first thin film transistor T1 and a second thin film transistor T2, the gate of the first thin film transistor T1 is connected to the output end of the gate driving signal G(n-m) of the n-mth stage, and the gate of the second thin film transistor T2 The gate is connected to the output terminal of the gate driving signal G(n+m) of the n+m stage, the source of the first thin film transistor T1 is connected to the output terminal of the forward scanning signal U2D, and the source of the second thin film transistor T2 is connected to the reverse scanning
- the output terminal of the signal D2U, the drains of the first thin film transistor T1 and the second thin film transistor T2 are both connected to the first node Q; both n and m are positive integers, and n>m.
- the phases of the forward scan signal U2D and the reverse scan signal D2U are opposite, that is, one of the forward scan signal U2D and the reverse scan signal D2U is at a high potential and the other is at
- the pull-down module 300 includes a fifth thin film transistor T5 and a sixth thin film transistor T6, the gate of the fifth thin film transistor T5 is connected to the output terminal of the n+mth clock signal CK (n+m) (during forward scanning) or The n-mth clock signal CK (n-m) output terminal (during reverse scanning), the source of the fifth thin film transistor T5 is connected to the first node Q, the drain of the fifth thin film transistor T5 is connected to the source of the sixth thin film transistor T6, The drain of the sixth thin film transistor T6 is connected to the constant low potential VGL.
- At least one of the first thin film transistor T1 , the second thin film transistor T2 and the fifth thin film transistor T5 is an oxide thin film transistor.
- the first thin film transistor T1 and the second thin film transistor T2 in the pull-up control module 100 are respectively connected to the first node Q
- the fifth thin film transistor T5 in the pull-down module 300 is connected to the first node Q.
- a node Q is connected
- at least one of the first thin film transistor T1, the second thin film transistor T2 and the fifth thin film transistor T5 is an oxide thin film transistor, so that the off-state leakage current of the oxide thin film transistor is small to reduce the first Node Q leakage current.
- the gate of the fifth thin film transistor T5 is connected to the output end of the n+mth clock signal CK(n+m) or the output end of the n-mth clock signal CK(n-m), so that the gate of the fifth thin film transistor T5 does not Like the gate of the sixth thin film transistor T6 connected to the second node P, it will be affected by the stress by maintaining a high potential for a long time, thereby enhancing the stability of the fifth thin film transistor T5, thereby improving the stability of the first node Q, so as to improve the gate Pole drive circuit stability.
- the first thin film transistor T1, the second thin film transistor T2 and the fifth thin film transistor T5 is an oxide thin film transistor, that is, the first thin film transistor T1, the second thin film transistor T2 and the fifth thin film transistor T2 can be selected Any one of the transistors T5 is an oxide thin film transistor, or any two are oxide thin film transistors, or all are oxide thin film transistors, so that the first The leakage current of the node Q keeps the potential of the first node Q stable.
- the low-temperature polycrystalline oxide (LTPO) technology combines the advantages of both LTPS and IGZO technologies, so that the display panel has the characteristics of strong driving capability and low power consumption at the same time, and meets the needs of high-frequency and low-frequency applications.
- LTPO technology is suitable for the requirements of dynamic frame rate technology, and can achieve the purpose of improving user visual experience and optimizing power consumption. Therefore, except that at least one of the first thin film transistor T1, the second thin film transistor T2, and the fifth thin film transistor T5 is an oxide thin film transistor in the gate driving circuit provided by the embodiment of the present application, all other thin film transistors can be made of low temperature polysilicon oxide.
- the gate drive circuit can not only achieve the effect of reducing the leakage current of the first node Q, but also improve the gate
- the driving capability of the driving circuit enables the gate driving circuit to meet the requirements of high frequency and low frequency at the same time.
- thin film transistors can be classified into N-type thin film transistors and P-type thin film transistors according to their electrical characteristics. Among them, because the carriers (many carriers) of N-type thin film transistors are electrons, and the carriers (multiple carriers) of P-type thin film transistors are The current (multiple) is a hole, so the mobility of the N-type thin film transistor is higher than that of the P-type thin film transistor; in addition, the N-type thin film transistor can be turned on with a positive voltage, while the P-type thin film transistor needs to be turned on with a negative voltage Therefore, from a control point of view, N-type thin film transistors are more convenient than P-type thin film transistors.
- current gate driving circuits are mostly made of N-type thin film transistors.
- the stability of the N-type thin film transistor is lower than that of the P-type thin film transistor, so the stability of the N-type thin film transistor is not as good as that of the P-type thin film transistor in a high-temperature environment, that is, the electrical characteristics of the N-type thin film transistor are better in a high-temperature environment. It is easy to change, so that the leakage current increases.
- the gate drive circuit provided by the embodiment of the present application is especially suitable for the gate drive circuit made of N-type thin film transistors, especially the thin film transistor connected to the first node Q is N type thin film transistor gate drive circuit, that is, in the gate drive circuit provided in the embodiment of the present application, the thin film transistors using oxide thin film transistors in the first thin film transistor T1, the second thin film transistor T2 and the fifth thin film transistor T5 are N type thin film transistors.
- the gate driving unit of the nth stage further includes a pull-up module 200
- the pull-up module 200 includes a third thin film transistor T3 and a fourth thin film transistor T4, and the gate of the third thin film transistor T3 is connected to a constant voltage High potential VGH
- the source of the third thin film transistor T3 is connected to the first node Q
- the drain of the third thin film transistor T3 and the gate of the fourth thin film transistor T4 are both connected to the fourth node M
- the source of the fourth thin film transistor T4 It is connected to the output terminal of the nth clock signal CK(n)
- the drain of the fourth thin film transistor T4 is connected to the output terminal of the nth stage gate driving signal G(n).
- the function of the third thin film transistor T3 is to prevent the high potential of the third node K from being poured back into the first node Q so that the potential of the third node K decreases, so as to keep the potential of the third node K stable.
- the gate driving unit at the nth stage further includes a front and back scanning module 400
- the front and back scanning module 400 includes a seventh thin film transistor T7 and an eighth thin film transistor T8, wherein the gate of the seventh thin film transistor T7 The pole is connected to the output terminal of the forward scanning signal U2D, the gate of the eighth thin film transistor T8 is connected to the output terminal of the reverse scanning module, and the source of the seventh thin film transistor T7 is connected to the output terminal of the n+m clock signal CK (n+m) , the source of the eighth thin film transistor T8 is connected to the n-mth clock signal CK (n-m) output terminal, and the drains of the seventh thin film transistor T7 and the eighth thin film transistor T8 are both connected to the third node K.
- the first-level gate driving unit scans the pixel rows from front to back; Scan the pixel row before.
- the gate driving unit at the nth stage further includes a pull-down control module 500
- the pull-down control module 500 includes a ninth thin film transistor T9 and a tenth thin film transistor T10, wherein the gate of the ninth thin film transistor T9 is connected to The third node K, the source of the ninth thin film transistor T9 is connected to the constant voltage high potential VGH, the drain of the ninth thin film transistor T9 and the source of the tenth thin film transistor T10 are connected to the second node P, and the gate of the tenth thin film transistor T10 The pole is connected to the first node Q, and the drain of the tenth thin film transistor T10 is connected to the constant low potential VGL.
- the pull-down module 300 further includes an eleventh thin film transistor T11, the gate of the eleventh thin film transistor T11 is connected to the second node P, and the source of the eleventh thin film transistor T11 is connected to the nth level gate driving signal
- the output terminal of G(n), the drain of the tenth thin film transistor T10 is connected to the constant voltage low potential VGL.
- the gate drive unit at the nth stage further includes a voltage stabilizing module 600
- the voltage stabilizing module 600 includes a first capacitor C1 and a second capacitor C2, wherein one end of the first capacitor C1 is connected to the first node Q , one end of the second capacitor C2 is connected to the second node P, and the other end of the first capacitor C1 and the other end of the second capacitor C2 are both connected to the constant voltage low potential VGL.
- every m continuous gate driving units form a minimum repeating unit, for example, a minimum repeating unit may be formed from the n-mth gate driving unit to the nth level gate driving unit.
- the gate drive unit of the nth stage further includes a gate signal opening module 700, and the function of the gate signal opening module 700 is to open the gate drive output of all gate drive units of the gate drive circuit. Signal, so as to remove the residual charge, so that there will be no residual image when the display panel is turned on or off, and all pixels can be charged to the intermediate voltage when the display panel is turned on, so as to quickly respond to the first display screen after turning on and improve the user experience. perception.
- the gate signal opening module 700 includes a twelfth thin film transistor T12, a thirteenth thin film transistor T13 and a fourteenth thin film transistor T14, the gate and drain of the twelfth thin film transistor T12, the thirteenth thin film transistor T13 and the gate of the fourteenth thin film transistor T14 are connected to the output terminal of the first global control signal GAS1, the source of the twelfth thin film transistor T12 is connected to the fourth node M, the source of the thirteenth thin film transistor T13 and The sources of the fourteenth thin film transistor T14 are both connected to the second node P, and the drains of the thirteenth thin film transistor T13 and the fourteenth thin film transistor T14 are both connected to the constant low potential VGL.
- the gate driving unit at the nth stage further includes a gate signal closing module 800, and the function of the gate signal closing module 800 is to insert a touch scanning phase B during the normal display phase A to control The touch signal is detected and collected. At this time, it is necessary to turn off the gate drive signal output by all the gate drive units of the gate drive circuit. After the touch signal detection and collection are completed, it is driven by the touch stop gate. The gate drive signal of the unit starts to output the gate drive signal step by step.
- the gate signal closing module 800 includes a fifteenth thin film transistor T15, the gate of the fifteenth thin film transistor T15 is connected to the output terminal of the second global control signal GAS2, and the source of the fifteenth thin film transistor T15 is connected to the gate of the nth stage.
- the drain of the fifteenth thin film transistor T15 is connected to the constant voltage low potential VGL.
- Fig. 2, Fig. 3 and Fig. 4 are timing schematic diagrams of the gate drive circuit provided by the embodiment of the present application respectively.
- the nth stage gate drive of the gate drive circuit The working process of the unit is described in detail.
- all the thin film transistors in the gate driving circuit are N-type thin film transistors, and the gate driving circuit adopts forward scanning as an example.
- the gate drive circuit includes a normal display phase A and a touch scanning phase B, and the touch scanning phase B is interspersed between the normal display phase A, that is, in the normal display phase A, if a touch signal is received, each display Stop during the signal and perform touch scanning, and then continue to input each display signal after the touch scanning is completed.
- the normal display phase A includes a pre-filling sub-phase t1, an output sub-phase t2 and a pull-down sub-phase t3.
- the gate driving signal G(n-m) of the n-mth stage is at a high level to turn on the first thin film transistor T1
- the forward scanning signal U2D is at a high level to increase the voltage of the first node Q and the fourth node M. potential, and make the first capacitor C1 be charged.
- the first node Q turns on the tenth thin film transistor T10 , so that the second node P is at the constant low potential VGL, and then turns off the sixth thin film transistor T6 and the tenth thin film transistor T10 .
- the second global control signal GAS2 is at a high potential, so that the gate drive signals are all at a low potential, and at the same time, each display signal is in a stop state.
- the second The thin film transistor T2 and the fifth thin film transistor T5 are in an off state, and since the second thin film transistor T2 and the fifth thin film transistor T5 are oxide thin film transistors, the off-state leakage current of the second thin film transistor T2 and the fifth thin film transistor T5 is relatively small , the potential of the first node Q can be maintained in a relatively stable high potential state.
- the gate driving signal G(n-m) of the n-mth stage is at a low level to turn off the first thin film transistor T1
- the first capacitor C1 keeps the first node Q at a high potential, so that the third node K is also High potential, so that the fourth thin film transistor T4 is turned on, and at the same time, the nth clock signal CK (n) is high potential, so that the potential of the third node M is further raised to a higher potential, and the nth level gate drive signal G (n) is high potential.
- the first node Q keeps the tenth thin film transistor T10 turned on, thereby keeping the second node P at a constant low potential VGL, and further keeps the sixth thin film transistor T6 and the tenth thin film transistor T10 off.
- the second global control signal GAS2 is at a high potential, so that the gate driving signals are all at a low potential, and at the same time, each display signal is in a stop state.
- the first The thin film transistor T1, the second thin film transistor T2, and the fifth thin film transistor T5 are in the off state. Since the first thin film transistor T1, the second thin film transistor T2, and the fifth thin film transistor T5 use oxide thin film transistors, the first thin film transistor T1, The off-state leakage currents of the second thin film transistor T2 and the fifth thin film transistor T5 are small, which can keep the potential of the first node Q at a relatively stable high potential state. After the touch scanning ends, enter the pull-down sub-stage t3.
- the n+mth clock signal CK (n+m) is at a high potential to increase the potential of the third node K and turn on the fifth thin film transistor T5, and the third node K is at a high potential to turn on the ninth thin film transistor T9 is turned on, so that the potential of the second node P is increased and the second capacitor C2 is charged, and the second node P makes the sixth thin film transistor T6 and the eleventh thin film transistor T11 turn on, and at this time the fifth thin film transistor T5 and the sixth thin film transistor T5
- the transistor T6 pulls down the potential of the first node Q
- the eleventh thin film transistor T11 pulls down the potential of the nth stage gate driving signal G(n)
- the second capacitor C2 keeps the second node P at a low potential.
- the second global control signal GAS2 is at a high potential, so that the gate driving signals are all at a low potential.
- each display signal is in the stop state, and at this time the first thin film transistor T1 and the second thin film transistor T2 are in the off state. Since the first thin film transistor T1 and the second thin film transistor T2 are oxide thin film transistors, the first thin film transistor T1 and the off-state leakage current of the second thin film transistor T2 are small, which can keep the potential of the first node Q in a relatively stable low potential state.
- the pole drive signal is the output process of the n+mth level gate drive signal.
- this embodiment of the present application also provides a display panel, the display panel 1 includes the above-mentioned gate drive circuit 2, and the display panel 1 has the same structure as the gate drive circuit 2 provided by the above-mentioned embodiments and beneficial effects. Since the structure and beneficial effects of the gate driving circuit 2 have been described in detail in the foregoing embodiments, details are not repeated here.
- the gate drive circuit 2 may be provided only on one side of the display panel 1; Gate driving circuits 2 are respectively arranged on opposite sides of the display panel 1 .
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Abstract
本申请提供一种栅极驱动电路及显示面板,每一级栅极驱动单元的上拉控制模块和下拉模块分别与第一节点连接,上拉控制模块和/或下拉模块中与第一节点连接的薄膜晶体管采用氧化物薄膜晶体管,从而利用氧化物薄膜晶体管的关态漏电流小的特点减少第一节点的漏电流,使得第一节点的电位在上拉阶段和触摸中停阶段能保持稳定。
Description
本申请实施例涉及显示技术领域,尤其涉及一种栅极驱动电路及显示面板。
GOA(Gate Driver On Array)技术是将显示面板的栅极驱动电路集成在玻璃基板上的一种栅极驱动技术,由于GOA技术能较少外接IC的绑定(bonding)工序,能降低产品成本,且更适合制作窄边框或无边框的显示产品。
现有的GOA电路包括级联的多个栅极驱动单元,每一级栅极驱动单元对应驱动一级水平扫描线。每一级栅极驱动单元主要包括上拉电路、上拉控制电路和下拉电路。上拉电路主要负责将时钟信号输出为栅极驱动信号;上拉控制电路通过提升上拉节点来控制上拉电路的打开时间,上拉控制电路一般连接前面级栅极驱动单元传递过来的栅极驱动信号;下拉电路负责在第一时间将上拉节点和栅极驱动信号拉低为低电位。
栅极驱动电路的上拉节点需要在上拉阶段和触摸中停阶段保持高电位,其中,触摸中停阶段是指针对触摸屏,栅极驱动电路在正常显示阶段的过程中需要对触摸信号进行侦测和采集,因此在该阶段不输出栅极驱动信号,而在触摸信号侦测和采集完毕之后才输出栅极驱动信号,在该阶段中,上拉节点需要持续保持高电位,即,比起上拉阶段的较短时间,触摸中停阶段时间更长,上拉节点需要保持高电位的时间更长。由此可以看出,上拉节点的电位稳定性对于GOA电路的稳定运行起到至关重要的作用。
另外,薄膜晶体管是组成栅极驱动电路的基本元件,根据薄膜晶体管的制作材料分类可以将薄膜晶体管分为非晶硅(A-Si)薄膜晶体管、低温多晶硅(LTPS)薄膜晶体管和氧化物(IGZO)薄膜晶体管等,由于低温多晶硅薄膜晶体管和氧化物薄膜晶体管的迁移率远大于非晶硅薄膜晶体管,而低温多晶硅薄膜晶体管的迁移率比氧化物薄膜晶体管的迁移率更大,因此栅极驱动电路多采用低温多晶硅薄膜晶体管制作,但是由于低温多晶硅薄膜晶体管的漏电流较大,因此栅极驱动电路的上拉节点的电位在上拉阶段和触摸中停阶段容易由于与其连接的薄膜晶体管的漏电而无法维持稳定的高电位,导致触摸中停级的栅极驱动单元失效,使得显示面板出现分屏现象。
因此,需要提出一种新的栅极驱动电路,以解决上述由于栅极驱动电路的上拉节点漏电可能导致显示面板显示异常的问题。
由于低温多晶硅薄膜晶体管的漏电流较大,因此栅极驱动电路的上拉节点的电位在上拉阶段和触摸中停阶段容易由于与其连接的薄膜晶体管的漏电而无法维持稳定的高电位,导致触摸中停级的栅极驱动单元失效,使得显示面板出现分屏现象。
为了解决目前的栅极驱动电路由于上拉节点漏电可能导致显示面板显示异常的问题,本申请实施例提供一种栅极驱动电路及显示面板。
第一方面,本申请实施例提供一种栅极驱动电路,该栅极驱动电路包括级联的多个栅极驱动单元,每一级所述栅极驱动单元包括:上拉控制模块100和下拉模块300,其中:
所述上拉控制模块100连接第一节点Q,并连接正向扫描信号输出端、反向扫描信号输出端、第n-m级栅极驱动信号输出端以及第n+m级栅极驱动信号输出端,用于在所述正向扫描信号输出端输出的信号、所述反向扫描信号输出端输出的信号、所述第n-m级栅极驱动信号输出端输出的信号以及所述第n+m级栅极驱动信号输出端输出的信号的控制下,提高所述第一节点的电位;n和m均为正整数,且n>m;
所述下拉模块连接所述第一节点,并连接恒压低电位、第n+m条时钟信号输出端以及第n-m条时钟信号输出端,用于在所述恒压低电位、所述第n+m条时钟信号以及所述第n-m条时钟信号的控制下,拉低所述第一节点的电位;
其中,所述上拉控制模块中和/或所述下拉模块中分别与所述第一节点Q连接的薄膜晶体管采用氧化物薄膜晶体管。
在一些实施例中,所述上拉控制模块包括第一薄膜晶体管和第二薄膜晶体管,所述第一薄膜晶体管的栅极连接第n-m级栅极驱动信号输出端,所述第二薄膜晶体管的栅极连接第n+m级栅极驱动信号输出端,所述第一薄膜晶体管的源极连接正向扫描信号输出端,所述第二薄膜晶体管的源极连接反向扫描信号输出端,所述第一薄膜晶体管的漏极和所述第二薄膜晶体管的漏极均连接第一节点;其中,所述第一薄膜晶体管和所述第二薄膜晶体管为氧化物薄膜晶体管。
在一些实施例中,所述下拉模块包括第五薄膜晶体管和第六薄膜晶体管,所述第五薄膜晶体管的栅极连接第n+m条时钟信号输出端或第n-m条时钟信号输出端,所述第五薄膜晶体管的源极连接所述第一节点,所述第五薄膜晶体管的漏极连接所述第六薄膜晶体管的源极,所述第六薄膜晶体管的漏极连接恒压低电位;其中,所述第五薄膜晶体管为氧化物薄膜晶体管。
在一些实施例中,第n级所述栅极驱动单元还包括上拉模块,所述上拉模块包括第三薄膜晶体管和第四薄膜晶体管,所述第三薄膜晶体管的栅极连接恒压高电位,所述第三薄膜晶体管的源极连接所述第一节点,所述第三薄膜晶体管的漏极和所述第四薄膜晶体管的栅极均连接第四节点,所述第四薄膜晶体管的源极连接所述第n条时钟信号输出端,所述第四薄膜晶体管的漏极连接所述第n级栅极驱动信号输出端。
在一些实施例中,所述下拉模块还包括第十一薄膜晶体管,所述第十一薄膜晶体管的栅极连接第二节点,所述第十一薄膜晶体管的源极连接所述第n级栅极驱动信号输出端,所述第十一薄膜晶体管的漏极连接恒压低电位。
在一些实施例中,第n级所述栅极驱动单元还包括稳压模块,所述稳压模块包括第一电容和第二电容,其中,所述第一电容的一端连接所述第一节点,所述第二电容的一端连接所述第二节点,所述第一电容的另一端和所述第二电容的另一端均连接所述恒压低电位输出端。
在一些实施例中,第n级所述栅极驱动单元还包括栅极信号开启模块,所述栅极信号开启模块包括第十二薄膜晶体管、第十三薄膜晶体管和第十四薄膜晶体管,所述第十二薄膜晶体管的栅极和漏极、所述第十三薄膜晶体管的栅极,以及所述第十四薄膜晶体管的栅极均连接第一全局控制信号输出端,所述第十二薄膜晶体管的源极连接第四节点,所述第十三薄膜晶体管的源极和所述第十四薄膜晶体管的源极均连接第二节点,所述第十三薄膜晶体管的漏极和所述第十四薄膜晶体管的漏极均连接恒压低电位输出端。
在一些实施例中,第n级所述栅极驱动单元还包括栅极信号关闭模块,所述栅极信号关闭模块包括第十五薄膜晶体管,所述第十五薄膜晶体管的栅极连接第二全局控制信号输出端,所述第十五薄膜晶体管的源极连接第n级栅极信号输出端,所述第十五薄膜晶体管的漏极连接恒压低电位输出端。
第二方面,本申请实施例还提供一种栅极驱动电路,该栅极驱动包括级联的多个栅极驱动单元,第n级所述栅极驱动单元包括:第一薄膜晶体管、第二薄膜晶体管和第五薄膜晶体管,所述第一薄膜晶体管的栅极连接第n-m级栅极驱动信号输出端,所述第二薄膜晶体管的栅极连接第n+m级栅极驱动信号输出端,所述第一薄膜晶体管的源极连接正向扫描信号输出端,所述第二薄膜晶体管的源极连接反向扫描信号输出端,所述第一薄膜晶体管的漏极和所述第二薄膜晶体管的漏极均连接第一节点;所述第五薄膜晶体管的栅极连接第n+m条时钟信号输出端或第n-m条时钟信号输出端,所述第五薄膜晶体管的源极连接所述第一节点,其中,所述第一薄膜晶体管、所述第二薄膜晶体管和所述第五薄膜晶体管中的至少一个为氧化物薄膜晶体管。
在一些实施例中,第n级所述栅极驱动单元还包括:第n级所述栅极驱动单元还包括:第六薄膜晶体管,所述第六薄膜晶体管的栅极连接第二节点,所述第五薄膜晶体管的漏极连接所述第六薄膜晶体管的源极,所述第六薄膜晶体管的漏极连接恒压低电位。
在一些实施例中,第n级所述栅极驱动单元还包括:第三薄膜晶体管和第四薄膜晶体管,所述第三薄膜晶体管的栅极连接恒压高电位,所述第三薄膜晶体管的源极连接所述第一节点,所述第三薄膜晶体管的漏极和所述第四薄膜晶体管的栅极均连接第四节点,所述第四薄膜晶体管的源极连接所述第n条时钟信号输出端,所述第四薄膜晶体管的漏极连接所述第n级栅极驱动信号输出端。
在一些实施例中,第n级所述栅极驱动单元还包括:第十一薄膜晶体管,所述第十一薄膜晶体管的栅极连接第二节点,所述第十一薄膜晶体管的源极连接所述第n级栅极驱动信号输出端,所述第十一薄膜晶体管的漏极连接恒压低电位。
在一些实施例中,第n级所述栅极驱动单元还包括:第一电容和第二电容,其中,所述第一电容的一端连接所述第一节点,所述第二电容的一端连接所述第二节点,所述第一电容的另一端和所述第二电容的另一端均连接所述恒压低电位输出端。
在一些实施例中,第十二薄膜晶体管、第十三薄膜晶体管和第十四薄膜晶体管,所述第十二薄膜晶体管的栅极和漏极、所述第十三薄膜晶体管的栅极,以及所述第十四薄膜晶体管的栅极均连接第一全局控制信号输出端,所述第十二薄膜晶体管的源极连接第四节点,所述第十三薄膜晶体管的源极和所述第十四薄膜晶体管的源极均连接第二节点,所述第十三薄膜晶体管的漏极和所述第十四薄膜晶体管的漏极均连接恒压低电位输出端。
在一些实施例中,第十五薄膜晶体管,所述第十五薄膜晶体管的栅极连接第二全局控制信号输出端,所述第十五薄膜晶体管的源极连接第n级栅极信号输出端,所述第十五薄膜晶体管的漏极连接恒压低电位输出端。
第三方面,本申请实施例还提供一种显示面板,该显示面板包括如上任一实施例所述的栅极驱动电路。
在一些实施例中,所述栅极驱动电路包括级联的多个栅极驱动单元,第n级所述栅极驱动单元包括:第一薄膜晶体管、第二薄膜晶体管和第五薄膜晶体管,所述第一薄膜晶体管的栅极连接第n-m级栅极驱动信号输出端,所述第二薄膜晶体管的栅极连接第n+m级栅极驱动信号输出端,所述第一薄膜晶体管的源极连接正向扫描信号输出端,所述第二薄膜晶体管的源极连接反向扫描信号输出端,所述第一薄膜晶体管的漏极和所述第二薄膜晶体管的漏极均连接第一节点;所述第五薄膜晶体管的栅极连接第n+m条时钟信号输出端或第n-m条时钟信号输出端,所述第五薄膜晶体管的源极连接所述第一节点,其中,所述第一薄膜晶体管、所述第二薄膜晶体管和所述第五薄膜晶体管中的至少一个为氧化物薄膜晶体管。
在一些实施例中,第n级所述栅极驱动单元还包括:第六薄膜晶体管,所述第六薄膜晶体管的栅极连接第二节点,所述第五薄膜晶体管的漏极连接所述第六薄膜晶体管的源极,所述第六薄膜晶体管的漏极连接恒压低电位。
在一些实施例中,第n级所述栅极驱动单元还包括:第三薄膜晶体管和第四薄膜晶体管,所述第三薄膜晶体管的栅极连接恒压高电位,所述第三薄膜晶体管的源极连接所述第一节点,所述第三薄膜晶体管的漏极和所述第四薄膜晶体管的栅极均连接第四节点,所述第四薄膜晶体管的源极连接第n条时钟信号输出端,所述第四薄膜晶体管的漏极连接第n级栅极驱动信号输出端。
在一些实施例中,第n级所述栅极驱动单元还包括:第十一薄膜晶体管,所述第十一薄膜晶体管的栅极连接第二节点,所述第十一薄膜晶体管的源极连接所述第n级栅极驱动信号输出端,所述第十一薄膜晶体管的漏极连接恒压低电位。
本申请实施例提供的栅极驱动电路及显示面板中,每一级栅极驱动单元的上拉控制模块和下拉模块分别与第一节点连接,其中,上拉控制模块和/或下拉模块中与第一节点连接的薄膜晶体管采用氧化物薄膜晶体管,从而利用氧化物薄膜晶体管的关态漏电流小的特点减少第一节点的漏电流,使得第一节点的电位在上拉阶段和触摸中停阶段保持稳定,防止显示面板由于第一节点的电位不稳定而出现画面异常的现象。
图1为本申请实施例提供的栅极驱动电路的电路示意图;
图2为本申请实施例提供的栅极驱动电路的第一种时序示意图;
图3为本申请实施例提供的栅极驱动电路的第二种时序示意图;
图4为本申请实施例提供的栅极驱动电路的第三种时序示意图;
图5为本申请实施例提供的显示面板的第一种结构示意图;
图6为本申请实施例提供的显示面板的第二种结构示意图。
为使本申请的目的、技术方案及效果更加清楚、明确,以下参照附图并举实施例对本申请进一步详细说明。应当理解,此处所描述的具体实施例仅用以解释本申请,并不用于限定本申请。
参考图1,图1为本申请实施例提供的栅极驱动电路的电路示意图,本申请实施例提供一种栅极驱动电路,该栅极驱动电路包括级联的多个栅极驱动单元,每一级栅极驱动单元包括:上拉控制模块100和下拉模块300。
上拉控制模块100连接第一节点Q,并连接正向扫描信号U2D输出端、反向扫描信号D2U输出端、第n-m级栅极驱动信号G(n-m)输出端以及第n+m级栅极驱动信号G(n+m)输出端,用于在正向扫描信号U2D、反向扫描信号D2U、第n-m级栅极驱动信号G(n-m)、以及第n+m级栅极驱动信号G(n+m)的控制下,提高第一节点Q的电位;n和m均为正整数;n和m均为正整数,且n>m;
具体地,上拉控制模块100连接第一节点Q,并连接正向扫描信号U2D输出端和第n-m级栅极驱动信号G(n-m)输出端,或者连接反向扫描信号D2U输出端和第n+m级栅极驱动信号G(n+m)输出端,用于在第n-m级栅极驱动信号G(n-m)的控制下,通过正向扫描信号U2D提高第一节点Q的电位,或者在第n+m级栅极驱动信号G(n+m)的控制下,通过反向扫描信号D2U提高第一节点Q的电位。
进一步地,下拉模块300连接第一节点Q和恒压低电位VGL,以及第n+m条时钟信号CK(n+m)输出端或第n-m条时钟信号CK(n-m)输出端,用于在第n+m条时钟信号CK(n+m)或第n-m条时钟信号CK(n-m)的控制下,通过恒压低电位VGL拉低第一节点Q的电位;
其中,上拉控制模块100中和/或下拉模块300中分别与第一节点Q连接的薄膜晶体管采用氧化物薄膜晶体管。
本申请实施例提供的栅极驱动电路,每一级栅极驱动单元的上拉控制模块100和下拉模块300分别与第一节点Q连接,其中,上拉控制模块100和/或下拉模块300中与第一节点Q连接的薄膜晶体管采用氧化物薄膜晶体管,从而利用氧化物薄膜晶体管的关态漏电流小的特点减少第一节点Q的漏电流,使得第一节点Q的电位在上拉阶段和触摸中停阶段保持稳定,防止显示面板由于第一节点Q的电位不稳定而出现画面异常的现象。
进一步地,上拉控制模块100包括第一薄膜晶体管T1和第二薄膜晶体管T2,第一薄膜晶体管T1的栅极连接第n-m级栅极驱动信号G(n-m)输出端,第二薄膜晶体管T2的栅极连接第n+m级栅极驱动信号G(n+m)输出端,第一薄膜晶体管T1的源极连接正向扫描信号U2D输出端,第二薄膜晶体管T2的源极连接反向扫描信号D2U输出端,第一薄膜晶体管T1的漏极和第二薄膜晶体管T2的漏极均连接第一节点Q;n和m均为正整数,且n>m。其中,正向扫描信号U2D和反向扫描信号D2U的相位相反,即正向扫描信号U2D和反向扫描信号D2U中的一个为高电位且另一个为低电位。
进一步地,下拉模块300包括第五薄膜晶体管T5和第六薄膜晶体管T6,第五薄膜晶体管T5的栅极连接第n+m条时钟信号CK(n+m)输出端(正向扫描时)或第n-m条时钟信号CK(n-m)输出端(反向扫描时),第五薄膜晶体管T5的源极连接第一节点Q,第五薄膜晶体管T5的漏极连接第六薄膜晶体管T6的源极,第六薄膜晶体管T6的漏极连接恒压低电位VGL。
其中,第一薄膜晶体管T1、第二薄膜晶体管T2和第五薄膜晶体管T5中的至少一个为氧化物薄膜晶体管。
本申请实施例提供的栅极驱动电路中,上拉控制模块100中的第一薄膜晶体管T1和第二薄膜晶体管T2分别与第一节点Q连接,下拉模块300中的第五薄膜晶体管T5与第一节点Q连接,将第一薄膜晶体管T1、第二薄膜晶体管T2和第五薄膜晶体管T5中的至少一个采用氧化物薄膜晶体管,从而利用氧化物薄膜晶体管的关态漏电流较小而减少第一节点Q的漏电流。另外,第五薄膜晶体管T5的栅极连接第n+m条时钟信号CK(n+m)输出端或第n-m条时钟信号CK(n-m)输出端,从而使得第五薄膜晶体管T5的栅极不会像第六薄膜晶体管T6的栅极连接第二节点P那样长期保持高电位而受到应力影响,由此增强第五薄膜晶体管T5的稳定,从而提高第一节点Q的稳定性,以提高该栅极驱动电路的稳定性。
可以理解的是,第一薄膜晶体管T1、第二薄膜晶体管T2和第五薄膜晶体管T5中的至少一个为氧化物薄膜晶体管,即可以选择第一薄膜晶体管T1、第二薄膜晶体管T2和第五薄膜晶体管T5中的任意一个为氧化物薄膜晶体管,或者任意两个为氧化物薄膜晶体管,或者全部为氧化物薄膜晶体管,从而根据氧化物薄膜晶体管在关态下的漏电流较小,减小第一节点Q的漏电流,使得第一节点Q的电位保持稳定。
需要说明的是,低温多晶氧化物(LTPO)技术由于结合了LTPS和IGZO两种技术的优点,使得显示面板同时具有强驱动能力和低功耗的特点,同时满足高频和低频的使用需求,因此LTPO技术适用于动态帧频技术的需求,能达到提升用户视觉体验并且优化功耗的目的。因此,本申请实施例提供的栅极驱动电路除了第一薄膜晶体管T1、第二薄膜晶体管T2和第五薄膜晶体管T5中的至少一个为氧化物薄膜晶体管以外,其余薄膜晶体管均可以采用低温多晶硅氧化物,从而基于低温多晶氧化物技术,结合氧化物薄膜晶体管和多晶硅氧化物的优点,使得该栅极驱动电路在实现减少第一节点Q的漏电流的效果之外,还能提高该栅极驱动电路的驱动能力,使得该栅极驱动电路能满足同时满足高频与低频的使用需求。
还需要说明的是,薄膜晶体管按照电学特性分类可以分为N型薄膜晶体管和P型薄膜晶体管,其中,由于N型薄膜晶体管的载流子(多子)为电子,而P型薄膜晶体管的载流子(多子)为空穴,因此,N型薄膜晶体管的迁移率比P型薄膜晶体管的迁移率高;另外,N型薄膜晶体管可以用正电压开启,而P型薄膜晶体管需要用负电压开启,因此从控制角度来说,N型薄膜晶体管比P型薄膜晶体管方便。基于上述两点,目前的栅极驱动电路多采用N型薄膜晶体管制作。但是,N型薄膜晶体管的稳定性比P型薄膜晶体管的稳定性低,因此在高温环境下N型薄膜晶体管没有P型薄膜晶体管稳定性好,即N型薄膜晶体管在高温环境下的电学特性更容易产生改变,使得漏电流增大,因此,本申请实施例提供的栅极驱动电路尤其适用于采用N型薄膜晶体管制作的栅极驱动电路,特别是与第一节点Q连接的薄膜晶体管为N型薄膜晶体管的栅极驱动电路,即本申请实施例提供的栅极驱动电路中,第一薄膜晶体管T1、第二薄膜晶体管T2和第五薄膜晶体管T5中采用氧化物薄膜晶体管的薄膜晶体管为N型薄膜晶体管的情况。
在一些实施例中,第n级所述栅极驱动单元还包括上拉模块200,上拉模块200包括第三薄膜晶体管T3和第四薄膜晶体管T4,第三薄膜晶体管T3的栅极连接恒压高电位VGH,第三薄膜晶体管T3的源极连接第一节点Q,第三薄膜晶体管T3的漏极和第四薄膜晶体管T4的栅极均连接第四节点M,第四薄膜晶体管T4的源极连接第n条时钟信号CK(n)输出端,第四薄膜晶体管T4的漏极连接第n级栅极驱动信号G(n)输出端。其中,第三薄膜晶体管T3的作用是为了防止第三节点K的高电位被倒灌到第一节点Q而使得第三节点K的电位降低,从而使第三节点K的电位保持稳定。
在一些实施例中,第n级所述栅极驱动单元还包括正反扫描模块400,正反扫描模块400包括第七薄膜晶体管T7和第八薄膜晶体管T8,其中,第七薄膜晶体管T7的栅极连接正向扫描信号U2D输出端,第八薄膜晶体管T8的栅极连接反向扫描模块输出端,第七薄膜晶体管T7的源极连接第n+m条时钟信号CK(n+m)输出端,第八薄膜晶体管T8的源极连接第n-m条时钟信号CK(n-m)输出端,第七薄膜晶体管T7的漏极和第八薄膜晶体管T8的漏极均连接第三节点K。
需要说明的是,栅极驱动电路若采用正向扫描,则由第一级栅极驱动单元从前到后对像素行进行扫描,若采用反向扫描,则由最后一级栅极驱动单元从后到前对像素行进行扫描。
可以理解的是,该栅极驱动电路正向扫描时,第一级栅极驱动单元的第一薄膜晶体管T1的栅极连接起始信号输出端;反向扫描时,最后一级栅极驱动单元的第二薄膜晶体管T2的栅极连接起始信号输出端。
在一些实施例中,第n级所述栅极驱动单元还包括下拉控制模块500,下拉控制模块500包括第九薄膜晶体管T9和第十薄膜晶体管T10,其中,第九薄膜晶体管T9的栅极连接第三节点K,第九薄膜晶体管T9的源极连接恒压高电位VGH,第九薄膜晶体管T9的漏极和第十薄膜晶体管T10的源极连接第二节点P,第十薄膜晶体管T10的栅极连接第一节点Q,第十薄膜晶体管T10的漏极连接恒压低电位VGL。
在一些实施例中,下拉模块300还包括第十一薄膜晶体管T11,第十一薄膜晶体管T11的栅极连接第二节点P,第十一薄膜晶体管T11的源极连接第n级栅极驱动信号G(n)输出端,第十薄膜晶体管T10的漏极连接恒压低电位VGL。
在一些实施例中,第n级所述栅极驱动单元还包括稳压模块600,稳压模块600包括第一电容C1和第二电容C2,其中,第一电容C1的一端连接第一节点Q,第二电容C2的一端连接第二节点P,第一电容C1的另一端和第二电容C2的另一端均连接恒压低电位VGL。
需要说明的是,该栅极驱动电路中,每连续的m个栅极驱动单元组成最小重复单元,例如可以为第n-m级栅极驱动单元到第n级栅极驱动单元组成一个最小重复单元。
进一步地,参考图1,第n级所述栅极驱动单元还包括栅极信号开启模块700,栅极信号开启模块700的作用是打开栅极驱动电路的所有栅极驱动单元输出的栅极驱动信号,从而去除残存电荷,使得显示面板开机或关机时不会出现残影,还可以在显示面板开机时将所有像素充电到中间电压,以便能迅速反应开机后的第一个显示画面,提高用户观感。
具体地,栅极信号开启模块700包括第十二薄膜晶体管T12、第十三薄膜晶体管T13和第十四薄膜晶体管T14,第十二薄膜晶体管T12的栅极和漏极、第十三薄膜晶体管T13的栅极,以及第十四薄膜晶体管T14的栅极均连接第一全局控制信号GAS1输出端,第十二薄膜晶体管T12的源极连接第四节点M,第十三薄膜晶体管T13的源极和第十四薄膜晶体管T14的源极均连接第二节点P,第十三薄膜晶体管T13的漏极和第十四薄膜晶体管T14的漏极均连接恒压低电位VGL。
进一步地,参考图1,第n级所述栅极驱动单元还包括栅极信号关闭模块800,栅极信号关闭模块800的作用是在正常显示阶段A的过程中插入触控扫描阶段B以对触控信号进行侦测和采集,此时需要关闭栅极驱动电路的所有栅极驱动单元输出的栅极驱动信号,待触控信号侦测和采集完毕之后再由触控中停级栅极驱动单元的栅极驱动信号开始继续逐级输出栅极驱动信号。
具体地,栅极信号关闭模块800包括第十五薄膜晶体管T15,第十五薄膜晶体管T15的栅极连接第二全局控制信号GAS2输出端,第十五薄膜晶体管T15的源极连接第n级栅极驱动信号G(n)输出端,第十五薄膜晶体管T15的漏极连接恒压低电位VGL。
基于上述实施例,图2、图3和图4分别为本申请实施例提供的栅极驱动电路的时序示意图,结合图1-图4,以下对该栅极驱动电路的第n级栅极驱动单元的工作过程进行详细说明。为了方便说明,以该栅极驱动电路中的薄膜晶体管均采用N型薄膜晶体管,且该栅极驱动电路采用正向扫描为例。
具体地,该栅极驱动电路包括正常显示阶段A和触控扫描阶段B,触控扫描阶段B穿插在正常显示阶段A之间,即在正常显示阶段A,如果收到触摸信号,则各显示信号中停并进行触控扫描,待触控扫描完毕之后再继续输入各显示信号。
其中,正常显示阶段A包括预充子阶段t1、输出子阶段t2和下拉子阶段t3。
在预充子阶段t1,第n-m级栅极驱动信号G(n-m)为高电平使第一薄膜晶体管T1打开,正向扫描信号U2D为高电平使提高第一节点Q和第四节点M的电位,并使得第一电容C1被充电。此时,第一节点Q使第十薄膜晶体管T10打开,从而使第二节点P为恒压低电位VGL,进而使第六薄膜晶体管T6和第十薄膜晶体管T10关闭。
若此时进入触控扫描阶段B,则如图2所示,第二全局控制信号GAS2为高电位,使栅极驱动信号均为低电位,同时各显示信号处于中停状态,此时第二薄膜晶体管T2和第五薄膜晶体管T5处于关闭状态,由于第二薄膜晶体管T2和第五薄膜晶体管T5采用氧化物薄膜晶体管,因此第二薄膜晶体管T2和第五薄膜晶体管T5的关态漏电流较小,可以使第一节点Q的电位保持较为稳定的高电位状态。待触控扫描结束之后,进入输出子阶段t2。
在输出子阶段t2,第n-m级栅极驱动信号G(n-m)为低电平使第一薄膜晶体管T1关闭,第一电容C1使第一节点Q保持高电位,从而使第三节点K也为高电位,使第四薄膜晶体管T4打开,同时第n条时钟信号CK(n)为高电位,使第三节点M的电位进一步升高到更高电位,并使第n级栅极驱动信号G(n)为高电位。此时,第一节点Q使第十薄膜晶体管T10保持打开,从而使第二节点P保持为恒压低电位VGL,进而使第六薄膜晶体管T6和第十薄膜晶体管T10保持关闭。
若此时进入触控扫描阶段B,则如图3所示,第二全局控制信号GAS2为高电位,使栅极驱动信号均为低电位,同时各显示信号处于中停状态,此时第一薄膜晶体管T1、第二薄膜晶体管T2和第五薄膜晶体管T5处于关闭状态,由于第一薄膜晶体管T1、第二薄膜晶体管T2和第五薄膜晶体管T5采用氧化物薄膜晶体管,因此第一薄膜晶体管T1、第二薄膜晶体管T2和第五薄膜晶体管T5的关态漏电流较小,可以使第一节点Q的电位保持较为稳定的高电位状态。待触控扫描结束之后,进入下拉子阶段t3。
在下拉子阶段t3,第n+m条时钟信号CK(n+m)为高电位提高第三节点K的电位并使第五薄膜晶体管T5打开,第三节点K为高电位使第九薄膜晶体管T9打开,从而提高第二节点P的电位并使得第二电容C2被充电,第二节点P使第六薄膜晶体管T6和第十一薄膜晶体管T11打开,此时第五薄膜晶体管T5和第六薄膜晶体管T6拉低第一节点Q的电位,第十一薄膜晶体管T11拉低第n级栅极驱动信号G(n)的电位,第二电容C2维持第二节点P保持低电位。
若此时进入触控扫描阶段B,则如图4所示,第二全局控制信号GAS2为高电位,使栅极驱动信号均为低电位。同时各显示信号处于中停状态,此时第一薄膜晶体管T1和第二薄膜晶体管T2处于关闭状态,由于第一薄膜晶体管T1和第二薄膜晶体管T2采用氧化物薄膜晶体管,因此第一薄膜晶体管T1和第二薄膜晶体管T2的关态漏电流较小,可以使第一节点Q的电位保持较为稳定的低电位状态,待触控扫描结束之后,进入第n级栅极驱动信号的下一级栅极驱动信号即第n+m级栅极驱动信号的输出过程。
基于上述实施例,本申请实施例还提供一种显示面板,该显示面板1包括如上所述的栅极驱动电路2,该显示面板1具有与前述实施例提供的栅极驱动电路2相同的结构和有益效果。由于前述实施例已经对该栅极驱动电路2的结构和有益效果进行了详细的描述,此处不再赘述。
需要说明的是,对于小尺寸的显示面板,如图5所示,可以仅在显示面板1的一侧设置栅极驱动电路2,而对于中大尺寸的显示面板,如图6所示,可以在显示面板1的相对两侧分别设置栅极驱动电路2。
可以理解的是,对本领域普通技术人员来说,可以根据本申请的技术方案及其发明构思加以等同替换或改变,而所有这些改变或替换都应属于本申请所附的权利要求的保护范围。
Claims (20)
- 一种栅极驱动电路,其包括级联的多个栅极驱动单元,第n级所述栅极驱动单元包括:上拉控制模块和下拉模块;所述上拉控制模块连接第一节点,并连接正向扫描信号输出端、反向扫描信号输出端、第n-m级栅极驱动信号输出端以及第n+m级栅极驱动信号输出端,用于在所述正向扫描信号输出端输出的信号、所述反向扫描信号输出端输出的信号、所述第n-m级栅极驱动信号输出端输出的信号以及所述第n+m级栅极驱动信号输出端输出的信号的控制下,提高所述第一节点的电位;n和m均为正整数,且n>m;所述下拉模块连接所述第一节点,并连接恒压低电位、第n+m条时钟信号输出端以及第n-m条时钟信号输出端,用于在所述恒压低电位、所述第n+m条时钟信号以及所述第n-m条时钟信号的控制下,拉低所述第一节点的电位;其中,所述上拉控制模块中和/或所述下拉模块中分别与所述第一节点连接的薄膜晶体管为氧化物薄膜晶体管。
- 如权利要求1所述的栅极驱动电路,其中,所述上拉控制模块包括第一薄膜晶体管和第二薄膜晶体管,所述第一薄膜晶体管的栅极连接第n-m级栅极驱动信号输出端,所述第二薄膜晶体管的栅极连接第n+m级栅极驱动信号输出端,所述第一薄膜晶体管的源极连接正向扫描信号输出端,所述第二薄膜晶体管的源极连接反向扫描信号输出端,所述第一薄膜晶体管的漏极和所述第二薄膜晶体管的漏极均连接第一节点;其中,所述第一薄膜晶体管和所述第二薄膜晶体管为氧化物薄膜晶体管。
- 如权利要求1所述的栅极驱动电路,其中,所述下拉模块包括第五薄膜晶体管和第六薄膜晶体管,所述第五薄膜晶体管的栅极连接第n+m条时钟信号输出端或第n-m条时钟信号输出端,所述第五薄膜晶体管的源极连接所述第一节点,所述第五薄膜晶体管的漏极连接所述第六薄膜晶体管的源极,所述第六薄膜晶体管的漏极连接恒压低电位;其中,所述第五薄膜晶体管为氧化物薄膜晶体管。
- 如权利要求1所述的栅极驱动电路,其中,第n级所述栅极驱动单元还包括上拉模块,所述上拉模块包括第三薄膜晶体管和第四薄膜晶体管,所述第三薄膜晶体管的栅极连接恒压高电位,所述第三薄膜晶体管的源极连接所述第一节点,所述第三薄膜晶体管的漏极和所述第四薄膜晶体管的栅极均连接第四节点,所述第四薄膜晶体管的源极连接第n条时钟信号输出端,所述第四薄膜晶体管的漏极连接第n级栅极驱动信号输出端。
- 如权利要求4所述的栅极驱动电路,其中,所述下拉模块还包括第十一薄膜晶体管,所述第十一薄膜晶体管的栅极连接第二节点,所述第十一薄膜晶体管的源极连接所述第n级栅极驱动信号输出端,所述第十一薄膜晶体管的漏极连接恒压低电位。
- 如权利要求5所述的栅极驱动电路,其中,第n级所述栅极驱动单元还包括稳压模块,所述稳压模块包括第一电容和第二电容,其中,所述第一电容的一端连接所述第一节点,所述第二电容的一端连接所述第二节点,所述第一电容的另一端和所述第二电容的另一端均连接所述恒压低电位输出端。
- 如权利要求1所述的栅极驱动电路,其中,第n级所述栅极驱动单元还包括栅极信号开启模块,所述栅极信号开启模块包括第十二薄膜晶体管、第十三薄膜晶体管和第十四薄膜晶体管,所述第十二薄膜晶体管的栅极和漏极、所述第十三薄膜晶体管的栅极,以及所述第十四薄膜晶体管的栅极均连接第一全局控制信号输出端,所述第十二薄膜晶体管的源极连接第四节点,所述第十三薄膜晶体管的源极和所述第十四薄膜晶体管的源极均连接第二节点,所述第十三薄膜晶体管的漏极和所述第十四薄膜晶体管的漏极均连接恒压低电位输出端。
- 如权利要求1所述的栅极驱动电路,其中,第n级所述栅极驱动单元还包括栅极信号关闭模块,所述栅极信号关闭模块包括第十五薄膜晶体管,所述第十五薄膜晶体管的栅极连接第二全局控制信号输出端,所述第十五薄膜晶体管的源极连接第n级栅极信号输出端,所述第十五薄膜晶体管的漏极连接恒压低电位输出端。
- 一种栅极驱动电路,其包括级联的多个栅极驱动单元,第n级所述栅极驱动单元包括:第一薄膜晶体管、第二薄膜晶体管和第五薄膜晶体管,所述第一薄膜晶体管的栅极连接第n-m级栅极驱动信号输出端,所述第二薄膜晶体管的栅极连接第n+m级栅极驱动信号输出端,所述第一薄膜晶体管的源极连接正向扫描信号输出端,所述第二薄膜晶体管的源极连接反向扫描信号输出端,所述第一薄膜晶体管的漏极和所述第二薄膜晶体管的漏极均连接第一节点;所述第五薄膜晶体管的栅极连接第n+m条时钟信号输出端或第n-m条时钟信号输出端,所述第五薄膜晶体管的源极连接所述第一节点,其中,所述第一薄膜晶体管、所述第二薄膜晶体管和所述第五薄膜晶体管中的至少一个为氧化物薄膜晶体管。
- 如权利要求9所述的栅极驱动电路,其中,第n级所述栅极驱动单元还包括:第六薄膜晶体管,所述第六薄膜晶体管的栅极连接第二节点,所述第五薄膜晶体管的漏极连接所述第六薄膜晶体管的源极,所述第六薄膜晶体管的漏极连接恒压低电位。
- 如权利要求9所述的栅极驱动电路,其中,第n级所述栅极驱动单元还包括:第三薄膜晶体管和第四薄膜晶体管,所述第三薄膜晶体管的栅极连接恒压高电位,所述第三薄膜晶体管的源极连接所述第一节点,所述第三薄膜晶体管的漏极和所述第四薄膜晶体管的栅极均连接第四节点,所述第四薄膜晶体管的源极连接第n条时钟信号输出端,所述第四薄膜晶体管的漏极连接第n级栅极驱动信号输出端。
- 如权利要求9所述的栅极驱动电路,其中,第n级所述栅极驱动单元还包括:第十一薄膜晶体管,所述第十一薄膜晶体管的栅极连接第二节点,所述第十一薄膜晶体管的源极连接所述第n级栅极驱动信号输出端,所述第十一薄膜晶体管的漏极连接恒压低电位。
- 如权利要求12所述的栅极驱动电路,其中,第n级所述栅极驱动单元还包括:第一电容和第二电容,其中,所述第一电容的一端连接所述第一节点,所述第二电容的一端连接所述第二节点,所述第一电容的另一端和所述第二电容的另一端均连接所述恒压低电位输出端。
- 如权利要求9所述的栅极驱动电路,其中,第十二薄膜晶体管、第十三薄膜晶体管和第十四薄膜晶体管,所述第十二薄膜晶体管的栅极和漏极、所述第十三薄膜晶体管的栅极,以及所述第十四薄膜晶体管的栅极均连接第一全局控制信号输出端,所述第十二薄膜晶体管的源极连接第四节点,所述第十三薄膜晶体管的源极和所述第十四薄膜晶体管的源极均连接第二节点,所述第十三薄膜晶体管的漏极和所述第十四薄膜晶体管的漏极均连接恒压低电位输出端。
- 如权利要求9所述的栅极驱动电路,其中,第十五薄膜晶体管,所述第十五薄膜晶体管的栅极连接第二全局控制信号输出端,所述第十五薄膜晶体管的源极连接第n级栅极信号输出端,所述第十五薄膜晶体管的漏极连接恒压低电位输出端。
- 一种显示面板,其包括权利要求1-15任一项所述的栅极驱动电路。
- 如权利要求16所述的显示面板,其中,所述栅极驱动电路包括级联的多个栅极驱动单元,第n级所述栅极驱动单元包括:第一薄膜晶体管、第二薄膜晶体管和第五薄膜晶体管,所述第一薄膜晶体管的栅极连接第n-m级栅极驱动信号输出端,所述第二薄膜晶体管的栅极连接第n+m级栅极驱动信号输出端,所述第一薄膜晶体管的源极连接正向扫描信号输出端,所述第二薄膜晶体管的源极连接反向扫描信号输出端,所述第一薄膜晶体管的漏极和所述第二薄膜晶体管的漏极均连接第一节点;所述第五薄膜晶体管的栅极连接第n+m条时钟信号输出端或第n-m条时钟信号输出端,所述第五薄膜晶体管的源极连接所述第一节点,其中,所述第一薄膜晶体管、所述第二薄膜晶体管和所述第五薄膜晶体管中的至少一个为氧化物薄膜晶体管。
- 如权利要求16所述的显示面板,其中,第n级所述栅极驱动单元还包括:第六薄膜晶体管,所述第六薄膜晶体管的栅极连接第二节点,所述第五薄膜晶体管的漏极连接所述第六薄膜晶体管的源极,所述第六薄膜晶体管的漏极连接恒压低电位。
- 如权利要求16所述的显示面板,其中,第n级所述栅极驱动单元还包括:第三薄膜晶体管和第四薄膜晶体管,所述第三薄膜晶体管的栅极连接恒压高电位,所述第三薄膜晶体管的源极连接所述第一节点,所述第三薄膜晶体管的漏极和所述第四薄膜晶体管的栅极均连接第四节点,所述第四薄膜晶体管的源极连接第n条时钟信号输出端,所述第四薄膜晶体管的漏极连接第n级栅极驱动信号输出端。
- 如权利要求19所述的显示面板,其中,第n级所述栅极驱动单元还包括:第十一薄膜晶体管,所述第十一薄膜晶体管的栅极连接第二节点,所述第十一薄膜晶体管的源极连接所述第n级栅极驱动信号输出端,所述第十一薄膜晶体管的漏极连接恒压低电位。
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