WO2023097477A1 - 移位寄存器单元、栅极驱动电路及显示装置 - Google Patents

移位寄存器单元、栅极驱动电路及显示装置 Download PDF

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Publication number
WO2023097477A1
WO2023097477A1 PCT/CN2021/134504 CN2021134504W WO2023097477A1 WO 2023097477 A1 WO2023097477 A1 WO 2023097477A1 CN 2021134504 W CN2021134504 W CN 2021134504W WO 2023097477 A1 WO2023097477 A1 WO 2023097477A1
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WIPO (PCT)
Prior art keywords
pole
transistor
pull
subcircuit
node
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PCT/CN2021/134504
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English (en)
French (fr)
Inventor
林允植
张舜航
李付强
李昌峰
刘立伟
胡合合
宁策
张慧
王洪润
李卓
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2021/134504 priority Critical patent/WO2023097477A1/zh
Priority to CN202180003682.XA priority patent/CN116802736A/zh
Priority to US17/996,293 priority patent/US20240221851A1/en
Publication of WO2023097477A1 publication Critical patent/WO2023097477A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the disclosure belongs to the field of display technology, and in particular relates to a shift register unit, a gate drive circuit and a display device.
  • GOA Gate Driver on Array, integrated gate drive circuit
  • COF Chip On Film, chip-on-film
  • COG Chip On Glass
  • the chip is directly fixed on the glass) process, which not only saves the cost, but also can achieve a symmetrical and beautiful design on both sides of the panel, and can also save the Bonding (pressure welding) area of the gate drive circuit and the peripheral wiring space, thereby realizing
  • the design of the narrow frame of the display device improves the production capacity and yield rate of the display device.
  • the active layer material of the thin film transistor used in the GOA circuit can be a-Si (amorphous silicon), LTPS (low temperature polysilicon), metal oxide semiconductor, such as a typical material IGZO (Indium Gallium Zinc Oxide, Indium Gallium Zinc Oxide) wait.
  • metal oxide transistors such as thin-film transistors whose active layer material is IGZO
  • IGZO Indium Gallium Zinc Oxide
  • GOA circuits usually use metal oxide transistors (such as thin-film transistors whose active layer material is IGZO) as thin-film transistors in the GOA circuit, but when the size and resolution of the display are further increased, it is necessary to use higher mobility Oxide material thin film transistors are used in GOA circuits.
  • the threshold voltage of the thin film transistor is unstable, and negative bias fluctuations are prone to occur, causing the thin film transistor to generate leakage current, which affects the working performance of the GOA circuit, and causes the display panel driven to be prone to poor display. question.
  • the present disclosure aims to solve at least one of the technical problems existing in the prior art, and provides a shift register unit, a gate driving circuit and a display device.
  • an embodiment of the present disclosure provides a shift register unit, wherein the shift register unit includes: an input subcircuit, an output subcircuit, at least one pull-down control subcircuit, at least one pull-down subcircuit, at least one first a noise reduction subcircuit and a reverse bias subcircuit;
  • the input subcircuit is configured to pull up the potential of the pull-up node through the input signal in response to the input signal at the signal input terminal; the pull-up node is at least simultaneously connected to the input subcircuit and the output subcircuit , the first noise reduction sub-circuit;
  • the output subcircuit is configured to output a signal through a signal output terminal and output a signal through a cascaded signal terminal in response to the potential of the pull-up node being pulled high;
  • the pull-down control subcircuit is configured to use the power supply voltage signal to control the potential of the pull-down node in response to the power supply voltage signal; the pull-down node is at least simultaneously connected to the pull-down control subcircuit, the pull-down subcircuit and the first a noise reduction sub-circuit;
  • the pull-down subcircuit is configured to pull down the potential of the pull-down node through a first reference level signal in response to the potential of the pull-up node and the signal input terminal;
  • the first noise reduction sub-circuit is configured to denoise the potential of the pull-up node through a first reference level signal in response to the potential of the pull-down node;
  • the reverse bias sub-circuit is configured to control at least some of the transistors in the sub-circuits connected to the pull-up node to be in a reverse bias state through a power supply voltage signal in response to the potential of the pull-up node; or, in response to At the potential of the cascade signal terminal, the transistors in at least part of the sub-circuits connected to the pull-up node are controlled by the cascade signal to be in a reverse bias state.
  • the reverse bias subcircuit includes: a reverse bias control transistor
  • the control electrode of the reverse bias control transistor is connected to the pull-up node, the first electrode is connected to the power supply voltage terminal, and the second electrode is connected to the input sub-circuit and the first noise reduction sub-circuit.
  • the reverse bias subcircuit includes: a reverse bias control transistor
  • control pole and the first pole of the reverse bias control transistor are both connected to the cascaded signal terminal, and the second pole is connected to the input sub-circuit and the first noise reduction sub-circuit.
  • the input subcircuit includes: at least two first transistors;
  • the control poles of the two first transistors are connected to the signal input terminal, the first pole of one of the first transistors is connected to the signal input terminal, and the second pole is connected to the first pole of the other first transistor. pole and the reverse bias subcircuit, and the second pole of the other first transistor is connected to the pull-up node.
  • the first noise reduction sub-circuit includes: at least two eighth transistors;
  • the control poles of the two eighth transistors are connected to the pull-down node, the first pole of one of the eighth transistors is connected to the first reference level terminal, and the second pole is connected to the first pole of the other eighth transistor and the reverse bias subcircuit, the second pole of the other eighth transistor is connected to the pull-up node.
  • the shift register unit further includes: a first reset subcircuit
  • the first reset subcircuit is configured to reset the potential of the pull-up node through a first reference level signal in response to a reset signal.
  • the first reset subcircuit includes: at least two second transistors;
  • the control poles of the two second transistors are connected to the reset signal terminal, the first pole of one of the second transistors is connected to the first reference level terminal, and the second pole is connected to the first pole of the other second transistor and In the reverse bias subcircuit, the second pole of the other second transistor is connected to the pull-up node.
  • the shift register unit further includes: a shift reset subcircuit
  • the shift reset subcircuit is configured to reset the potential of the pull-up node through a first reference level signal in response to a shift reset signal.
  • the shift reset subcircuit includes: at least two fifteenth transistors;
  • the control poles of the two fifteenth transistors are connected to the shift reset signal terminal, the first pole of one of the fifteenth transistors is connected to the first reference level terminal, and the second pole is connected to the other fifteenth transistor.
  • the first electrode of the transistor is connected to the reverse bias sub-circuit, and the second electrode of the other fifteenth transistor is connected to the pull-up node.
  • the shift register unit further includes: a second reset subcircuit
  • the second reset subcircuit is configured to reset the potential of the signal output terminal through a second reference level signal in response to the reset signal.
  • the second reset subcircuit includes: a fourth transistor
  • the control pole of the fourth transistor is connected to the reset signal terminal, the first pole is connected to the second reference level terminal, and the second pole is connected to the signal output terminal.
  • the shift register unit further includes: at least one second noise reduction sub-circuit;
  • the second denoising sub-circuit is configured to denoise the potential of the signal output terminal through a second reference level signal in response to the potential of the pull-down node.
  • the second noise reduction sub-circuit includes: a thirteenth transistor
  • the control pole of the thirteenth transistor is connected to the pull-down node, the first pole is connected to the second reference level terminal, and the second pole is connected to the signal output terminal.
  • the shift register unit further includes: at least one third noise reduction sub-circuit:
  • the third denoising sub-circuit is configured to denoise the potential of the cascaded signal terminal through a first reference level signal in response to the potential of the pull-down node.
  • the third noise reduction sub-circuit includes: a twelfth transistor
  • the control pole of the twelfth transistor is connected to the pull-down node, the first pole is connected to the first reference level terminal, and the second pole is connected to the cascade signal terminal.
  • the output subcircuit includes: a third transistor, an eleventh transistor, and a storage capacitor;
  • the control pole of the third transistor is connected to the pull-up node, the first pole is connected to the clock signal terminal, and the second pole is connected to the signal output terminal;
  • the control pole of the eleventh transistor is connected to the pull-up node, the first pole is connected to the clock signal terminal, and the second pole is connected to the cascade signal terminal;
  • One end of the storage capacitor is connected to the pull-up node, and the other end is connected to the signal output end.
  • the pull-down control subcircuit includes: a fifth transistor
  • Both the control electrode and the first electrode of the fifth transistor are connected to the power supply voltage terminal, and the second electrode is connected to the pull-down node.
  • the pull-down sub-circuit includes: a sixth transistor and a seventh transistor;
  • the control pole of the sixth transistor is connected to the pull-up node, the first pole is connected to the first reference level terminal, and the second pole is connected to the pull-down node;
  • the control pole of the seventh transistor is connected to the signal input terminal, the first pole is connected to the first reference level terminal, and the second pole is connected to the pull-down node.
  • an embodiment of the present disclosure provides a shift register unit, wherein the shift register unit includes: an input subcircuit, an output subcircuit, at least one pull-down control subcircuit, at least one pull-down subcircuit, at least one first Noise reduction subcircuit, at least one second noise reduction subcircuit, at least one third noise reduction subcircuit, first reset subcircuit, second reset subcircuit, shift reset subcircuit and reverse bias subcircuit; above
  • the pull node is at least simultaneously connected to the input subcircuit, the output subcircuit, and the first noise reduction subcircuit;
  • the pull-down node is at least simultaneously connected to the pull-down control subcircuit, the pull-down subcircuit, and the first noise reduction subcircuit sub-circuit;
  • the input subcircuit includes: at least two first transistors; the output subcircuit includes: a third transistor, an eleventh transistor, and a storage capacitor; the pull-down control subcircuit includes: a fifth transistor; the pull-down subcircuit Including: a sixth transistor and a seventh transistor; the first noise reduction sub-circuit includes: at least two eighth transistors; the second noise reduction sub-circuit includes: a thirteenth transistor; the third noise reduction sub-circuit Including: a twelfth transistor; the first reset subcircuit includes: at least two second transistors; the second reset subcircuit includes: a fourth transistor; the shift reset subcircuit includes: at least two second transistors Fifteen transistors; the reverse bias subcircuit includes: a reverse bias control transistor;
  • the control poles of the two first transistors are connected to the signal input terminal, the first pole of one of the first transistors is connected to the signal input terminal, and the second pole is connected to the first pole of the other first transistor and The second pole of the reverse bias control transistor, and the second pole of the other first transistor is connected to the pull-up node;
  • the control pole of the third transistor is connected to the pull-up node, the first pole is connected to the clock signal terminal, and the second pole is connected to the signal output terminal;
  • the control pole of the eleventh transistor is connected to the pull-up node, the first pole is connected to the clock signal terminal, and the second pole is connected to the cascade signal terminal;
  • One end of the storage capacitor is connected to the pull-up node, and the other end is connected to the signal output end;
  • Both the control pole and the first pole of the fifth transistor are connected to the power supply voltage terminal, and the second pole is connected to the pull-down node;
  • the control pole of the sixth transistor is connected to the pull-up node, the first pole is connected to the first reference level terminal, and the second pole is connected to the pull-down node;
  • the control pole of the seventh transistor is connected to the signal input terminal, the first pole is connected to the first reference level terminal, and the second pole is connected to the pull-down node;
  • the control poles of the two eighth transistors are connected to the pull-down node, the first pole of one of the eighth transistors is connected to the first reference level terminal, and the second pole is connected to the first pole of the other eighth transistor and the second pole of the reverse bias control transistor, and the second pole of the other eighth transistor is connected to the pull-up node;
  • the control pole of the thirteenth transistor is connected to the pull-down node, the first pole is connected to the second reference level terminal, and the second pole is connected to the signal output terminal;
  • the control pole of the twelfth transistor is connected to the pull-down node, the first pole is connected to the first reference level terminal, and the second pole is connected to the cascade signal terminal;
  • the control poles of the two second transistors are connected to the reset signal terminal, the first pole of one of the second transistors is connected to the first reference level terminal, and the second pole is connected to the first pole of the other second transistor and In the reverse bias subcircuit, the second pole of the other second transistor is connected to the pull-up node;
  • the control pole of the fourth transistor is connected to the reset signal terminal, the first pole is connected to the second reference level terminal, and the second pole is connected to the signal output terminal;
  • the control poles of the two fifteenth transistors are connected to the shift reset signal terminal, the first pole of one of the fifteenth transistors is connected to the first reference level terminal, and the second pole is connected to the other fifteenth transistor.
  • the first pole of the transistor and the second pole of the reverse bias control transistor, and the second pole of the other fifteenth transistor is connected to the pull-up node;
  • the control pole of the reverse bias control transistor is connected to the pull-up node, the first pole is connected to the power supply voltage terminal, and the second pole is connected to the second pole of one of the first transistors and the second pole of one of the eighth transistors. pole, a second pole of the second transistor and a second pole of the fifteenth transistor.
  • an embodiment of the present disclosure provides a shift register unit, wherein the shift register unit includes: an input subcircuit, an output subcircuit, at least one pull-down control subcircuit, at least one pull-down subcircuit, at least one first Noise reduction subcircuit, at least one second noise reduction subcircuit, at least one third noise reduction subcircuit, first reset subcircuit, second reset subcircuit, shift reset subcircuit and reverse bias subcircuit; above
  • the pull node is at least simultaneously connected to the input subcircuit, the output subcircuit, and the first noise reduction subcircuit;
  • the pull-down node is at least simultaneously connected to the pull-down control subcircuit, the pull-down subcircuit, and the first noise reduction subcircuit sub-circuit;
  • the input subcircuit includes: at least two first transistors; the output subcircuit includes: a third transistor, an eleventh transistor, and a storage capacitor; the pull-down control subcircuit includes: a fifth transistor; the pull-down subcircuit Including: a sixth transistor and a seventh transistor; the first noise reduction sub-circuit includes: at least two eighth transistors; the second noise reduction sub-circuit includes: a thirteenth transistor; the third noise reduction sub-circuit Including: a twelfth transistor; the first reset subcircuit includes: at least two second transistors; the second reset subcircuit includes: a fourth transistor; the shift reset subcircuit includes: at least two second transistors Fifteen transistors; the reverse bias subcircuit includes: a reverse bias control transistor;
  • the control poles of the two first transistors are connected to the signal input terminal, the first pole of one of the first transistors is connected to the signal input terminal, and the second pole is connected to the first pole of the other first transistor and The second pole of the reverse bias control transistor, and the second pole of the other first transistor is connected to the pull-up node;
  • the control pole of the third transistor is connected to the pull-up node, the first pole is connected to the clock signal terminal, and the second pole is connected to the signal output terminal;
  • the control pole of the eleventh transistor is connected to the pull-up node, the first pole is connected to the clock signal terminal, and the second pole is connected to the cascade signal terminal;
  • One end of the storage capacitor is connected to the pull-up node, and the other end is connected to the signal output end;
  • Both the control pole and the first pole of the fifth transistor are connected to the power supply voltage terminal, and the second pole is connected to the pull-down node;
  • the control pole of the sixth transistor is connected to the pull-up node, the first pole is connected to the first reference level terminal, and the second pole is connected to the pull-down node;
  • the control pole of the seventh transistor is connected to the signal input terminal, the first pole is connected to the first reference level terminal, and the second pole is connected to the pull-down node;
  • the control poles of the two eighth transistors are connected to the pull-down node, the first pole of one of the eighth transistors is connected to the first reference level terminal, and the second pole is connected to the first pole of the other eighth transistor and the second pole of the reverse bias control transistor, and the second pole of the other eighth transistor is connected to the pull-up node;
  • the control pole of the thirteenth transistor is connected to the pull-down node, the first pole is connected to the second reference level terminal, and the second pole is connected to the signal output terminal;
  • the control pole of the twelfth transistor is connected to the pull-down node, the first pole is connected to the first reference level terminal, and the second pole is connected to the cascade signal terminal;
  • the control poles of the two second transistors are connected to the reset signal terminal, the first pole of one of the second transistors is connected to the first reference level terminal, and the second pole is connected to the first pole of the other second transistor and In the reverse bias subcircuit, the second pole of the other second transistor is connected to the pull-up node;
  • the control pole of the fourth transistor is connected to the reset signal terminal, the first pole is connected to the second reference level terminal, and the second pole is connected to the signal output terminal;
  • the control poles of the two fifteenth transistors are connected to the shift reset signal terminal, the first pole of one of the fifteenth transistors is connected to the first reference level terminal, and the second pole is connected to the other fifteenth transistor.
  • the first pole of the transistor and the second pole of the reverse bias control transistor, and the second pole of the other fifteenth transistor is connected to the pull-up node;
  • the control pole and the first pole of the reverse bias control transistor are connected to the cascade signal terminal, and the second pole is connected to the second pole of the first transistor, the second pole of the eighth transistor, and the second pole of the eighth transistor. a second pole of the second transistor and a second pole of said fifteenth transistor.
  • an embodiment of the present disclosure provides a gate driving circuit, wherein the gate driving circuit includes a plurality of shift register units cascaded to each other as provided above.
  • an embodiment of the present disclosure provides a display device, wherein the display device includes the gate driving circuit as provided above.
  • an embodiment of the present disclosure provides a driving method for a shift register unit, which is used to drive the shift register unit provided above, wherein the driving method for the shift register unit includes:
  • the reverse bias subcircuit is used to write the power supply voltage signal or the cascaded signal into the input subcircuit and the first noise reduction subcircuit, so that the input subcircuit and the The transistors in the first noise reduction sub-circuit are in a reverse biased state.
  • Fig. 1 is a schematic diagram of the circuit structure of an exemplary shift register unit
  • FIG. 2 is a schematic diagram of a circuit structure of a shift register unit provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of a circuit structure of another shift register unit provided by an embodiment of the present disclosure.
  • the transistors used in the embodiments of the present disclosure can be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistors used are symmetrical, there is no difference in their source and drain functions. of. In the embodiments of the present disclosure, in order to distinguish the source and drain of the transistor, one of them is called the first pole, the other is called the second pole, and the gate is called the control pole. In addition, according to the characteristics of transistors, transistors can be divided into N-type and P-type. In the following embodiments, N-type transistors are used for illustration. The source of the N-type transistor, when the gate is input with a high level, the source and drain are turned on, and the P-type is opposite. It is conceivable that the realization by using P-type transistors can be easily thought of by those skilled in the art without any creative efforts, and thus also falls within the protection scope of the embodiments of the present invention.
  • the third reference level signal in this embodiment refers to a high level signal, and both the first reference level signal and the second reference level signal refer to a low level signal; correspondingly, the power supply voltage terminal refers to the signal terminal VDD; the first reference level terminal refers to the first low level terminal LVGL, the first reference level signal refers to the first low level signal; the second reference level terminal refers to the second low level terminal VGL, The second reference level signal refers to a second low level signal, wherein the voltage of the first low level signal is lower than the voltage of the second low level signal.
  • Fig. 1 is a schematic circuit structure diagram of an exemplary shift register unit.
  • the shift register unit includes: an input subcircuit 101, an output subcircuit 102, at least one pull-down control subcircuit 103, at least one Pull-down subcircuit 104, at least one first noise reduction subcircuit 105, at least one second noise reduction subcircuit 106, at least one third noise reduction subcircuit 107, first reset subcircuit 108, second reset subcircuit 109 and shift Bit reset subcircuit 110 .
  • the pull-up node PU is at least simultaneously connected to the input subcircuit 101, the output subcircuit 102, the first noise reduction subcircuit 105, the first reset subcircuit 108, and the shift reset subcircuit 110; the pull-down node PD is at least simultaneously connected to the pull-down control subcircuit 103 , the pull-down subcircuit 104 and the first noise reduction subcircuit 105 , the second noise reduction subcircuit 106 and the third noise reduction subcircuit 107 .
  • the input sub-circuit 101 includes: a first transistor M1.
  • the output sub-circuit 102 includes: a third transistor M3, an eleventh transistor M11 and a storage capacitor C.
  • the pull-down control sub-circuit 103 includes: a fifth transistor M5.
  • the pull-down sub-circuit 104 includes: a sixth transistor M6 and a seventh transistor M7.
  • the first noise reduction sub-circuit 105 includes: an eighth transistor M8.
  • the second noise reduction sub-circuit 106 includes: a thirteenth transistor M13.
  • the third noise reduction sub-circuit 107 includes: a twelfth transistor M12.
  • the first reset sub-circuit 108 includes: a second transistor M2.
  • the second reset sub-circuit 109 includes: a fourth transistor M4.
  • the shift reset sub-circuit 110 includes: a fifteenth transistor M15. Wherein, both the gate and the source of the first transistor M1 are connected to the signal input terminal Input, and the drain is connected to the pull-up node PU.
  • the gate of the third transistor M3 is connected to the pull-up node PU, the source is connected to the clock signal terminal CLK, and the drain is connected to the signal output terminal Output.
  • the gate of the eleventh transistor M11 is connected to the pull-up node PU, the source is connected to the clock signal terminal CLK, and the drain is connected to the cascade signal terminal Out-C.
  • One end of the storage capacitor C is connected to the pull-up node PU, and the other end is connected to the signal output terminal Output.
  • Both the gate and the source of the fifth transistor M5A are connected to the power supply voltage terminal VDD, and the drain is connected to the first pull-down node PD1.
  • the gate and source of the fifth transistor M5B are both connected to the power supply voltage terminal VDD, and the drain is connected to the second pull-down node PD2.
  • the gate of the sixth transistor M6A is connected to the pull-up node PU, the source is connected to the first low-level terminal LVGL, and the drain is connected to the first pull-down node PD1.
  • the gate of the sixth transistor M6B is connected to the pull-up node PU, the source is connected to the first low level terminal LVGL, and the drain is connected to the second pull-down node PD2.
  • the gate of the seventh transistor M7 is connected to the signal input terminal Input, the source is connected to the first low level terminal LVGL, and the drain is connected to the pull-down node PD.
  • the gate of the eighth transistor M8 is connected to the pull-down node PD, the source is connected to the first low level terminal LVGL, and the drain is connected to the pull-up node PU.
  • the gate of the thirteenth transistor M13 is connected to the pull-down node PD, the source is connected to the second low level terminal VGL, and the drain is connected to the signal output terminal Output.
  • the gate of the twelfth transistor M12 is connected to the pull-down node PD, the source is connected to the first low level terminal LVGL, and the drain is connected to the cascade signal terminal Out-C.
  • the gate of the second transistor M2 is connected to the reset signal terminal Reset, the source is connected to the first low level terminal LVGL, and the drain is connected to the pull-up node PU.
  • the gate of the fourth transistor M4 is connected to the reset signal terminal Reset, the source is connected to the second low level terminal VGL, and the drain is connected to the signal output terminal Output.
  • the gate of the fifteenth transistor M15 is connected to the shift reset signal terminal T-RST, the source is connected to the first low level terminal LVGL, and the drain is connected to the pull-up node PU.
  • the shift register shown in FIG. 1 and the shift register provided by the following embodiments of the present disclosure may include at least one pull-down control sub-circuit 103, at least one pull-down sub-circuit 104, at least one first pull-down Noise sub-circuit 105 , at least one second noise reduction sub-circuit 106 , at least one third noise reduction sub-circuit 107 .
  • the following will take two pull-down control sub-circuits 103, two pull-down sub-circuits 104, two first noise reduction sub-circuits 105, two second noise reduction sub-circuits 106, and two third noise reduction sub-circuits 107 as examples illustrate.
  • the working principle of the two subcircuits with the same function is the same, for example, the working principle of the two pull-down control subcircuits 103 is the same, and the two can work at different times to reduce the pull-down control subcircuit 103.
  • the workload of the transistors thereby increasing the service life of the transistors therein.
  • the service life of the transistors in the pull-down sub-circuit 104 , the first noise reduction sub-circuit 105 , the second noise reduction sub-circuit 106 , and the third noise reduction sub-circuit 107 can be improved.
  • Pre-charging stage the signal input terminal Input inputs a high-level signal, and the first transistor M1 is turned on. At this time, the high-level signal input by the signal input terminal Input pulls up the potential of the pull-up node PU, and stores it through the storage capacitor C.
  • Output stage the signal input terminal Input inputs a low-level signal, and the first transistor M1 is turned off.
  • the potential of the pull-up node PU is further pulled up; since the gates of the third transistor M3 and the eleventh transistor M11 are connected to the pull-up node PU, the third transistor M3 and the The eleventh transistor M11 is turned on, the output signal terminal Output outputs the clock signal of the clock signal terminal CLK as an output signal, and the cascade signal terminal Out-C outputs the clock signal as a cascade signal.
  • the clock signal is a high-level signal
  • the output signal is also a high-level signal.
  • Reset stage the signal input terminal Input inputs a low-level signal, and the first transistor M1 is turned off.
  • the reset signal terminal Reset inputs a high-level signal
  • the second transistor M2 and the fourth transistor M4 are turned on
  • the pull-up node PU is written into the first low-level signal of the first low-level terminal LVGL
  • the signal output terminal Output is With the second low-level signal written into the second low-level signal terminal VGL, the potentials of the pull-up node PU and the signal output terminal Output are reset.
  • Noise reduction stage the signal input terminal Input inputs a low-level signal, and the first transistor M1 is turned off.
  • the reset signal terminal Reset inputs a low-level signal, and the second transistor M2 and the fourth transistor M4 are turned off.
  • the potential of the pull-up node PU remains the potential of the reset phase, which is the first low-level potential
  • the potential of the signal output terminal Output remains the potential of the reset phase, which is the second low-level potential.
  • the pull-down node PD (the first pull-down node PD1 and the second pull-down node PD2) is at a high level potential
  • the eighth transistor M8, the thirteenth transistor M13, and the twelfth transistor M12 are turned on
  • the pull-up nodes PU The signal output terminal Output and the cascaded signal terminal Out-C are continuously noise-reduced.
  • the shift reset signal terminal T-RST writes a high-level signal
  • the fifteenth transistor M15 is turned on
  • the pull-up node is written into the first-level signal of the first low-level signal terminal LVGL.
  • the potential of the node PU is pulled to reset.
  • the Vth (threshold voltage) of the thin film transistor is unstable, and the higher the mobility, the easier the threshold voltage of the thin film transistor is.
  • the occurrence of negative bias fluctuations makes it harder to maintain the voltage of the pull-up node PU.
  • the pull-up node PU leaks electricity through the eighth transistor M8, making the signal output by the signal output terminal Output unstable, which affects the working performance of the shift register unit circuit, causing all The driven display panel is prone to poor display problems.
  • embodiments of the present disclosure provide a shift register unit, a gate drive circuit, and a display device.
  • the shift register unit, gate drive circuit, and display device provided by the embodiments of the present disclosure will be The device is described in further detail.
  • FIG. 2 is a schematic circuit structure diagram of a shift register unit provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of another shift register unit provided by an embodiment of the present disclosure.
  • the shift register unit provided by the embodiment of the present disclosure includes: an input sub-circuit 101, an output sub-circuit 102, at least one pull-down control sub-circuit 103, at least one pull-down sub-circuit 104, At least one first noise reduction sub-circuit 105 and a reverse bias sub-circuit 111 .
  • the input sub-circuit 101 is configured to respond to the input signal of the signal input terminal Input, and pull up the potential of the pull-up node PU through the input signal; the pull-up node PU is at least simultaneously connected to the input sub-circuit 101, the output sub-circuit 102, the first Noise reduction sub-circuit 105 .
  • the output sub-circuit 102 is configured to output a signal through the signal output terminal Output and output a signal through the cascaded signal terminal Out-C in response to the potential of the pull-up node PU being pulled high.
  • the pull-down control subcircuit 103 is configured to control the potential of the pull-down node PD with the power supply voltage signal in response to the power supply voltage signal; the pull-down node PD is at least simultaneously connected to the pull-down control subcircuit 103 , the pull-down subcircuit 104 and the first noise reduction subcircuit 105 .
  • the pull-down sub-circuit 104 is configured to pull down the potential of the pull-down node PD through the first low level signal in response to the potential of the pull-up node PU and the signal input terminal Input.
  • the first denoising sub-circuit 105 is configured to denoise the potential of the pull-up node PU through the first low-level signal in response to the potential of the pull-down node PD.
  • the reverse bias sub-circuit 111 is configured to control at least part of the transistors in the sub-circuits connected to the pull-up node PU to be in a reverse bias state through a power supply voltage signal in response to the potential of the pull-up node PU;
  • the potential of the signal terminal Out-C controls the transistors in at least some of the sub-circuits connected to the pull-up node PU to be in a reverse biased state through cascaded signals.
  • the reverse bias subcircuit 111 can control the transistors in the subcircuit connected to the pull-up node PU to be at In a reverse bias state, for example, when the potential of the pull-up node PU is a high level potential, the reverse bias subcircuit 111 can input a power supply voltage signal or a cascaded signal to the input subcircuit 101 to control the input subcircuit 101 The transistor in is in a reverse bias state, so that the input signal of the input signal terminal Input can be effectively input to the pull-up node PU, ensuring that the potential of the pull-up node PU can be maintained stably.
  • the reverse bias sub-circuit 111 can input the power supply voltage signal or the cascaded signal to the first noise reduction sub-circuit 105 to control the transistors in the first noise reduction sub-circuit 105 to be in a reverse bias state to avoid pulling up the node The PU leaks electricity.
  • each subcircuit connected to the pull-up node PU (the input subcircuit 101 and the first noise reduction subcircuit 105, etc.) cooperates with the reverse bias subcircuit 111 , it can ensure that the potential of the pull-up node PU can reach the preset potential, and avoid the negative shift of the threshold voltage of the transistor in each sub-circuit from affecting the potential of the pull-up node PU, thereby ensuring the output signal of the signal output terminal Output stability, and thus can ensure a good display effect of the driven display panel.
  • the reverse bias subcircuit 111 includes: a reverse bias control transistor M0; the gate of the reverse bias control transistor M0 is connected to the pull-up node PU, and the source is connected to the power supply voltage The drain of the terminal VDD is connected to the input sub-circuit 101 and the first noise reduction sub-circuit 105 .
  • the reverse bias control transistor M0 When the potential of the pull-up node PU is a high level potential, the reverse bias control transistor M0 is turned on, and the power supply voltage signal is input to the input sub-circuit 101, which can control the transistor in the input sub-circuit 101 to be in a reverse bias state, The input signal of the input signal terminal Input can be effectively input to the pull-up node PU, so as to ensure that the potential of the pull-up node PU can be maintained stably.
  • the power supply voltage signal is input to the first noise reduction sub-circuit 105, and the transistors in the first noise reduction sub-circuit 105 are controlled to be in a reverse bias state, so as to avoid leakage of the pull-up node PU.
  • the reverse bias subcircuit 111 includes: a reverse bias control transistor M0; the gate and source of the reverse bias control transistor M0 are both connected to the cascaded signal terminal Out- C, the drain is connected to the input sub-circuit 101 and the first noise reduction sub-circuit 105 .
  • the reverse bias control transistor M0 When the potential of the pull-up node PU is a high-level potential, the reverse bias control transistor M0 is turned on, and the cascade signal is a high-level signal at this time, and the cascade signal is input to the input sub-circuit 101 to control the input sub-circuit
  • the transistor in 101 is in a reverse bias state, so that the input signal at the input signal terminal Input can be effectively input to the pull-up node PU, ensuring that the potential of the pull-up node PU can be maintained stably.
  • the cascaded signal is input to the first noise reduction sub-circuit 105 to control the transistors in the first noise reduction sub-circuit 105 to be in a reverse bias state, so as to avoid leakage of the pull-up node PU.
  • the difference from the aforementioned shift register unit shown in FIG. 2 is that the source of the reverse bias control transistor M0 in the shift register unit shown in FIG. 3 is connected to the cascaded signal terminal Out-C, so that The reverse bias control transistor M0 is independently connected to the power supply voltage terminal VDD, which can save energy consumption of the shift register unit.
  • the input subcircuit 101 includes: at least two first transistors M1 (the two first transistors M1 are represented by M1A and M1B respectively); two first transistors M1A and The gates of M1B are all connected to the signal input terminal Input, the source of one of the first transistors M1A is connected to the signal input terminal Input, the drain is connected to the source of the other first transistor M1B and the reverse bias sub-circuit 111, and the other first transistor M1A is connected to the source of the reverse bias sub-circuit 111.
  • a drain of a transistor M1B is connected to the pull-up node PU.
  • a high level signal is written into the signal input terminal Input
  • the first transistors M1A and M1B are turned on, and the pull-up node can be precharged by the high level signal written into the signal input terminal Input.
  • the dual transistors of the first transistors M1A and M1B are adopted, and the two first transistors M1A and M1B can work at the same time, which can alleviate the threshold voltage shift of the two first transistors M1A and M1B, and cooperate with the
  • the reverse bias sub-circuit 111 can make the input signal of the input signal terminal Input effectively input to the pull-up node PU, so as to ensure that the potential of the pull-up node PU can be maintained stably.
  • a first noise reduction sub-circuit 105 includes: at least two eighth transistors M8 (the two eighth transistors M8 are represented by M8A1 and M8A respectively); The gates of the eight transistors M8A1 and M8A are connected to the first pull-down node PD, that is, the gate of the eighth transistor M8A1 is connected to the first pull-down node PD1, and the gate of the eighth transistor M8A is connected to the second pull-down node PD2.
  • the source of the eighth transistor M8A1 is connected to the first low-level terminal LVGL, the drain is connected to the source of another eighth transistor M8A and the reverse bias sub-circuit 111 , and the drain of the other eighth transistor M8A is connected to the pull-up node PU.
  • the other first noise reduction sub-circuit 105 also adopts the same setting method, and the two eighth transistors M8 are denoted by M8B1 and M8B respectively, and the connection method is the same as above, which will not be repeated here.
  • the eighth transistors M8A1 and M8A are both turned on, and at this time the first low-level The signal denoises the pull node PU.
  • the double transistors of the eighth transistors M8A1 and M8A are adopted, and the two eighth transistors M8A1 and M8A can work at the same time, which can alleviate the threshold voltage shift of the two eighth transistors M8A1 and M8A, and at the same time Cooperating with the reverse bias sub-circuit 111, it is possible to prevent the eighth transistors M8A1 and M8A from being fully turned on, thereby avoiding the leakage of the pull-up node PU.
  • the implementation principle of the other first noise reduction sub-circuit 105 is similar to the above, and will not be repeated here.
  • the shift register unit further includes: a first reset subcircuit 108; the first reset subcircuit 108 is configured to pass a first low level signal in response to a reset signal The potential of the pull-up node PU is reset.
  • the first reset sub-circuit 108 includes: at least two second transistors M2 (the two second transistors M2 are represented by M2A and M2B respectively); the gates of the two second transistors M2A and M2B are connected to the reset signal terminal Reset , the source of one second transistor M2A is connected to the first low-level terminal LVGL, the drain is connected to the source of the other second transistor M2B and the reverse bias sub-circuit 111, and the drain of the other second transistor M2B is connected to Pull node PU.
  • the reset signal terminal Reset inputs a high-level signal, and the second transistors M2A and M2B are turned on. At this time, the pull-up node PU can be reset through the second low-level signal.
  • the dual transistors of the second transistors M2A and M2B are used, and the two second transistors M2A and M2B can work simultaneously, which can alleviate the threshold voltage shift of the two second transistors M2A and M2B, and cooperate with the Reverse biasing the sub-circuit 111 can prevent the second transistors M2A and M2B from being fully turned on and prevent the pull-up node PU from leaking.
  • the shift register unit further includes: a shift reset subcircuit 110; the shift reset subcircuit 110 is configured to respond to the shift reset signal through the first A low level signal resets the potential of the pull-up node PU.
  • the shift reset sub-circuit 110 includes: at least two fifteenth transistors M15 (the two fifteenth transistors M15 are represented by M15A and M15B respectively); the gates of the two fifteenth transistors M15A and M15B are both Connect the shift reset signal terminal T-RST, where the source of one fifteenth transistor M15A is connected to the first low-level terminal LVGL, and the drain is connected to the source of the other fifteenth transistor M15B and the reverse bias sub-circuit 111 , the drain of another fifteenth transistor M15B is connected to the pull-up node PU.
  • the shift reset signal terminal T-RST writes a high level signal
  • the fifteenth transistors M15A and M15B are turned on, and the pull-up node PU is written into the first level of the first low level signal terminal LVGL signal to reset the potential of the pull-up node PU.
  • the dual transistors of the fifteenth transistors M15A and M15B are adopted, and the two fifteenth transistors M15A and M15B can work at the same time, which can alleviate the threshold voltage shift of the two fifteenth transistors M15A and M15B , and at the same time cooperate with the reverse bias sub-circuit 111 to prevent the fifteenth transistors M15A and M15B from being fully turned on, and to prevent the leakage of the pull-up node PU.
  • the shift register unit further includes: a second reset subcircuit 109; the second reset subcircuit 109 is configured to respond to the reset signal by passing the second reference level signal Reset the potential of the signal output terminal Output.
  • the second reset sub-circuit 109 includes: a fourth transistor M4; the gate of the fourth transistor M4 is connected to the reset signal terminal Reset, the source is connected to the second low level terminal VGL, and the drain is connected to the signal output terminal Output.
  • the reset signal terminal Reset inputs a high-level signal, and the fourth transistor M4 is turned on. At this time, the signal output terminal Output can be reset through the first low-level signal.
  • the shift register unit further includes: at least one second noise reduction sub-circuit 106; the second noise reduction sub-circuit 106 is configured to respond to the potential of the pull-down node PD, Noise reduction is performed on the potential of the signal output terminal Output through the second low-level signal.
  • a second noise reduction sub-circuit 106 includes: a thirteenth transistor M13A; the gate of the thirteenth transistor M13A is connected to the first pull-down node PD1, the source is connected to the second low-level terminal VGL, and the drain is connected to the signal output Terminal Output.
  • Another second noise reduction sub-circuit 106 includes: a thirteenth transistor M13B, the connection method of which is similar to the connection method of the above-mentioned thirteenth transistor M13A, which will not be repeated here.
  • the thirteenth transistor M13A is turned on, and at this time, the signal output terminal Output can be denoised through the second low level signal.
  • the second pull-down node PD2 is at a high level
  • the thirteenth transistor M13B is turned on, and at this time, the noise reduction of the signal output terminal Output can be performed through the second low level signal.
  • the two thirteenth transistors M13A and M13B are turned on in time-sharing to improve the service life of the thirteenth transistors M13A and M13B.
  • the shift register unit further includes: at least one third noise reduction sub-circuit 107: the third noise reduction sub-circuit 107 is configured to respond to the potential of the pull-down node PD, Noise reduction is performed on the potential of the cascaded signal terminal Out-C through the first low-level signal.
  • a third noise reduction sub-circuit 107 includes: a twelfth transistor M12A; the gate of the twelfth transistor M12A is connected to the first pull-down node PD1, the source is connected to the first low-level terminal, and the drain is connected to the cascaded signal Terminal Out-C.
  • Another third noise reduction sub-circuit 107 includes: a twelfth transistor M12B; its connection method is similar to that of the above-mentioned twelfth transistor M12A, and will not be repeated here.
  • the twelfth transistor M12A is turned on, and at this time, the cascaded signal terminal Out-C can be denoised through the first low level signal.
  • the twelfth transistor M12B is turned on, and at this time, the cascaded signal terminal Out-C can be denoised through the first low level signal.
  • the two twelfth transistors M12A and M12B are turned on in time-sharing to improve the service life of the twelfth transistors M12A and M12B.
  • the output subcircuit 102 includes: a third transistor M3, an eleventh transistor M11, and a storage capacitor C; the gate of the third transistor M3 is connected to the pull-up node PU, and the source The pole is connected to the clock signal terminal CLK, the drain is connected to the signal output terminal Output; the gate of the eleventh transistor M11 is connected to the pull-up node PU, the source is connected to the clock signal terminal CLK, and the drain is connected to the cascade signal terminal Out-C; the storage capacitor One end of C is connected to the pull-up node PU, and the other end is connected to the signal output terminal Output.
  • Output stage the signal input terminal Input inputs a low-level signal, and the first transistor M1 is turned off.
  • the potential of the pull-up node PU is further pulled up; since the gates of the third transistor M3 and the eleventh transistor M11 are connected to the pull-up node PU, the third transistor M3 and the The eleventh transistor M11 is turned on, the output signal terminal Output outputs the clock signal of the clock signal terminal CLK as an output signal, and the cascade signal terminal Out-C outputs the clock signal as a cascade signal.
  • the clock signal is a high-level signal
  • the output signal is also a high-level signal.
  • a pull-down control subcircuit 103 includes: a fifth transistor M5A; the gate and source of the fifth transistor M5A are connected to the power supply voltage terminal VDDo, and the drain is connected to the first Pull down node PD1.
  • Another pull-down control sub-circuit 103 includes: a fifth transistor M5B; the connection method of the fifth transistor M5B is similar to the above, and will not be repeated here.
  • the gate and source of the fifth transistor M5A are connected to the power supply voltage terminal VDDo, that is, when the power supply voltage signal is written, the fifth transistor M5A is turned on at this time, and the potential of the first pull-down node PD1 is the potential of the power supply voltage. That is, the potential of the first pull-down node PD is at a high level.
  • the gate and source of the fifth transistor M5B are connected to the power supply voltage terminal VDDe, that is, when the power supply voltage signal is written, the fifth transistor M5B is turned on at this time, and the potential of the second pull-down node PD2 is the potential of the power supply voltage, that is, The potential of the second pull-down node PD2 is high level.
  • a pull-down sub-circuit 104 includes: a sixth transistor M6A and a seventh transistor M7A; the gate of the sixth transistor M6A is connected to the pull-up node PU, and the source is connected to the first The drain of the low-level terminal LVGL is connected to the first pull-down node PD1; the gate of the seventh transistor M7A is connected to the signal input terminal Output, the source is connected to the first low-level terminal LVGL, and the drain is connected to the first pull-down node PD1.
  • Another pull-down sub-circuit 104 includes: a sixth transistor M6B and a seventh transistor M7B; the connection of the sixth transistor M6B and the seventh transistor M7B is similar to the above, and will not be repeated here.
  • the seventh transistor M7A When the signal input terminal Input writes a high-level signal, the seventh transistor M7A is turned on, the first pull-down node PD1 is written with the first low-level signal, and at the same time, the pull-up node PU is written with a high-level signal, and the sixth transistor M6A When it is turned on, the first pull-down node PD1 can be continuously written with the first low-level signal, ensuring that the potential of the first pull-down node PD1 is continuously pulled down. Similarly, the sixth transistor M6B and the seventh transistor M7B can ensure that the potential of the second pull-down node PD2 is continuously pulled down.
  • the shift register unit includes: an input subcircuit 101, an output subcircuit 102, at least one pull-down control subcircuit 103, and at least one pull-down subcircuit 104 , at least one first noise reduction subcircuit 105, at least one second noise reduction subcircuit 106, at least one third noise reduction subcircuit 107, first reset subcircuit 108, second reset subcircuit 109, shift reset subcircuit
  • the pull-up node PU is at least simultaneously connected to the input subcircuit 101, the output subcircuit 102, and the first noise reduction subcircuit 105;
  • the pull-down node PD is at least simultaneously connected to the pull-down control subcircuit 103, the pull-down subcircuit circuit 104 and the first noise reduction sub-circuit 105.
  • the input subcircuit 101 includes: at least two first transistors M1A and M1B; the output subcircuit 102 includes: the third transistor Mmhg3, the eleventh transistor M11 and the storage capacitor C; the pull-down control subcircuit 103 includes: the fifth transistors M5A and M5B
  • the pull-down subcircuit 104 includes: the sixth transistors M6A and M6B, the seventh transistors M7A and M7B; the first noise reduction subcircuit 105 includes: at least two eighth transistors M8A1, M8A, M8B1 and M8B; the second noise reduction subcircuit 106 includes: the thirteenth transistors M13A and M13B; the third noise reduction sub-circuit 107 includes: the twelfth transistors M12A and M12B; the first reset sub-circuit 108 includes: at least two second transistors M2A and M2B; the second reset sub-circuit
  • the circuit 109 includes: a fourth transistor M4; the shift reset sub-circuit 110 includes:
  • the gate of the reverse bias control transistor M0 is connected to the pull-up node PU, the source is connected to the power supply voltage terminal VDD, and the drain is connected to the drain of a first transistor M1A, the drain of an eighth transistor M8A, and a second the drain of transistor M2A and a drain of a fifteenth transistor M15A.
  • the connection methods and implementation principles of other transistors are similar to those described above, and will not be repeated here.
  • the embodiment of the present disclosure also provides another shift register unit. As shown in FIG. 104. At least one first noise reduction subcircuit 105, at least one second noise reduction subcircuit 106, at least one third noise reduction subcircuit 107, first reset subcircuit 108, second reset subcircuit 109, shift reset The subcircuit 110 and the reverse bias subcircuit 111; the pull-up node PU is at least simultaneously connected to the input subcircuit 101, the output subcircuit 102, and the first noise reduction subcircuit 105; the pull-down node PD is at least simultaneously connected to the pull-down control subcircuit 103, the pull-down sub-circuit 104 and a first noise reduction sub-circuit 105 .
  • the input subcircuit 101 includes: at least two first transistors M1A and M1B; the output subcircuit 102 includes: a third transistor M3, an eleventh transistor M11 and a storage capacitor C; the pull-down control subcircuit 103 includes: fifth transistors M5A and M5B
  • the pull-down subcircuit 104 includes: the sixth transistors M6A and M6B, the seventh transistors M7A and M7B; the first noise reduction subcircuit 105 includes: at least two eighth transistors M8A1, M8A, M8B1 and M8B; the second noise reduction subcircuit 106 includes: the thirteenth transistors M13A and M13B; the third noise reduction sub-circuit 107 includes: the twelfth transistors M12A and M12B; the first reset sub-circuit 108 includes: at least two second transistors M2A and M2B; the second reset sub-circuit
  • the circuit 109 includes: a fourth transistor M4; the shift reset sub-circuit 110 includes: at least
  • the gate and source of the reverse bias control transistor M0 are connected to the cascade signal terminal Out-C, and the drain is connected to the drain of a first transistor M1A, the drain of an eighth transistor M8A, and a second transistor M2A and the drain of a fifteenth transistor M15A.
  • the connection methods and implementation principles of other transistors are similar to those described above, and will not be repeated here.
  • the difference from the aforementioned shift register unit shown in FIG. 2 is that the source of the reverse bias control transistor M0 in the shift register unit shown in FIG. 3 is connected to the cascaded signal terminal Out-C, so that The reverse bias control transistor M0 is independently connected to the power supply voltage terminal VDD, which can save energy consumption of the shift register unit.
  • An embodiment of the present disclosure further provides a gate driving circuit, the gate driving circuit includes a plurality of shift register units as provided in any one of the foregoing embodiments, which are cascaded to each other.
  • the gate drive circuit provided by the embodiments of the present disclosure can output scan signals step by step to drive the display panel to scan row by row to realize the display function.
  • the reverse bias subcircuit 111 since the reverse bias subcircuit 111 is added in the shift register unit, the reverse bias subcircuit 111 can control the transistors in the subcircuit connected to the pull-up node PU to be in reverse.
  • each sub-circuit connected to the pull-up node PU adopts a double-transistor structure.
  • the reverse bias subcircuit 111 can input a power supply voltage signal or a cascaded signal to the input subcircuit 101 to control the transistors in the input subcircuit 101 to be in the reverse direction.
  • the input sub-circuit 101 adopts a double-transistor structure, so that the input signal of the input signal terminal Input can be effectively input to the pull-up node PU, ensuring that the potential of the pull-up node PU can be maintained stably.
  • the reverse bias sub-circuit 111 can input the power supply voltage signal or the cascaded signal to the first noise reduction sub-circuit 105, and control the transistors in the first noise reduction sub-circuit 105 to be in a reverse bias state, while the first noise reduction
  • the noise sub-circuit 105 adopts a double-transistor structure to avoid electric leakage at the pull-up node PU.
  • each subcircuit connected to the pull-up node PU (such as the input subcircuit 101 and the first noise reduction subcircuit 105, etc.) cooperates with the reverse bias subcircuit 111 Under this condition, it can ensure that the potential of the pull-up node PU can reach the preset potential, and avoid the negative shift of the threshold voltage of the transistor in each sub-circuit from affecting the potential of the pull-up node PU, thereby ensuring the output of the signal output terminal Output
  • the stability of the signal can further ensure a good display effect of the driven display panel.
  • An embodiment of the present disclosure also provides a display device, which includes the gate drive circuit provided in any one of the above embodiments.
  • the display device can be a display device such as a large-size TV, a monitor, and a car navigation. Its implementation principle and The technical effect is the same as the implementation principle and technical effect of the gate drive circuit provided by any of the above embodiments, and will not be repeated here.
  • An embodiment of the present disclosure also provides a driving method for a shift register unit, which is used to drive the shift register unit provided in any of the above embodiments, wherein the driving method for the shift register unit includes: when the potential of the pull-up node When it is high level, the power supply voltage signal or cascaded signal is written into the input subcircuit and the first noise reduction subcircuit by using the reverse bias subcircuit, so that the transistors in the input subcircuit and the first noise reduction subcircuit are in reverse bias state.
  • the power supply voltage signal or the cascaded signal can be written into the input subcircuit or the first noise reduction subcircuit, so that the input subcircuit and the first noise reduction subcircuit
  • the transistor is in a reverse bias state, which can ensure that the potential of the pull-up node PU can reach the preset potential, and avoid the negative shift of the threshold voltage of the transistor in each sub-circuit from affecting the potential of the pull-up node PU, thereby ensuring The output signal of the signal output terminal Output is stable, thereby ensuring a good display effect of the driven display panel.

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Abstract

一种移位寄存器单元、栅极驱动电路及显示装置，属于显示技术领域，其可解决现有的移位寄存器单元中的薄膜晶体管的阈值电压不稳定，容易产生漏电流的问题。移位寄存器单元包括：输入子电路(101)、输出子电路(102)、至少一个下拉控制子电路(103)、至少一个下拉子电路(104)、至少一个第一降噪子电路(105)和反向偏置子电路(111)；反向偏置子电路(111)被配置为响应于上拉节点(PU)的电位，通过电源电压信号控制连接上拉节点(PU)的至少部分子电路中的晶体管处于反向偏置状态；或者，响应于级联信号端(Out-C)的电位，通过级联信号控制连接上拉节点(PU)的至少部分子电路中的晶体管处于反向偏置状态。

Description

移位寄存器单元、栅极驱动电路及显示装置 技术领域
本公开属于显示技术领域，具体涉及一种移位寄存器单元、栅极驱动电路及显示装置。
背景技术
GOA(Gate Driver on Array，集成栅极驱动电路)技术可以将栅极驱动电路集成在显示面板的阵列基板上，相比传统的COF(Chip On Film，覆晶薄膜)或COG(Chip On Glass，芯片直接固定在玻璃上)工艺，其不仅节约了成本，而且可以做到面板两边对称的美观设计，同时也可省去栅极驱动电路的Bonding(压焊)区域以及外围布线空间，从而实现了显示装置窄边框的设计，提高了显示装置的产能和良率。
GOA电路中所用的薄膜晶体管其有源层材料可选用a-Si(非晶硅)、LTPS(低温多晶硅)、金属氧化物半导体，如典型的材料IGZO(Indium Gallium Zinc Oxide，氧化铟镓锌)等。大尺寸显示屏通常选用金属氧化物晶体管(如有源层材料为IGZO的薄膜晶体管)作为GOA电路中的薄膜晶体管，但当显示器尺寸以及分辨率进一步增大时，需要选用具有更高迁移率的氧化物材料薄膜晶体管应用于GOA电路。当选用更高迁移率的薄膜晶体管时，薄膜晶体管的阈值电压不稳定，易发生负偏波动，造成薄膜晶体管产生漏电流，而影响GOA电路的工作性能，造成所驱动的显示面板容易发生显示不良问题。
发明内容
本公开旨在至少解决现有技术中存在的技术问题之一，提供一种移位寄 存器单元、栅极驱动电路及显示装置。
第一方面，本公开实施例提供一种移位寄存器单元，其中，所述移位寄存器单元包括：输入子电路、输出子电路、至少一个下拉控制子电路、至少一个下拉子电路、至少一个第一降噪子电路和反向偏置子电路；
所述输入子电路被配置为响应于信号输入端的输入信号，通过所述输入信号对上拉节点的电位进行拉高；所述上拉节点至少同时连接所述输入子电路、所述输出子电路、所述第一降噪子电路；
所述输出子电路被配置为响应于所述上拉节点被拉高后的电位，通过信号输出端输出信号及通过级联信号端输出信号；
所述下拉控制子电路被配置为响应于电源电压信号，利用所述电源电压信号控制下拉节点的电位；所述下拉节点至少同时连接所述下拉控制子电路、所述下拉子电路和所述第一降噪子电路；
所述下拉子电路被配置为响应于所述上拉节点和所述信号输入端的电位，通过第一参考电平信号下拉所述下拉节点的电位；
所述第一降噪子电路被配置为响应于所述下拉节点的电位，通过第一参考电平信号对所述上拉节点的电位进行降噪；
所述反向偏置子电路被配置为响应于所述上拉节点的电位，通过电源电压信号控制连接所述上拉节点的至少部分子电路中的晶体管处于反向偏置状态；或者，响应于级联信号端的电位，通过级联信号控制连接所述上拉节点的至少部分子电路中的晶体管处于反向偏置状态。
可选地，所述反向偏置子电路包括：反向偏置控制晶体管；
所述反向偏置控制晶体管的控制极连接所述上拉节点，第一极连接电源电压端，第二极连接所述输入子电路和所述第一降噪子电路。
可选地，所述反向偏置子电路包括：反向偏置控制晶体管；
所述反向偏置控制晶体管的控制极和第一极均连接所述级联信号端，第 二极连接所述输入子电路和所述第一降噪子电路。
可选地，所述输入子电路包括：至少两个第一晶体管；
两个所述第一晶体管的控制极均连接所述信号输入端，其中一个所述第一晶体管的第一极连接所述信号输入端，第二极连接另一个所述第一晶体管的第一极和所述反向偏置子电路，另一个所述第一晶体管的第二极连接所述上拉节点。
可选地，所述第一降噪子电路包括：至少两个第八晶体管；
两个所述第八晶体管的控制极均连接所述下拉节点，其中一个所述第八晶体管的第一极连接第一参考电平端，第二极连接另一个所述第八晶体管的第一极和所述反向偏置子电路，另一个所述第八晶体管的第二极连接所述上拉节点。
可选地，所述移位寄存器单元还包括：第一复位子电路；
所述第一复位子电路被配置为响应于复位信号，通过第一参考电平信号对所述上拉节点的电位进行复位。
可选地，所述第一复位子电路包括：至少两个第二晶体管；
两个所述第二晶体管的控制极均连接复位信号端，其中一个所述第二晶体管的第一极连接第一参考电平端，第二极连接另一个所述第二晶体管的第一极和所述反向偏置子电路，另一个所述第二晶体管的第二极连接所述上拉节点。
可选地，所述移位寄存器单元还包括：移位重置子电路；
所述移位重置子电路被配置为响应于移位重置信号，通过第一参考电平信号对所述上拉节点的电位进行重置。
可选地，所述移位重置子电路包括：至少两个第十五晶体管；
两个所述第十五晶体管的控制极均连接移位重置信号端，其中一个所述第十五晶体管的第一极连接第一参考电平端，第二极连接另一个所述第十五 晶体管的第一极和所述反向偏置子电路，另一个所述第十五晶体管的第二极连接所述上拉节点。
可选地，所述移位寄存器单元还包括：第二复位子电路；
所述第二复位子电路被配置为响应于所述复位信号，通过第二参考电平信号对所述信号输出端的电位进行复位。
可选地，所述第二复位子电路包括：第四晶体管；
所述第四晶体管的控制极连接复位信号端，第一极连接第二参考电平端，第二极连接所述信号输出端。
可选地，所述移位寄存器单元还包括：至少一个第二降噪子电路；
所述第二降噪子电路被配置为响应于所述下拉节点的电位，通过第二参考电平信号对所述信号输出端的电位进行降噪。
可选地，所述第二降噪子电路包括：第十三晶体管；
所述第十三晶体管的控制极连接所述下拉节点，第一极连接第二参考电平端，第二极连接所述信号输出端。
可选地，所述移位寄存器单元还包括：至少一个第三降噪子电路：
所述第三降噪子电路被配置为响应于所述下拉节点的电位，通过第一参考电平信号对所述级联信号端的电位进行降噪。
可选地，所述第三降噪子电路包括：第十二晶体管；
所述第十二晶体管的控制极连接所述下拉节点，第一极连接第一参考电平端，第二极连接所述级联信号端。
可选地，所述输出子电路包括：第三晶体管、第十一晶体管和存储电容；
所述第三晶体管的控制极连接所述上拉节点，第一极连接时钟信号端，第二极连接信号输出端；
所述第十一晶体管的控制极连接所述上拉节点，第一极连接时钟信号端，第二极连接级联信号端；
所述存储电容的一端连接所述上拉节点，另一端连接信号输出端。
可选地，所述下拉控制子电路包括：第五晶体管；
所述第五晶体管的控制极和第一极均连接电源电压端，第二极连接所述下拉节点。
可选地，所述下拉子电路包括：第六晶体管和第七晶体管；
所述第六晶体管的控制极连接所述上拉节点，第一极连接第一参考电平端，第二极连接所述下拉节点；
所述第七晶体管的控制极连接所述信号输入端，第一极连接第一参考电平端，第二极连接所述下拉节点。
第二方面本公开实施例提供一种移位寄存器单元，其中，所述移位寄存器单元包括：输入子电路、输出子电路、至少一个下拉控制子电路、至少一个下拉子电路、至少一个第一降噪子电路、至少一个第二降噪子电路、至少一个第三降噪子电路、第一复位子电路、第二复位子电路、移位重置子电路和反向偏置子电路；上拉节点至少同时连接所述输入子电路、所述输出子电路、所述第一降噪子电路；下拉节点至少同时连接所述下拉控制子电路、所述下拉子电路和所述第一降噪子电路；
所述输入子电路包括：至少两个第一晶体管；所述输出子电路包括：第三晶体管、第十一晶体管和存储电容；所述下拉控制子电路包括：第五晶体管；所述下拉子电路包括：第六晶体管和第七晶体管；所述第一降噪子电路包括：至少两个第八晶体管；所述第二降噪子电路包括：第十三晶体管；所述第三降噪子电路包括：第十二晶体管；所述第一复位子电路包括：至少两个第二晶体管；所述第二复位子电路包括：第四晶体管；所述移位重置子电路包括：至少两个第十五晶体管；所述反向偏置子电路包括：反向偏置控制晶体管；
两个所述第一晶体管的控制极均连接信号输入端，其中一个所述第一晶 体管的第一极连接所述信号输入端，第二极连接另一个所述第一晶体管的第一极和所述反向偏置控制晶体管的第二极，另一个所述第一晶体管的第二极连接所述上拉节点；
所述第三晶体管的控制极连接所述上拉节点，第一极连接时钟信号端，第二极连接信号输出端；
所述第十一晶体管的控制极连接所述上拉节点，第一极连接时钟信号端，第二极连接级联信号端；
所述存储电容的一端连接所述上拉节点，另一端连接信号输出端；
所述第五晶体管的控制极和第一极均连接电源电压端，第二极连接所述下拉节点；
所述第六晶体管的控制极连接所述上拉节点，第一极连接第一参考电平端，第二极连接所述下拉节点；
所述第七晶体管的控制极连接所述信号输入端，第一极连接第一参考电平端，第二极连接所述下拉节点；
两个所述第八晶体管的控制极均连接所述下拉节点，其中一个所述第八晶体管的第一极连接第一参考电平端，第二极连接另一个所述第八晶体管的第一极和所述反向偏置控制晶体管的第二极，另一个所述第八晶体管的第二极连接所述上拉节点；
所述第十三晶体管的控制极连接所述下拉节点，第一极连接第二参考电平端，第二极连接所述信号输出端；
所述第十二晶体管的控制极连接所述下拉节点，第一极连接第一参考电平端，第二极连接所述级联信号端；
两个所述第二晶体管的控制极均连接复位信号端，其中一个所述第二晶体管的第一极连接第一参考电平端，第二极连接另一个所述第二晶体管的第一极和所述反向偏置子电路，另一个所述第二晶体管的第二极连接所述上拉 节点；
所述第四晶体管的控制极连接复位信号端，第一极连接第二参考电平端，第二极连接所述信号输出端；
两个所述第十五晶体管的控制极均连接移位重置信号端，其中一个所述第十五晶体管的第一极连接第一参考电平端，第二极连接另一个所述第十五晶体管的第一极和所述反向偏置控制晶体管的第二极，另一个所述第十五晶体管的第二极连接所述上拉节点；
所述反向偏置控制晶体管的控制极连接所述上拉节点，第一极连接电源电压端，第二极连接一个所述第一晶体管的第二极、一个所述第八晶体管的第二极、一个所述第二晶体管的第二极和一个所述第十五晶体管的第二极。
第三方面本公开实施例提供一种移位寄存器单元，其中，所述移位寄存器单元包括：输入子电路、输出子电路、至少一个下拉控制子电路、至少一个下拉子电路、至少一个第一降噪子电路、至少一个第二降噪子电路、至少一个第三降噪子电路、第一复位子电路、第二复位子电路、移位重置子电路和反向偏置子电路；上拉节点至少同时连接所述输入子电路、所述输出子电路、所述第一降噪子电路；下拉节点至少同时连接所述下拉控制子电路、所述下拉子电路和所述第一降噪子电路；
所述输入子电路包括：至少两个第一晶体管；所述输出子电路包括：第三晶体管、第十一晶体管和存储电容；所述下拉控制子电路包括：第五晶体管；所述下拉子电路包括：第六晶体管和第七晶体管；所述第一降噪子电路包括：至少两个第八晶体管；所述第二降噪子电路包括：第十三晶体管；所述第三降噪子电路包括：第十二晶体管；所述第一复位子电路包括：至少两个第二晶体管；所述第二复位子电路包括：第四晶体管；所述移位重置子电路包括：至少两个第十五晶体管；所述反向偏置子电路包括：反向偏置控制晶体管；
两个所述第一晶体管的控制极均连接信号输入端，其中一个所述第一晶体管的第一极连接所述信号输入端，第二极连接另一个所述第一晶体管的第一极和所述反向偏置控制晶体管的第二极，另一个所述第一晶体管的第二极连接所述上拉节点；
所述第三晶体管的控制极连接所述上拉节点，第一极连接时钟信号端，第二极连接信号输出端；
所述第十一晶体管的控制极连接所述上拉节点，第一极连接时钟信号端，第二极连接级联信号端；
所述存储电容的一端连接所述上拉节点，另一端连接信号输出端；
所述第五晶体管的控制极和第一极均连接电源电压端，第二极连接所述下拉节点；
所述第六晶体管的控制极连接所述上拉节点，第一极连接第一参考电平端，第二极连接所述下拉节点；
所述第七晶体管的控制极连接所述信号输入端，第一极连接第一参考电平端，第二极连接所述下拉节点；
两个所述第八晶体管的控制极均连接所述下拉节点，其中一个所述第八晶体管的第一极连接第一参考电平端，第二极连接另一个所述第八晶体管的第一极和所述反向偏置控制晶体管的第二极，另一个所述第八晶体管的第二极连接所述上拉节点；
所述第十三晶体管的控制极连接所述下拉节点，第一极连接第二参考电平端，第二极连接所述信号输出端；
所述第十二晶体管的控制极连接所述下拉节点，第一极连接第一参考电平端，第二极连接所述级联信号端；
两个所述第二晶体管的控制极均连接复位信号端，其中一个所述第二晶体管的第一极连接第一参考电平端，第二极连接另一个所述第二晶体管的第 一极和所述反向偏置子电路，另一个所述第二晶体管的第二极连接所述上拉节点；
所述第四晶体管的控制极连接复位信号端，第一极连接第二参考电平端，第二极连接所述信号输出端；
两个所述第十五晶体管的控制极均连接移位重置信号端，其中一个所述第十五晶体管的第一极连接第一参考电平端，第二极连接另一个所述第十五晶体管的第一极和所述反向偏置控制晶体管的第二极，另一个所述第十五晶体管的第二极连接所述上拉节点；
所述反向偏置控制晶体管的控制极和第一极连接级联信号端，第二极连接一个所述第一晶体管的第二极、一个所述第八晶体管的第二极、一个所述第二晶体管的第二极和一个所述第十五晶体管的第二极。
第四方面本公开实施例提供一种栅极驱动电路，其中，所述栅极驱动电路包括多个相互级联的如上述提供地移位寄存器单元。
第五方面本公开实施例提供一种显示装置，其中，所述显示装置包括如上述提供的栅极驱动电路。
第六方面本公开实施例提供一种移位寄存器单元的驱动方法，用于驱动如上述提供的移位寄存器单元，其中，所述移位寄存器单元的驱动方法包括：
当上拉节点的电位为第三参考电平时，利用反向偏置子电路将电源电压信号或级联信号写入输入子电路和第一降噪子电路，使得所述输入子电路和所述第一降噪子电路中的晶体管处于反向偏置状态。
附图说明
图1为一种示例性的移位寄存器单元的电路结构示意图；
图2为本公开实施例提供的一种移位寄存器单元的电路结构示意图；
图3为本公开实施例提供的另一种移位寄存器单元的电路结构示意图。
具体实施方式
为使本领域技术人员更好地理解本公开的技术方案，下面结合附图和具体实施方式对本公开作进一步详细描述。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
本公开实施例中所采用的晶体管可以为薄膜晶体管或场效应管或其他特性的相同器件，由于采用的晶体管的源极和漏极是对称的，所以其源极、漏极功能上是没有区别的。在本公开实施例中，为区分晶体管的源极和漏极，将其中一极称为第一极，另一极称为第二极，栅极称为控制极。此外按照晶体管的特性区分可以将晶体管分为N型和P型，以下实施例中是以N型晶体管进行说明的，当采用N型晶体管时，第一极为N型晶体管的漏极，第二极为N型晶体管的源极，栅极输入高电平时，源漏极导通，P型相反。可以想到的是采用P型晶体管实现是本领域技术人员可以在没有付出创造性劳动前提下轻易想到的，因此也是在本发明实施例的保护范围内的。
在此需要说明的是，本实施例中第三参考电平信号是指高电平信号，第一参考电平信号和第二参考电平信号均是指低电平信号；相应的，电源电压端是指信号端VDD；第一参考电平端是指第一低电平端LVGL，第一参考电 平信号是指第一低电平信号；第二参考电平端是指第二低电平端VGL，第二参考电平信号是指第二低电平信号，其中，第一低电平信号的电压低于第二低电平信号的电压。
图1为一种示例性的移位寄存器单元的电路结构示意图，如图1所示，该移位寄存器单元包括：输入子电路101、输出子电路102、至少一个下拉控制子电路103、至少一个下拉子电路104、至少一个第一降噪子电路105、至少一个第二降噪子电路106、至少一个第三降噪子电路107、第一复位子电路108、第二复位子电路109和移位重置子电路110。上拉节点PU至少同时连接输入子电路101、输出子电路102、第一降噪子电路105、第一复位子电路108和移位重置子电路110；下拉节点PD至少同时连接下拉控制子电路103、下拉子电路104和第一降噪子电路105、第二降噪子电路106和第三降噪子电路107。
具体地，输入子电路101包括：第一晶体管M1。输出子电路102包括：第三晶体管M3、第十一晶体管M11和存储电容C。下拉控制子电路103包括：第五晶体管M5。下拉子电路104包括：第六晶体管M6和第七晶体管M7。第一降噪子电路105包括：第八晶体管M8。第二降噪子电路106包括：第十三晶体管M13。第三降噪子电路107包括：第十二晶体管M12。第一复位子电路108包括：第二晶体管M2。第二复位子电路109包括：第四晶体管M4。移位重置子电路110包括：第十五晶体管M15。其中，第一晶体管M1的栅极和源极均连接信号输入端Input，漏极连接上拉节点PU。第三晶体管M3的栅极连接上拉节点PU，源极连接时钟信号端CLK，漏极连接信号输出端Output。第十一晶体管M11的栅极连接上拉节点PU，源极连接时钟信号端CLK，漏极连接级联信号端Out-C。存储电容C的一端连接上拉节点PU，另一端连接信号输出端Output。第五晶体管M5A的栅极连接和源极均连接电源电压端VDD，漏极连接第一下拉节点PD1。第五晶体管M5B的 栅极连接和源极均连接电源电压端VDD，漏极连接第二下拉节点PD2。第六晶体管M6A的栅极连接上拉节点PU，源极连接第一低电平电平端LVGL，漏极连接第一下拉节点PD1。第六晶体管M6B的栅极连接上拉节点PU，源极连接第一低电平电平端LVGL，漏极连接第二下拉节点PD2。第七晶体管M7的栅极连接信号输入端Input，源极连接第一低电平电平端LVGL，漏极连接下拉节点PD。第八晶体管M8的栅极连接下拉节点PD，源极连接第一低电平电平端LVGL，漏极连接上拉节点PU。第十三晶体管M13的栅极连接下拉节点PD，源极连接第二低电平电平端VGL，漏极连接信号输出端Output。第十二晶体管M12的栅极连接下拉节点PD，源极连接第一低电平电平端LVGL，漏极连接级联信号端Out-C。第二晶体管M2的栅极连接复位信号端Reset，源极连接第一低电平电平端LVGL，漏极连接上拉节点PU。第四晶体管M4的栅极连接复位信号端Reset，源极连接第二低电平电平端VGL，漏极连接信号输出端Output。第十五晶体管M15的栅极连接移位重置信号端T-RST，源极连接第一低电平电平端LVGL，漏极连接上拉节点PU。
在此需要说明的是，图1所示的移位寄存器以及之后的本公开实施例提供的移位寄存器中可以包括至少一个下拉控制子电路103、至少一个下拉子电路104、至少一个第一降噪子电路105、至少一个第二降噪子电路106、至少一个第三降噪子电路107。下面将以两个下拉控制子电路103、两个下拉子电路104、两个第一降噪子电路105、两个第二降噪子电路106、两个第三降噪子电路107为例进行说明。其中的两个功能相同的子电路的工作原理是相同的，例如两个下拉控制子电路103的工作原理是相同的，二者可以在不同的时间进行工作，以减少下拉控制子电路103中的晶体管的工作负荷，从而提高其中的晶体管的使用寿命。同样地，可以提高下拉子电路104、第一降噪子电路105、第二降噪子电路106、第三降噪子电路107中的晶体管的使用寿命。
相应地，下拉节点PD的数量为两个，即PD1和PD2；第五晶体管M5为两个，第一个第五晶体管M5用M5A表示，第二个第五晶体管M5用M5B表示，其对应连接的电源电压端VDD分别用VDDo和VDDe表示；第六晶体管M6为两个，第一个第六晶体管M6用M6A表示，第二个第六晶体管M6用M6B表示；第六晶体管M6为两个，第一个第六晶体管M6用M6A表示，第二个第六晶体管M6用M6B表示；第七晶体管M7为两个，第一个第七晶体管M7用M7A表示，第二个第七晶体管M7用M7B表示；第八晶体管M8为两个，第一个第八晶体管M8用M8A表示，第二个第八晶体管M8用M8B表示；第十三晶体管M13为两个，第一个第十三晶体管M13用M13A表示，第二个第十三晶体管M13用M13B表示；第十二晶体管M12为两个，第一个第十二晶体管M12用M12A表示，第二个第十二晶体管M12用M12B表示。
对于图1所示的移位寄存器单元，其具体的工作过程可以包括如下阶段：
预充阶段：信号输入端Input输入高电平信号，第一晶体管M1打开，此时信号输入端Input输入的高电平信号拉高上拉节点PU的电位，并通过存储电容C进行存储。
输出阶段：信号输入端Input输入低电平信号，第一晶体管M1关闭。此时由于在预充阶段存储电容C被充电，上拉节点PU的电位被进一步拉高；由于第三晶体管M3和第十一晶体管M11的栅极均连接上拉节点PU，第三晶体管M3和第十一晶体管M11被打开，输出信号端Output将时钟信号端CLK的时钟信号作为输出信号输出，级联信号端Out-C将时钟信号作为级联信号输出。此时时钟信号为高电平信号，输出信号也为高电平信号。
复位阶段：信号输入端Input输入低电平信号，第一晶体管M1关闭。此时复位信号端Reset输入高电平信号，第二晶体管M2和第四晶体管M4被打开，上拉节点PU被写入第一低电平端LVGL的第一低电平信号，信号 输出端Output被写入第二低电平信号端VGL的第二低电平信号，上拉节点PU和信号输出端Output的电位被复位。
降噪阶段：信号输入端Input输入低电平信号，第一晶体管M1关闭。复位信号端Reset输入低电平信号，第二晶体管M2和第四晶体管M4被关闭。此时上拉节点PU的电位保持复位阶段的电位，为第一低电平电位，信号输出端Output的电位保持复位阶段的电位，为第二低电平电位。此时，下拉节点PD(第一下拉节点PD1和第二下拉节点PD2)为高电平电位，第八晶体管M8和第十三晶体管M13、第十二晶体管M12被打开，上拉节点PU、信号输出端Output和级联信号端Out-C被持续降噪。
结束阶段：移位重置信号端T-RST写入高电平信号，第十五晶体管M15被打开，上拉节点被写入第一低电平信号端LVGL的第一电平信号，对上拉节点PU的电位进行重置。
在大尺寸及高分辨率的显示器中，当选用了具有更高迁移率的氧化物薄膜晶体管时，薄膜晶体管的Vth(阈值电压)不稳定，并且迁移率越高，薄膜晶体管的阈值电压越容易发生负偏波动，导致上拉节点PU的电压越不容易保持。例如，当第八晶体管M8发生负偏波动时，造成上拉节点PU通过第八晶体管M8发生漏电，使得信号输出端Output输出的信号不稳定，而影响移位寄存器单元电路的工作性能，造成所驱动的显示面板容易发生显示不良问题。
为了至少解决上述的技术问题之一，本公开实施例提供了一种移位寄存器单元、栅极驱动电路及显示装置，下面将对本公开实施例提供的移位寄存器单元、栅极驱动电路及显示装置进行进一步详细描述。
本公开实施例提供了一种移位寄存器单元，图2为本公开实施例提供的一种移位寄存器单元的电路结构示意图，图3为本公开实施例提供的另一种移位寄存器单元的电路结构示意图，如图2和图3所示，本公开实施例提供 的移位寄存器单元包括：输入子电路101、输出子电路102、至少一个下拉控制子电路103、至少一个下拉子电路104、至少一个第一降噪子电路105和反向偏置子电路111。输入子电路101被配置为响应于信号输入端Input的输入信号，通过输入信号对上拉节点PU的电位进行拉高；上拉节点PU至少同时连接输入子电路101、输出子电路102、第一降噪子电路105。输出子电路102被配置为响应于上拉节点PU被拉高后的电位，通过信号输出端Output输出信号及通过级联信号端Out-C输出信号。下拉控制子电路103被配置为响应于电源电压信号，利用电源电压信号控制下拉节点PD的电位；下拉节点PD至少同时连接下拉控制子电路103、下拉子电路104和第一降噪子电路105。下拉子电路104被配置为响应于上拉节点PU和信号输入端Input的电位，通过第一低电平信号下拉下拉节点PD的电位。第一降噪子电路105被配置为响应于下拉节点PD的电位，通过第一低电平信号对上拉节点PU的电位进行降噪。反向偏置子电路111被配置为响应于上拉节点PU的电位，通过电源电压信号控制连接上拉节点PU的至少部分子电路中的晶体管处于反向偏置状态；或者，响应于级联信号端Out-C的电位，通过级联信号控制连接上拉节点PU的至少部分子电路中的晶体管处于反向偏置状态。
本公开实施例提供的移位寄存器单元中，由于在移位寄存器单元中增加了反向偏置子电路111，反向偏置子电路111可以控制连接上拉节点PU的子电路中的晶体管处于反向偏置状态，例如，在上拉节点PU的电位为高电平电位时，反向偏置子电路111可以将电源电压信号或者级联信号输入至输入子电路101，控制输入子电路101中的晶体管处于反向偏置状态，使得输入信号端Input的输入信号可以有效输入上拉节点PU，保证上拉节点PU的电位可以稳定保持。同时，反向偏置子电路111可以将电源电压信号或级联信号输入至第一降噪子电路105，控制第一降噪子电路105中的晶体管处于反 向偏置状态，避免上拉节点PU发生漏电。可以看出，本公开实施例提供的移位寄存器单元中连接上拉节点PU的各个子电路(输入子电路101和第一降噪子电路105等)在反向偏置子电路111的配合下，可以保证上拉节点PU的电位可以达到预设电位，避免各个子电路中的晶体管的阈值电压发生负向偏移对上拉节点PU的电位造成影响，从而可以保证信号输出端Output的输出信号的稳定，进而可以保证所驱动的显示面板良好的显示效果。
在一些实施例中，如图2所示，反向偏置子电路111包括：反向偏置控制晶体管M0；反向偏置控制晶体管M0的栅极连接上拉节点PU，源极连接电源电压端VDD，漏极连接输入子电路101和第一降噪子电路105。
当上拉节点PU的电位为高电平电位时，反向偏置控制晶体管M0被打开，电源电压信号输入至输入子电路101，可以控制输入子电路101中的晶体管处于反向偏置状态，使得输入信号端Input的输入信号可以有效输入上拉节点PU，保证上拉节点PU的电位可以稳定保持。同时，电源电压信号输入至第一降噪子电路105，控制第一降噪子电路105中的晶体管处于反向偏置状态，避免上拉节点PU发生漏电。
在一些实施例中，如图3所示，反向偏置子电路111包括：反向偏置控制晶体管M0；反向偏置控制晶体管M0的栅极和源极均连接级联信号端Out-C，漏极连接输入子电路101和第一降噪子电路105。
当上拉节点PU的电位为高电平电位时，反向偏置控制晶体管M0被打开，此时级联信号为高电平信号，级联信号输入至输入子电路101，可以控制输入子电路101中的晶体管处于反向偏置状态，使得输入信号端Input的输入信号可以有效输入上拉节点PU，保证上拉节点PU的电位可以稳定保持。同时，级联信号输入至第一降噪子电路105，控制第一降噪子电路105中的晶体管处于反向偏置状态，避免上拉节点PU发生漏电。与上述的图2所示的移位寄存器单元不同之处在于，图3所示的移位寄存器单元中的反向 偏置控制晶体管M0的源极连接级联信号端Out-C，可以不必将反向偏置控制晶体管M0单独连接至电源电压端VDD，这样可以节约移位寄存器单元的能耗。
在一些实施例中，如图2和图3所示，输入子电路101包括：至少两个第一晶体管M1(两个第一晶体管M1分别用M1A和M1B表示)；两个第一晶体管M1A和M1B的栅极均连接信号输入端Input，其中一个第一晶体管M1A的源极连接信号输入端Input，漏极连接另一个第一晶体管M1B的源极和反向偏置子电路111，另一个第一晶体管M1B的漏极连接上拉节点PU。
在输入阶段，信号输入端Input写入高电平信号，第一晶体管M1A和M1B被打开，可以通过信号输入端Input写入的高电平信号对上拉节点进行预充电。在本公开实施例中，采用第一晶体管M1A和M1B的双晶体管，两个第一晶体管M1A和M1B可以同时工作，这样可以缓解两个第一晶体管M1A和M1B的阈值电压发生偏移，同时配合反向偏置子电路111，可以使得输入信号端Input的输入信号可以有效输入上拉节点PU，保证上拉节点PU的电位可以稳定保持。
在一些实施例中，如图2和图3所示，一个第一降噪子电路105包括：至少两个第八晶体管M8(两个第八晶体管M8分别用M8A1和M8A表示)；两个第八晶体管M8A1和M8A的栅极均连接第一下拉节点PD，即第八晶体管M8A1的栅极连接第一下拉节点PD1，第八晶体管M8A的栅极连接第二下拉节点PD2，其中一个第八晶体管M8A1的源极连接第一低电平端LVGL，漏极连接另一个第八晶体管M8A的源极和反向偏置子电路111，另一个第八晶体管M8A的漏极连接上拉节点PU。另一个第一降噪子电路105也采用同样的设置方式，其中的两个第八晶体管M8分别用M8B1和M8B表示，其连接方式与上述相同，在此不再赘述。
在降噪阶段，以其中一个第一降噪子电路105为例，第一下拉节点PD1 为高电平电位时，第八晶体管M8A1和M8A均被打开，此时可以通过第一低电平信号对拉节点PU进行降噪。在本公开实施例中，采用第八晶体管M8A1和M8A的双晶体管，两个第第八晶体管M8A1和M8A可以同时工作，这样可以缓解两个第八晶体管M8A1和M8A的阈值电压发生偏移，同时配合反向偏置子电路111，可以避免第八晶体管M8A1和M8A发生不完全打开，从而可以避免上拉节点PU发生漏电。另一个第一降噪子电路105的实现原理与上述类似，在此不再赘述。
在一些实施例中，如图2和图3所示，移位寄存器单元还包括：第一复位子电路108；第一复位子电路108被配置为响应于复位信号，通过第一低电平信号对上拉节点PU的电位进行复位。具体地，第一复位子电路108包括：至少两个第二晶体管M2(两个第二晶体管M2分别用M2A和M2B表示)；两个第二晶体管M2A和M2B的栅极均连接复位信号端Reset，其中一个第二晶体管M2A的源极连接第一低电平端LVGL，漏极连接另一个第二晶体管M2B的源极和反向偏置子电路111，另一个第二晶体管M2B的漏极连接上拉节点PU。
在复位阶段，复位信号端Reset输入高电平信号，第二晶体管M2A和M2B被打开，此时可以通过第二低电平信号对上拉节点PU进行复位。在本公开实施例中，采用第二晶体管M2A和M2B的双晶体管，两个第二晶体管M2A和M2B可以同时工作，这样可以缓解两个第二晶体管M2A和M2B的阈值电压发生偏移，同时配合反向偏置子电路111，可以避免第二晶体管M2A和M2B发生不完全打开，可以避免上拉节点PU发生漏电。
在一些实施例中，如图2和图3所示，移位寄存器单元还包括：移位重置子电路110；移位重置子电路110被配置为响应于移位重置信号，通过第一低电平信号对上拉节点PU的电位进行重置。具体地，移位重置子电路110包括：至少两个第十五晶体管M15(两个第十五晶体管M15分别用M15A 和M15B表示)；两个第十五晶体管M15A和M15B的栅极极均连接移位重置信号端T-RST，其中一个第十五晶体管M15A的源极连接第一低电平端LVGL，漏极连接另一个第十五晶体管M15B的源极和反向偏置子电路111，另一个第十五晶体管M15B的漏极连接上拉节点PU。
在结束阶段，移位重置信号端T-RST写入高电平信号，第十五晶体管M15A和M15B被打开，上拉节点PU被写入第一低电平信号端LVGL的第一电平信号，对上拉节点PU的电位进行重置。在本公开实施例中，采用第十五晶体管M15A和M15B的双晶体管，两个第十五晶体管M15A和M15B可以同时工作，这样可以缓解两个第十五晶体管M15A和M15B的阈值电压发生偏移，同时配合反向偏置子电路111，可以避免第十五晶体管M15A和M15B发生不完全打开，可以避免上拉节点PU发生漏电。
在一些实施例中，如图2和图3所示，移位寄存器单元还包括：第二复位子电路109；第二复位子电路109被配置为响应于复位信号，通过第二参考电平信号对信号输出端Output的电位进行复位。具体地，第二复位子电路109包括：第四晶体管M4；第四晶体管M4的栅极连接复位信号端Reset，源极连接第二低电平端VGL，漏极连接信号输出端Output。
在复位阶段，复位信号端Reset输入高电平信号，第四晶体管M4被打开，此时可以通过第一低电平信号对信号输出端Output进行复位。
在一些实施例中，如图2和图3所示，移位寄存器单元还包括：至少一个第二降噪子电路106；第二降噪子电路106被配置为响应于下拉节点PD的电位，通过第二低电平信号对信号输出端Output的电位进行降噪。具体地，一个第二降噪子电路106包括：第十三晶体管M13A；第十三晶体管M13A的栅极连接第一下拉节点PD1，源极连接第二低电平端VGL，漏极连接信号输出端Output。另一个第二降噪子电路106包括：第十三晶体管M13B，其连接方式与上述的第十三晶体管M13A的连接方式类似，在此不再赘述。
在降噪阶段，第一下拉节点PD1为高电平电位时，第十三晶体管M13A被打开，此时可以通过第二低电平信号对信号输出端Output进行降噪。第二下拉节点PD2为高电平时，第十三晶体管M13B被打开，此时可以通过第二低电平信号对信号输出端Output进行降噪。两个第十三晶体管M13A和M13B分时开启，以提高第十三晶体管M13A和M13B的使用寿命。
在一些实施例中，如图2和图3所示，移位寄存器单元还包括：至少一个第三降噪子电路107：第三降噪子电路107被配置为响应于下拉节点PD的电位，通过第一低电平信号对级联信号端Out-C的电位进行降噪。具体地，一个第三降噪子电路107包括：第十二晶体管M12A；第十二晶体管M12A的栅极连接第一下拉节点PD1，源极连接第一低电平端，漏极连接级联信号端Out-C。另一个第三降噪子电路107包括：第十二晶体管M12B；其连接方式与上述的第十二晶体管M12A的连接方式类似，在此不再赘述。
在降噪阶段，第一下拉节点PD1为高电平电位时，第十二晶体管M12A被打开，此时可以通过第一低电平信号对级联信号端Out-C进行降噪。第二下拉节点PD2为高电平时，第十二晶体管M12B被打开，此时可以通过第一低电平信号对级联信号端Out-C进行降噪。两个第十二晶体管M12A和M12B分时开启，以提高第十二晶体管M12A和M12B的使用寿命。
在一些实施例中，如图2和图3所示，输出子电路102包括：第三晶体管M3、第十一晶体管M11和存储电容C；第三晶体管M3的栅极连接上拉节点PU，源极连接时钟信号端CLK，漏极连接信号输出端Output；第十一晶体管M11的栅极连接上拉节点PU，源极连接时钟信号端CLK，漏极连接级联信号端Out-C；存储电容C的一端连接上拉节点PU，另一端连接信号输出端Output。
输出阶段：信号输入端Input输入低电平信号，第一晶体管M1关闭。此时由于在预充阶段存储电容C被充电，上拉节点PU的电位被进一步拉高； 由于第三晶体管M3和第十一晶体管M11的栅极均连接上拉节点PU，第三晶体管M3和第十一晶体管M11被打开，输出信号端Output将时钟信号端CLK的时钟信号作为输出信号输出，级联信号端Out-C将时钟信号作为级联信号输出。此时时钟信号为高电平信号，输出信号也为高电平信号。
在一些实施例中，如图2和图3所示，一个下拉控制子电路103包括：第五晶体管M5A；第五晶体管M5A的栅极和源极均连接电源电压端VDDo，漏极连接第一下拉节点PD1。另一个下拉控制子电路103包括：第五晶体管M5B；第五晶体管M5B的连接方式与上述类似，在此不在赘述。
第五晶体管M5A的栅极和源极连接电源电压端VDDo，也即被写入电源电压信号时，此时第五晶体管M5A打开，第一下拉节点PD1的电位则为电源电压的电位，也即第一下拉节点PD的电位为高电平。第五晶体管M5B的栅极和源极连接电源电压端VDDe，也即被写入电源电压信号时，此时第五晶体管M5B打开，第二下拉节点PD2的电位则为电源电压的电位，也即第二下拉节点PD2的电位为高电平。
在一些实施例中，如图2和图3所示，一个下拉子电路104包括：第六晶体管M6A和第七晶体管M7A；第六晶体管M6A的栅极连接上拉节点PU，源极连接第一低电平端LVGL，漏极连接第一下拉节点PD1；第七晶体管M7A的栅极连接信号输入端Output，源极连接第一低电平端LVGL，漏极连接第一下拉节点PD1。另一个下拉子电路104包括：第六晶体管M6B和第七晶体管M7B；第六晶体管M6B和第七晶体管M7B的连接方式与上述类似，在此不再赘述。
信号输入端Input写入高电平信号时，第七晶体管M7A打开，第一下拉节点PD1被写入第一低电平信号，同时上拉节点PU写入高电平信号，第六晶体管M6A打开，第一下拉节点PD1可以持续被写入第一低电平信号，保证第一下拉节点PD1的电位被持续拉低。同理，第六晶体管M6B和第七晶 体管M7B可以保证第二下拉节点PD2的电位持续被拉低。
本公开实施例还提供了一种移位寄存器单元，如图2所示，移位寄存器单元包括：输入子电路101、输出子电路102、至少一个下拉控制子电路103、至少一个下拉子电路104、至少一个第一降噪子电路105、至少一个第二降噪子电路106、至少一个第三降噪子电路107、第一复位子电路108、第二复位子电路109、移位重置子电路110和反向偏置子电路111；上拉节点PU至少同时连接输入子电路101、输出子电路102、第一降噪子电路105；下拉节点PD至少同时连接下拉控制子电路103、下拉子电路104和第一降噪子电路105。
输入子电路101包括：至少两个第一晶体管M1A和M1B；输出子电路102包括：第三晶体管Mmhg3、第十一晶体管M11和存储电容C；下拉控制子电路103包括：第五晶体管M5A和M5B；下拉子电路104包括：第六晶体管M6A和M6B、第七晶体管M7A和M7B；第一降噪子电路105包括：至少两个第八晶体管M8A1、M8A、M8B1和M8B；第二降噪子电路106包括：第十三晶体管M13A和M13B；第三降噪子电路107包括：第十二晶体管M12A和M12B；第一复位子电路108包括：至少两个第二晶体管M2A和M2B；第二复位子电路109包括：第四晶体管M4；移位重置子电路110包括：至少两个第十五晶体管M15A和M15B；反向偏置子电路111包括：反向偏置控制晶体管M0。其中，反向偏置控制晶体管M0的栅极连接上拉节点PU，源极连接电源电压端VDD，漏极连接一个第一晶体管M1A的漏极、一个第八晶体管M8A的漏极、一个第二晶体管M2A的漏极和一个第十五晶体管M15A的漏极。其他各个晶体管的连接方式及实现原理与上述类似，在此不再赘述。
本公开实施例还提供了另一种移位寄存器单元，如图3所示，移位寄存器单元包括：输入子电路101、输出子电路102、至少一个下拉控制子电路 103、至少一个下拉子电路104、至少一个第一降噪子电路105、至少一个第二降噪子电路106、至少一个第三降噪子电路107、第一复位子电路108、第二复位子电路109、移位重置子电路110和反向偏置子电路111；上拉节点PU至少同时连接输入子电路101、输出子电路102、第一降噪子电路105；下拉节点PD至少同时连接下拉控制子电路103、下拉子电路104和第一降噪子电路105。
输入子电路101包括：至少两个第一晶体管M1A和M1B；输出子电路102包括：第三晶体管M3、第十一晶体管M11和存储电容C；下拉控制子电路103包括：第五晶体管M5A和M5B；下拉子电路104包括：第六晶体管M6A和M6B、第七晶体管M7A和M7B；第一降噪子电路105包括：至少两个第八晶体管M8A1、M8A、M8B1和M8B；第二降噪子电路106包括：第十三晶体管M13A和M13B；第三降噪子电路107包括：第十二晶体管M12A和M12B；第一复位子电路108包括：至少两个第二晶体管M2A和M2B；第二复位子电路109包括：第四晶体管M4；移位重置子电路110包括：至少两个第十五晶体管M15A和M15B；反向偏置子电路111包括：反向偏置控制晶体管M0。其中，反向偏置控制晶体管M0的栅极和源极连接级联信号端Out-C，漏极连接一个第一晶体管M1A的漏极、一个第八晶体管M8A的漏极、一个第二晶体管M2A的漏极和一个第十五晶体管M15A的漏极。其他各个晶体管的连接方式及实现原理与上述类似，在此不再赘述。
与上述的图2所示的移位寄存器单元不同之处在于，图3所示的移位寄存器单元中的反向偏置控制晶体管M0的源极连接级联信号端Out-C，可以不必将反向偏置控制晶体管M0单独连接至电源电压端VDD，这样可以节约移位寄存器单元的能耗。
本公开实施例还提供了一种栅极驱动电路，该栅极驱动电路包括多个相互级联的如上述任一实施例提供的移位寄存器单元。
本公开实施例提供的栅极驱动电路可以逐级输出扫描信号，以驱动显示面板进行逐行扫描，以实现显示功能。栅极驱动电路的移位寄存器单元中，由于在移位寄存器单元中增加了反向偏置子电路111，反向偏置子电路111可以控制连接上拉节点PU的子电路中的晶体管处于反向偏置状态，另外连接上拉节点PU的各个子电路采用双晶体管的结构。例如，在上拉节点PU的电位为高电平电位时，反向偏置子电路111可以将电源电压信号或者级联信号输入至输入子电路101，控制输入子电路101中的晶体管处于反向偏置状态，同时输入子电路101采用双晶体管的结构，使得输入信号端Input的输入信号可以有效输入上拉节点PU，保证上拉节点PU的电位可以稳定保持。同时，反向偏置子电路111可以将电源电压信号或级联信号输入至第一降噪子电路105，控制第一降噪子电路105中的晶体管处于反向偏置状态，同时第一降噪子电路105采用双晶体管的结构，避免上拉节点PU发生漏电。可以看出，本公开实施例提供的移位寄存器单元中连接上拉节点PU的各个子电路(例如输入子电路101和第一降噪子电路105等)在反向偏置子电路111的配合下，可以保证上拉节点PU的电位可以达到预设电位，避免各个子电路中的晶体管的阈值电压发生负向偏移对上拉节点PU的电位造成影响，从而可以保证信号输出端Output的输出信号的稳定，进而可以保证所驱动的显示面板良好的显示效果。
本公开实施例还提供了一种显示装置，该显示装置包括如上述任一实施例提供的栅极驱动电路，该显示装置可以为大尺寸电视、显示器、车载导航等显示设备，其实现原理及技术效果与上述任一实施例提供的栅极驱动电路的实现原理及技术效果相同，在此不在赘述。
本公开实施例还提供了一种移位寄存器单元的驱动方法，用于驱动如上述任一实施例提供的移位寄存器单元，其中，移位寄存器单元的驱动方法包括：当上拉节点的电位为高电平时，利用反向偏置子电路将电源电压信号或 级联信号写入输入子电路和第一降噪子电路，使得输入子电路和第一降噪子电路中的晶体管处于反向偏置状态。
本公开实施例提供的移位寄存器单元的驱动方法中，可以将电源电压信号或级联信号写入输入子电路或第一降噪子电路，使得输入子电路和第一降噪子电路中的晶体管处于反向偏置状态，可以保证上拉节点PU的电位可以达到预设电位，避免各个子电路中的晶体管的阈值电压发生负向偏移对上拉节点PU的电位造成影响，从而可以保证信号输出端Output的输出信号的稳定，进而可以保证所驱动的显示面板良好的显示效果。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (23)

  1. 一种移位寄存器单元，其中，所述移位寄存器单元包括：输入子电路、输出子电路、至少一个下拉控制子电路、至少一个下拉子电路、至少一个第一降噪子电路和反向偏置子电路；
    所述输入子电路被配置为响应于信号输入端的输入信号，通过所述输入信号对上拉节点的电位进行拉高；所述上拉节点至少同时连接所述输入子电路、所述输出子电路、所述第一降噪子电路；
    所述输出子电路被配置为响应于所述上拉节点被拉高后的电位，通过信号输出端输出信号及通过级联信号端输出信号；
    所述下拉控制子电路被配置为响应于电源电压信号，利用所述电源电压信号控制下拉节点的电位；所述下拉节点至少同时连接所述下拉控制子电路、所述下拉子电路和所述第一降噪子电路；
    所述下拉子电路被配置为响应于所述上拉节点和所述信号输入端的电位，通过第一参考电平信号下拉所述下拉节点的电位；
    所述第一降噪子电路被配置为响应于所述下拉节点的电位，通过第一参考电平信号对所述上拉节点的电位进行降噪；
    所述反向偏置子电路被配置为响应于所述上拉节点的电位，通过电源电压信号控制连接所述上拉节点的至少部分子电路中的晶体管处于反向偏置状态；或者，响应于级联信号端的电位，通过级联信号控制连接所述上拉节点的至少部分子电路中的晶体管处于反向偏置状态。
  2. 根据权利要求1所述的移位寄存器单元，其中，所述反向偏置子电路包括：反向偏置控制晶体管；
    所述反向偏置控制晶体管的控制极连接所述上拉节点，第一极连接电源电压端，第二极连接所述输入子电路和所述第一降噪子电路。
  3. 根据权利要求1所述的移位寄存器单元，其中，所述反向偏置子电路包括：反向偏置控制晶体管；
    所述反向偏置控制晶体管的控制极和第一极均连接所述级联信号端，第二极连接所述输入子电路和所述第一降噪子电路。
  4. 根据权利要求1所述的移位寄存器单元，其中，所述输入子电路包括：至少两个第一晶体管；
    两个所述第一晶体管的控制极均连接所述信号输入端，其中一个所述第一晶体管的第一极连接所述信号输入端，第二极连接另一个所述第一晶体管的第一极和所述反向偏置子电路，另一个所述第一晶体管的第二极连接所述上拉节点。
  5. 根据权利要求1所述的移位寄存器单元，其中，所述第一降噪子电路包括：至少两个第八晶体管；
    两个所述第八晶体管的控制极均连接所述下拉节点，其中一个所述第八晶体管的第一极连接第一参考电平端，第二极连接另一个所述第八晶体管的第一极和所述反向偏置子电路，另一个所述第八晶体管的第二极连接所述上拉节点。
  6. 根据权利要求1所述的移位寄存器单元，其中，所述移位寄存器单元还包括：第一复位子电路；
    所述第一复位子电路被配置为响应于复位信号，通过第一参考电平信号对所述上拉节点的电位进行复位。
  7. 根据权利要求6所述的移位寄存器单元，其中，所述第一复位子电路包括：至少两个第二晶体管；
    两个所述第二晶体管的控制极均连接复位信号端，其中一个所述第二晶体管的第一极连接第一参考电平端，第二极连接另一个所述第二晶体管的第一极和所述反向偏置子电路，另一个所述第二晶体管的第二极连接所述上拉节点。
  8. 根据权利要求1所述的移位寄存器单元，其中，所述移位寄存器单元还包括：移位重置子电路；
    所述移位重置子电路被配置为响应于移位重置信号，通过第一参考电平信号对所述上拉节点的电位进行重置。
  9. 根据权利要求8所述的移位寄存器单元，其中，所述移位重置子电路包括：至少两个第十五晶体管；
    两个所述第十五晶体管的控制极均连接移位重置信号端，其中一个所述第十五晶体管的第一极连接第一参考电平端，第二极连接另一个所述第十五晶体管的第一极和所述反向偏置子电路，另一个所述第十五晶体管的第二极连接所述上拉节点。
  10. 根据权利要求1所述的移位寄存器单元，其中，所述移位寄存器单元还包括：第二复位子电路；
    所述第二复位子电路被配置为响应于所述复位信号，通过第二参考电平信号对所述信号输出端的电位进行复位。
  11. 根据权利要求10所述的移位寄存器单元，其中，所述第二复位子电路包括：第四晶体管；
    所述第四晶体管的控制极连接复位信号端，第一极连接第二参考电平端，第二极连接所述信号输出端。
  12. 根据权利要求1所述的移位寄存器单元，其中，所述移位寄存器单元还包括：至少一个第二降噪子电路；
    所述第二降噪子电路被配置为响应于所述下拉节点的电位，通过第二参考电平信号对所述信号输出端的电位进行降噪。
  13. 根据权利要求12所述的移位寄存器单元，其中，所述第二降噪子电路包括：第十三晶体管；
    所述第十三晶体管的控制极连接所述下拉节点，第一极连接第二参考电平端，第二极连接所述信号输出端。
  14. 根据权利要求1所述的移位寄存器单元，其中，所述移位寄存器单元还包括：至少一个第三降噪子电路：
    所述第三降噪子电路被配置为响应于所述下拉节点的电位，通过第一参考电平信号对所述级联信号端的电位进行降噪。
  15. 根据权利要求14所述的移位寄存器单元，其中，所述第三降噪子电路包括：第十二晶体管；
    所述第十二晶体管的控制极连接所述下拉节点，第一极连接第一参考电平端，第二极连接所述级联信号端。
  16. 根据权利要求1所述的移位寄存器单元，其中，所述输出子电路包括：第三晶体管、第十一晶体管和存储电容；
    所述第三晶体管的控制极连接所述上拉节点，第一极连接时钟信号端，第二极连接信号输出端；
    所述第十一晶体管的控制极连接所述上拉节点，第一极连接时钟信号端，第二极连接级联信号端；
    所述存储电容的一端连接所述上拉节点，另一端连接信号输出端。
  17. 根据权利要求1所述的移位寄存器单元，其中，所述下拉控制子电路包括：第五晶体管；
    所述第五晶体管的控制极和第一极均连接电源电压端，第二极连接所述下拉节点。
  18. 根据权利要求1所述的移位寄存器单元，其中，所述下拉子电路包括：第六晶体管和第七晶体管；
    所述第六晶体管的控制极连接所述上拉节点，第一极连接第一参考电平端，第二极连接所述下拉节点；
    所述第七晶体管的控制极连接信号输入端，第一极连接第一参考电平端，第二极连接所述下拉节点。
  19. 一种移位寄存器单元，其中，所述移位寄存器单元包括：输入子电路、输出子电路、至少一个下拉控制子电路、至少一个下拉子电路、至少一个第一降噪子电路、至少一个第二降噪子电路、至少一个第三降噪子电路、 第一复位子电路、第二复位子电路、移位重置子电路和反向偏置子电路；上拉节点至少同时连接所述输入子电路、所述输出子电路、所述第一降噪子电路；下拉节点至少同时连接所述下拉控制子电路、所述下拉子电路和所述第一降噪子电路；
    所述输入子电路包括：至少两个第一晶体管；所述输出子电路包括：第三晶体管、第十一晶体管和存储电容；所述下拉控制子电路包括：第五晶体管；所述下拉子电路包括：第六晶体管和第七晶体管；所述第一降噪子电路包括：至少两个第八晶体管；所述第二降噪子电路包括：第十三晶体管；所述第三降噪子电路包括：第十二晶体管；所述第一复位子电路包括：至少两个第二晶体管；所述第二复位子电路包括：第四晶体管；所述移位重置子电路包括：至少两个第十五晶体管；所述反向偏置子电路包括：反向偏置控制晶体管；
    两个所述第一晶体管的控制极均连接所述信号输入端，其中一个所述第一晶体管的第一极连接所述信号输入端，第二极连接另一个所述第一晶体管的第一极和所述反向偏置控制晶体管的第二极，另一个所述第一晶体管的第二极连接所述上拉节点；
    所述第三晶体管的控制极连接所述上拉节点，第一极连接时钟信号端，第二极连接信号输出端；
    所述第十一晶体管的控制极连接所述上拉节点，第一极连接时钟信号端，第二极连接级联信号端；
    所述存储电容的一端连接所述上拉节点，另一端连接信号输出端；
    所述第五晶体管的控制极和第一极均连接电源电压端，第二极连接所述下拉节点；
    所述第六晶体管的控制极连接所述上拉节点，第一极连接第一参考电平端，第二极连接所述下拉节点；
    所述第七晶体管的控制极连接所述信号输入端，第一极连接第一参考电 平端，第二极连接所述下拉节点；
    两个所述第八晶体管的控制极均连接所述下拉节点，其中一个所述第八晶体管的第一极连接第一参考电平端，第二极连接另一个所述第八晶体管的第一极和所述反向偏置控制晶体管的第二极，另一个所述第八晶体管的第二极连接所述上拉节点；
    所述第十三晶体管的控制极连接所述下拉节点，第一极连接第二参考电平端，第二极连接所述信号输出端；
    所述第十二晶体管的控制极连接所述下拉节点，第一极连接第一参考电平端，第二极连接所述级联信号端；
    两个所述第二晶体管的控制极均连接复位信号端，其中一个所述第二晶体管的第一极连接第一参考电平端，第二极连接另一个所述第二晶体管的第一极和所述反向偏置子电路，另一个所述第二晶体管的第二极连接所述上拉节点；
    所述第四晶体管的控制极连接复位信号端，第一极连接第二参考电平端，第二极连接所述信号输出端；
    两个所述第十五晶体管的控制极均连接移位重置信号端，其中一个所述第十五晶体管的第一极连接第一参考电平端，第二极连接另一个所述第十五晶体管的第一极和所述反向偏置控制晶体管的第二极，另一个所述第十五晶体管的第二极连接所述上拉节点；
    所述反向偏置控制晶体管的控制极连接所述上拉节点，第一极连接电源电压端，第二极连接一个所述第一晶体管的第二极、一个所述第八晶体管的第二极、一个所述第二晶体管的第二极和一个所述第十五晶体管的第二极。
  20. 一种移位寄存器单元，其中，所述移位寄存器单元包括：输入子电路、输出子电路、至少一个下拉控制子电路、至少一个下拉子电路、至少一个第一降噪子电路、至少一个第二降噪子电路、至少一个第三降噪子电路、第一复位子电路、第二复位子电路、移位重置子电路和反向偏置子电路；上 拉节点至少同时连接所述输入子电路、所述输出子电路、所述第一降噪子电路；下拉节点至少同时连接所述下拉控制子电路、所述下拉子电路和所述第一降噪子电路；
    所述输入子电路包括：至少两个第一晶体管；所述输出子电路包括：第三晶体管、第十一晶体管和存储电容；所述下拉控制子电路包括：第五晶体管；所述下拉子电路包括：第六晶体管和第七晶体管；所述第一降噪子电路包括：至少两个第八晶体管；所述第二降噪子电路包括：第十三晶体管；所述第三降噪子电路包括：第十二晶体管；所述第一复位子电路包括：至少两个第二晶体管；所述第二复位子电路包括：第四晶体管；所述移位重置子电路包括：至少两个第十五晶体管；所述反向偏置子电路包括：反向偏置控制晶体管；
    两个所述第一晶体管的控制极均连接信号输入端，其中一个所述第一晶体管的第一极连接所述信号输入端，第二极连接另一个所述第一晶体管的第一极和所述反向偏置控制晶体管的第二极，另一个所述第一晶体管的第二极连接所述上拉节点；
    所述第三晶体管的控制极连接所述上拉节点，第一极连接时钟信号端，第二极连接信号输出端；
    所述第十一晶体管的控制极连接所述上拉节点，第一极连接时钟信号端，第二极连接级联信号端；
    所述存储电容的一端连接所述上拉节点，另一端连接信号输出端；
    所述第五晶体管的控制极和第一极均连接电源电压端，第二极连接所述下拉节点；
    所述第六晶体管的控制极连接所述上拉节点，第一极连接第一参考电平端，第二极连接所述下拉节点；
    所述第七晶体管的控制极连接所述信号输入端，第一极连接第一参考电平端，第二极连接所述下拉节点；
    两个所述第八晶体管的控制极均连接所述下拉节点，其中一个所述第八晶体管的第一极连接第一参考电平端，第二极连接另一个所述第八晶体管的第一极和所述反向偏置控制晶体管的第二极，另一个所述第八晶体管的第二极连接所述上拉节点；
    所述第十三晶体管的控制极连接所述下拉节点，第一极连接第二参考电平端，第二极连接所述信号输出端；
    所述第十二晶体管的控制极连接所述下拉节点，第一极连接第一参考电平端，第二极连接所述级联信号端；
    两个所述第二晶体管的控制极均连接复位信号端，其中一个所述第二晶体管的第一极连接第一参考电平端，第二极连接另一个所述第二晶体管的第一极和所述反向偏置子电路，另一个所述第二晶体管的第二极连接所述上拉节点；
    所述第四晶体管的控制极连接复位信号端，第一极连接第二参考电平端，第二极连接所述信号输出端；
    两个所述第十五晶体管的控制极均连接移位重置信号端，其中一个所述第十五晶体管的第一极连接第一参考电平端，第二极连接另一个所述第十五晶体管的第一极和所述反向偏置控制晶体管的第二极，另一个所述第十五晶体管的第二极连接所述上拉节点；
    所述反向偏置控制晶体管的控制极和第一极连接级联信号端，第二极连接一个所述第一晶体管的第二极、一个所述第八晶体管的第二极、一个所述第二晶体管的第二极和一个所述第十五晶体管的第二极。
  21. 一种栅极驱动电路，其中，所述栅极驱动电路包括多个相互级联的如权利要求1-20任一项所述的移位寄存器单元。
  22. 一种显示装置，其中，所述显示装置包括如权利要求21所述的栅极驱动电路。
  23. 一种移位寄存器单元的驱动方法，用于驱动如权利要求1-20任一 项所述的移位寄存器单元，其中，所述移位寄存器单元的驱动方法包括：
    当上拉节点的电位为第三参考电平时，利用反向偏置子电路将电源电压信号或级联信号写入输入子电路和第一降噪子电路，使得所述输入子电路和所述第一降噪子电路中的晶体管处于反向偏置状态。
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