WO2022062415A1 - 电荷共享电路、方法、显示驱动模组和显示装置 - Google Patents

电荷共享电路、方法、显示驱动模组和显示装置 Download PDF

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Publication number
WO2022062415A1
WO2022062415A1 PCT/CN2021/092101 CN2021092101W WO2022062415A1 WO 2022062415 A1 WO2022062415 A1 WO 2022062415A1 CN 2021092101 W CN2021092101 W CN 2021092101W WO 2022062415 A1 WO2022062415 A1 WO 2022062415A1
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Prior art keywords
output
control
clock signal
terminal
electrically connected
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PCT/CN2021/092101
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English (en)
French (fr)
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赵新江
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北京奕斯伟计算技术有限公司
合肥奕斯伟集成电路有限公司
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Priority to US17/420,699 priority Critical patent/US11749189B2/en
Publication of WO2022062415A1 publication Critical patent/WO2022062415A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0814—Several active elements per pixel in active matrix panels used for selection purposes, e.g. logical AND for partial update
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G09G2330/023—Power management, e.g. power saving using energy recovery or conservation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a charge sharing circuit, a method, a display driving module and a display device.
  • the gate driving signal connected to the gate of the data writing transistor in the pixel circuit is controlled by the clock signal provided by the corresponding clock signal generating circuit, so it can be output by the clock signal of the clock signal generating unit in different stages
  • a sharing switch is arranged between the terminals, so as to realize the gate charge sharing of the data writing transistors in the pixel circuits of different rows on the display panel.
  • a shared signal is generated according to the first clock signal and the second clock signal, and then the shared signal is converted to the low-voltage VGL negative voltage power domain through a level shift circuit, and then passed through a level shift
  • the circuit is converted to the shared switching power supply domain to control the on-off of the shared switch; the charge sharing circuit in the related art adopts a large number of level conversion circuits, which occupies a large area of the chip.
  • the main purpose of the present disclosure is to provide a charge sharing circuit, a method, a display driving module and a display device, so as to solve the technical problem that the charge sharing circuit in the related art adopts a large number of level conversion circuits and occupies a large area of the chip. .
  • the present disclosure provides a charge sharing circuit, which is applied to a display device, the display device includes a gate driving circuit and a clock signal generating circuit, and the gate driving circuit includes a multi-level shift register unit;
  • the clock signal generation circuit includes at least two clock signal generation units; the two clock signal generation units in the at least two clock signal generation circuits respectively provide corresponding clock signals for two adjacent shift register units;
  • the signal generating unit includes a clock signal output terminal, a first output control terminal and a first output module, and the first output module is used to control whether to pass the first output control signal provided by the first output control terminal.
  • the clock signal output terminal outputs a first voltage signal;
  • the charge sharing circuit includes a control unit and a switch unit, wherein,
  • the control unit is respectively electrically connected to the first output control terminals included in the two clock signal generating units, and is used for controlling not to output when the first output module is under the control of the first output control signal When the first voltage signal is used, an opening control signal is provided to the switch unit through the control signal output terminal;
  • the switch unit is respectively electrically connected to the control signal output end and the clock signal output end included in the two clock signal generating units, and is used for controlling the two clocks to be turned on under the control of the turn-on control signal
  • the signal generating unit includes connections between clock signal output terminals.
  • the switch unit includes a first switch transistor and a second switch transistor;
  • Both the control electrode of the first switching transistor and the control electrode of the second switching transistor are electrically connected to the control signal output terminal;
  • the first pole of the first switching transistor is electrically connected to the clock signal output end of the first clock signal generating unit of the two clock signal generating units, and the second pole of the first switching transistor is electrically connected to the first clock signal generating unit.
  • the first poles of the two switching transistors are electrically connected, and the second poles of the second switching transistors are electrically connected to the clock signal output terminal of the second clock signal generating unit in the two clock signal generating units;
  • Both the first switching transistor and the second switching transistor are p-type transistors; or, both the first switching transistor and the second switching transistor are n-type transistors.
  • the first output module is configured to control not to output the first voltage signal through the clock signal output terminal when the first output control signal is a low voltage signal;
  • the control unit includes a NOR gate and a control module
  • the first input terminal of the NOR gate is electrically connected to the first output of the first clock signal generating unit, and the second input terminal of the NOR gate is electrically connected to the first output terminal of the second clock signal generating unit.
  • an output control terminal is electrically connected;
  • the control module is electrically connected to the output terminal of the NOR gate, and is used for controlling both the first switching transistor and the second switching transistor to be turned on when the NOR gate outputs a high voltage signal through its output terminal.
  • both the first switch transistor and the second switch transistor are p-type transistors
  • the control module includes a first level conversion circuit and a first p-type drive circuit
  • the first level conversion circuit is electrically connected to the output end of the NOR gate, and the first level conversion circuit is used to perform level conversion on the signal output by the NOR gate through its output end, and convert the The first control signal obtained by level conversion is provided to the input end of the first p-type driving circuit;
  • the output end of the first p-type drive circuit is electrically connected to the control signal output end, and the first p-type drive circuit is used for inverting the first control signal to obtain a second control signal, and The second control signal is output to the control electrode of the first switching transistor through the control signal output terminal, and the driving capability of the output terminal of the first p-type driving circuit can be improved.
  • both the first switch transistor and the second switch transistor are n-type transistors
  • the control module includes a first level conversion circuit and a first n-type drive circuit
  • the first level conversion circuit is electrically connected to the output end of the NOR gate, and the first level conversion circuit is used to perform level conversion on the signal output by the NOR gate through its output end, and convert the The first control signal obtained by level conversion is provided to the input end of the first n-type driving circuit;
  • the output terminal of the first n-type driving circuit is electrically connected to the control signal output terminal, and the first n-type driving circuit is used for providing the first control signal to the first n-type driving circuit through the control signal output terminal.
  • a control electrode of a switching transistor can improve the driving capability of the output end of the first n-type driving circuit.
  • the first output module is configured to control not to output the first voltage signal through the gate driving signal when the first output control signal is a high voltage signal;
  • the control unit includes a NAND gate and a control module
  • the first input terminal of the NAND gate is electrically connected to the first output of the first clock signal generating unit, and the second input terminal of the NAND gate is electrically connected to the first output terminal of the second clock signal generating unit.
  • an output control terminal is electrically connected;
  • the control module is electrically connected to the output terminal of the NAND gate, and is used for controlling both the first switching transistor and the second switching transistor to be turned on when the NAND gate outputs a low voltage signal through its output terminal.
  • the present disclosure also provides a charge sharing method, which is applied to the above-mentioned charge sharing circuit, and the charge sharing method includes:
  • the control unit When the first output module is controlled not to output the first voltage signal under the control of the first output control signal, the control unit provides an opening control signal to the switch unit through the control signal output terminal;
  • the switch unit controls the connection between the clock signal output terminals included in the two clock signal generating units to be turned on under the control of the open control signal.
  • the present disclosure also provides a display driving module, including a clock signal generating circuit and the above-mentioned charge sharing circuit.
  • the clock signal generating circuit includes a plurality of clock signal generating units
  • the clock signal generating unit includes a clock signal output terminal, a first output control terminal, a second output control terminal, a first output module and a second output module;
  • the first output module is configured to control whether to output the first voltage signal through the clock signal output end under the control of the first output control signal provided by the first output control end;
  • the second output module is configured to control whether to output a second voltage signal through the clock signal output end under the control of the second output control signal provided by the second output control end.
  • the present disclosure also provides a display device including the above-mentioned display driving module.
  • the charge sharing circuit, method, display driving module, and display device described in the embodiments of the present disclosure control the control unit through the first output control terminal included in the two clock signal generating units of the at least two clock signal generating units by the control unit.
  • an opening control signal is provided to the switching unit, and the switching unit, under the control of the opening control signal, controls to turn on the clocks included in the two clock signal generating units
  • the connection between the signal output terminals is used for charge sharing, which can reduce the number of level conversion circuits used and save the chip area.
  • 1 is a structural diagram of an embodiment of a clock signal generation unit
  • FIG. 2 is a structural diagram of a charge sharing circuit according to an embodiment of the present disclosure
  • FIG. 3 is a circuit diagram of a charge sharing circuit according to another embodiment of the present disclosure.
  • FIG. 4 is a circuit diagram of a specific embodiment of the charge sharing circuit described in the present disclosure.
  • the transistors used in all the embodiments of the present disclosure may be triodes, thin film transistors, field effect transistors, or other devices with the same characteristics.
  • one pole is called the first pole, and the other pole is called the second pole.
  • control electrode when the transistor is a triode, the control electrode may be the base electrode, the first electrode may be the collector electrode, and the second electrode may be the emitter electrode; or the control electrode may be the base electrode electrode, the first electrode can be an emitter electrode, and the second electrode can be a collector electrode.
  • the control electrode when the transistor is a thin film transistor or a field effect transistor, the control electrode may be a gate electrode, the first electrode may be a drain electrode, and the second electrode may be a source electrode;
  • the control electrode may be a gate electrode, the first electrode may be a source electrode, and the second electrode may be a drain electrode.
  • the charge sharing circuit described in the embodiments of the present disclosure is applied to a display device, where the display device includes a gate driving circuit and a clock signal generating circuit, the gate driving circuit includes a plurality of shift register units, and the clock signal generating circuit
  • the circuit includes at least two clock signal generating units; the two clock signal generating units in the at least two clock signal generating circuits respectively provide corresponding clock signals for two adjacent shift register units;
  • the clock signal generating units include a clock signal output terminal, a first output control terminal and a first output module, the first output module is used to control whether to pass the clock signal under the control of the first output control signal provided by the first output control terminal
  • the output terminal outputs a first voltage signal;
  • the charge sharing circuit according to the embodiment of the present disclosure includes a control unit and a switch unit, wherein,
  • the control unit is respectively electrically connected to the first output control terminals included in the two clock signal generating units, and is used for controlling not to output when the first output module is under the control of the first output control signal When the first voltage signal is used, an opening control signal is provided to the switch unit through the control signal output terminal;
  • the switch unit is respectively electrically connected to the control signal output end and the clock signal output end included in the two clock signal generating units, and is used for controlling the two clocks to be turned on under the control of the turn-on control signal
  • the signal generating unit includes connections between clock signal output terminals.
  • the control unit controls the two clock signal generating units at the first output control end included in the two clock signal generating units when neither of the two clock signal generating units outputs the first voltage signal , providing an opening control signal to the switch unit, and under the control of the open control signal, the switch unit controls the connection between the clock output terminals included in the two clock signal generating units to be turned on to perform charge sharing.
  • the embodiment of the present disclosure no longer controls the on-off of the switching unit (the switching unit is the sharing unit for sharing the charge) by performing level conversion on the sharing signal, but
  • the first output control terminal is used to control the on-off of the switch unit, and when the first output module in the two clock signal generation units is controlled not to output the first voltage signal, the switch unit is controlled to be turned on to realize the two Road sharing, so that charge sharing can be achieved, the number of level conversion circuits used can be reduced, and the chip area can be saved.
  • the display driving module described in the embodiment of the present disclosure may include more than one charge sharing circuit described in the embodiment of the present disclosure, so as to realize n-way sharing (n is an integer greater than 1), which can save level conversion.
  • n is an integer greater than 1
  • the number of circuits is more.
  • the first voltage signal when the data writing transistor electrically connected to the control electrode and the gate line in the pixel circuit is a p-type transistor, the first voltage signal may be a low voltage signal; when the control electrode in the pixel circuit is a p-type transistor, the first voltage signal may be a high voltage signal; but it is not limited thereto.
  • control electrodes of the data writing transistors may be electrically connected to the corresponding row gate lines
  • the first electrodes of the data writing transistors may be electrically connected to the corresponding column data lines
  • the data writing transistors are used for Under the control of the gate driving signal on the gate line of the corresponding row, the data voltage on the data line of the corresponding column is controlled to be written into the corresponding pixel circuit, but not limited thereto.
  • a display device may include a display driving module, and the display driving module may include a gate driving circuit, a clock signal generating circuit and the charge sharing circuit;
  • the gate driving circuit includes a multi-level shifter A register unit, the display device further includes a display panel, the display panel may include multiple rows of gate lines and multiple rows and multiple columns of pixel circuits, and corresponding row shift register units in the gate driving circuit may pass through the corresponding row gate lines , providing gate drive signals for gates of transistors in corresponding row pixel circuits included in the display panel;
  • the clock signal generating circuit is used for providing gate driving signals for the gate driving circuit
  • the clock signal generating circuit includes at least two clock signal generating units
  • Two clock signal generating units in the at least two clock signal generating units respectively provide corresponding clock signals for two adjacent shift register units.
  • the odd-numbered stage shift register unit may be electrically connected to the clock signal output end of the first clock signal generating unit, and the even-numbered stage shift register unit may be electrically connected to the clock signal output end of the first clock signal generating unit.
  • the bit register unit can be electrically connected with the clock signal output end of the second clock signal generating unit;
  • the 4P-3 stage shift register unit can be electrically connected to the clock signal output end of the first clock signal generating unit, and the 4P-2 stage shift register unit
  • the register unit may be electrically connected to the clock signal output end of the second clock signal generating unit, the 4P-1 stage shift register unit may be electrically connected to the clock signal output end of the third clock signal generating unit, and the 4P stage shift register unit may be electrically connected to the clock signal output end of the third clock signal generating unit.
  • the register unit may be electrically connected to the clock signal output end of the fourth clock signal generating unit; P is a positive integer.
  • the clock signal output terminal of the clock signal generating unit when charge sharing is performed, may be in a high impedance state.
  • an embodiment of the clock signal generating unit may include a clock signal output terminal CLK0, a first output control terminal S1, a second output control terminal S2, a first output module 11, a second output module 12 and output control module 13;
  • the first output module 11 is respectively electrically connected to the first output control terminal S1, the first voltage terminal V1 and the clock signal output terminal CLK0, and is used for the first output provided at the first output control terminal S1 Under the control of the control signal, control the connection or disconnection between the clock signal output terminal CLK0 and the first voltage terminal V1; the first voltage terminal V1 is used to provide a first voltage signal;
  • the second output module 12 is respectively electrically connected to the second output control terminal S2, the second voltage terminal V2 and the clock signal output terminal CLK0, and is used for the second output provided at the second output control terminal S2 Under the control of the control signal, control the connection or disconnection between the clock signal output terminal CLK0 and the second voltage terminal V2; the second voltage terminal V2 is used to provide a second voltage signal;
  • the output control module 13 is electrically connected to the first output control terminal S1 and the second output control terminal S2, respectively, for providing the first output control signal for the first output control terminal S1, and for The second output control terminal S2 provides the second output control signal.
  • the fact that the clock signal output terminal CLK0 is in a high-impedance state means that when the first output module 11 is controlled by the first output control signal, it controls the clock signal output terminal CLK0 and all When the first voltage terminal V1 is disconnected, the second output module 12 controls the clock signal output terminal CLK0 to be disconnected from the second voltage terminal V2 under the control of the second output control signal. CLK0 is in a high impedance state.
  • the first output module may include an n-type transistor
  • the second output module may include a p-type transistor, but not limited thereto.
  • the first output module may also include p-type transistors, and the second output module may also include n-type transistors.
  • the gate driving circuit is used to provide a gate driving signal to the pixel circuit
  • the data writing transistor in the pixel circuit whose gate is electrically connected to the gate driving signal output terminal is an n-type transistor, the first voltage signal is a low voltage signal, and the second voltage signal is a high voltage signal; or ,
  • the data writing transistor is a p-type transistor, the first voltage signal is a high voltage signal, and the second voltage signal is a low voltage signal.
  • the charge sharing circuit is applied to a display device, and the display device includes a clock signal generation circuit; the clock signal generation circuit includes a first clock signal generation unit and a second clock signal signal generation unit, where,
  • the first clock signal generating unit includes a first clock signal output terminal CLK1, a first first output control terminal S11, a first second output control terminal S12, a first first output module 111, a first The second output module 112, the first output control module 113;
  • the first first output module 111 is respectively electrically connected to the first first output control terminal S11, the low voltage terminal and the first clock signal output terminal CLK1, and is used for the first first output provided at S11 Under the control of the control signal, the connection between CLK1 and the low voltage terminal is controlled to be connected or disconnected; the low voltage terminal is used to provide the low voltage signal VGL, and the low voltage signal can be a -10V DC voltage signal;
  • the first second output module 112 is electrically connected to the first second output control terminal S12, the high voltage terminal and the first clock signal output terminal CLK1, respectively, for controlling the first second output Under the control of the first second output control signal provided by the terminal S12, the connection or disconnection between CLK1 and the high voltage terminal is controlled; the high voltage terminal is used to provide the high voltage signal VGH, and the high voltage signal can be It is a 30V DC voltage signal;
  • the first output control module 113 is electrically connected to S11 and S12, respectively, for providing the first first output control signal for S11, and for providing the first second output control signal for S12;
  • the second clock signal generation unit includes a second clock signal output terminal CLK2, a second first output control terminal S21, a second second output control terminal S22, a second first output module 121, a second first output module 121, and a second first output control terminal S21. a second output module 122, a second output control module 123;
  • the second first output module 121 is electrically connected to the second first output control terminal S21, the low voltage terminal and the second clock signal output terminal CLK2, respectively, for the second first output provided at S21 Under the control of the control signal, the connection or disconnection between CLK2 and the low voltage terminal is controlled; the low voltage terminal is used to provide a low voltage signal, and the low voltage signal can be a -10V DC voltage signal;
  • the second second output module 122 is electrically connected to the second second output control terminal S22, the high voltage terminal and the second clock signal output terminal CLK2, respectively, for the second second output provided at S22 Under the control of the control signal, the connection or disconnection between CLK2 and the high-voltage terminal is controlled; the high-voltage terminal is used to provide a high-voltage signal; the high-voltage signal can be a 30V DC voltage signal;
  • the second output control module 123 is electrically connected to S21 and S22, respectively, for providing the second first output control signal for S21, and for providing the second second output control signal for S22;
  • the charge sharing circuit includes a control unit 31 and a switch unit 32, wherein,
  • the control unit 31 is electrically connected to S11 and S21 respectively, and is used to control not to output the low voltage signal through CLK1 under the control of the first first output control signal provided by the first first output module 111 at S11 , and the second first output control module 121, under the control of the second first output control signal provided by S21, controls not to output the low voltage signal through CLK2, and sends the control signal output terminal to the switch unit through the control signal output terminal.
  • 32 provides an opening control signal
  • the switch unit 32 is electrically connected to the control signal output terminals, CLK1 and CLK2, respectively, and is used for controlling the connection between CLK1 and CLK2 to be turned on under the control of the open control signal.
  • the switch unit 32 when both CLK1 and CLK2 output high-voltage signals, the switch unit 32 also controls the communication between CLK1 and CLK2, but since the charge sharing will not affect the pixel circuit at this time, it will not Affects the functionality of the entire system.
  • the switch unit includes a first switch transistor and a second switch transistor;
  • Both the control electrode of the first switching transistor and the control electrode of the second switching transistor are electrically connected to the control signal output terminal;
  • the first pole of the first switching transistor is electrically connected to the clock signal output end of the first clock signal generating unit of the two clock signal generating units, and the second pole of the first switching transistor is electrically connected to the first clock signal generating unit.
  • the first poles of the two switching transistors are electrically connected, and the second poles of the second switching transistors are electrically connected to the clock signal output terminal of the second clock signal generating unit in the two clock signal generating units;
  • Both the first switching transistor and the second switching transistor are p-type transistors; or, both the first switching transistor and the second switching transistor are n-type transistors.
  • the first output module may be configured to control not to output the first voltage signal through the clock signal output terminal when the first output control signal is a low voltage signal;
  • the control unit includes a NOR gate and a control module
  • the first input terminal of the NOR gate is electrically connected to the first output of the first clock signal generating unit, and the second input terminal of the NOR gate is electrically connected to the first output terminal of the second clock signal generating unit.
  • an output control terminal is electrically connected;
  • the control module is electrically connected to the output terminal of the NOR gate, and is used to control both the first switching transistor and the second switching transistor to be turned on when the NOR gate outputs a high voltage signal through its output terminal.
  • both the first switch transistor and the second switch transistor are p-type transistors
  • the control module includes a first level conversion circuit and a first p-type drive circuit
  • the first level conversion circuit is electrically connected to the output end of the NOR gate, and the first level conversion circuit is used to perform level conversion on the signal output by the NOR gate through its output end, and convert the providing the first control signal obtained by level conversion to the first p-type driving circuit;
  • the output end of the first p-type drive circuit is electrically connected to the control signal output end, and the first p-type drive circuit is used for inverting the first control signal to obtain a second control signal, and The second control signal is output to the control electrode of the first switching transistor through the control signal output terminal, and the driving capability of the output terminal of the first p-type driving circuit can be improved.
  • both the first switching transistor and the second switching transistor may be p-type transistors. At this time, when the gate-source voltage of the first switching transistor is less than the threshold voltage of the first switching transistor, and the When the gate-source voltage of the two switching transistors is less than the threshold voltage of the second switching transistor, the first switching transistor and the second switching transistor are turned on.
  • both the first switch transistor and the second switch transistor are n-type transistors
  • the control module includes a first level conversion circuit and a first n-type drive circuit
  • the first level conversion circuit is electrically connected to the output end of the NOR gate, and the first level conversion circuit is used to perform level conversion on the signal output by the NOR gate through its output end, and convert the providing the first control signal obtained by level conversion to the first n-type driving circuit;
  • the output terminal of the first n-type driving circuit is electrically connected to the control signal output terminal, and the first n-type driving circuit is used for providing the first control signal to the first n-type driving circuit through the control signal output terminal.
  • a control electrode of a switching transistor can improve the driving capability of the output end of the first n-type driving circuit.
  • both the first switching transistor and the second switching transistor may be n-type transistors. At this time, when the gate-source voltage of the first switching transistor is greater than the threshold voltage of the first switching transistor, and the When the gate-source voltage of the two switching transistors is greater than the threshold voltage of the second switching transistor, the first switching transistor and the second switching transistor are turned on.
  • the first output module may be configured to control not to output the first voltage signal through the clock signal output terminal when the first output control signal is a high voltage signal;
  • the control unit includes a NAND gate and a control module
  • the first input terminal of the NAND gate is electrically connected to the first output of the first clock signal generating unit, and the second input terminal of the NAND gate is electrically connected to the first output terminal of the second clock signal generating unit.
  • an output control terminal is electrically connected;
  • the control module is electrically connected to the output terminal of the NAND gate, and is used for controlling both the first switching transistor and the second switching transistor to be turned on when the NAND gate outputs a low voltage signal through its output terminal.
  • the control unit may include a NAND gate and a control module.
  • the control module controls both the first switching transistor and the second switching transistor to be turned on.
  • the switch unit 32 includes a first switch transistor M1 and a second switch transistor M2;
  • the gate of the first switching transistor M1 and the gate of the second switching transistor M2 are both electrically connected to the control signal output end;
  • the drain of the first switch transistor M1 is electrically connected to G1, the source of the first switch transistor M1 is electrically connected to the drain of M1, and the source of the second switch transistor M1 is electrically connected to G2;
  • the first output transistor included in the first first output module 111 and the first output transistor included in the second first output module 121 are both n-type transistors;
  • the control unit includes a first NOR gate NOR1 and a control module;
  • the first input terminal of NOR1 is connected to S11, and the second input terminal of NOR2 is electrically connected to S21;
  • the control module includes a first level conversion circuit 41 and a first p-type drive circuit 50;
  • the first level conversion circuit 41 is electrically connected to the output terminal of NOR1, and the first level conversion circuit 41 is used to perform level conversion on the signal output by NOR1 through its output terminal, and convert the level converted into the first signal.
  • a control signal is provided to the first p-type driving circuit 50;
  • the first p-type driving circuit 50 is configured to invert the first control signal to obtain a second control signal, and output the second control signal to the first control signal through the control signal output terminal The gate of the switching transistor M1.
  • both M1 and M2 are NMOS transistors (N-type metal-oxide-semiconductor transistors), but not limited thereto.
  • the first first output module 111 includes a first output transistor N1, the first second output module 112 includes a second output transistor P1, and the second first output module 121 includes a third output transistor N2 , the second second output transistor 122 includes a fourth output transistor P2;
  • the first output control module 113 includes a first inverter F1, a first OR gate OR1, a second OR gate OR2, a second inverter F2, a third inverter F3, and a second level conversion circuit 51 , the third level conversion circuit 52, the second p-type driving circuit 61 and the first n-type driving circuit 62;
  • the input end of F1 is connected to the input clock signal CLK_IN, the output end of F1 is electrically connected to the first input end of OR1, and the second input end of OR1 is connected to the shared signal CSEN;
  • OR2 The first input terminal of OR2 is connected to CSEN, and the second input terminal of OR2 is connected to CLK_IN;
  • the input terminal of F2 is electrically connected to the output terminal of OR1, and the input terminal of F3 is electrically connected to the output terminal of OR2;
  • the output terminal of F2 is electrically connected to the input terminal of the second level conversion circuit 51, and the output terminal of F3 is electrically connected to the input terminal of the third level conversion circuit 52;
  • the second level conversion circuit 51 is used for level conversion of the voltage signal connected to its input terminal to obtain a third control signal, to convert the potential of the third control signal to a high voltage domain, and to convert the the third control signal is provided to the input end of the second p-type driving circuit 61;
  • the third level conversion circuit 52 is used to perform level conversion of the voltage signal connected to its input terminal to obtain a fourth control signal, convert the potential of the fourth control signal to the negative voltage domain, and convert the the fourth control signal is provided to the input end of the first n-type driving circuit 62;
  • the output terminal of the second p-type driving circuit 61 is electrically connected to the gate of P1 for providing the third control signal to the gate of P1 and enhancing the output terminal of the second p-type driving circuit 61 .
  • the output terminal of the first n-type driving circuit 62 is electrically connected to the gate of N1 for providing the fourth control signal to the gate of N1 and enhancing the output terminal of the first n-type driving circuit 62 .
  • the second output control module 123 includes a fourth inverter F4, a third OR gate OR3, a fourth OR gate OR4, a fifth inverter F5, a sixth inverter F6, and a fourth level conversion circuit 53 , the fifth level conversion circuit 54, the third p-type driving circuit 63 and the second n-type driving circuit 64;
  • the input end of F4 is connected to CLK_IN, the output end of F4 is electrically connected to the first input end of OR3, and the second input end of OR3 is connected to the shared signal CSEN;
  • the first input terminal of OR4 is connected to CSEN, and the second input terminal of OR4 is connected to CLK_IN;
  • the input end of F5 is electrically connected with the output end of OR3, and the input end of F6 is electrically connected with the output end of OR4;
  • the output terminal of F5 is electrically connected to the input terminal of the fourth level conversion circuit 53, and the output terminal of F6 is electrically connected to the input terminal of the fifth level conversion circuit 54;
  • the fourth level conversion circuit 53 is used to perform level conversion on the voltage signal connected to its input terminal to obtain a fifth control signal, convert the potential of the fifth control signal into a high voltage domain, and convert all the voltage signals into the high voltage domain.
  • the fifth control signal is provided to the input end of the third p-type driving circuit 63;
  • the fifth level conversion circuit 54 is used to perform level conversion on the voltage signal connected to its input terminal to obtain a sixth control signal, convert the potential of the sixth control signal into a negative voltage domain, and convert all the voltage signals into the negative voltage domain.
  • the sixth control signal is provided to the input end of the second n-type driving circuit 64;
  • the output terminal of the third p-type driving circuit 63 is electrically connected to the gate of P2 for providing the fifth control signal to the gate of P2 and enhancing the output terminal of the third p-type driving circuit 63 .
  • the output terminal of the second n-type driving circuit 64 is electrically connected to the gate of N2 for providing the sixth control signal to the gate of N2 and enhancing the output terminal of the second n-type driving circuit 64 . Drive capability.
  • NOR2 is the second NOR gate
  • the first input terminal of NOR2 is connected to the first clock signal CLK_X
  • the second input terminal of NOR2 is connected to the second clock signal CLK_Y
  • NOR2 The output is used to output CSEN.
  • the potential of the shared signal CSEN may be between 0V and 5V
  • the high voltage domain may be 25V to 30V
  • the negative voltage domain may be -10V to -5V.
  • the potential of the voltage signal connected to the input terminal of the second level conversion circuit 51, the potential of the voltage signal connected to the input terminal of the third level conversion circuit 52, and the input of the fourth level conversion circuit 53 The potential of the voltage signal connected to the terminal and the potential of the voltage signal connected to the input terminal of the fifth level conversion circuit 54 can be switched between 0V and 5V, then the potential of the third control signal and the fifth control signal
  • the potential of the 1 can be switched between 25V and 30V
  • the potential of the fourth control signal and the potential of the sixth control signal can be switched between -10V and -5V.
  • the charge sharing method described in the embodiment of the present disclosure is applied to the above-mentioned charge sharing circuit, and the charge sharing method includes:
  • the control unit When the first output module is controlled not to output the first voltage signal under the control of the first output control signal, the control unit provides an opening control signal to the switch unit through the control signal output terminal;
  • the switch unit controls the connection between the clock signal output terminals included in the two clock signal generating units to be turned on under the control of the open control signal.
  • the control unit controls the generation of the two clock signals at the first output control end included in the two clock signal generation units in the at least two clock signal generation units
  • an opening control signal is provided to the switching unit, and the switching unit, under the control of the opening control signal, controls the conduction between the clock signal output terminals included in the two clock signal generating units. connected for charge sharing.
  • the display driving module described in the embodiments of the present disclosure includes a clock signal generating circuit and the above-mentioned charge sharing circuit.
  • the clock signal generating circuit includes a plurality of clock signal generating units
  • the clock signal generating unit includes a clock signal output terminal, a first output control terminal, a second output control terminal, a first output module and a second output module;
  • the first output module is configured to control whether to output the first voltage signal through the clock signal output end under the control of the first output control signal provided by the first output control end;
  • the second output module is configured to control whether to output the second voltage signal through the clock signal output terminal under the control of the second output control signal provided by the second output control terminal.
  • the display device includes the above-mentioned display driving module.
  • the display device may be a liquid crystal display device, but not limited thereto.
  • the display device may also be an OLED (Organic Light Emitting Diode) display device.
  • the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.

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Abstract

提供一种电荷共享电路、方法、显示驱动模组和显示装置。电荷共享电路包括控制单元（31）和开关单元（32），其中，控制单元（31）分别与两个时钟信号生成单元包括的第一输出控制端电连接，用于当第一输出模块（11）在第一输出控制信号的控制下，控制不输出第一电压信号时，通过控制信号输出端向开关单元（32）提供打开控制信号；开关单元（32）在打开控制信号的控制下，控制导通所述两个时钟信号生成单元包括的时钟信号输出端之间的连接。

Description

电荷共享电路、方法、显示驱动模组和显示装置
相关申请的交叉引用
本申请主张在2020年9月28日在中国提交的中国专利申请号No.202011041981.6的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种电荷共享电路、方法、显示驱动模组和显示装置。
背景技术
在显示装置中，考虑到省电的需求，需要在不同行像素电路之间实现栅极电荷共享，将待关断的晶体管的栅极上的电荷转移至待开启的晶体管的栅线上，从而减少栅极开启耗电。
在显示装置中，像素电路中的数据写入晶体管的栅极接入的栅极驱动信号由相应的时钟信号生成电路提供的时钟信号控制，因此可以通过在不同级时钟信号生成单元的时钟信号输出端之间设置共享开关，以实现显示面板上不同行像素电路中的数据写入晶体管的栅极电荷共享。
在相关技术中的电荷共享电路中，根据第一时钟信号和第二时钟信号产生共享信号，然后共享信号通过一个电平转换电路转换至低电压VGL负压电源域，然后再通过一个电平转换电路转换至共享开关电源域，以控制共享开关的通断；相关技术中的电荷共享电路采用的电平转换电路的个数多，占用芯片的面积大。
发明内容
本公开的主要目的在于提供一种电荷共享电路、方法、显示驱动模组和显示装置，解决相关技术中的电荷共享电路采用的电平转换电路的个数多，占用芯片的面积大的技术问题。
为了达到上述目的，本公开提供了一种电荷共享电路，应用于显示装置， 所述显示装置包括栅极驱动电路和时钟信号生成电路，所述栅极驱动电路包括多级移位寄存器单元；所述时钟信号生成电路包括至少两个时钟信号生成单元；所述至少两个时钟信号生成电路中的两个时钟信号生成单元分别为相邻的两移位寄存器单元提供相应的时钟信号；所述时钟信号生成单元包括时钟信号输出端、第一输出控制端和第一输出模块，所述第一输出模块用于在所述第一输出控制端提供的第一输出控制信号的控制下，控制是否通过所述时钟信号输出端输出第一电压信号；所述电荷共享电路包括控制单元和开关单元，其中，
所述控制单元分别与所述两个时钟信号生成单元包括的所述第一输出控制端电连接，用于当所述第一输出模块在所述第一输出控制信号的控制下，控制不输出所述第一电压信号时，通过控制信号输出端向所述开关单元提供打开控制信号；
所述开关单元分别与所述控制信号输出端和所述两个时钟信号生成单元包括的时钟信号输出端电连接，用于在所述打开控制信号的控制下，控制导通所述两个时钟信号生成单元包括的时钟信号输出端之间的连接。
可选地，所述开关单元包括第一开关晶体管和第二开关晶体管；
所述第一开关晶体管的控制极和所述第二开关晶体管的控制极都与所述控制信号输出端电连接；
所述第一开关晶体管的第一极与所述两个时钟信号生成单元中的第一个时钟信号生成单元的时钟信号输出端电连接，所述第一开关晶体管的第二极与所述第二开关晶体管的第一极电连接，所述第二开关晶体管的第二极与所述两个时钟信号生成单元中的第二个时钟信号生成单元的时钟信号输出端电连接；
所述第一开关晶体管和所述第二开关晶体管都为p型晶体管；或者，所述第一开关晶体管和所述第二开关晶体管都为n型晶体管。
可选地，所述第一输出模块用于当所述第一输出控制信号为低电压信号时，控制不通过所述时钟信号输出端输出第一电压信号；
所述控制单元包括或非门和控制模块；
所述或非门的第一输入端与所述第一个时钟信号生成单元的第一输出控 制电连接，所述或非门的第二输入端与所述第二个时钟信号生成单元的第一输出控制端电连接；
所述控制模块与所述或非门的输出端电连接，用于当所述或非门通过其输出端输出高电压信号时，控制所述第一开关晶体管和第二开关晶体管都打开。
可选地，所述第一开关晶体管和所述第二开关晶体管都为p型晶体管；
所述控制模块包括第一电平转换电路和第一p型驱动电路；
所述第一电平转换电路与所述或非门的输出端电连接，所述第一电平转换电路用于对所述或非门通过其输出端输出的信号进行电平转换，并将电平转换得到的第一控制信号提供至所述第一p型驱动电路的输入端；
所述第一p型驱动电路的输出端与所述控制信号输出端电连接，所述第一p型驱动电路用于对所述第一控制信号进行反相，以得到第二控制信号，并通过所述控制信号输出端将所述第二控制信号输出至所述第一开关晶体管的控制极，并能够提升所述第一p型驱动电路的输出端的驱动能力。
可选地，所述第一开关晶体管和所述第二开关晶体管都为n型晶体管；
所述控制模块包括第一电平转换电路和第一n型驱动电路；
所述第一电平转换电路与所述或非门的输出端电连接，所述第一电平转换电路用于对所述或非门通过其输出端输出的信号进行电平转换，并将电平转换得到的第一控制信号提供至所述第一n型驱动电路的输入端；
所述第一n型驱动电路的输出端与所述控制信号输出端电连接，所述第一n型驱动电路用于通过所述控制信号输出端将所述第一控制信号提供至所述第一开关晶体管的控制极，并能够提升所述第一n型驱动电路的输出端的驱动能力。
可选地，所述第一输出模块用于当所述第一输出控制信号为高电压信号时，控制不通过所述栅极驱动信号输出第一电压信号；
所述控制单元包括与非门和控制模块；
所述与非门的第一输入端与所述第一个时钟信号生成单元的第一输出控制电连接，所述与非门的第二输入端与所述第二个时钟信号生成单元的第一输出控制端电连接；
所述控制模块与所述与非门的输出端电连接，用于当所述与非门通过其输出端输出低电压信号时，控制所述第一开关晶体管和第二开关晶体管都打开。
本公开还提供了一种电荷共享方法，应用于上述的电荷共享电路，所述电荷共享方法包括：
当第一输出模块在第一输出控制信号的控制下，控制不输出第一电压信号时，控制单元通过控制信号输出端向开关单元提供打开控制信号；
所述开关单元在所述打开控制信号的控制下，控制导通两个时钟信号生成单元包括的时钟信号输出端之间的连接。
本公开还提供了一种显示驱动模组，包括时钟信号生成电路和上述的电荷共享电路。
可选地，所述时钟信号生成电路包括多个时钟信号生成单元；
所述时钟信号生成单元包括时钟信号输出端、第一输出控制端、第二输出控制端、第一输出模块和第二输出模块；
所述第一输出模块用于在所述第一输出控制端提供的第一输出控制信号的控制下，控制是否通过所述时钟信号输出端输出第一电压信号；
所述第二输出模块用于在所述第二输出控制端提供的第二输出控制信号的控制下，控制是否通过所述时钟信号输出端输出第二电压信号。
本公开还提供了一种显示装置，包括上述的显示驱动模组。
本公开实施例所述的电荷共享电路、方法、显示驱动模组和显示装置通过控制单元在所述至少两个时钟信号生成单元中的两个时钟信号生成单元包括的第一输出控制端控制所述两个时钟信号生成单元都不输出第一电压信号时，向开关单元提供打开控制信号，开关单元在所述打开控制信号的控制下，控制导通所述两个时钟信号生成单元包括的时钟信号输出端之间的连接，以进行电荷共享，并能够减少采用的电平转换电路的个数，节省芯片面积。
附图说明
图1是时钟信号生成单元的一实施例的结构图；
图2是本公开实施例所述的电荷共享电路的结构图；
图3是本公开另一实施例所述的电荷共享电路的电路图；
图4是本公开所述的电荷共享电路的一具体实施例的电路图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为三极管、薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除控制极之外的两极，将其中一极称为第一极，另一极称为第二极。
在实际操作时，当所述晶体管为三极管时，所述控制极可以为基极，所述第一极可以为集电极，所述第二极可以发射极；或者，所述控制极可以为基极，所述第一极可以为发射极，所述第二极可以集电极。
在实际操作时，当所述晶体管为薄膜晶体管或场效应管时，所述控制极可以为栅极，所述第一极可以为漏极，所述第二极可以为源极；或者，所述控制极可以为栅极，所述第一极可以为源极，所述第二极可以为漏极。
本公开实施例所述的电荷共享电路，应用于显示装置，所述显示装置包括栅极驱动电路和时钟信号生成电路，所述栅极驱动电路包括多个移位寄存器单元，所述时钟信号生成电路包括至少两个时钟信号生成单元；所述至少两个时钟信号生成电路中的两个时钟信号生成单元分别为相邻的两移位寄存器单元提供相应的时钟信号；所述时钟信号生成单元包括时钟信号输出端、第一输出控制端和第一输出模块，所述第一输出模块用于在所述第一输出控制端提供的第一输出控制信号的控制下，控制是否通过所述时钟信号输出端输出第一电压信号；本公开实施例所述的电荷共享电路包括控制单元和开关单元，其中，
所述控制单元分别与所述两个时钟信号生成单元包括的所述第一输出控制端电连接，用于当所述第一输出模块在所述第一输出控制信号的控制下，控制不输出所述第一电压信号时，通过控制信号输出端向所述开关单元提供 打开控制信号；
所述开关单元分别与所述控制信号输出端和所述两个时钟信号生成单元包括的时钟信号输出端电连接，用于在所述打开控制信号的控制下，控制导通所述两个时钟信号生成单元包括的时钟信号输出端之间的连接。
本公开实施例所述的电荷共享电路在工作时，通过控制单元在所述两个时钟信号生成单元包括的第一输出控制端控制所述两个时钟信号生成单元都不输出第一电压信号时，向开关单元提供打开控制信号，开关单元在所述打开控制信号的控制下，控制导通所述两个时钟信号生成单元包括的时钟输出端之间的连接，以进行电荷共享。
与相关技术中的电荷共享电路相比，本公开实施例不再通过对共享信号进行电平转换来控制开关单元(所述开关单元为用于共享电荷的共享单元)的通断，而是通过第一输出控制端来控制开关单元的通断，当所述两个时钟信号生成单元中的第一输出模块都控制不输出所述第一电压信号时，控制所述开关单元导通，实现两路共享，从而可以实现电荷共享，减少采用的电平转换电路的个数，节省芯片面积。
在具体实施时，本公开实施例所述的显示驱动模组可以包括一个以上本公开实施例所述的电荷共享电路，实现n路共享(n为大于1的整数)，可以节省的电平转换电路的个数更多。
在本公开实施例中，当像素电路中的控制极与栅线电连接的数据写入晶体管为p型晶体管时，所述第一电压信号可以为低电压信号；当所述像素电路中的控制极与栅线电连接的数据写入晶体管为n型晶体管时，所述第一电压信号可以为高电压信号；但不以此为限。
在实际操作时，所述数据写入晶体管的控制极可以与相应行栅线电连接，所述数据写入晶体管的第一极可以与相应列数据线电连接，所述数据写入晶体管用于在相应行栅线上的栅极驱动信号的控制下，控制将相应列数据线上的数据电压写入相应的像素电路，但不以此为限。
在相关技术中，显示装置可以包括显示驱动模组，所述显示驱动模组可以包括栅极驱动电路、时钟信号生成电路和所述的电荷共享电路；所述栅极驱动电路包括多级移位寄存器单元，所述显示装置还包括显示面板，所述显 示面板可以包括多行栅线和多行多列像素电路，所述栅极驱动电路中的相应行移位寄存器单元可以通过相应行栅线，为所述显示面板包括的相应行像素电路中的晶体管的栅极提供栅极驱动信号；
所述时钟信号生成电路用于为所述栅极驱动电路提供栅极驱动信号；
所述时钟信号生成电路包括至少两个时钟信号生成单元；
所述至少两个时钟信号生成单元中的两个时钟信号生成单元分别为相邻的两移位寄存器单元提供相应的时钟信号。
在本公开实施例中，当所述时钟信号生成电路包括两个时钟信号生成单元时，则奇数级移位寄存器单元可以与第一个时钟信号生成单元的时钟信号输出端电连接，偶数级移位寄存器单元可以与第二个时钟信号生成单元的时钟信号输出端电连接；
当所述时钟信号生成电路包括四个时钟信号生成单元时，则第4P-3级移位寄存器单元可以与第一个时钟信号生成单元的时钟信号输出端电连接，第4P-2级移位寄存器单元可以与第二个时钟信号生成单元的时钟信号输出端电连接，第4P-1级移位寄存器单元可以与第三个时钟信号生成单元的时钟信号输出端电连接，第4P级移位寄存器单元可以与第四个时钟信号生成单元的时钟信号输出端电连接；P为正整数。
在显示装置中，考虑到省电的需求，需要在不同行栅线之间实现栅线电荷共享，将待关断的栅线电荷转移至待开启的栅线上，以减少显示面板中的晶体管开启的耗电量。并由于所述栅线上的栅极驱动信号是由时钟信号提供的，因此可以通过两个时钟信号生成单元的时钟信号输出端的电荷共享，来实现显示面板中不同行像素电路中的晶体管的栅极之间的电荷共享。
在本公开实施例中，在进行电荷共享时，所述时钟信号生成单元的时钟信号输出端可以处于高阻态。
如图1所示，所述时钟信号生成单元的一实施例可以包括时钟信号输出端CLK0、第一输出控制端S1、第二输出控制端S2、第一输出模块11、第二输出模块12和输出控制模块13；
所述第一输出模块11分别与所述第一输出控制端S1、第一电压端V1和所述时钟信号输出端CLK0电连接，用于在所述第一输出控制端S1提供的第 一输出控制信号的控制下，控制所述时钟信号输出端CLK0与所述第一电压端V1之间连通或断开；所述第一电压端V1用于提供第一电压信号；
所述第二输出模块12分别与所述第二输出控制端S2、第二电压端V2和所述时钟信号输出端CLK0电连接，用于在所述第二输出控制端S2提供的第二输出控制信号的控制下，控制所述时钟信号输出端CLK0与所述第二电压端V2之间连通或断开；所述第二电压端V2用于提供第二电压信号；
所述输出控制模块13分别与所述第一输出控制端S1和所述第二输出控制端S2电连接，用于为所述第一输出控制端S1提供所述第一输出控制信号，并为所述第二输出控制端S2提供所述第二输出控制信号。
在图1中，所述时钟信号输出端CLK0处于高阻态指的是：当所述第一输出模块11在所述第一输出控制信号的控制下，控制所述时钟信号输出端CLK0与所述第一电压端V1之间断开，所述第二输出模块12在所述第二输出控制信号的控制下，控制所述时钟信号输出端CLK0与所述第二电压端V2之间断开时，CLK0处于高阻态。
在本公开实施例中，所述第一输出模块可以包括n型晶体管，所述第二输出模块可以包括p型晶体管，但不以此为限。
在实际操作时，所述第一输出模块也可以包括p型晶体管，所述第二输出模块也可以包括n型晶体管。
在本公开实施例中，所述栅极驱动电路用于提供栅极驱动信号至像素电路；
像素电路中的栅极与所述栅极驱动信号输出端电连接的数据写入晶体管为n型晶体管，所述第一电压信号为低电压信号，所述第二电压信号为高电压信号；或者，
所述数据写入晶体管为p型晶体管，所述第一电压信号为高电压信号，所述第二电压信号为低电压信号。
如图2所示，本公开实施例所述的电荷共享电路应用于显示装置，所述显示装置包括时钟信号生成电路；所述时钟信号生成电路包括第一个时钟信号生成单元和第二个时钟信号生成单元，其中，
所述第一个时钟信号生成单元包括第一时钟信号输出端CLK1、第一个 第一输出控制端S11、第一个第二输出控制端S12、第一个第一输出模块111、第一个第二输出模块112、第一个输出控制模块113；
所述第一个第一输出模块111分别与第一个第一输出控制端S11、低电压端和所述第一时钟信号输出端CLK1电连接，用于在S11提供的第一个第一输出控制信号的控制下，控制CLK1与低电压端之间连通或断开；所述低电压端用于提供低电压信号VGL，所述低电压信号可以为-10V直流电压信号；
所述第一个第二输出模块112分别与第一个第二输出控制端S12、高电压端和所述第一时钟信号输出端CLK1电连接，用于在所述第一个第二输出控制端S12提供的第一个第二输出控制信号的控制下，控制CLK1与所述高电压端之间连通或断开；所述高电压端用于提供高电压信号VGH，所述高电压信号可以为30V直流电压信号；
所述第一个输出控制模块113分别与S11和S12电连接，用于为S11提供所述第一个第一输出控制信号，并用于为S12提供所述第一个第二输出控制信号；
所述第二个时钟信号生成单元包括第二时钟信号输出端CLK2、第二个第一输出控制端S21、第二个第二输出控制端S22、第二个第一输出模块121、第二个第二输出模块122、第二个输出控制模块123；
所述第二个第一输出模块121分别与第二个第一输出控制端S21、低电压端和所述第二时钟信号输出端CLK2电连接，用于在S21提供的第二个第一输出控制信号的控制下，控制CLK2与低电压端之间连通或断开；所述低电压端用于提供低电压信号，所述低电压信号可以为-10V直流电压信号；
所述第二个第二输出模块122分别与第二个第二输出控制端S22、高电压端和所述第二时钟信号输出端CLK2电连接，用于在S22提供的第二个第二输出控制信号的控制下，控制CLK2与所述高电压端之间连通或断开；所述高电压端用于提供高电压信号；所述高电压信号可以为30V直流电压信号；
所述第二个输出控制模块123分别与S21和S22电连接，用于为S21提供所述第二个第一输出控制信号，并用于为S22提供所述第二个第二输出控制信号；
如图2所示，本公开实施例所述的电荷共享电路包括控制单元31和开关 单元32，其中，
所述控制单元31分别与S11和S21电连接，用于在第一个第一输出模块111在S11提供的第一个第一输出控制信号的控制下，控制不通过CLK1输出所述低电压信号时，并第二个第一输出控制模块121在S21提供的第二个第一输出控制信号的控制下，控制不通过CLK2输出所述低电压信号时，通过控制信号输出端向所述开关单元32提供打开控制信号；
所述开关单元32分别与所述控制信号输出端、CLK1和CLK2电连接，用于在所述打开控制信号的控制下，控制导通CLK1和CLK2之间的连接。
在本公开实施例中，当CLK1和CLK2都输出高电压信号时，所述开关单元32也会控制CLK1和CLK2之间连通，但是由于此时电荷共享对像素电路不会产生影响，因此不会影响整个系统的功能。
可选地，所述开关单元包括第一开关晶体管和第二开关晶体管；
所述第一开关晶体管的控制极和所述第二开关晶体管的控制极都与所述控制信号输出端电连接；
所述第一开关晶体管的第一极与所述两个时钟信号生成单元中的第一个时钟信号生成单元的时钟信号输出端电连接，所述第一开关晶体管的第二极与所述第二开关晶体管的第一极电连接，所述第二开关晶体管的第二极与所述两个时钟信号生成单元中的第二个时钟信号生成单元的时钟信号输出端电连接；
所述第一开关晶体管和所述第二开关晶体管都为p型晶体管；或者，所述第一开关晶体管和所述第二开关晶体管都为n型晶体管。
在具体实施时，所述第一输出模块可以用于当所述第一输出控制信号为低电压信号时，控制不通过所述时钟信号输出端输出第一电压信号；
所述控制单元包括或非门和控制模块；
所述或非门的第一输入端与所述第一个时钟信号生成单元的第一输出控制电连接，所述或非门的第二输入端与所述第二个时钟信号生成单元的第一输出控制端电连接；
所述控制模块与所述或非门的输出端电连接，用于当所述或非门通过其输出端输出高电压信号时，控制所述第一开关晶体管和第二开关晶体管都打 开。
根据一种具体实施方式，所述第一开关晶体管和所述第二开关晶体管都为p型晶体管；
所述控制模块包括第一电平转换电路和第一p型驱动电路；
所述第一电平转换电路与所述或非门的输出端电连接，所述第一电平转换电路用于对所述或非门通过其输出端输出的信号进行电平转换，并将电平转换得到的第一控制信号提供至所述第一p型驱动电路；
所述第一p型驱动电路的输出端与所述控制信号输出端电连接，所述第一p型驱动电路用于对所述第一控制信号进行反相，以得到第二控制信号，并通过所述控制信号输出端将所述第二控制信号输出至所述第一开关晶体管的控制极，并能够提升所述第一p型驱动电路的输出端的驱动能力。
在实际操作时，所述第一开关晶体管和第二开关晶体管可以都为p型晶体管，此时，当所述第一开关晶体管的栅源电压小于第一开关晶体管的阈值电压，并所述第二开关晶体管的栅源电压小于第二开关晶体管的阈值电压时，第一开关晶体管和第二开关晶体管打开。
根据另一种具体实施方式，所述第一开关晶体管和所述第二开关晶体管都为n型晶体管；
所述控制模块包括第一电平转换电路和第一n型驱动电路；
所述第一电平转换电路与所述或非门的输出端电连接，所述第一电平转换电路用于对所述或非门通过其输出端输出的信号进行电平转换，并将电平转换得到的第一控制信号提供至所述第一n型驱动电路；
所述第一n型驱动电路的输出端与所述控制信号输出端电连接，所述第一n型驱动电路用于通过所述控制信号输出端将所述第一控制信号提供至所述第一开关晶体管的控制极，并能够提升所述第一n型驱动电路的输出端的驱动能力。
在实际操作时，所述第一开关晶体管和第二开关晶体管可以都为n型晶体管，此时，当所述第一开关晶体管的栅源电压大于第一开关晶体管的阈值电压，并所述第二开关晶体管的栅源电压大于第二开关晶体管的阈值电压时，第一开关晶体管和第二开关晶体管打开。
在具体实施时，所述第一输出模块可以用于当所述第一输出控制信号为高电压信号时，控制不通过所述时钟信号输出端输出第一电压信号；
所述控制单元包括与非门和控制模块；
所述与非门的第一输入端与所述第一个时钟信号生成单元的第一输出控制电连接，所述与非门的第二输入端与所述第二个时钟信号生成单元的第一输出控制端电连接；
所述控制模块与所述与非门的输出端电连接，用于当所述与非门通过其输出端输出低电压信号时，控制所述第一开关晶体管和第二开关晶体管都打开。
在本公开实施例中，当所述第一输出模块包括的第一输出晶体管为p型晶体管时，当所述第一输出控制信号为高电压信号时，控制不通过所述时钟信号端输出第一电压信号，此时所述控制单元可以包括与非门和控制模块，当与非门输出低电压信号时，所述控制模块控制所述第一开关晶体管和第二开关晶体管都打开。
如图3所示，在图2所示的电荷共享电路的实施例的基础上，所述开关单元32包括第一开关晶体管M1和第二开关晶体管M2；
所述第一开关晶体管M1的栅极和所述第二开关晶体管M2的栅极都与所述控制信号输出端电连接；
所述第一开关晶体管M1的漏极与G1电连接，所述第一开关晶体管M1的源极与M1的漏极电连接，所述第二开关晶体管M1的源极与G2连接；
所述第一个第一输出模块111包括的第一输出晶体管和所述第二个第一输出模块121包括的第一输出晶体管都为n型晶体管；
所述控制单元包括第一或非门NOR1和控制模块；
NOR1的第一输入端与S11连接，NOR2的第二输入端与S21电连接；
所述控制模块包括第一电平转换电路41和第一p型驱动电路50；
所述第一电平转换电路41与NOR1的输出端电连接，所述第一电平转换电路41用于对NOR1通过其输出端输出的信号进行电平转换，并将电平转换得到的第一控制信号提供至所述第一p型驱动电路50；
所述第一p型驱动电路50用于对所述第一控制信号进行反相，以得到第 二控制信号，并通过所述控制信号输出端将所述第二控制信号输出至所述第一开关晶体管M1的栅极。
在图3所示的实施例中，M1和M2都为NMOS管(N型金属-氧化物-半导体晶体管)，但不以此为限。
本公开如图3所示的电荷共享电路的实施例在工作时，当S11和S12都输出低电压信号时，NOR1输出第一高电压，所述第一电平转换电路41对NOR1输出的第一高电压进行电平转换，生成第二高电压，第二高电压大于第一高电压，所述第一p型驱动电路50对所述第二高电压进行反相操作，以控制M1和M2都打开，以实现电荷共享。
如图4所示，在图3所示的电荷共享电路的实施例的基础上，
所述第一个第一输出模块111包括第一输出晶体管N1，所述第一个第二输出模块112包括第二输出晶体管P1，所述第二个第一输出模块121包括第三输出晶体管N2，所述第二个第二输出晶体管122包括第四输出晶体管P2；
所述第一个输出控制模块113包括第一反相器F1、第一或门OR1、第二或门OR2、第二反相器F2、第三反相器F3、第二电平转换电路51、第三电平转换电路52、第二p型驱动电路61和第一n型驱动电路62；
F1的输入端接入输入时钟信号CLK_IN，F1的输出端与OR1的第一输入端电连接，OR1的第二输入端接入共享信号CSEN；
OR2的第一输入端接入CSEN，OR2的第二输入端接入CLK_IN；
F2的输入端与OR1的输出端电连接，F3的输入端与OR2的输出端电连接；
F2的输出端与所述第二电平转换电路51的输入端电连接，F3的输出端与所述第三电平转换电路52的输入端电连接；
所述第二电平转换电路51用于对其输入端接入的电压信号进行电平转换，以得到第三控制信号，以将所述第三控制信号的电位转换至高电压域，并将所述第三控制信号提供至所述第二p型驱动电路61的输入端；
所述第三电平转换电路52用于对其输入端接入的电压信号进行电平转换，以得到第四控制信号，将该第四控制信号的电位转换至负电压域，并将所述第四控制信号提供至所述第一n型驱动电路62的输入端；
所述第二p型驱动电路61的输出端与P1的栅极电连接，用于将所述第三控制信号提供至P1的栅极，并增强所述第二p型驱动电路61的输出端的驱动能力；
所述第一n型驱动电路62的输出端与N1的栅极电连接，用于将所述第四控制信号提供至N1的栅极，并增强所述第一n型驱动电路62的输出端的驱动能力；
所述第二个输出控制模块123包括第四反相器F4、第三或门OR3、第四或门OR4、第五反相器F5、第六反相器F6、第四电平转换电路53、第五电平转换电路54、第三p型驱动电路63和第二n型驱动电路64；
F4的输入端接入CLK_IN，F4的输出端与OR3的第一输入端电连接，OR3的第二输入端接入共享信号CSEN；
OR4的第一输入端接入CSEN，OR4的第二输入端接入CLK_IN；
F5的输入端与OR3的输出端电连接，F6的输入端与OR4的输出端电连接；
F5的输出端与第四电平转换电路53的输入端电连接，F6的输出端与所述第五电平转换电路54的输入端电连接；
所述第四电平转换电路53用于对其输入端接入的电压信号进行电平转换，以得到第五控制信号，将所述第五控制信号的电位转换为高电压域，并将所述第五控制信号提供至所述第三p型驱动电路63的输入端；
所述第五电平转换电路54用于对其输入端接入的电压信号进行电平转换，以得到第六控制信号，将所述第六控制信号的电位转换为负电压域，并将所述第六控制信号提供至所述第二n型驱动电路64的输入端；
所述第三p型驱动电路63的输出端与P2的栅极电连接，用于将所述第五控制信号提供至P2的栅极，并增强所述第三p型驱动电路63的输出端的驱动能力；
所述第二n型驱动电路64的输出端与N2的栅极电连接，用于将所述第六控制信号提供至N2的栅极，并增强所述第二n型驱动电路64的输出端的驱动能力。
在图4所示的实施例中，标号为NOR2的为第二或非门，NOR2的第一 输入端接入第一时钟信号CLK_X，NOR2的第二输入端接入第二时钟信号CLK_Y；NOR2的输出端用于输出CSEN。
在图4所示的实施例中，所述共享信号CSEN的电位可以在0V至5V之间，所述高电压域可以为25V至30V，所述负电压域可以为-10V至-5V，所述第二电平转换电路51的输入端接入的电压信号的电位、所述第三电平转换电路52的输入端接入的电压信号的电位、所述第四电平转换电路53的输入端接入的电压信号的电位，和所述第五电平转换电路54的输入端接入的电压信号的电位可以在0V和5V之间切换，则第三控制信号的电位和第五控制信号的电位可以在25V与30V之间切换，第四控制信号的电位和第六控制信号的电位可以在-10V与-5V之间切换。
本公开实施例所述的电荷共享方法，应用于上述的电荷共享电路，所述电荷共享方法包括：
当第一输出模块在第一输出控制信号的控制下，控制不输出第一电压信号时，控制单元通过控制信号输出端向开关单元提供打开控制信号；
所述开关单元在所述打开控制信号的控制下，控制导通所述两个时钟信号生成单元包括的时钟信号输出端之间的连接。
本公开实施例所述的电荷共享电路在工作时，通过控制单元在所述至少两个时钟信号生成单元中的两个时钟信号生成单元包括的第一输出控制端控制所述两个时钟信号生成单元都不输出第一电压信号时，向开关单元提供打开控制信号，开关单元在所述打开控制信号的控制下，控制导通所述两个时钟信号生成单元包括的时钟信号输出端之间的连接，以进行电荷共享。
本公开实施例所述的显示驱动模组包括时钟信号生成电路和上述的电荷共享电路。
在本公开实施例中，所述时钟信号生成电路包括多个时钟信号生成单元；
所述时钟信号生成单元包括时钟信号输出端、第一输出控制端、第二输出控制端、第一输出模块和第二输出模块；
所述第一输出模块用于在所述第一输出控制端提供的第一输出控制信号的控制下，控制是否通过所述时钟动信号输出端输出第一电压信号；
所述第二输出模块用于在所述第二输出控制端提供的第二输出控制信号 的控制下，控制是否通过所述时钟信号输出端输出第二电压信号。
本公开实施例所述的显示装置包括上述的显示驱动模组。
在本公开实施例中，所述显示装置可以为液晶显示装置，但不以此为限。在实际操作时，所述显示装置也可以为OLED(有机发光二极管)显示装置。
本公开实施例所提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述是本公开的可选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (10)

  1. 一种电荷共享电路，应用于显示装置，所述显示装置包括栅极驱动电路和时钟信号生成电路，所述栅极驱动电路包括多级移位寄存器单元；所述时钟信号生成电路包括至少两个时钟信号生成单元；所述至少两个时钟信号生成电路中的两个时钟信号生成单元分别为相邻的两移位寄存器单元提供相应的时钟信号；所述时钟信号生成单元包括时钟信号输出端、第一输出控制端和第一输出模块，所述第一输出模块用于在所述第一输出控制端提供的第一输出控制信号的控制下，控制是否通过所述时钟信号输出端输出第一电压信号；所述电荷共享电路包括控制单元和开关单元，其中，
    所述控制单元分别与所述两个时钟信号生成单元包括的所述第一输出控制端电连接，用于当所述第一输出模块在所述第一输出控制信号的控制下，控制不输出所述第一电压信号时，通过控制信号输出端向所述开关单元提供打开控制信号；
    所述开关单元分别与所述控制信号输出端和所述两个时钟信号生成单元包括的时钟信号输出端电连接，用于在所述打开控制信号的控制下，控制导通所述两个时钟信号生成单元包括的时钟信号输出端之间的连接。
  2. 如权利要求1所述的电荷共享电路，其中，所述开关单元包括第一开关晶体管和第二开关晶体管；
    所述第一开关晶体管的控制极和所述第二开关晶体管的控制极都与所述控制信号输出端电连接；
    所述第一开关晶体管的第一极与所述两个时钟信号生成单元中的第一个时钟信号生成单元的时钟信号输出端电连接，所述第一开关晶体管的第二极与所述第二开关晶体管的第一极电连接，所述第二开关晶体管的第二极与所述两个时钟信号生成单元中的第二个时钟信号生成单元的时钟信号输出端电连接；
    所述第一开关晶体管和所述第二开关晶体管都为p型晶体管；或者，所述第一开关晶体管和所述第二开关晶体管都为n型晶体管。
  3. 如权利要求2所述的电荷共享电路，其中，
    所述第一输出模块用于当所述第一输出控制信号为低电压信号时，控制不通过所述时钟信号输出端输出第一电压信号；
    所述控制单元包括或非门和控制模块；
    所述或非门的第一输入端与所述第一个时钟信号生成单元的第一输出控制电连接，所述或非门的第二输入端与所述第二个时钟信号生成单元的第一输出控制端电连接；
    所述控制模块与所述或非门的输出端电连接，用于当所述或非门通过其输出端输出高电压信号时，控制所述第一开关晶体管和第二开关晶体管都打开。
  4. 如权利要求3所述的电荷共享电路，其中，所述第一开关晶体管和所述第二开关晶体管都为p型晶体管；
    所述控制模块包括第一电平转换电路和第一p型驱动电路；
    所述第一电平转换电路与所述或非门的输出端电连接，所述第一电平转换电路用于对所述或非门通过其输出端输出的信号进行电平转换，并将电平转换得到的第一控制信号提供至所述第一p型驱动电路的输入端；
    所述第一p型驱动电路的输出端与所述控制信号输出端电连接，所述第一p型驱动电路用于对所述第一控制信号进行反相，以得到第二控制信号，并通过所述控制信号输出端将所述第二控制信号输出至所述第一开关晶体管的控制极，并能够提升所述第一p型驱动电路的输出端的驱动能力。
  5. 如权利要求3所述的电荷共享电路，其中，所述第一开关晶体管和所述第二开关晶体管都为n型晶体管；
    所述控制模块包括第一电平转换电路和第一n型驱动电路；
    所述第一电平转换电路与所述或非门的输出端电连接，所述第一电平转换电路用于对所述或非门通过其输出端输出的信号进行电平转换，并将电平转换得到的第一控制信号提供至所述第一n型驱动电路的输入端；
    所述第一n型驱动电路的输出端与所述控制信号输出端电连接，所述第一n型驱动电路用于通过所述控制信号输出端将所述第一控制信号提供至所述第一开关晶体管的控制极，并能够提升所述第一n型驱动电路的输出端的驱动能力。
  6. 如权利要求2所述的电荷共享电路，其中，
    所述第一输出模块用于当所述第一输出控制信号为高电压信号时，控制不通过所述栅极驱动信号输出第一电压信号；
    所述控制单元包括与非门和控制模块；
    所述与非门的第一输入端与所述第一个时钟信号生成单元的第一输出控制电连接，所述与非门的第二输入端与所述第二个时钟信号生成单元的第一输出控制端电连接；
    所述控制模块与所述与非门的输出端电连接，用于当所述与非门通过其输出端输出低电压信号时，控制所述第一开关晶体管和第二开关晶体管都打开。
  7. 一种电荷共享方法，应用于如权利要求1至6中任一权利要求所述的电荷共享电路，所述电荷共享方法包括：
    当第一输出模块在第一输出控制信号的控制下，控制不输出第一电压信号时，控制单元通过控制信号输出端向开关单元提供打开控制信号；
    所述开关单元在所述打开控制信号的控制下，控制导通两个时钟信号生成单元包括的时钟信号输出端之间的连接。
  8. 一种显示驱动模组，包括时钟信号生成电路和如权利要求1至6中任一权利要求所述的电荷共享电路。
  9. 如权利要求8所述的显示驱动模组，其中，所述时钟信号生成电路包括多个时钟信号生成单元；
    所述时钟信号生成单元包括时钟信号输出端、第一输出控制端、第二输出控制端、第一输出模块和第二输出模块；
    所述第一输出模块用于在所述第一输出控制端提供的第一输出控制信号的控制下，控制是否通过所述时钟信号输出端输出第一电压信号；
    所述第二输出模块用于在所述第二输出控制端提供的第二输出控制信号的控制下，控制是否通过所述时钟信号输出端输出第二电压信号。
  10. 一种显示装置，包括如权利要求8或9所述的显示驱动模组。
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