WO2016095300A1 - 一种栅极驱动电路 - Google Patents

一种栅极驱动电路 Download PDF

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Publication number
WO2016095300A1
WO2016095300A1 PCT/CN2015/070566 CN2015070566W WO2016095300A1 WO 2016095300 A1 WO2016095300 A1 WO 2016095300A1 CN 2015070566 W CN2015070566 W CN 2015070566W WO 2016095300 A1 WO2016095300 A1 WO 2016095300A1
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Prior art keywords
pull
control signal
gate
terminal
control
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PCT/CN2015/070566
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English (en)
French (fr)
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肖军城
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深圳市华星光电技术有限公司
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Priority to US14/418,166 priority Critical patent/US9483992B2/en
Publication of WO2016095300A1 publication Critical patent/WO2016095300A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0417—Special arrangements specific to the use of low carrier mobility technology
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0248—Precharge or discharge of column electrodes before or after applying exact column voltages

Definitions

  • the present invention relates to the technical field of liquid crystal display, in particular to a gate drive circuit of a liquid crystal display.
  • an array substrate gate drive (Gate Driver On Array, GOA) technology is used to fabricate a gate drive circuit on an array substrate, so as to realize the progressive scanning and driving of the gate lines. .
  • GOA Gate Driver On Array
  • the GOA circuit usually includes multiple levels of GOA units, and each level of GOA unit drives a row of horizontal scan lines correspondingly.
  • Each level of GOA unit mainly includes pull-up unit (Pull-up part), pull-up control unit (Pull-up control part), download unit (Transfer Part), first pull-down unit (Key Pull-down Part), Pull-down holding unit (Pull-down Holding Part), as well as a boost unit (Boost Part) that completes the potential rise and a reset unit (Reset Part) that resets the potential.
  • Boost Part boost unit that completes the potential rise
  • Reset Part resets the potential.
  • the pull-up unit is mainly used to output the clock signal as a gate signal; the pull-up control unit is used to control the working time of the pull-up unit, and is connected to the downstream signal output by the previous GOA unit; the first pull-down unit It is used to pull the gate signal to a low potential; the pull-down holding unit is used to maintain the gate signal and the control signal of the pull-up circuit at a low potential.
  • CMOS photomasks are mostly about 12 channels, while NMOS and PMOS photomasks for single-type transistors have 9 channels or even less. Therefore, in order to save manufacturing costs, single-type LTPS-based GOA circuits are widely used.
  • One of the technical problems to be solved by the present invention is to provide a single-type gate drive circuit based on LTPS to improve the service life of the GOA circuit.
  • the present invention provides a gate drive circuit, which includes multi-stage GOA drive units, wherein each stage of GOA drive unit includes:
  • a pull-up control unit which is used to output a pull-up control signal
  • the control terminal of the pull-up unit is coupled to the output terminal of the pull-up control unit to pull up the potential of the gate signal output terminal according to the pull-up control signal and the clock signal, so that the GOA drive unit of the current stage outputs the gate signal ;
  • the first pull-down unit which is coupled between the control terminal of the pull-up unit and the DC power supply, to pull down the potential of the control terminal of the pull-up unit to the potential of the DC power supply according to the pull-down control signal, thereby turning off the pull-up unit;
  • a pull-down holding unit which is coupled between the gate signal output terminal, the control terminal of the pull-up unit and the DC power supply, the pull-down holding unit includes a bridge module, a first and a second pull-down holding module;
  • the phases of the pull-down hold control signals output by the first and second pull-down hold modules are complementary, so that the first and second pull-down hold modules work alternately to control the pull-down hold control signal according to the pull-down hold control signal.
  • the potential of the gate signal output terminal and/or the potential of the control terminal of the pull-up unit is maintained at the potential of the DC power supply.
  • control end of the bridge module is coupled to the output end of the pull-up control unit, and the first end and the second end of the bridge module are respectively coupled to the first and second pull-down holding modules The pull-down keeps the control signal output terminal.
  • it further includes:
  • a boost unit the first terminal and the second terminal of which are respectively coupled to the output terminal and the gate signal output terminal of the pull-up control unit, so as to raise the potential of the control terminal of the pull-up unit according to the pull-up control signal;
  • the circuit reset unit includes a reset transistor, the gate of which receives a reset signal, and its first terminal and second terminal are respectively coupled to the output terminal of the pull-up control unit and the DC power supply, so as to respond to the The reset signal eliminates the accumulation of static electricity at the output terminal of the pull-up control unit.
  • the first and second pull-down holding modules respectively include: To
  • the first control sub-module the control terminal of which receives the first control signal, and the output terminal of which is coupled to the pull-down hold control signal output terminal;
  • the second control sub-module the control terminal of which receives the second control signal, and the output terminal of which is coupled to the pull-down hold control signal output terminal;
  • a first pull-down transistor the gate of which is coupled to the pull-down holding control signal output terminal, the first terminal of which is coupled to the gate signal output terminal, and the second terminal of which is coupled to the DC power supply;
  • a second pull-down transistor the gate of which is coupled to the pull-down holding control signal output terminal, the first terminal of which is coupled to the output terminal of the pull-up control unit, and the second terminal of which is coupled to the DC power supply;
  • the phases of the first control signal and the second control signal are complementary.
  • the gate of the third pull-down transistor is coupled to the output terminal of the pull-up control unit, the first terminal is coupled to the pull-down holding control signal output terminal, and the second terminal is coupled to The DC power supply.
  • the first control sub-module of the first pull-down holding module includes a first transistor, the gate of which is shorted to the first terminal to receive the first control signal, and the second terminal is coupled to the first transistor.
  • the first control sub-module of the second pull-down holding module includes a second transistor, the gate of which is shorted to the first end to receive the second control signal, and the second end is coupled to the pull-down holding control of the second pull-down holding module Signal output terminal.
  • the first control submodule of the first pull-down holding module includes a first Darlington tube, the base of which is shorted to the first end to receive the first control signal, and the second end is coupled to To the pull-down hold control signal output terminal of the first pull-down hold module;
  • the first control sub-module of the second pull-down holding module includes a second Darlington tube, the base of which is shorted to the first end to receive the second control signal, and the second end is coupled to the second pull-down holding module Pull down to maintain the control signal output terminal.
  • the second control submodule of the first pull-down holding module includes a third transistor, the gate of which receives the second control signal, the first end of which is coupled to the DC power supply, and the second end of which Coupled to the pull-down hold control signal output terminal of the first pull-down hold module;
  • the second control sub-module of the second pull-down holding module includes a fourth transistor, the gate of which receives the first control signal, the first end of which is coupled to the DC power source, and the second end of which is coupled to the second pull-down holding
  • the pull-down of the module keeps the control signal output terminal.
  • the second control sub-module of the first pull-down holding module includes a third transistor, the gate of which To Receiving the second control signal, the first end of which receives the first control signal, and the second end of which is coupled to the pull-down holding control signal output end of the first pull-down holding module;
  • the second control sub-module of the second pull-down holding module includes a fourth transistor, the gate of which receives the first control signal, the first end of which receives the second control signal, and the second end of which is coupled to the second pull-down holding module. Pull down to maintain the control signal output terminal.
  • the first control signal is the clock signal.
  • the first control signal is a low-frequency pulse signal, and when the next-stage GOA driving unit outputs a high-potential gate signal, the first control signal is inverted.
  • the pull-up control unit includes a pull-up control transistor, the gate of which is shorted to the first terminal to receive the gate signal output by the GOA driving unit of the previous stage, and the second terminal of which outputs the up Pull the control signal.
  • the first pull-down unit includes a pull-down transistor whose gate receives the pull-down control signal, and its first terminal and second terminal are respectively coupled to the output terminal and the output terminal of the pull-up control unit. Said DC power supply,
  • the pull-down control signal is the gate signal output by the GOA driving unit of the next stage.
  • the present invention Compared with the existing GOA drive unit, the present invention has the following advantages.
  • the pull-down holding unit is configured as a three-stage voltage division mode, which can ensure the proper potential of the P(N) and K(N) points during the active and non-active periods of the circuit. Makes the P(N) and K(N) points lower potential during the operation of the GOA unit at this level, effectively preventing the leakage of Q(N) and G(N).
  • P(N) and K(N) are provided with an appropriate high potential during the non-active period to ensure that P(N) and K(N) can generate a higher potential during the non-active period to maintain Q(N) And G(N) has low potential during non-action period.
  • the present invention uses the gate output signal G(N) to control the upper and lower transmissions, and does not need the ST(N) transmission signals in the conventional GOA drive circuit, which can effectively simplify the circuit configuration, save wiring space, and reduce power consumption .
  • the present invention uses a Darlington tube in the control sub-module of the pull-down holding unit to reduce the leakage of P(N) and K(N) points during the non-acting period, and to ensure smoother pull-down of the G(N) and Q(N) potentials. .
  • the control signal for controlling the two pull-down holding modules to work alternately in the pull-down holding unit is set as a low-frequency pulse signal, which can effectively reduce the power consumption of the entire GOA drive circuit. Furthermore, because the low-frequency pulse signal is used to control the two pull-down holding modules to work alternately, instead of using a clock signal to control the alternate operation of the pull-down holding modules, the duty cycle of the clock signal can be flexibly configured according to different components and product configurations. .
  • FIG. 1 is a schematic diagram of the circuit structure of a GOA driving unit according to the first embodiment of the present invention
  • FIG. 2 is a schematic diagram of the circuit structure of the GOA driving unit according to the second embodiment of the present invention.
  • FIG. 3 is a schematic diagram of the circuit structure of a GOA driving unit according to the third embodiment of the present invention.
  • FIG. 4 is a schematic diagram of the circuit structure of a GOA driving unit according to the fourth embodiment of the present invention.
  • FIG. 5 is a signal timing diagram of the GOA driving unit in the first embodiment to the fourth embodiment
  • FIG. 6 is a schematic diagram of the circuit structure of a GOA driving unit according to the fifth embodiment of the present invention.
  • FIG. 7 is a signal timing diagram of the GOA driving unit in the fifth embodiment.
  • the embodiment of the present invention provides a single-type gate drive GOA circuit based on LTPS.
  • the channel width (W) of the LTPS transistor is relatively small compared to the channel length (L). Therefore, the parasitic resistance and parasitic capacitance of the TFT element are small, which has a weak influence on the stability of the circuit.
  • the threshold (Vth) drift of LTPS transistors under positive and negative voltage conditions is very small, and there is no need for ripple elimination like amorphous silicon (a-Si) TFT elements. Therefore, the gate drive circuit based on LTPS does not need to include many pull-down sustaining elements like the traditional amorphous silicon GOA circuit, which can simplify the gate drive circuit, and only need to construct a basic GOA circuit to achieve good display quality.
  • the embodiments of the present invention are particularly suitable for flat panel display (Flat Panel Display, FPD) products, and can realize the design of narrow and frameless display products.
  • the LTPS components included in the GOA circuit provided in the example are all To It is a single-type (NMOS or PMOS) device, which can reduce the number of masks in the manufacturing process, and can greatly save manufacturing costs.
  • FIG. 1 is a schematic diagram of the circuit structure of the GOA driving unit according to this embodiment. This figure shows only one stage of the multi-stage GOA drive unit, marked as N. For the convenience of description, the previous stage of the GOA drive unit is labeled N-1, and the next stage of the GOA drive unit is labeled N+1.
  • the GOA driving unit shown in FIG. 1 includes a pull-up control unit 100, a pull-up unit 200, a boost unit 300, a first pull-down unit 400, a pull-down holding unit 500, and a circuit reset unit 600.
  • the pull-up control unit 100 includes a pull-up control transistor T1.
  • the gate of the pull-up control transistor T1 is short-circuited with the first end, receives the gate signal G(N-1) output by the N-1th GOA unit, and outputs the pull-up control signal G(N-1).
  • the pull-up unit 200 includes a pull-up transistor T2.
  • the gate of the pull-up transistor T2 is coupled to the output terminal (point Q(N) in the figure) of the pull-up control unit 100, and receives the pull-up control signal G(N-1) output by the pull-up control unit 100.
  • the transistor T2 pulls up the potential of the gate signal output terminal (point G(N) in the figure) according to the clock signal CKN, so that the GOA drive unit of this stage outputs the gate signal .
  • the boosting unit 300 includes a storage capacitor Cb.
  • the upper and lower electrodes of the storage capacitor Cb are respectively coupled to the output terminal (point Q(N) in the figure) and the gate signal output terminal (point G(N) in the figure) of the pull-up control unit 100.
  • the storage capacitor Cb raises the potential of the Q(N) point twice to ensure that the GOA drive unit of this stage can normally output the gate signal G(N).
  • the first pull-down unit 400 includes a pull-down transistor T3.
  • the gate of the pull-down transistor T3 receives the pull-down control signal, that is, the gate signal G(N+1) output by the GOA driving unit of the N+1th stage.
  • the source and drain of the transistor T3 are respectively coupled to the output terminal (point Q(N) in the figure) of the pull-up control unit 100 and the DC power supply VSS.
  • the pull-down holding unit 500 is coupled between the gate signal output terminal (point G(N) in the figure), the control terminal of the pull-up unit (point Q(N) in the figure) and the DC power supply VSS.
  • the pull-down holding unit 500 includes a bridge module 510, a first pull-down holding module 520, and a second pull-down holding module 530.
  • the first pull-down holding module 520 includes transistors T6, T7, T8, T15, and T16.
  • the first transistor T6 constitutes a first control sub-module
  • the third transistor T7 constitutes a second control sub-module.
  • the gate and the first end of the first transistor T6 are short-circuited to receive the first control signal CKN, and the second end of the first transistor T6 is coupled to the pull-down holding signal output end of the pull-down holding module 520 (point P(N) in the figure).
  • the gate of the third transistor T7 receives the second control signal XCKN, and its source and drain are respectively coupled to the DC power source VSS and the P(N) point.
  • the first pull-down transistor T15 and the second pull-down transistor T16 To The gate is coupled to the P(N) point to receive the pull-down holding signal output by the transistors T6 and T7.
  • the source and drain of the transistor T15 are respectively coupled to the gate signal output terminal (point G(N) in the figure) and the DC power supply VSS.
  • the source and drain of the transistor T16 are respectively coupled to the output terminal (point Q(N) in the figure) of the pull-up control unit 100 and the DC power supply VSS.
  • the gate of the third pull-down transistor T8 is coupled to the output terminal (point Q(N) in the figure) of the pull-up control unit 100, and its source and drain are respectively coupled to the P(N) point and the DC power supply VSS.
  • the second pull-down holding module 530 includes transistors T10, T11, T12, T13, and T14, and the pull-down holding signal output terminal is point K(N) in the figure. Only the second transistor T10 receives the second control signal XCKN, and the gate of the fourth transistor T12 receives the first control signal CKN.
  • the bridge module 510 includes a transistor T18, the gate of which is coupled to the output terminal (point Q(N) in the figure) of the pull-up control unit 100, and its source and drain are respectively coupled to the P(N) of the first pull-down holding module 520 ) Point and the K(N) point of the second pull-down holding module 530.
  • the circuit reset unit 600 includes a reset transistor T4.
  • the gate of the reset transistor T4 receives the reset signal, and its source and drain are respectively coupled to the output terminal (point Q(N) in the figure) of the pull-up control unit 100 and the DC power supply VSS.
  • the reset signal is provided in a blanking time (Blanking Time) of one or more frames.
  • the DC power supply VSS can be set as a negative voltage source to eliminate the accumulation of static electricity at point Q(N) in the figure according to the reset signal.
  • the first clock signal CKN and the second clock signal XCKN are two sets of pulse signals with complementary phases, and the duty ratios of the clock signals CKN and XCKN are slightly less than 50%. It should be noted that for transistors with good electrical characteristics such as IGZO (indium gallium zinc oxide) and LTPS, the duty cycle of the clock signal can be designed to be less than 50%.
  • IGZO indium gallium zinc oxide
  • G(N-1) is at a high potential
  • T1 is turned on, and the output terminal of T1 is at a high potential, so the storage capacitor Cb is charged to the first potential under the action of G(N-1), that is, Q
  • the potential of (N) rises to the first potential
  • T2, T8, T11 and T18 are turned on.
  • T8 is turned on, so that the point P(N) is connected to the DC power supply VSS.
  • T11 is turned on, so that point K(N) is connected to the DC power supply VSS.
  • CKN is at a low potential and XCKN is at a high potential
  • T6 and T12 are off, and T7 and T10 are on.
  • T7 is turned on, so that the point P(N) is connected to the DC power supply VSS.
  • T10 is turned on, so that the K(N) point is connected to the high potential of XCKN. Since T18 is turned on, the end of P(N) and K(N) at low potential will pull the other end at high potential low, making T13, T14, T15 and T16 cut off, preventing Q(N) and G( N) Leakage. Since T2 is turned on and CKN is low, G(N) remains at CKN low.
  • T2 is at a low potential, and T1 is turned off. Due to the energy storage effect of Cb, the gate of T2 remains at a high potential, and T2 remains on. Since Q(N) remains at a high potential, T8, T11, and T18 remain on. T8 turns on, To Make the point P(N) communicate with the DC power supply VSS. T11 is turned on, so that point K(N) is connected to the DC power supply VSS. In addition, since CKN is at a high potential and XCKN is at a low potential, T6 and T12 are turned on, and T7 and T10 are turned off.
  • T6 is turned on, so that the P(N) point is connected to the high potential of CKN.
  • T12 is turned on, so that point K(N) is connected to the DC power supply VSS. Since T18 is turned on, the end of P(N) and K(N) at low potential will pull the other end at high potential low, making T13, T14, T15 and T16 cut off, preventing Q(N) and G( N) Leakage.
  • T2 Since T2 is turned on and CKN is at a high potential, Cb is recharged under the action of CKN to reach a second potential higher than the first potential, that is, the potential of Q(N) is raised to a second potential higher than the first potential . Since T2 is turned on and CKN is high, G(N) is pulled up to CKN high.
  • T3 is turned on. Since T3 is turned on, the potential at the point Q(N) drops to the potential of the DC power supply VSS. Since the Q(N) point is at a low potential, T2, T8, T11, and T18 remain off. In addition, since CKN is at a low potential and XCKN is at a high potential, T6 and T12 are off, and T7 and T10 are on.
  • T7 is turned on, so that the point P(N) is connected to the DC power supply VSS.
  • T10 is turned on, so that the K(N) point is connected to the high potential of XCKN.
  • T7, T18 and T10 are connected in series to form a three-stage resistor divider circuit.
  • the potential at point P(N) is the low potential of the DC power supply VSS, and the potential at point K(N) is the high potential of XCKN. That is, the P(N) point and the K(N) point are complementary in phase.
  • T15 and T16 are cut off. Since the K(N) point is at a high potential, T13 and T14 are turned on, so that the potentials at the G(N) and Q(N) points are maintained at the low potential of the DC power supply VSS.
  • T8 T11, and T18 remain off.
  • CKN is a high potential
  • XCKN is a low potential
  • T6 and T12 are turned on
  • T7 and T10 are turned off.
  • T6 is turned on, so that the P(N) point is connected to the high potential of CKN.
  • T12 is turned on, so that point K(N) is connected to the DC power supply VSS.
  • T6 and T12 are turned on, which is equivalent to the small resistance.
  • T6, T18 and T12 are connected in series to form a three-stage resistor divider circuit.
  • the potential at point K(N) is the low potential of the DC power supply VSS
  • the potential at point P(N) is the high potential of XCKN. That is, the P(N) point and the K(N) point are complementary in phase.
  • T13 and T14 are cut off. Since the P(N) point is at a high potential, T15 and T16 are turned on, so that the potentials of the G(N) and Q(N) points are maintained at the low potential of the DC power supply VSS.
  • T8 and T11 have a strong pull-down effect on the potentials at points P(N) and K(N).
  • the first pull-down module 520 and the second pull-down module 530 work alternately.
  • the transistors T6, T18, and T12 are a group
  • the transistors T10, T18, and T7 are a group.
  • Group circuits act alternately to control the acting time of T15, T16 and T13, T14 respectively. It is ensured that the P(N) and K(N) points alternately appear high potentials, so that the potentials of the gate signal output terminal G(N) and the control terminal of the pull-up unit 200 are maintained at a low potential, thereby improving stability.
  • the service life of the pull-down holding unit 500 can be increased.
  • FIG. 2 shows a schematic diagram of the circuit structure of the GOA driving unit of this embodiment.
  • This circuit is a further improvement of the pull-down holding unit 500 on the basis of the circuit shown in FIG. 1.
  • the source of the third transistor T7 receives the first control signal CKN
  • the source of the fourth transistor T12 receives the second control signal XCKN.
  • the absolute value of the low potential of the CKN and XCKN signals is set to be greater than the absolute value of the potential of the DC power supply VSS, so that the low potential of the CKN and XCKN signals can be used to achieve a stronger low-potential pull-down capability during the inactive period.
  • FIG. 3 shows a schematic diagram of the circuit structure of the GOA driving unit of this embodiment.
  • This circuit is a further improvement of the pull-down holding unit 500 on the basis of the circuit shown in FIG. 1. Specifically, the circuit adds transistors T5 and T9, so that T5 and T6 form a first Darlington tube, and T9 and T10 form a second Darlington tube.
  • the base of the first Darlington tube is shorted to the first terminal to receive the first control signal CKN, and the second terminal is coupled to the pull-down holding control signal output terminal P(N) of the first pull-down holding module.
  • the gate and the first end of the transistor T5 are short-circuited to receive the first control signal CKN.
  • the gate of the transistor T6 is coupled to the second terminal of T5, the first terminal of T6 is coupled to the gate of T5, and the second terminal of T6 is coupled to the P(N) point.
  • the base of the second Darling tube is shorted to the first end to receive the second control signal XCKN, and the second end is coupled to the pull-down holding control signal output terminal K(N) of the second pull-down holding module.
  • the gate and the first end of the transistor T9 are short-circuited to receive the second control signal XCKN.
  • the gate of the transistor T10 is coupled to the second terminal of T9, and the first terminal of T10 To The gate of T9 is coupled, and the second terminal of T10 is coupled to point K(N).
  • the introduction of transistors T5 and T9 can reduce the leakage of P(N) and K(N) during the non-acting period, and ensure G(N) and The Q(N) potential pulls down more smoothly.
  • FIG. 4 shows a schematic diagram of the circuit structure of the GOA driving unit of this embodiment.
  • This circuit is an integration of the three GOA drive units shown in Figure 1, Figure 2 and Figure 3, and has all the functions and advantages of the three circuits. The functions and advantages of various drive units have been described in detail above, and will not be repeated here.
  • FIG. 6 shows a schematic diagram of the circuit structure of the GOA driving unit of this embodiment. This figure is based on the GOA driving unit shown in FIG. 4, and the two control signals input to the two pull-down holding modules 520 and 530 are changed to low-frequency clock signals LC1 and LC2 to reduce the power of the entire pull-down holding unit 500. Consumption.
  • FIG. 7 shows a timing diagram of the GOA driving unit in this embodiment.
  • the working principle of the circuit will be described in detail below taking time period t3 and time period t4 as examples.
  • T3 is turned on. Since T3 is turned on, the potential at the point Q(N) drops to the potential of the DC power supply VSS. Since the Q(N) point is at a low potential, T2, T8, T11, and T18 remain off. In addition, since LC1 is at a low potential and LC2 is at a high potential, T5, T6, and T12 are off, and T7, T9, and T10 are on.
  • T7 is turned on, so that the point P(N) is connected to the DC power supply VSS.
  • T9 and T10 are turned on, so that the K(N) point is connected to the high potential of LC2.
  • T7, T18, T9 and T10 are connected in series to form a three-stage resistor divider circuit.
  • the potential at point P(N) is the low potential of the clock signal LC1
  • the potential at point K(N) is the high potential of LC2. That is, the P(N) point and the K(N) point are complementary in phase. Since the P(N) point is at a low potential, T15 and T16 are cut off. Since the K(N) point is at a high potential, T13 and T14 are turned on, so that the potentials at the G(N) and Q(N) points are maintained at the low potential of the DC power supply VSS.
  • the absolute value of the low potential of the LC1 and LC2 signals can be set to be greater than the absolute value of the VSS potential of the DC power supply, so that the low potential of the LC1 and LC2 signals can be used to achieve a stronger low-potential pull-down capability during non-action . Since it is not necessary to use a clock signal to control the alternate of the pull-down holding module, the duty cycle of the clock signal can be flexibly configured according to different components and product configurations.
  • timing signal configuration in the foregoing embodiment is for N-type switching elements.
  • P-type switching elements the high and low potentials of the circuit nodes can be interchanged, and the timing remains unchanged, and the technical solutions in the foregoing embodiments can still be implemented.

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Abstract

一种栅极驱动电路包括多级GOA驱动单元，其中每一级GOA驱动单元包括上拉控制单元（100）、上拉单元（200）、第一下拉单元（400）和下拉保持单元（500），所述下拉保持单元（500）包括桥接模块（510）、第一和第二下拉保持模块（520、530）。其中，当所述桥接模块（510）处于关闭状态时，第一和第二下拉保持模块（520、530）交替工作，以根据下拉保持控制信号将栅极信号输出端的电位和／或上拉单元（200）的控制端的电位保持在直流电源的电位。

Description

一种栅极驱动电路
相关申请的交叉引用
本申请要求享有2014年12月19日提交的名称为“一种栅极驱动电路”的中国专利申请CN201410804017.2的优先权，其全部内容通过引用并入本文中。
技术领域
本发明涉及液晶显示技术领域，具体地说，涉及一种液晶显示器的栅极驱动电路。
背景技术
现有技术中，通常在液晶显示面板的阵列制程阶段，采用阵列基板栅极驱动(Gate Driver On Array，GOA)技术将栅极驱动电路制作在阵列基板上，从而实现对栅线逐行扫描驱动。该技术可减少外接IC的绑定(bonding)工序，并提高液晶显示面板的集成度。
GOA电路通常包括多级GOA单元，每一级GOA单元对应驱动一行水平扫描线。每一级GOA单元主要包括上拉单元(Pull-up part)，上拉控制单元(Pull-up control part)，下传单元(Transfer Part)，第一下拉单元(Key Pull-down Part)，下拉保持单元(Pull-down Holding Part)，以及完成电位抬升的升压单元(Boost Part)和重置电位的重置单元(Reset Part)。
其中，上拉单元主要用于将时钟信号输出为栅极信号；上拉控制单元用于控制上拉单元的工作时间，一股连接前一级GOA单元输出的下传信号；第一下拉单元用于将栅极信号拉低为低电位；下拉保持单元用于将栅极信号和上拉电路的控制信号维持在低电位。
此外，自从低温多晶硅(LoW Temprature Poly-silicon，LTPS)出现后，GOA电路架构和电路类型呈现较大的差异性，通常可分为NMOS、PMOS和CMOS的GOA电路类型。在制程过程中，CMOS光罩多为12道左右，而NMOS和PMOS这种单型晶体管的光罩则为9道甚至更少。因此，为了节约制造成本，单型的基于LTPS的GOA电路得到广泛应用。
然而，常规的基于LTPS的单型GOA电路一股采用单组下拉保持单元，由于下拉保持电路的处于长时间的工作状态，对电路寿命造成不利影响。其次，对于大尺寸的LTPS 显示面板，由于栅极驱动电路的RC负载很大，也会降低整个GOA电路的使用寿命。
发明内容
本发明所要解决的技术问题之一是需要提供一种基于LTPS的单型栅极驱动电路，来提高GOA电路的使用寿命。
本发明提供一种栅极驱动电路，包括多级GOA驱动单元，其中每一级GOA驱动单元包括：
上拉控制单元，其用于输出上拉控制信号；
上拉单元，其控制端耦接在所述上拉控制单元的输出端，以根据所述上拉控制信号和时钟信号上拉栅极信号输出端的电位，使本级GOA驱动单元输出栅极信号；
第一下拉单元，其耦接在所述上拉单元的控制端和直流电源之间，以根据下拉控制信号将上拉单元的控制端的电位下拉至所述直流电源的电位，从而关闭上拉单元；
下拉保持单元，其耦接在所述栅极信号输出端、上拉单元的控制端和直流电源之间，所述下拉保持单元包括桥接模块、第一和第二下拉保持模块；
其中，当所述桥接模块处于关闭状态时，第一和第二下拉保持模块输出的下拉保持控制信号相位互补，使得第一和第二下拉保持模块交替工作，以根据下拉保持控制信号将所述栅极信号输出端的电位和/或上拉单元的控制端的电位保持在所述直流电源的电位。
在一个实施例中，所述桥接模块的控制端耦接在所述上拉控制单元的输出端，所述桥接模块的第一端和第二端分别耦接在第一和第二下拉保持模块的下拉保持控制信号输出端。
在一个实施例中，进一步包括：
升压单元，其第一端和第二端分别耦接所述上拉控制单元的输出端和栅极信号输出端，以根据所述上拉控制信号抬升所述上拉单元控制端的电位；
电路重置单元，其包括一重置晶体管，其栅极接收重置信号，其第一端和第二端分别耦接所述上拉控制单元的输出端和所述直流电源，以根据所述重置信号消除所述上拉控制单元的输出端的静电积累。
在一个实施例中，所述第一和第二下拉保持模块分别包括：
第一控制子模块，其控制端接收第一控制信号，其输出端耦接至下拉保持控制信号输出端；
第二控制子模块，其控制端接收第二控制信号，其输出端耦接至下拉保持控制信号输出端；
第一下拉晶体管，其栅极耦接在所述下拉保持控制信号输出端，其第一端耦接在所述栅极信号输出端，其第二端耦接至所述直流电源；
第二下拉晶体管，其栅极耦接在所述下拉保持控制信号输出端，其第一端耦接在所述上拉控制单元的输出端，其第二端耦接至所述直流电源；
其中所述第一控制信号和第二控制信号的相位互补。
在一个实施例中，第三下拉晶体管，其栅极耦接在所述上拉控制单元的输出端，其第一端耦接在所述下拉保持控制信号输出端，其第二端耦接至所述直流电源。
在一个实施例中，所述第一下拉保持模块的第一控制子模块包括第一晶体管，其栅极短接第一端，以接收第一控制信号，其第二端耦接至第一下拉保持模块的下拉保持控制信号输出端；
所述第二下拉保持模块的第一控制子模块包括第二晶体管，其栅极短接第一端，以接收第二控制信号，其第二端耦接至第二下拉保持模块的下拉保持控制信号输出端。
在一个实施例中，所述第一下拉保持模块的第一控制子模块包括第一达林顿管，其基极短接第一端，以接收第一控制信号，其第二端耦接至第一下拉保持模块的下拉保持控制信号输出端；
所述第二下拉保持模块的第一控制子模块包括第二达林顿管，其基极短接第一端，以接收第二控制信号，其第二端耦接至第二下拉保持模块的下拉保持控制信号输出端。
在一个实施例中，所述第一下拉保持模块的第二控制子模块包括第三晶体管，其栅极接收第二控制信号，其第一端耦接至所述直流电源，其第二端耦接至第一下拉保持模块的下拉保持控制信号输出端；
所述第二下拉保持模块的第二控制子模块包括第四晶体管，其栅极接收第一控制信号，其第一端耦接至所述直流电源，其第二端耦接至第二下拉保持模块的下拉保持控制信号输出端。
在一个实施例中，所述第一下拉保持模块的第二控制子模块包括第三晶体管，其栅极 接收第二控制信号，其第一端接收第一控制信号，其第二端耦接在第一下拉保持模块的下拉保持控制信号输出端；
所述第二下拉保持模块的第二控制子模块包括第四晶体管，其栅极接收第一控制信号，其第一端接收第二控制信号，其第二端耦接在第二下拉保持模块的下拉保持控制信号输出端。
在一个实施例中，所述第一控制信号为所述时钟信号。
在一个实施例中，所述第一控制信号为低频脉冲信号，当下一级GOA驱动单元输出高电位的栅极信号时，所述第一控制信号发生翻转。
在一个实施例中，所述上拉控制单元包括一上拉控制晶体管，其栅极短接第一端，以接收上一级GOA驱动单元输出的栅极信号，其第二端输出所述上拉控制信号。
在一个实施例中，所述第一下拉单元包括一下拉晶体管，其栅极接收所述下拉控制信号，其第一端和第二端分别耦接所述上拉控制单元的输出端和所述直流电源，
其中，所述下拉控制信号为下一级GOA驱动单元输出的栅极信号。
与现有的GOA驱动单元相比，本发明具有以下优点。
l、本发明将下拉保持单元配置为三段分压的模式，可保证电路在作用期间和非作用期间的P(N)和K(N)点的合适电位。使得在本级GOA单元作用期间提供给P(N)和K(N)点更低电位，有效的防止Q(N)和G(N)的漏电。同时，非作用期间提供给P(N)和K(N)一个适当的高电位，以确保P(N)和K(N)在非作用期间能够产生较高的电位，来维持Q(N)和G(N)的在非作用期间低电位。
2、本发明采用栅极输出信号G(N)控制上下级传，并不需要常规的GOA驱动电路中的ST(N)级传信号，能够有效简化电路配置，节省布线空间，并降低功耗。
3、本发明在下拉保持单元的控制子模块中采用达林顿管，在非作用期间减少P(N)和K(N)点漏电，保证G(N)和Q(N)电位下拉更顺畅。
4、本发明将下拉保持单元中控制两个下拉保持模块交替工作的控制信号设置成低频脉冲信号，可有效降低整个GOA驱动电路的功耗。进一步来说，因为采用低频脉冲信号控制两个下拉保持模块交替工作，而并非采用时钟信号来控制下拉保持模块的交替，因此，可根据不同的元件和产品配型灵活配置时钟信号的占空比。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显 而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
附图用来提供对本申请技术方案或现有技术的进一步理解，并且构成说明书的一部分，但并不构成对本申请技术方案的限制。
附图用来提供对本发明的进一步理解，并且构成说明书的一部分，与本发明的实施例共同用于解释本发明，并不构成对本发明的限制。在附图中：
图1是根据本发明实施例一的GOA驱动单元的电路结构示意图；
图2是根据本发明实施例二的GOA驱动单元的电路结构示意图；
图3是根据本发明实施例三的GOA驱动单元的电路结构示意图；
图4是根据本发明实施例四的GOA驱动单元的电路结构示意图；
图5是实施例一至实施例四中GOA驱动单元的信号时序图；
图6是根据本发明实施例五的GOA驱动单元的电路结构示意图；
图7是实施例五中GOA驱动单元的信号时序图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，以下结合附图对本发明作进一步地详细说明。
本发明的实施例提供一种基于LTPS的单型栅极驱动GOA电路。LTPS晶体管的沟道宽度(W)与沟道长度(L)之比较小，因此，TFT元件的寄生电阻和寄生电容较小，对电路的稳定性影响很弱。另外，LTPS晶体管在正负压条件下的阈值(Vth)漂移很小，无需象非晶硅(a-Si)TFT元件那样作波纹(Ripple)消除处理。因此，基于LTPS的栅极驱动电路不必象传统的非晶硅GOA电路那样包含很多下拉维持元件，能够简化栅级驱动电路，仅需构建基本的GOA电路即可实现良好的显示品质。
本发明的实施例特别适用于平板显示(Flat Panel Display，FPD)产品，可以实现显示产品的窄边框和无边框的设计。并且，在示例中所提供的GOA电路所包含的LTPS元件均 为单型(NMOS或者PMOS)元件，在制程中可减少光罩次数，能大幅度节省制造成本。
实施例一
图1为根据本实施例的GOA驱动单元的电路结构示意图。该图仅显示了多级GOA驱动单元中的一级，标示为N。为了方便说明，将该GOA驱动单元的前一级标示为N-1，将该GOA驱动单元的后一级标示为N+1。
图1所示的GOA驱动单元包括上拉控制单元100、上拉单元200、升压单元300、第一下拉单元400、下拉保持单元500和电路重置单元600。
上拉控制单元100包括上拉控制晶体管T1。上拉控制晶体管T1的栅极和第一端短接，接收第N-1级GOA单元输出的栅极信号G(N-1)，并输出上拉控制信号G(N-1)。
上拉单元200包括上拉晶体管T2。上拉晶体管T2的栅极耦接上拉控制单元100的输出端(图中Q(N)点)，接收上拉控制单元100输出的上拉控制信号G(N-1)。在上拉控制信号G(N-1)的作用下，晶体管T2根据时钟信号CKN上拉栅极信号输出端(图中G(N)点)的电位，使得本级GOA驱动单元输出栅极信号。
升压单元300包括存储电容器Cb。存储电容器Cb的上下电极分别耦接上拉控制单元100的输出端(图中Q(N)点)和栅极信号输出端(图中G(N)点)。存储电容器Cb通过二次抬升Q(N)点的电位来保证本级GOA驱动单元能够正常输出栅极信号G(N)。
第一下拉单元400包括下拉晶体管T3。下拉晶体管T3的栅极接收下拉控制信号，即第N+1级GOA驱动单元输出的栅极信号G(N+1)。晶体管T3源极和漏极分别耦接上拉控制单元100的输出端(图中Q(N)点)和直流电源VSS。
下拉保持单元500耦接在栅极信号输出端(图中G(N)点)、上拉单元的控制端(图中Q(N)点)和直流电源VSS之间。下拉保持单元500包括桥接模块510、第一下拉保持模块520和第二下拉保持模块530。
以第一下拉保持模块520为例，其包括晶体管T6、T7、T8、T15和T16。其中，第一晶体管T6构成第一控制子模块，第三晶体管T7构成第二控制子模块。第一晶体管T6的栅极和第一端短接，接收第一控制信号CKN，其第二端耦接下拉保持模块520的下拉保持信号输出端(图中P(N)点)。第三晶体管T7的栅极接收第二控制信号XCKN，其源极和漏极分别耦接直流电源VSS和P(N)点。第一下拉晶体管T15和第二下拉晶体管T16的 栅极耦接P(N)点，以接收晶体管T6和T7输出的下拉保持信号。晶体管T15的源极和漏极分别耦接栅极信号输出端(图中G(N)点)和直流电源VSS。晶体管T16的源极和漏极分别耦接上拉控制单元100的输出端(图中Q(N)点)和直流电源VSS。第三下拉晶体管T8的栅极耦接上拉控制单元100的输出端(图中Q(N)点)，其源极和漏极分别耦接P(N)点和直流电源VSS。
与第一下拉保持模块520类似地，第二下拉保持模块530包括晶体管T10、T11、T12、T13和T14，下拉保持信号输出端为图中K(N)点。只是第二晶体管T10接收第二控制信号XCKN，第四晶体管T12的栅极接收第一控制信号CKN。
桥接模块510包括晶体管T18，其栅极耦接上拉控制单元100的输出端(图中Q(N)点)，其源极和漏极分别耦接第一下拉保持模块520的P(N)点和第二下拉保持模块530的K(N)点。
电路重置单元600包括包括重置晶体管T4。重置晶体管T4的栅极接收重置信号，其源极和漏极分别耦接上拉控制单元100的输出端(图中Q(N)点)和直流电源VSS。优选地，在一帧或者多个帧的消隐时间(Blanking Time)提供该重置信号。其中，直流电源VSS可设置为负压源，以根据所述重置信号消除图中Q(N)点的静电积累。
以下结合图5所示的信号时序图详细说明第N级GOA驱动单元的工作原理。在图5的示例中，第一时钟信号CKN和第二时钟信号XCKN为相位互补的两组脉冲信号，时钟信号CKN和XCKN的占空比略小于50％。需要说明的是，针对诸如IGZO(indium gallium zinc oxide)和LTPS等电特性较好的电晶体，可将时钟信号的占空比设计为小于50％。
在时段t1期间，G(N-1)为高电位，T1导通，T1的输出端为高电位，因此存储电容器Cb在G(N-1)的作用下充电达到第一电位，也即将Q(N)的电位抬升至第一电位，同时T2、T8、T11和T18导通。T8导通，使得P(N)点与直流电源VSS连通。T11导通，使得K(N)点与直流电源VSS连通。此外，由于CKN为低电位，且XCKN为高电位，T6和T12截止，T7和T10导通。T7导通，使得P(N)点与直流电源VSS连通。T10导通，使得K(N)点与XCKN高电位连通。由于T18导通，P(N)点和K(N)点中处于低电位的一端将处于高电位的另一端拉低，使得T13、T14、T15和T16截止，防止Q(N)和G(N)漏电。由于T2导通且CKN为低电位，因此，G(N)保持在CKN低电位。
在时段t2期间，G(N-1)为低电位，T1截止。由于Cb的储能作用，T2的栅极保持在高电位，T2保持导通。由于Q(N)保持在高电位，T8、T11和T18保持导通。T8导通， 使得P(N)点与直流电源VSS连通。T11导通，使得K(N)点与直流电源VSS连通。此外，由于CKN为高电位，且XCKN为低电位，T6和T12导通，T7和T10截止。
T6导通，使得P(N)点与CKN高电位连通。T12导通，使得K(N)点与直流电源VSS连通。由于T18导通，P(N)点和K(N)点中处于低电位的一端将处于高电位的另一端拉低，使得T13、T14、T15和T16截止，防止Q(N)和G(N)漏电。
由于T2导通且CKN为高电位，Cb在CKN的作用下再次充电而达到比第一电位更高的第二电位，即将Q(N)的电位抬升至比第一电位更高的第二电位。由于T2导通且CKN为高电位，因此，G(N)上拉至CKN高电位。
在时段t3期间，由于第(N+1)级GOA驱动单元输出的栅极信号G(N+1)为高电位，因此T3导通。由于T3导通，Q(N)点的电位下降至直流电源VSS的电位。由于Q(N)点为低电位，T2、T8、T11和T18保持截止。此外，由于CKN为低电位，且XCKN为高电位，T6和T12截止，T7和T10导通。
T7导通，使得P(N)点与直流电源VSS连通。T10导通，使得K(N)点与XCKN高电位连通。此时，由于T18为截止状态，相当于大电阻关闭状态；而T7和T10导通，其相当于小电阻。T7、T18和T10串联构成三段式电阻分压电路。P(N)点电位为直流电源VSS的低电位，而K(N)点电位为XCKN高电位。即P(N)点和K(N)点相位互补。
由于P(N)点为低电位，T15和T16截止。由于K(N)点为高电位，T13和T14导通，进而使得G(N)和Q(N)点的电位保持在直流电源VSS的低电位。
在时段t4期间，由于前一时段Q(N)点已被下拉至直流电源VSS的低电位，T8、T11和T18保持截止。此外，CKN为高电位，XCKN为低电位，T6和T12导通，T7和T10截止。
T6导通，使得P(N)点与CKN高电位连通。T12导通，使得K(N)点与直流电源VSS连通。此时，由于T18为截止状态，相当于大电阻关闭状态；而T6和T12导通，相当于小电阻。T6、T18和T12串联构成三段式电阻分压电路。K(N)点电位为直流电源VSS的低电位，而P(N)点电位为XCKN高电位。即P(N)点和K(N)点相位互补。
由于K(N)点为低电位，T13和T14截止。由于P(N)点为高电位，T15和T16导通，进而使得G(N)和Q(N)点的电位保持在直流电源VSS的低电位。
此后，只要没有新的第(N-1)级GOA驱动单元的高电位栅极输出信号G(N-1)到来， 第N级GOA驱动单元就会在时段t3和t4的工作状态之间来回切换。
由上述的信号时序分析可以看出，在栅极信号G(N)作用期间，T8和T11对P(N)和K(N)点的电位有较强下拉作用。在栅极信号G(N)非作用期间，第一下拉模块520和第二下拉模块530交替工作，其中，晶体管T6、T18、T12为一组，晶体管T10、T18、T7为一组，两组电路交替作用，分别控制T15、T16和T13、T14的作用时间。保证P(N)和K(N)点交替出现高电位，使得栅极信号输出端G(N)和上拉单元200控制端的电位保持在低电位，提高稳定性。
从而通过采用桥接模块510、第一下拉模块520和第二下拉模块530的三段式分压原理的GOA单元，可以增加下拉保持单元500的使用寿命。
实施例二
图2显示了本实施例的GOA驱动单元的电路结构示意图。该电路是在图1所示的电路基础上对其中的下拉保持单元500做出了进一步改进。具体地，第三晶体管T7的源极接收第一控制信号CKN，第四晶体管T12的源极接收第二控制信号XCKN。将CKN和XCKN信号低电位的绝对值设置为大于直流电源VSS电位的绝对值，这样可利用CKN和XCKN信号的低电位来达到非作用期间更强的低电位下拉能力。
实施例三
图3显示了本实施例的GOA驱动单元的电路结构示意图。该电路是在图1所示的电路基础上对其中的下拉保持单元500做出了进一步改进。具体地，该电路新增了晶体管T5和T9，使得T5和T6构成达第一林顿管，T9和T10构成第二达林顿管。
第一达林顿管的基极短接第一端，以接收第一控制信号CKN，其第二端耦接至第一下拉保持模块的下拉保持控制信号输出端P(N)点。具体来说，晶体管T5的栅极和第一端短接，接收第一控制信号CKN。晶体管T6的栅极耦接T5的第二端，T6的第一端耦接T5的栅极，T6的第二端耦接P(N)点。
第二达林段管的基极短接第一端，以接收第二控制信号XCKN，其第二端耦接至第二下拉保持模块的下拉保持控制信号输出端K(N)点。具体来说，晶体管T9的栅极和第一端短接，接收第二控制信号XCKN。晶体管T10的栅极耦接T9的第二端，T10的第一端 耦接T9的栅极，T10的第二端耦接K(N)点。
由于达林顿管具有增益高、开关速度快、稳定性好等优点，通过引入晶体管T5和T9，可以在非作用期间减少P(N)和K(N)点漏电，保证G(N)和Q(N)电位下拉更顺畅。
实施例四
图4显示了本实施例的GOA驱动单元的电路结构示意图。该电路是图1、图2和图3所示的三种GOA驱动单元的整合，具备三种电路的所有功能和优点。各种驱动单元的功能和优点在上文已详细介绍，在此不再赘述。
实施例五
图6显示了本实施例的GOA驱动单元的电路结构示意图。该图是在图4所示的GOA驱动单元的基础上，将输入两个下拉保持模块520和530的两个控制信号改为低频的时钟信号LC1和LC2，以降低整个下拉保持单元500的功耗。
图7显示了本实施例中GOA驱动单元的时序图。下面以时段t3和时段t4为例详细说明该电路的工作原理。
在时段t3期间，由于第(N+1)级GOA驱动单元输出的栅极信号G(N+1)为高电位，因此T3导通。由于T3导通，Q(N)点的电位下降至直流电源VSS的电位。由于Q(N)点为低电位，T2、T8、T11和T18保持截止。此外，由于LC1为低电位，且LC2为高电位，T5、T6和T12截止，T7、T9和T10导通。
T7导通，使得P(N)点与直流电源VSS连通。T9和T10导通，使得K(N)点与LC2高电位连通。此时，由于T18为截止状态，相当于大电阻关闭状态；而T7导通，T9和T10导通，T7、T9和T10均相当于小电阻。T7、T18、T9和T10串联构成三段式电阻分压电路。
P(N)点电位为时钟信号LC1的低电位，而K(N)点电位为LC2的高电位。即P(N)点和K(N)点相位互补。由于P(N)点为低电位，T15和T16截止。由于K(N)点为高电位，T13和T14导通，进而使得G(N)和Q(N)点的电位保持在直流电源VSS的低电位。
在时段t4期间，由于LC1为低电位，且LC2为高电位，T5、T6和T12截止，T7、T9和T10导通。由于Q(N)点为低电位，T2、T8、T11和T18保持截止。P(N)点电位保持 在时钟信号LC1的低电位，而K(N)点电位保持在LC2的高电位。
从上面的信号时序分析可以看出，从时段t3开始，只有下拉保持模块530持续工作，将G(N)和Q(N)点的电位保持在直流电源VSS的低电位。直到新的第(N+1)级GOA驱动单元的高电位栅极输出信号G(N+1)到来，时钟信号LC1和LC2发生翻转，使得下拉保持模块520开始工作，而下拉保持模块530停止工作。从而使得P(N)和K(N)点的电位在LC1和LC2控制下不断下拉，防止G(N)和Q(N)异常输出。
与实施例二类似，可将LC1和LC2信号低电位的绝对值设置为大于直流电源VSS电位的绝对值，这样可利用LC1和LC2信号的低电位来达到非作用期间更强的低电位下拉能力。由于不必采用时钟信号来控制下拉保持模块的交替，因此，可根据不同的元件和产品配型灵活配置时钟信号的占空比。
需要说明的是，上述实施例中的时序信号配置是针对N型开关元件而言。本领域技术人员容易理解，对于P型开关元件则可将电路节点的高低电位互换，时序保持不变，仍然能够实现上述实施例中的技术方案。
虽然本发明所公开的实施方式如上，但所述的内容只是为了便于理解本发明而采用的实施方式，并非用以限定本发明。任何本发明所属技术领域内的技术人员，在不脱离本发明所公开的精神和范围的前提下，可以在实施的形式上及细节上作任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (20)

  1. 一种栅极驱动电路，包括多级GOA驱动单元，其中每一级GOA驱动单元包括：
    上拉控制单元，其用于输出上拉控制信号；
    上拉单元，其控制端耦接在所述上拉控制单元的输出端，以根据所述上拉控制信号和时钟信号上拉栅极信号输出端的电位，使本级GOA驱动单元输出栅极信号；
    第一下拉单元，其耦接在所述上拉单元的控制端和直流电源之间，以根据下拉控制信号将上拉单元的控制端的电位下拉至所述直流电源的电位，从而关闭上拉单元；
    下拉保持单元，其耦接在所述栅极信号输出端、上拉单元的控制端和直流电源之间，所述下拉保持单元包括桥接模块、第一和第二下拉保持模块；
    其中，当所述桥接模块处于关闭状态时，第一和第二下拉保持模块输出的下拉保持控制信号相位互补，使得第一和第二下拉保持模块交替工作，以根据下拉保持控制信号将所述栅极信号输出端的电位和/或上拉单元的控制端的电位保持在所述直流电源的电位。
  2. 如权利要求1所述的栅极驱动电路，其中，所述桥接模块的控制端耦接在所述上拉控制单元的输出端，所述桥接模块的第一端和第二端分别耦接在第一和第二下拉保持模块的下拉保持控制信号输出端。
  3. 如权利要求1所述的栅极驱动电路，其中，进一步包括：
    升压单元，其第一端和第二端分别耦接所述上拉控制单元的输出端和栅极信号输出端，以根据所述上拉控制信号抬升所述上拉单元控制端的电位；
    电路重置单元，其包括一重置晶体管，其栅极接收重置信号，其第一端和第二端分别耦接所述上拉控制单元的输出端和所述直流电源，以根据所述重置信号消除所述上拉控制单元的输出端的静电积累。
  4. 如权利要求1所述的栅极驱动电路，其中，所述第一和第二下拉保持模块分别包括：
    第一控制子模块，其控制端接收第一控制信号，其输出端耦接至下拉保持控制信号输出端；
    第二控制子模块，其控制端接收第二控制信号，其输出端耦接至下拉保持控制信号输出端；
    第一下拉晶体管，其栅极耦接在所述下拉保持控制信号输出端，其第一端耦接在所述栅极信号输出端，其第二端耦接至所述直流电源；
    第二下拉晶体管，其栅极耦接在所述下拉保持控制信号输出端，其第一端耦接在所述上拉控制单元的输出端，其第二端耦接至所述直流电源；
    其中所述第一控制信号和第二控制信号的相位互补。
  5. 如权利要求4所述的栅极驱动电路，其中，所述第一和第二下拉保持模块进一步包括：
    第三下拉晶体管，其栅极耦接在所述上拉控制单元的输出端，其第一端耦接在所述下拉保持控制信号输出端，其第二端耦接至所述直流电源。
  6. 如权利要求4所述的栅极驱动电路，其中，所述第一下拉保持模块的第一控制子模块包括第一晶体管，其栅极短接第一端，以接收第一控制信号，其第二端耦接至第一下拉保持模块的下拉保持控制信号输出端；
    所述第二下拉保持模块的第一控制子模块包括第二晶体管，其栅极短接第一端，以接收第二控制信号，其第二端耦接至第二下拉保持模块的下拉保持控制信号输出端。
  7. 如权利要求4所述的栅极驱动电路，其中，所述第一下拉保持模块的第一控制子模块包括第一达林顿管，其基极短接第一端，以接收第一控制信号，其第二端耦接至第一下拉保持模块的下拉保持控制信号输出端；
    所述第二下拉保持模块的第一控制子模块包括第二达林顿管，其基极短接第一端，以接收第二控制信号，其第二端耦接至第二下拉保持模块的下拉保持控制信号输出端。
  8. 如权利要求6所述的栅极驱动电路，其中，所述第一下拉保持模块的第二控制子模块包括第三晶体管，其栅极接收第二控制信号，其第一端耦接至所述直流电源，其第二端耦接至第一下拉保持模块的下拉保持控制信号输出端；
    所述第二下拉保持模块的第二控制子模块包括第四晶体管，其栅极接收第一控制信号，其第一端耦接至所述直流电源，其第二端耦接至第二下拉保持模块的下拉保持控制信号输出端。
  9. 如权利要求7所述的栅极驱动电路，其中，所述第一下拉保持模块的第二控制子模块包括第三晶体管，其栅极接收第二控制信号，其第一端耦接至所述直流电源，其第二端耦接至第一下拉保持模块的下拉保持控制信号输出端；
    所述第二下拉保持模块的第二控制子模块包括第四晶体管，其栅极接收第一控制信号，其第一端耦接至所述直流电源，其第二端耦接至第二下拉保持模块的下拉保持控制信号输出端。
  10. 如权利要求6所述的栅极驱动电路，其中，所述第一下拉保持模块的第二控制子模块包括第三晶体管，其栅极接收第二控制信号，其第一端接收第一控制信号，其第二端耦接在第一下拉保持模块的下拉保持控制信号输出端；
    所述第二下拉保持模块的第二控制子模块包括第四晶体管，其栅极接收第一控制信号，其第一端接收第二控制信号，其第二端耦接在第二下拉保持模块的下拉保持控制信号输出端。
  11. 如权利要求7所述的栅极驱动电路，其中，所述第一下拉保持模块的第二控制子模块包括第三晶体管，其栅极接收第二控制信号，其第一端接收第一控制信号，其第二端耦接在第一下拉保持模块的下拉保持控制信号输出端；
    所述第二下拉保持模块的第二控制子模块包括第四晶体管，其栅极接收第一控制信号，其第一端接收第二控制信号，其第二端耦接在第二下拉保持模块的下拉保持控制信号输出端。
  12. 如权利要求4所述的栅极驱动电路，其中，所述第一控制信号为所述时钟信号。
  13. 如权利要求4所述的栅极驱动电路，其中，所述第一控制信号为低频脉冲信号，当下一级GOA驱动单元输出高电位的栅极信号时，所述第一控制信号发生翻转。
  14. 如权利要求1所述的栅极驱动电路，其中，所述上拉控制单元包括一上拉控制晶体管，其栅极短接第一端，以接收上一级GOA驱动单元输出的栅极信号，其第二端输出所述上拉控制信号。
  15. 如权利要求2所述的栅极驱动电路，其中，所述第一下拉单元包括一下拉晶体管，其栅极接收所述下拉控制信号，其第一端和第二端分别耦接所述上拉控制单元的输出端和所述直流电源，所述下拉控制信号为下一级GOA驱动单元输出的栅极信号。
  16. 如权利要求3所述的栅极驱动电路，其中，所述第一下拉单元包括一下拉晶体管，其栅极接收所述下拉控制信号，其第一端和第二端分别耦接所述上拉控制单元的输出端和所述直流电源，所述下拉控制信号为下一级GOA驱动单元输出的栅极信号。
  17. 如权利要求4所述的栅极驱动电路，其中，所述第一下拉单元包括一下拉晶体管， 其栅极接收所述下拉控制信号，其第一端和第二端分别耦接所述上拉控制单元的输出端和所述直流电源，所述下拉控制信号为下一级GOA驱动单元输出的栅极信号。
  18. 如权利要求5所述的栅极驱动电路，其中，所述第一下拉单元包括一下拉晶体管，其栅极接收所述下拉控制信号，其第一端和第二端分别耦接所述上拉控制单元的输出端和所述直流电源，所述下拉控制信号为下一级GOA驱动单元输出的栅极信号。
  19. 如权利要求12所述的栅极驱动电路，其中，所述第一下拉单元包括一下拉晶体管，其栅极接收所述下拉控制信号，其第一端和第二端分别耦接所述上拉控制单元的输出端和所述直流电源，所述下拉控制信号为下一级GOA驱动单元输出的栅极信号。
  20. 如权利要求13所述的栅极驱动电路，其中，所述第一下拉单元包括一下拉晶体管，其栅极接收所述下拉控制信号，其第一端和第二端分别耦接所述上拉控制单元的输出端和所述直流电源，所述下拉控制信号为下一级GOA驱动单元输出的栅极信号。
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