WO2017190521A1 - 栅极驱动电路、阵列基板、显示面板及其驱动方法 - Google Patents

栅极驱动电路、阵列基板、显示面板及其驱动方法 Download PDF

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Publication number
WO2017190521A1
WO2017190521A1 PCT/CN2017/000022 CN2017000022W WO2017190521A1 WO 2017190521 A1 WO2017190521 A1 WO 2017190521A1 CN 2017000022 W CN2017000022 W CN 2017000022W WO 2017190521 A1 WO2017190521 A1 WO 2017190521A1
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Prior art keywords
clock
terminal
clock signal
signal
gate
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PCT/CN2017/000022
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English (en)
French (fr)
Inventor
陈华斌
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京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Priority to US15/541,696 priority Critical patent/US10255861B2/en
Publication of WO2017190521A1 publication Critical patent/WO2017190521A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0205—Simultaneous scanning of several lines in flat panels
    • G09G2310/021—Double addressing, i.e. scanning two or more lines, e.g. lines 2 and 3; 4 and 5, at a time in a first field, followed by scanning two or more lines in another combination, e.g. lines 1 and 2; 3 and 4, in a second field
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a gate driving circuit, an array substrate, a display panel, and a driving method thereof.
  • the display device includes an array substrate on which a pixel array is formed, a gate driving circuit, and a data driving circuit.
  • the gate driving circuit sequentially turns on each pixel row in the pixel array to input the data voltage output by the data driving circuit to the corresponding pixel.
  • the gate drive circuit is formed on an array substrate and is referred to as a "gate driver on array (GOA)."
  • a gate drive circuit having a dual scan capability has been widely used. In the forward scan mode, the gate drive circuit sequentially turns on each pixel row from top to bottom. In the reverse scan mode, the gate drive circuit sequentially turns on each pixel row from bottom to top. Typically, additional signal lines are required to achieve dual scanning.
  • a gate driving circuit comprising: n stages arranged in sequence, wherein n is an integer greater than or equal to 4, wherein the n stages are divided into a first level group of the 4k+1th order of the n stages, a second level group including the 4k+2th stage of the n stages, including the 4k+3 of the n stages a third level group of ranks and a fourth level group including 4th (k+1)th of the n levels, where k is an integer greater than or equal to 0, wherein the first level group, the second level The level group, the third level group, and the fourth level group are configured to receive respective different combinations of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal, wherein the level of the first level group
  • the stages of the tertiary group are cascaded with each other, and the levels of the second level group and the levels of the fourth level group are cascaded with each other, and wherein the first two of the n levels are
  • the gate driving circuit further includes: a first clock line transmitting the first clock signal, a second clock line transmitting the second clock signal, and a third transmitting the third clock signal a third clock line, and a fourth clock line transmitting the fourth clock signal, wherein each of the n stages includes a first clock terminal, a second clock terminal, a third clock terminal, and a fourth clock terminal, wherein the first clock line is connected to a third clock terminal of each stage of the first level group, a second clock terminal of each stage of the second level group, and each of the third level groups a first clock terminal of each stage, and a fourth clock terminal of each of the fourth level groups; wherein the second clock line is connected to a fourth clock terminal of each stage of the first stage group a third clock terminal of each of the second level groups, a second clock terminal of each of the third level groups, and a first clock terminal of each of the fourth level groups; Wherein the third clock line is connected to the first clock of each stage of the first level group a terminal, a fourth clock line transmitting
  • the gate driving circuit further includes: a first scan start signal line that transmits the first scan start signal and a second scan start signal line that transmits the second scan start signal, where
  • Each of the n stages further includes an input terminal, an output terminal, a reset terminal, and a gate-off voltage terminal configured to receive a gate-off voltage, wherein an output terminal of each stage of the first-stage group is connected to Input terminals of respective next stages of the third level group, and output terminals of each stage of the third level group are connected to reset terminals of respective previous stages of the first level group and corresponding next stages of the first level group Input terminals, wherein output terminals of each of the second level groups are connected to input terminals of respective next stages of the fourth level group, and output terminals of each of the fourth level groups are connected to the second level group Corresponding to the reset terminal of the previous stage and the input terminal of the corresponding next stage of the second stage group, and wherein the input terminals of the first two of the n stages are connected to the first scan start signal line
  • each of the n stages comprises: a first node; a buffer, Operable for selectively supplying a signal applied to the second clock terminal or a signal applied to the fourth clock terminal to a signal based on a signal applied to the input terminal and a signal applied to the reset terminal a first node; a charging portion operable to perform charging based on a signal supplied to the first node by the buffer portion; a pull-up portion operable to select based on a voltage at the first node Supplying a signal applied to the third clock terminal to the output terminal; a pull-down portion operable to selectively select based on a signal applied to the input terminal and a signal applied to the reset terminal a signal applied to the gate-off voltage terminal is supplied to the output terminal; and a holding portion operable to maintain a signal applied to the gate-off voltage terminal based on a signal applied to the first clock terminal Supply to the output terminal.
  • the buffer portion includes a first transistor and a second transistor, wherein the first transistor includes a gate electrode connected to the input terminal, a first electrode connected to the first node, and a connection To a second electrode of the second clock terminal, and the second transistor includes a gate electrode connected to the reset terminal, a first electrode connected to the fourth clock terminal, and connected to the first node The second electrode.
  • the charging portion includes a first capacitor, wherein the first capacitor includes a first terminal connected to the first node and a second terminal connected to the output terminal.
  • the pull up portion includes a third transistor, wherein the third transistor includes a gate electrode connected to the first node, a first electrode connected to the output terminal, and connected to the a second electrode of the third clock terminal.
  • the pull-down portion includes a fourth transistor and a seventh transistor, wherein the fourth transistor includes a gate electrode connected to the reset terminal, a first electrode connected to the gate-off voltage terminal, And a second electrode connected to the output terminal, and the seventh transistor includes a gate electrode connected to the input terminal, a first electrode connected to the gate-off voltage terminal, and a connection to the output terminal The second electrode.
  • each of the n stages further includes a second node and a third node
  • the holding portion includes a fifth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor
  • the fifth transistor includes a gate electrode connected to the second node, a first electrode connected to the third node, and a second electrode connected to the first clock terminal
  • the ninth transistor including a gate electrode connected to the first clock terminal, a first electrode connected to the second node, and a first clock terminal connected a second electrode
  • the tenth transistor comprising a gate electrode connected to the third node, a first electrode connected to the gate-off voltage terminal, and a second electrode connected to the first node
  • the eleventh transistor includes a gate electrode connected to the third node, a first electrode connected to the gate-off voltage terminal, and a second electrode connected to the output terminal.
  • the buffer portion further includes a sixth transistor and an eighth transistor, wherein the sixth transistor includes a gate electrode connected to the first node, and a first connection to the gate-off voltage terminal An electrode, and a second electrode connected to the third node, and the eighth transistor includes a gate electrode connected to the first node, a first electrode connected to the gate-off voltage terminal, and a connection to a second electrode of the second node.
  • the gate drive circuit is configured to operate in a forward scan mode in response to application of the first scan start signal to an input terminal of a first two of the n stages.
  • each of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal is a pulse signal that is periodically repeated in a period of 2H, wherein H is a horizontal scanning period
  • the first clock signal and the third clock signal have a phase difference of 180°
  • the second clock signal and the fourth clock signal have a phase difference of 180°
  • the first clock signal leads the phase in the phase
  • the fourth clock signal is 90°.
  • the first scan start signal is a pulse signal having a pulse width of 1.5H or 1H, and a rising edge of the first scan start signal is synchronized with a rising edge of the third clock signal.
  • the gate drive circuit is configured to operate in a reverse scan mode in response to application of the second scan start signal to a reset terminal of a last two of the n stages.
  • each of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal is a pulse signal that is periodically repeated in a period of 2H, wherein H is a horizontal scanning period
  • the first clock signal and the third clock signal have a phase difference of 180°
  • the second clock signal and the fourth clock signal have a phase difference of 180°
  • the fourth clock signal is 90°.
  • the second scan start signal is a pulse signal having a pulse width of 1.5H or 1H, and a rising edge of the second scan start signal is synchronized with a rising edge of the second clock signal.
  • an array substrate comprising: a display region including a plurality of gate lines and a plurality of data lines intersecting the plurality of gate lines; and a gate as described above a pole drive circuit, wherein the gate drive circuit is formed in a peripheral region of the array substrate other than the display region, and is configured to supply a gate signal to the plurality of gate lines.
  • a display panel comprising the array substrate as described above.
  • a method of driving a display panel as described above comprising: supplying a first clock signal, a second clock signal, a third clock signal, to the gate driving circuit, a fourth clock signal and a first scan start signal, driving the display panel to operate in a forward scan mode, wherein the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal
  • Each of the pulse signals is periodically repeated in a period of 2H, H is a horizontal scanning period
  • the first clock signal and the third clock signal have a phase difference of 180°
  • the second clock signal and the fourth clock signal Having a phase difference of 180°
  • the first scan start signal being a pulse signal having a pulse width of 1.5H or 1H
  • the a rising edge of a scan start signal is synchronized with a rising edge of the third clock signal
  • a first clock signal, a second clock signal, and a third clock signal are supplied to the gate drive circuit
  • FIG. 1 is a plan view schematically showing a display panel according to an embodiment of the present invention.
  • FIG. 2 is a block diagram schematically showing a gate driving circuit according to an embodiment of the present invention.
  • FIG. 3 is a circuit diagram schematically showing one stage of the gate driving circuit shown in FIG. 2;
  • FIG. 4A and 4B are timing charts schematically showing driving methods of the gate driving circuit shown in FIG. 2 in the forward scanning mode and the reverse scanning mode, respectively;
  • 5A, 5B, 5C, and 5D are timings schematically showing operations of the first stage, the second stage, the third stage, and the fourth stage of the gate driving circuit shown in FIG. 2 in the forward scanning mode, respectively.
  • 6A and 6B are timing charts schematically showing operations of the eighth stage and the seventh stage of the gate driving circuit shown in Fig. 2 in the reverse scanning mode, respectively.
  • FIG. 1 is a plan view schematically showing a display panel 100 according to an embodiment of the present invention.
  • the display panel 100 includes an array substrate 110, a data driving circuit(s) 120 for outputting a data voltage, and a gate driving circuit 200 for outputting a gate signal.
  • the array substrate 110 includes a display area DA on which an image is displayed and a peripheral area PA other than the display area DA.
  • the pixel P1 includes a thin film transistor Tr.
  • the thin film transistor Tr includes a gate electrode connected to the gate line GL1 and a first electrode connected to the data line DL1.
  • the second electrode of the thin film transistor Tr is connected to the pixel electrode.
  • the display panel 100 is an organic light emitting diode
  • the second electrode of the thin film transistor Tr is connected to, for example, a gate electrode of a driving transistor for supplying a driving current to the OLED.
  • the gate driving circuit 200 is disposed in the peripheral area PA and is connected to the gate lines GL1-GLn to sequentially output gate signals to the gate lines GL1-GLn.
  • the gate driving circuit 200 may be formed simultaneously with the thin film transistor Tr, thereby obtaining a GOA circuit.
  • the gate driving circuit 200 may be formed as a separate integrated circuit (IC) chip and mounted directly on the display panel 100 or mounted on a separate printed circuit board (not shown). on.
  • a plurality of data driving circuits 120 are disposed in the peripheral area PA and connected to the data lines DL1-DLm to output data voltages to the data lines DL1-DLm.
  • FIG. 2 is a block diagram schematically showing a gate driving circuit 200 in accordance with one embodiment of the present invention.
  • the gate driving circuit 100 includes n stages ST1, ST2, ... STn-1, STn which are sequentially arranged, where n is an integer greater than or equal to 4. These n stages ST1, ST2, ... STn-1, STn form a shift register.
  • Each of the n stages ST1, ST2, ... STn-1, STn has a first clock terminal CLKB, a second clock terminal CLKB', a third clock terminal CLK, a fourth clock terminal CLK', a gate
  • the output terminals OUTPUT of the n stages ST1, ST2, ... STn-1, STn are connected to corresponding gate lines GL1, GL2, ... GLn-1, GLn, and output Corresponding gate signal.
  • These gate signals have a high level as a gate-on voltage and a low level as a gate-off voltage.
  • the gate turn-off voltage may be supplied via the gate-off voltage terminal VSS.
  • the n stages ST1, ST2, ... STn-1, STn are divided into a first level group SG1, a second level group SG2, a third level group SG3, and a fourth level group SG4.
  • the first level group SG1 includes the 4k+1th of the n stages
  • the second level group SG2 includes the 4k+2th of the n levels
  • the third level group SG3 includes the n
  • the fourth level group SG4 includes the 4th (k+1)th order of the n stages, where k is an integer greater than or equal to 0.
  • the rightmost reference numerals "SG1", “SG2”, “SG3”, and “SG4" indicate the level groups to which the respective stages ST1, ST2, ... STn-1, STn belong.
  • the second level ST2 belongs to the second level group SG2
  • the third level ST3 belongs to the third level group SG3
  • the fourth level ST4 belongs to the fourth level group SG4
  • the fifth level ST5 (not shown) belongs to The first level group SG1, and so on.
  • the first level group SG1, the second level group SG2, the third level group SG3, and the fourth level group SG4 are configured to pass their respective first clock terminal CLKB, second clock terminal CLKB', third clock terminal CLK, and
  • the four clock terminal CLK' receives different combinations of the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, and the fourth clock signal CLK4.
  • each stage of the first level group SG1 is configured to receive a first combination of the four clock signals
  • each stage of the second level group SG2 being configured to receive a second combination of the four clock signals
  • Each stage of the tertiary group SG3 is configured to receive a third combination of the four clock signals
  • each stage of the fourth level group SG4 is configured to receive a fourth combination of the four clock signals.
  • the first clock line transmitting the first clock signal CLK1 is connected to the third clock terminal CLK of each stage of the first stage group SG1, and the second clock of each stage of the second stage group SG2
  • the second clock line transmitting the second clock signal CLK2 is connected to the fourth clock terminal CLK' of each stage of the first stage group SG1, the third clock terminal CLK of each stage of the second stage group SG2, and the third level group
  • the third clock line transmitting the third clock signal CLK3 is connected to the first clock terminal CLKB of each stage of the first stage group SG1, the fourth clock terminal CLK' of each stage of the second stage group SG2, and the third level group
  • the fourth clock line transmitting the fourth clock signal CLK4 is connected to the second clock terminal CLKB' of each stage of the first stage group SG1, the first clock terminal CLKB of each stage of the second stage group SG2, and the third level group
  • the level of the first level group SG1 and the level of the third level group SG3 are cascaded with each other, and the second level group The stages of SG2 and the stages of the fourth level group SG4 are cascaded with each other.
  • the output terminal OUTPUT of each stage of the first stage group SG1 is connected to the input terminal INPUT of the corresponding next stage of the third stage group SG3, and the output terminal of each stage of the third stage group SG3
  • the OUTPUT is connected to the reset terminal RESET of the corresponding previous stage of the first stage group SG1 and the input terminal INPUT of the corresponding next stage of the first stage group SG1.
  • the output terminal OUTPUT of each stage of the second stage group SG2 is connected to the input terminal INPUT of the corresponding next stage of the fourth stage group SG4, and the output terminal OUTPUT of each stage of the fourth stage group SG4 is connected to the second level group
  • first two stages ST1 and ST2 of the n stages ST1, ST2, ... STn-1, STn are configured to receive the first scan start signal STV_F
  • n stages ST1, ST2 The last two stages STn-1 and STn in STn-1, STn are configured to receive the second scan start signal STV_R.
  • an input terminal INPUT of the first two stages ST1 and ST2 of the n stages ST1, ST2, ... STn-1, STn is connected to a first scan start signal line that transmits the first scan start signal STV_F
  • the reset terminal RESET of the last two stages STn-1 and STn of the n stages ST1, ST2, ... STn-1, STn is connected to the second scan start signal line transmitting the second scan start signal STV_R .
  • the gate driving circuit 200 operates in the forward scanning mode in response to the first scanning start signal STV_F, and operates in the reverse scanning mode in response to the second scanning start signal STV_R.
  • the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, and the fourth clock signal CLK4 have a first timing pattern.
  • the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, and the fourth clock signal CLK4 have a second timing pattern.
  • the second timing pattern is different from the first timing pattern.
  • the switching between the forward scan and the reverse scan can be realized by utilizing one of the two scan start signals and by changing the timing of the clock signal without requiring an additional signal line. This facilitates simplification of the circuit and thus a reduction in circuit footprint.
  • FIG. 3 is a circuit diagram schematically showing one stage STx of the gate driving circuit 200 shown in FIG. 2.
  • Each of the stages in the gate driving circuit 200 has the same structure, and therefore, the stage STx shown in Fig. 3 represents each of the n stages ST1, ST2, ... STn-1, STn.
  • the stage STx includes a first node PU, a buffer unit 310, a charging unit 320, The pull-up portion 330, the pull-down portion 340, and the holding portion 350.
  • the buffer portion 310 is operable to selectively supply a signal applied to the second clock terminal CLKB' or a signal applied to the fourth clock terminal CLK' based on a signal applied to the input terminal INPUT and a signal applied to the reset terminal RESET Go to the first node PU.
  • buffer relates to the operation of charging a first node PU, as will be described later.
  • the buffer portion 310 includes a first transistor M1 and a second transistor M2.
  • the first transistor M includes a gate electrode connected to the input terminal INPUT, a first electrode connected to the first node PU, and a second electrode connected to the second clock terminal CLKB'.
  • the second transistor M2 includes a gate electrode connected to the reset terminal RESET, a first electrode connected to the fourth clock terminal CLK', and a second electrode connected to the first node PU.
  • the buffer portion 310 further includes a sixth transistor M6 and an eighth transistor M8.
  • the sixth transistor M6 includes a gate electrode connected to the first node PU, a first electrode connected to the gate-off voltage terminal VSS, and a second electrode connected to the third node PD.
  • the eighth transistor M8 includes a gate electrode connected to the first node PU, a first electrode connected to the gate-off voltage terminal VSS, and a second electrode connected to the second node PD_CN.
  • the charging section 320 is operable to perform charging based on a signal supplied to the first node PU by the buffer section 310.
  • the charging section 320 includes a first capacitor C1.
  • the first capacitor C1 includes a first terminal connected to the first node PU and a second terminal connected to the output terminal OUTPUT.
  • the pull up portion 330 is operable to selectively supply a signal applied to the third clock terminal CLK to the output terminal OUTPUT based on a voltage at the first node PU.
  • the pull-up portion 330 includes a third transistor M3.
  • the third transistor M3 includes a gate electrode connected to the first node PU, a first electrode connected to the output terminal OUTPUT, and a second electrode connected to the third clock terminal CLK.
  • the pull-down portion 340 is operable to selectively supply a signal applied to the gate-off voltage terminal VSS to the output terminal OUTPUT based on a signal applied to the input terminal INPUT and a signal applied to the reset terminal RESET.
  • the pull-down portion 340 includes a fourth transistor M4 and a seventh transistor M7.
  • the fourth transistor M4 includes a gate electrode connected to the reset terminal RESET, a first electrode connected to the gate-off voltage terminal VSS, and a second electrode connected to the output terminal OUTPUT.
  • the seventh transistor M7 includes a gate electrode connected to the input terminal INPUT, a first electrode connected to the gate-off voltage terminal VSS, and a second electrode connected to the output terminal OUTPUT.
  • the holding portion 350 is operable to maintain a supply of a signal applied to the gate-off voltage terminal VSS to a supply of the output terminal OUTPUT based on a signal applied to the first clock terminal CLKB.
  • stage STx further includes a second node PD_CN and a third node PD.
  • the fifth transistor M5 includes a gate electrode connected to the second node PD_CN, a first electrode connected to the third node PD, and a second electrode connected to the first clock terminal CLKB.
  • the ninth transistor M9 includes a gate electrode connected to the first clock terminal CLKB, a first electrode connected to the second node PD_CN, and a second electrode connected to the first clock terminal CLKB.
  • the tenth transistor M10 includes a gate electrode connected to the third node PD, a first electrode connected to the gate-off voltage terminal VSS, and a second electrode connected to the first node PU.
  • the eleventh transistor M11 includes a gate electrode connected to the third node PD, a first electrode connected to the gate-off voltage terminal VSS, and a second electrode connected to the output terminal OUTPUT.
  • the various transistors are shown as n-type transistors in FIG. 3, in other embodiments, p-type transistors may be used.
  • the voltage for turning on the transistor is a low level voltage
  • the voltage for turning off the transistor is a high level voltage.
  • each transistor is formed as a thin film transistor.
  • the source electrode and the drain electrode are used interchangeably.
  • FIG. 4A and 4B are timing charts schematically showing driving methods of the gate driving circuit 200 shown in FIG. 2 in the forward scanning mode and the reverse scanning mode, respectively.
  • the gate driving circuit 200 is configured to be responsive to the first scan start signal STV_F to the input terminal INPUT of the first two of the eight stages (ST1 and ST2)
  • the application works in the forward scan mode.
  • the gate signals are sequentially output to the gate lines GL1, GL2, ..., GL8 as shown in Fig. 4A.
  • each of the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, and the fourth clock signal CLK4 is a pulse signal that is periodically repeated in a period of 2H, where H is a horizontal scanning period,
  • the gate signal is at a high level as a gate-on voltage during the horizontal scanning period.
  • the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, and the fourth clock signal CLK4 have a first timing pattern.
  • the first clock signal CLK1 and the third clock signal CLK3 have a phase difference of 180°
  • the second clock signal CLK2 and the fourth clock signal CLK4 have a phase difference of 180°
  • the first clock signal CLK1 leads in phase.
  • Four clock signals CLK4 90°.
  • the first scan start signal STV_F is a pulse signal having a pulse width of 1.5H
  • the rising edge of the first scan start signal STV_F is synchronized with the rising edge of the third clock signal CLK3.
  • the gate driving circuit 200 is configured to operate in the reverse scan mode in response to the application of the second scan start signal STV_R to the reset terminals of the last two of the eight stages (ST8 and ST7).
  • the gate signals are sequentially output to the gate lines GL8, GL7, ..., GL1 as shown in Fig. 4B.
  • the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, and the fourth clock signal CLK4 have a second timing pattern.
  • the second timing pattern is different from the first timing pattern.
  • the first clock signal CLK1 and the third clock signal CLK3 have a phase difference of 180°
  • the second clock signal CLK2 and the fourth clock signal CLK4 have a phase difference of 180°
  • the first clock signal CLK1 is behind in phase.
  • the fourth clock signal CLK4 is 90°.
  • the second scan start signal STV_R is a pulse signal having a pulse width of 1.5H
  • the rising edge of the second scan start signal STV_R is synchronized with the rising edge of the second clock signal CLK2.
  • FIGS. 2, 3, 5A, 5B, 5C, and 5D The operation of the gate driving circuit 200 according to an embodiment of the present invention will be described below with reference to FIGS. 2, 3, 5A, 5B, 5C, and 5D and FIGS. 6A and 6B.
  • 5A, 5B, 5C, and 5D are schematic diagrams showing the first stage ST1, the second stage ST2, the third stage ST3, and the fourth stage ST4 of the gate driving circuit 200 shown in FIG. 2 in the forward scanning mode, respectively. Timing diagram of the operation below. Each level of operation includes five phases P1, P2, P3, P4, and P5.
  • the high level of the first scan start signal STV_F is applied to the input terminal INPUT such that the first transistor M1 is turned on to supply the fourth clock signal CLK4 to the first node PU via the second clock terminal CLKB' .
  • the high level of the fourth clock signal CLK4 charges the first capacitor C1 such that the sixth transistor M6 and the eighth transistor M8 are turned on to turn off the gate-off voltage via the gate-off voltage terminal VSS. It is supplied to the second node PD_CN and the third node PD, and the third transistor M3 is turned on to prepare to output a high level to the gate line GL1 via the output terminal OUTPUT.
  • the high level of the first clock signal CLK1 is applied to the third clock terminal CLK, and the voltage across the first capacitor C1 maintains the third transistor M3 in an on state, so that the first clock signal CLK1 is at the high level. It is supplied to the output terminal OUTPUT via the third transistor M3, and is output to the gate line GL1.
  • the high level (GL3) output from the third stage ST3 is applied to the reset terminal RESET of the first stage ST1, so that the fourth transistor M4 is turned on to supply the gate-off voltage via the gate-off voltage terminal VSS.
  • the output terminal OUTPUT is pulled to lower the gate signal output to the gate line GL1 to a low level.
  • the second transistor M2 is turned on to supply the second clock signal CLK2 to the first node PU via the fourth clock terminal CLK'.
  • the low level of the second clock signal CLK2 is supplied to the first node PU to discharge the first capacitor C1.
  • each transistor is in a closed state such that the output terminal OUTPUT is suspended at a low level.
  • the gate signal output to the gate line GL1 is at a low level.
  • the high level of the third clock signal CLK3 is applied to the first clock terminal CLKB, so that the ninth transistor M9 and the fifth transistor M5 are turned on to supply the high level of the third clock signal CLK3 to the first Two nodes PD_CN and a third node PD. Since the third node PD is at the high level, the tenth transistor M10 is turned on to discharge the first capacitor C1, and the eleventh transistor M11 is turned on to keep the gate signal output to the gate line GL1 via the output terminal OUTPUT at Low level.
  • the high level of the first scan start signal STV_F is applied to the input terminal INPUT such that the first transistor M1 is turned on to supply the first clock signal CLK1 to the first node PU via the second clock terminal CLKB' .
  • the high level of the first clock signal CLK1 charges the first capacitor C1 to make the sixth transistor M6 and the eighth transistor M8 are turned on to supply the gate-off voltage to the second node PD_CN and the third node PD via the gate-off voltage terminal VSS, and the third transistor M3 is turned on to prepare to the gate line via the output terminal OUTPUT GL2 outputs a high level.
  • the high level of the second clock signal CLK2 is applied to the third clock terminal CLK, and the voltage across the first capacitor C1 maintains the third transistor M3 in an on state, so that the second clock signal CLK2 is at the high level. It is supplied to the output terminal OUTPUT via the third transistor M3, and is output to the gate line GL2.
  • the high level (GL4) output from the fourth stage ST4 is applied to the reset terminal RESET of the second stage ST2, so that the fourth transistor M4 is turned on to supply the gate-off voltage via the gate-off voltage terminal VSS.
  • the output terminal OUTPUT is pulled to lower the gate signal output to the gate line GL2 to a low level.
  • the second transistor M2 is turned on to supply the third clock signal CLK3 to the first node PU via the fourth clock terminal CLK'.
  • the low level of the third clock signal CLK3 is supplied to the first node PU to discharge the first capacitor C1.
  • each transistor is in a closed state such that the output terminal OUTPUT is suspended at a low level.
  • the gate signal output to the gate line GL2 is at a low level.
  • the high level of the fourth clock signal CLK4 is applied to the first clock terminal CLKB, so that the ninth transistor M9 and the fifth transistor M5 are turned on to supply the high level of the fourth clock signal CLK4 to the first Two nodes PD_CN and a third node PD. Since the third node PD is at the high level, the tenth transistor M10 is turned on to discharge the first capacitor C1, and the eleventh transistor M11 is turned on to keep the gate signal output to the gate line GL2 via the output terminal OUTPUT at Low level.
  • the high level of the output of the first stage ST1 is applied to the input terminal INPUT, so that the first transistor M1 is turned on to supply the second clock signal CLK2 to the first node PU via the second clock terminal CLKB'.
  • the high level of the second clock signal CLK2 charges the first capacitor C1 such that the sixth transistor M6 and the eighth transistor M8 are turned on to turn off the gate-off voltage via the gate-off voltage terminal VSS. It is supplied to the second node PD_CN and the third node PD, and the third transistor M3 is turned on to prepare to output a high level to the gate line GL3 via the output terminal OUTPUT.
  • the high level of the third clock signal CLK3 is applied to the third clock terminal CLK, and the voltage across the first capacitor C1 maintains the third transistor M3 in an open state,
  • the high level of the third clock signal CLK3 is supplied to the output terminal OUTPUT via the third transistor M3, and is output to the gate line GL3.
  • the high level (GL5) output from the fifth stage ST5 is applied to the reset terminal RESET of the third stage ST3, so that the fourth transistor M4 is turned on to supply the gate-off voltage via the gate-off voltage terminal VSS.
  • the output terminal OUTPUT is pulled to lower the gate signal output to the gate line GL3 to a low level.
  • the second transistor M2 is turned on to supply the fourth clock signal CLK4 to the first node PU via the fourth clock terminal CLK'.
  • the low level of the fourth clock signal CLK4 is supplied to the first node PU to discharge the first capacitor C1.
  • each transistor is in a closed state such that the output terminal OUTPUT is suspended at a low level.
  • the gate signal output to the gate line GL3 is at a low level.
  • the high level of the first clock signal CLK1 is applied to the first clock terminal CLKB, so that the ninth transistor M9 and the fifth transistor M5 are turned on to supply the high level of the first clock signal CLK1 to the first Two nodes PD_CN and a third node PD. Since the third node PD is at the high level, the tenth transistor M10 is turned on to discharge the first capacitor C1, and the eleventh transistor M11 is turned on to keep the gate signal output to the gate line GL3 via the output terminal OUTPUT at Low level.
  • the high level of the output of the second stage ST2 is applied to the input terminal INPUT, so that the first transistor M1 is turned on to supply the third clock signal CLK3 to the first node PU via the second clock terminal CLKB'.
  • the high level of the third clock signal CLK3 charges the first capacitor C1 such that the sixth transistor M6 and the eighth transistor M8 are turned on to turn off the gate-off voltage via the gate-off voltage terminal VSS. It is supplied to the second node PD_CN and the third node PD, and the third transistor M3 is turned on to prepare to output a high level to the gate line GL4 via the output terminal OUTPUT.
  • the high level of the fourth clock signal CLK4 is applied to the third clock terminal CLK, and the voltage across the first capacitor C1 maintains the third transistor M3 in an on state, so that the fourth clock signal CLK4 is at the high level. It is supplied to the output terminal OUTPUT via the third transistor M3, and is output to the gate line GL4.
  • the high level (GL6) outputted by the sixth stage ST6 is applied to the reset terminal RESET of the fourth stage ST4, so that the fourth transistor M4 is turned on to supply the gate-off voltage via the gate-off voltage terminal VSS.
  • the output terminal OUTPUT which will output to The gate signal of the gate line GL4 is pulled low to a low level.
  • the second transistor M2 is turned on to supply the first clock signal CLK1 to the first node PU via the fourth clock terminal CLK'.
  • the low level of the first clock signal CLK1 is supplied to the first node PU to discharge the first capacitor C1.
  • each transistor is in a closed state such that the output terminal OUTPUT is suspended at a low level.
  • the gate signal output to the gate line GL4 is at a low level.
  • the high level of the second clock signal CLK2 is applied to the first clock terminal CLKB, so that the ninth transistor M9 and the fifth transistor M5 are turned on to supply the high level of the second clock signal CLK2 to the first Two nodes PD_CN and a third node PD. Since the third node PD is at a high level, the tenth transistor M10 is turned on to discharge the first capacitor C1, and the eleventh transistor M11 is turned on to keep the gate signal output to the gate line GL4 via the output terminal OUTPUT at Low level.
  • first scan start signal STV_F is described as having a pulse width of 1.5H in the above embodiment, in other embodiments, the first scan start signal STV_F may have a pulse width of 1H.
  • Each level of operation includes five phases P1, P2, P3, P4, and P5.
  • the high level of STV_R is applied to the reset terminal RESET, so that the second transistor M2 is turned on to supply the first clock signal CLK1 to the first node PU via the fourth clock terminal CLK'.
  • the high level of the first clock signal CLK1 charges the first capacitor C1 such that the sixth transistor M6 and the eighth transistor M8 are turned on to turn off the gate-off voltage via the gate-off voltage terminal VSS. It is supplied to the second node PD_CN and the third node PD, and the third transistor M3 is turned on in preparation for outputting a high level to the gate line GL8 via the output terminal OUTPUT.
  • the high level of the fourth clock signal CLK4 is applied to the third clock terminal CLK, and the voltage across the first capacitor C1 maintains the third transistor M3 in an on state, so that the fourth clock signal CLK4 is at the high level. It is supplied to the output terminal OUTPUT via the third transistor M3, and is output to the gate line GL8.
  • the high level (GL6) outputted by the sixth stage ST6 is applied to the eighth stage ST8.
  • Input terminal INPUT such that the seventh transistor M7 is turned on to supply a gate-off voltage to the output terminal OUTPUT via the gate-off voltage terminal VSS, thereby pulling the gate signal output to the gate line GL8 to a low level .
  • the first transistor M1 is turned on to supply the third clock signal CLK3 to the first node PU via the second clock terminal CLKB'.
  • the low level of the third clock signal CLK3 is supplied to the first node PU to discharge the first capacitor C1.
  • each transistor is in a closed state such that the output terminal OUTPUT is suspended at a low level.
  • the gate signal output to the gate line GL8 is at a low level.
  • the high level of the second clock signal CLK2 is applied to the first clock terminal CLKB, so that the ninth transistor M9 and the fifth transistor M5 are turned on to supply the high level of the second clock signal CLK2 to the first Two nodes PD_CN and a third node PD. Since the third node PD is at a high level, the tenth transistor M10 is turned on to discharge the first capacitor C1, and the eleventh transistor M11 is turned on to keep the gate signal output to the gate line GL8 via the output terminal OUTPUT at Low level.
  • the high level of STV_R is applied to the reset terminal RESET, so that the second transistor M2 is turned on to supply the fourth clock signal CLK4 to the first node PU via the fourth clock terminal CLK'.
  • the high level of the fourth clock signal CLK4 charges the first capacitor C1 such that the sixth transistor M6 and the eighth transistor M8 are turned on to turn off the gate-off voltage via the gate-off voltage terminal VSS.
  • the second node PD_CN and the third node PD are supplied, and the third transistor M3 is turned on to prepare to output a high level to the gate line GL7 via the output terminal OUTPUT.
  • the high level of the third clock signal CLK3 is applied to the third clock terminal CLK, and the voltage across the first capacitor C1 maintains the third transistor M3 in an on state, so that the third clock signal CLK3 is at the high level. It is supplied to the output terminal OUTPUT via the third transistor M3, and is output to the gate line GL7.
  • the high level (GL5) output from the fifth stage ST5 is applied to the input terminal INPUT of the seventh stage ST7, so that the seventh transistor M7 is turned on to supply the gate-off voltage via the gate-off voltage terminal VSS.
  • the output terminal OUTPUT is pulled to lower the gate signal output to the gate line GL7 to a low level.
  • the first transistor M1 is turned on to supply the second clock signal CLK2 to the first node PU via the second clock terminal CLKB'.
  • the low level of the second clock signal CLK2 is supplied to the first section
  • the PU is turned on to discharge the first capacitor C1.
  • each transistor is in a closed state such that the output terminal OUTPUT is suspended at a low level.
  • the gate signal output to the gate line GL7 is at a low level.
  • the high level of the first clock signal CLK1 is applied to the first clock terminal CLKB, so that the ninth transistor M9 and the fifth transistor M5 are turned on to supply the high level of the first clock signal CLK1 to the first Two nodes PD_CN and a third node PD. Since the third node PD is at a high level, the tenth transistor M10 is turned on to discharge the first capacitor C1, and the eleventh transistor M11 is turned on to keep the gate signal output to the gate line GL7 via the output terminal OUTPUT at Low level.
  • the second scan start signal STV_R is described as having a pulse width of 1.5H in the above embodiment, in other embodiments, the second scan start signal STV_R may have a pulse width of 1H.
  • the gate drive circuit can be enabled to perform forward scanning and reverse scanning by utilizing the first scan start signal STV_F and the second scan start signal STV_R and by changing the timing of the clock signal without additional Signal line.

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Abstract

一种栅极驱动电路（200）、包括该栅极驱动电路（200）的阵列基板（110）、包括该阵列基板（110）的显示面板（100）以及该显示面板（100）的驱动方法。栅极驱动电路（200）包括：顺序布置的n个级（ST1，ST2，...STn-1，STn），其中n是大于或等于4的整数。n个级（ST1，ST2，...STn-1，STn）被划分为第一级组（SG1）、第二级组（SG2）、第三级组（SG3）和第四级组（SG4），它们被配置成接收第一时钟信号（CLK1）、第二时钟信号（CLK2）、第三时钟信号（CLK3）和第四时钟信号（CLK4）的相应不同组合。第一级组（SG1）的级与第三级组（SG3）的级彼此级联，并且第二级组（SG2）的级与第四级组（SG4）的级彼此级联。

Description

栅极驱动电路、阵列基板、显示面板及其驱动方法 技术领域
本发明涉及显示技术领域，具体来说涉及一种栅极驱动电路、阵列基板、显示面板及其驱动方法。
背景技术
显示装置包括其上形成像素阵列的阵列基板、栅极驱动电路和数据驱动电路。栅极驱动电路顺序打开像素阵列中的各像素行，以将数据驱动电路输出的数据电压输入到对应的像素。在一些应用中，栅极驱动电路形成在阵列基板上，并且被称为“阵列基板栅极驱动器(gate driver on array，GOA)”。
具有双扫描(dual scan)能力的栅极驱动电路已经被广泛使用。在正向扫描模式下，栅极驱动电路从上到下依次打开各像素行。在反向扫描模式下，栅极驱动电路从下到上依次打开各像素行。典型地，需要附加的信号线来实现双扫描。
发明内容
有利的是实现一种栅极驱动电路，其基于两个扫描开始信号和四个时钟信号而实现双扫描。还期望的是提供一种包括所述栅极驱动电路的阵列基板、包括所述阵列基板的显示面板以及该显示面板的驱动方法。
根据本发明的第一方面，提供了一种一种栅极驱动电路，包括：顺序布置的n个级，其中n是大于或等于4的整数，其中，所述n个级被划分为包括所述n个级中的第4k+1个级的第一级组、包括所述n个级中的第4k+2个级的第二级组、包括所述n个级中的第4k+3个级的第三级组和包括所述n个级中的第4(k+1)个级的第四级组，其中k是大于或等于0的整数，其中，第一级组、第二级组、第三级组和第四级组被配置成接收第一时钟信号、第二时钟信号、第三时钟信号和第四时钟信号的相应不同组合，其中，第一级组的级与第三级组的级彼此级联，并且第二级组的级与第四级组的级彼此级联，并且其中，所述n个级中的最先两个级被配置成接收第一扫描开始信号，并且所 述n个级中的最后两个级被配置成接收第二扫描开始信号。
在一些实施例中，所述栅极驱动电路还包括：传送所述第一时钟信号的第一时钟线、传送所述第二时钟信号的第二时钟线、传送所述第三时钟信号的第三时钟线、以及传送所述第四时钟信号的第四时钟线，其中，所述n个级中的每个包括第一时钟端子、第二时钟端子、第三时钟端子和第四时钟端子，其中，所述第一时钟线连接到所述第一级组的每个级的第三时钟端子、所述第二级组的每个级的第二时钟端子、所述第三级组的每个级的第一时钟端子、以及所述第四级组的每个级的第四时钟端子；其中，所述第二时钟线连接到所述第一级组的每个级的第四时钟端子、所述第二级组的每个级的第三时钟端子、所述第三级组的每个级的第二时钟端子、以及所述第四级组的每个级的第一时钟端子；其中，所述第三时钟线连接到所述第一级组的每个级的第一时钟端子、所述第二级组的每个级的第四时钟端子、所述第三级组的每个级的第三时钟端子、以及所述第四级组的每个级的第二时钟端子；并且其中，所述第四时钟线连接到所述第一级组的每个级的第二时钟端子、所述第二级组的每个级的第一时钟端子、所述第三级组的每个级的第四时钟端子、以及所述第四级组的每个级的第三时钟端子。
在一些实施例中，所述栅极驱动电路还包括：传送所述第一扫描开始信号的第一扫描开始信号线和传送所述第二扫描开始信号的第二扫描开始信号线，其中，所述n个级中的每个还包括输入端子、输出端子、复位端子、以及被配置成接收栅极截止电压的栅极截止电压端子，其中，第一级组的每个级的输出端子连接到第三级组的相应下一个级的输入端子，并且第三级组的每个级的输出端子连接到第一级组的相应前一个级的复位端子和第一级组的相应下一个级的输入端子，其中，第二级组的每个级的输出端子连接到第四级组的相应下一个级的输入端子，并且第四级组的每个级的输出端子连接到第二级组的相应前一个级的复位端子和第二级组的相应下一个级的输入端子，并且其中，所述n个级中的最先两个级的输入端子连接到所述第一扫描开始信号线，并且所述n个级中的最后两个级的复位端子连接到所述第二扫描开始信号线。
在一些实施例中，所述n个级中的每个包括：第一节点；缓冲部， 可操作用于基于施加到所述输入端子的信号和施加到所述复位端子的信号而选择性地将施加到所述第二时钟端子的信号或施加到所述第四时钟端子的信号供给到所述第一节点；充电部，可操作用于基于所述缓冲部供给到所述第一节点处的信号进行充电；上拉部，可操作用于基于所述第一节点处的电压而选择性地将施加到所述第三时钟端子的信号供给到所述输出端子；下拉部，可操作用于基于施加到所述输入端子的信号和施加到所述复位端子的信号而选择性地将施加到所述栅极截止电压端子的信号供给到所述输出端子；以及保持部，可操作用于基于施加到所述第一时钟端子的信号而保持施加到所述栅极截止电压端子的信号到所述输出端子的供给。
在一些实施例中，所述缓冲部包括第一晶体管和第二晶体管，其中所述第一晶体管包括连接到所述输入端子的栅电极、连接到所述第一节点的第一电极、以及连接到所述第二时钟端子的第二电极，并且所述第二晶体管包括连接到所述复位端子的栅电极、连接到所述第四时钟端子的第一电极、以及连接到所述第一节点的第二电极。
在一些实施例中，所述充电部包括第一电容器，其中所述第一电容器包括连接到所述第一节点的第一端子和连接到所述输出端子的第二端子。
在一些实施例中，所述上拉部包括第三晶体管，其中所述第三晶体管包括连接到所述第一节点的栅电极、连接到所述输出端子的第一电极、以及连接到所述第三时钟端子的第二电极。
在一些实施例中，所述下拉部包括第四晶体管和第七晶体管，其中所述第四晶体管包括连接到所述复位端子的栅电极、连接到所述栅极截止电压端子的第一电极、以及连接到所述输出端子的第二电极，并且所述第七晶体管包括连接到所述输入端子的栅电极、连接到所述栅极截止电压端子的第一电极、以及连接到所述输出端子的第二电极。
在一些实施例中，所述n个级中的每个还包括第二节点和第三节点，并且其中，所述保持部包括第五晶体管、第九晶体管、第十晶体管和第十一晶体管，其中所述第五晶体管包括连接到所述第二节点的栅电极、连接到所述第三节点的第一电极、以及连接到所述第一时钟端子的第二电极，所述第九晶体管包括连接到所述第一时钟端子的栅电极、连接到所述第二节点的第一电极、以及连接到所述第一时钟端 子的第二电极，所述第十晶体管包括连接到所述第三节点的栅电极、连接到所述栅极截止电压端子的第一电极、以及连接到所述第一节点的第二电极，并且所述第十一晶体管包括连接到所述第三节点的栅电极、连接到所述栅极截止电压端子的第一电极、以及连接到所述输出端子的第二电极。
在一些实施例中，所述缓冲部还包括第六晶体管和第八晶体管，其中所述第六晶体管包括连接到所述第一节点的栅电极、连接到所述栅极截止电压端子的第一电极、以及连接到所述第三节点的第二电极，并且所述第八晶体管包括连接到所述第一节点的栅电极、连接到所述栅极截止电压端子的第一电极、以及连接到所述第二节点的第二电极。
在一些实施例中，所述栅极驱动电路被配置成响应于所述第一扫描开始信号到所述n个级中的最先两个级的输入端子的施加而工作在正向扫描模式。
在一些实施例中，所述第一时钟信号、第二时钟信号、第三时钟信号和第四时钟信号中的每个是以2H的周期周期性重复的脉冲信号，其中，H是水平扫描周期，所述第一时钟信号和第三时钟信号具有180°的相位差，所述第二时钟信号和第四时钟信号具有180°的相位差，并且所述第一时钟信号在相位上领先所述第四时钟信号90°。
在一些实施例中，所述第一扫描开始信号是具有1.5H或1H的脉冲宽度的脉冲信号，并且所述第一扫描开始信号的上升沿与所述第三时钟信号的上升沿同步。
在一些实施例中，所述栅极驱动电路被配置成响应于所述第二扫描开始信号到所述n个级中的最后两个级的复位端子的施加而工作在反向扫描模式。
在一些实施例中，所述第一时钟信号、第二时钟信号、第三时钟信号和第四时钟信号中的每个是以2H的周期周期性重复的脉冲信号，其中，H是水平扫描周期，所述第一时钟信号和第三时钟信号具有180°的相位差，所述第二时钟信号和第四时钟信号具有180°的相位差，并且所述第一时钟信号在相位上落后所述第四时钟信号90°。
在一些实施例中，所述第二扫描开始信号是具有1.5H或1H的脉冲宽度的脉冲信号，并且所述第二扫描开始信号的上升沿与所述第二时钟信号的上升沿同步。
根据本发明的另一方面，提供了一种阵列基板，包括：显示区，包括多个栅极线和与所述多个栅极线彼此相交的多个数据线；以及如上文所述的栅极驱动电路，其中，所述栅极驱动电路形成在所述阵列基板的除所述显示区之外的外围区中，并且被配置成向所述多个栅极线供给栅极信号。
根据本发明的再另一方面，提供了一种显示面板，包括如上文所述的阵列基板。
根据本发明的又另一方面，提供了一种驱动如上文所述的显示面板的方法，包括：通过向所述栅极驱动电路供给第一时钟信号、第二时钟信号、第三时钟信号、第四时钟信号和第一扫描开始信号，驱动所述显示面板在正向扫描模式下操作，其中，所述第一时钟信号、第二时钟信号、第三时钟信号和所述第四时钟信号中的每个是以2H的周期周期性重复的脉冲信号，H是水平扫描周期，所述第一时钟信号和第三时钟信号具有180°的相位差，所述第二时钟信号和第四时钟信号具有180°的相位差，所述第一时钟信号在相位上领先所述第四时钟信号90°，所述第一扫描开始信号是具有1.5H或1H的脉冲宽度的脉冲信号，并且所述第一扫描开始信号的上升沿与所述第三时钟信号的上升沿同步；并且通过向所述栅极驱动电路供给第一时钟信号、第二时钟信号、第三时钟信号、第四时钟信号和第二扫描开始信号，驱动所述显示面板在反向扫描模式下操作，其中，所述第一时钟信号、第二时钟信号、第三时钟信号和所述第四时钟信号中的每个是以2H的周期周期性重复的脉冲信号，H是水平扫描周期，所述第一时钟信号和第三时钟信号具有180°的相位差，所述第二时钟信号和第四时钟信号具有180°的相位差，所述第一时钟信号在相位上落后所述第四时钟信号90°，所述第二扫描开始信号是具有1.5H或1H的脉冲宽度的脉冲信号，并且所述第二扫描开始信号的上升沿与所述第二时钟信号的上升沿同步。
根据在下文中所描述的实施例，本发明的这些和其它方面将是清楚明白的，并且将参考在下文中所描述的实施例而被阐明。
附图说明
在下面结合附图对于示例性实施例的描述中，本发明的更多细节、 特征和优点被公开，在附图中：
图1是示意性示出根据本发明一个实施例的显示面板的平面图；
图2是示意性示出根据本发明一个实施例的栅极驱动电路的框图；
图3是示意性示出如图2所示的栅极驱动电路的一个级的电路图；
图4A和4B是分别示意性示出如图2所示的栅极驱动电路在正向扫描模式和反向扫描模式下的驱动方法的时序图；
图5A、5B、5C和5D是分别示意性示出如图2所示的栅极驱动电路的第一级、第二级、第三级和第四级在正向扫描模式下的操作的时序图；并且
图6A和6B是分别示意性示出如图2所示的栅极驱动电路的第八级和第七级在反向扫描模式下的操作的时序图。
具体实施方式
现在，将参照其中表示本发明的示范性实施例的附图更完整地描述本发明。然而，本发明可以按很多不同的方式体现，不应解读为局限于这里所述的实施例。相反，提供这些实施例使得本公开是详尽和完整的，并且向本领域的技术人员完全传达本发明的范围。全文中，相似的参考数字指代相似的元素。
图1是示意性示出根据本发明一个实施例的显示面板100的平面图。
参照图1，显示面板100包括阵列基板110、用于输出数据电压的(多个)数据驱动电路120以及用于输出栅极信号的栅极驱动电路200。如图1所示，阵列基板110包括其上显示图像的显示区DA和除显示区DA之外的外围区PA。
在显示区DA中，设置栅极线GL1-GLn和与栅极线GL1-GLn绝缘的数据线DL1-DLm。数据线DL1-DLm与栅极线GL1-GLn彼此交叉以限定多个像素。多个像素呈阵列布置在显示区DA中，并且具有基本相同的结构和功能。因此，现在将仅更详细地描述一个像素P1(如虚线框所指示的)。在示例性实施例中，像素P1包括薄膜晶体管Tr。薄膜晶体管Tr包括连接到栅极线GL1的栅电极和连接到数据线DL1的第一电极。在显示面板100为液晶显示面板的情况下，薄膜晶体管Tr的第二电极连接到像素电极。在显示面板100为有机发光二极管 (OLED)显示面板的情况下，薄膜晶体管Tr的第二电极连接到例如用于为OLED提供驱动电流的驱动晶体管的栅电极。
栅极驱动电路200设置在外围区PA中并且连接到栅极线GL1-GLn，以向栅极线GL1-GLn顺序地输出栅极信号。在示例性实施例中，在像素的薄膜晶体管Tr的制造工艺过程中，栅极驱动电路200可以与薄膜晶体管Tr同时形成，从而得到GOA电路。在另一示例性实施例中，栅极驱动电路200可以形成为单独的集成电路(IC)芯片，并且被直接安装在显示面板100上，或者被安装在单独的印刷电路板(未示出)上。另外，多个数据驱动电路120设置在外围区PA中并且连接到数据线DL1-DLm，以向数据线DL1-DLm输出数据电压。
图2是示意性示出根据本发明一个实施例的栅极驱动电路200的框图。
参照图2，栅极驱动电路100包括顺序布置的n个级ST1，ST2，...STn-1，STn，其中n是大于或等于4的整数。这n个级ST1，ST2，...STn-1，STn形成一个移位寄存器。
所述n个级ST1，ST2，...STn-1，STn中的每个具有第一时钟端子CLKB、第二时钟端子CLKB′、第三时钟端子CLK、第四时钟端子CLK′、栅极截止电压端子VSS、输入端子INPUT、输出端子OUTPUT和复位端子RESET。
如图2所示，所述n个级ST1，ST2，...STn-1，STn的输出端子OUTPUT被连接到对应的栅极线GL1，GL2，...GLn-1，GLn，并且输出对应的栅极信号。这些栅极信号具有作为栅极导通电压的高电平和作为栅极截止电压的低电平。栅极截止电压可以经由栅极截止电压端子VSS供应。
所述n个级ST1，ST2，...STn-1，STn被划分为第一级组SG1、第二级组SG2、第三级组SG3和第四级组SG4。第一级组SG1包括所述n个级中的第4k+1个级，第二级组SG2包括所述n个级中的第4k+2个级，第三级组SG3包括所述n个级中的第4k+3个级，并且第四级组SG4包括所述n个级中的第4(k+1)个级，其中k是大于或等于0的整数。
在图2中，最右侧的参考标记“SG1”、“SG2”、“SG3”和“SG4”指示各个级ST1，ST2，...STn-1，STn所属的级组。例如，第一级ST1 属于第一级组SG1，第二级ST2属于第二级组SG2，第三级ST3属于第三级组SG3，第四级ST4属于第四级组SG4，第五级ST5(未示出)属于第一级组SG1，等等。
将理解的是，虽然图2中示出的级的数目为4的整数倍(因为最后一个级STn属于级组SG4)，但是在其他实施例中其他数目是可能的。
第一级组SG1、第二级组SG2、第三级组SG3和第四级组SG4被配置成经由它们相应的第一时钟端子CLKB、第二时钟端子CLKB′、第三时钟端子CLK和第四时钟端子CLK′接收第一时钟信号CLK1、第二时钟信号CLK2、第三时钟信号CLK3和第四时钟信号CLK4的不同组合。
具体地，第一级组SG1的每个级被配置成接收这四个时钟信号的第一组合，第二级组SG2的每个级被配置成接收这四个时钟信号的第二组合，第三级组SG3的每个级被配置成接收这四个时钟信号的第三组合，并且第四级组SG4的每个级被配置成接收这四个时钟信号的第四组合。
更具体地，参照图2，传送第一时钟信号CLK1的第一时钟线连接到第一级组SG1的每个级的第三时钟端子CLK、第二级组SG2的每个级的第二时钟端子CLKB′、第三级组SG3的每个级的第一时钟端子CLKB、以及第四级组SG4的每个级的第四时钟端子CLK′。传送第二时钟信号CLK2的第二时钟线连接到第一级组SG1的每个级的第四时钟端子CLK′、第二级组SG2的每个级的第三时钟端子CLK、第三级组SG3的每个级的第二时钟端子CLKB′、以及第四级组SG4的每个级的第一时钟端子CLKB。传送第三时钟信号CLK3的第三时钟线连接到第一级组SG1的每个级的第一时钟端子CLKB、第二级组SG2的每个级的第四时钟端子CLK′、第三级组SG3的每个级的第三时钟端子CLK、以及第四级组SG4的每个级的第二时钟端子CLKB′。传送第四时钟信号CLK4的第四时钟线连接到第一级组SG1的每个级的第二时钟端子CLKB′、第二级组SG2的每个级的第一时钟端子CLKB、第三级组SG3的每个级的第四时钟端子CLK′、以及第四级组SG4的每个级的第三时钟端子CLK。
第一级组SG1的级与第三级组SG3的级彼此级联，并且第二级组 SG2的级与第四级组SG4的级彼此级联。
具体地，参照图2，第一级组SG1的每个级的输出端子OUTPUT连接到第三级组SG3的相应下一个级的输入端子INPUT，并且第三级组SG3的每个级的输出端子OUTPUT连接到第一级组SG1的相应前一个级的复位端子RESET和第一级组SG1的相应下一个级的输入端子INPUT。第二级组SG2的每个级的输出端子OUTPUT连接到第四级组SG4的相应下一个级的输入端子INPUT，并且第四级组SG4的每个级的输出端子OUTPUT连接到第二级组SG2的相应前一个级的复位端子RESET和第二级组SG2的相应下一个级的输入端子INPUT。
另外，所述n个级ST1，ST2，...STn-1，STn中的最先两个级ST1和ST2被配置成接收第一扫描开始信号STV_F，并且所述n个级ST1，ST2，...STn-1，STn中的最后两个级STn-1和STn被配置成接收第二扫描开始信号STV_R。
具体地，所述n个级ST1，ST2，...STn-1，STn中的最先两个级ST1和ST2的输入端子INPUT连接到传送第一扫描开始信号STV_F的第一扫描开始信号线，并且所述n个级ST1，ST2，...STn-1，STn中的最后两个级STn-1和STn的复位端子RESET连接到传送第二扫描开始信号STV_R的第二扫描开始信号线。
如稍后将描述的，栅极驱动电路200响应于第一扫描开始信号STV_F而在正向扫描模式下操作，并且响应于第二扫描开始信号STV_R而在反向扫描模式下操作。在正向扫描模式下，第一时钟信号CLK1、第二时钟信号CLK2、第三时钟信号CLK3和第四时钟信号CLK4具有第一时序型式(pattern)。在反向扫描模式下，第一时钟信号CLK1、第二时钟信号CLK2、第三时钟信号CLK3和第四时钟信号CLK4具有第二时序型式。第二时序型式不同于第一时序型式。
因此，可以通过利用两个扫描开始信号之一并通过改变时钟信号的时序来实现正向扫描与反向扫描的切换，而不需要附加的信号线。这有利于电路的简化，并且因而电路占用面积(footprint)的减小。
图3是示意性示出如图2所示的栅极驱动电路200的一个级STx的电路图。栅极驱动电路200中的每个级具有相同的结构，因此，如图3所示的级STx代表n个级ST1，ST2，...STn-1，STn中的每一个。
参照图3，级STx包括第一节点PU、缓冲部310、充电部320、 上拉部330、下拉部340和保持部350。
缓冲部310可操作用于基于施加到输入端子INPUT的信号和施加到复位端子RESET的信号而选择性地将施加到第二时钟端子CLKB′的信号或施加到第四时钟端子CLK′的信号供给到第一节点PU。
术语缓冲，在本文中使用时，涉及对第一节点PU充电的操作，如稍后将描述的。
具体地，缓冲部310包括第一晶体管M1和第二晶体管M2。第一晶体管M包括连接到输入端子INPUT的栅电极、连接到第一节点PU的第一电极、以及连接到第二时钟端子CLKB′的第二电极。第二晶体管M2包括连接到复位端子RESET的栅电极、连接到第四时钟端子CLK′的第一电极、以及连接到第一节点PU的第二电极。
另外，在示例性实施例中，缓冲部310还包括第六晶体管M6和第八晶体管M8。第六晶体管M6包括连接到第一节点PU的栅电极、连接到栅极截止电压端子VSS的第一电极、以及连接到第三节点PD的第二电极。第八晶体管M8包括连接到第一节点PU的栅电极、连接到栅极截止电压端子VSS的第一电极、以及连接到第二节点PD_CN的第二电极。
充电部320可操作用于基于缓冲部310供给到第一节点PU处的信号进行充电。
具体地，充电部320包括第一电容器C1。第一电容器C1包括连接到第一节点PU的第一端子和连接到输出端子OUTPUT的第二端子。
上拉部330可操作用于基于第一节点PU处的电压而选择性地将施加到第三时钟端子CLK的信号供给到输出端子OUTPUT。
具体地，上拉部330包括第三晶体管M3。第三晶体管M3包括连接到第一节点PU的栅电极、连接到输出端子OUTPUT的第一电极、以及连接到第三时钟端子CLK的第二电极。
下拉部340可操作用于基于施加到输入端子INPUT的信号和施加到复位端子RESET的信号而选择性地将施加到栅极截止电压端子VSS的信号供给到输出端子OUTPUT。
具体地，下拉部340包括第四晶体管M4和第七晶体管M7。第四晶体管M4包括连接到复位端子RESET的栅电极、连接到栅极截止电压端子VSS的第一电极、以及连接到输出端子OUTPUT的第二电极。 第七晶体管M7包括连接到输入端子INPUT的栅电极、连接到栅极截止电压端子VSS的第一电极、以及连接到输出端子OUTPUT的第二电极。
保持部350可操作用于基于施加到第一时钟端子CLKB的信号而保持施加到栅极截止电压端子VSS的信号到输出端子OUTPUT的供给。
具体地，保持部350包括第五晶体管M5、第九晶体管M9、第十晶体管M10和第十一晶体管M11。仍然参照图3，级STx还包括第二节点PD_CN和第三节点PD。
第五晶体管M5包括连接到第二节点PD_CN的栅电极、连接到第三节点PD的第一电极、以及连接到第一时钟端子CLKB的第二电极。第九晶体管M9包括连接到第一时钟端子CLKB的栅电极、连接到第二节点PD_CN的第一电极、以及连接到第一时钟端子CLKB的第二电极。第十晶体管M10包括连接到第三节点PD的栅电极、连接到栅极截止电压端子VSS的第一电极、以及连接到第一节点PU的第二电极。第十一晶体管M11包括连接到第三节点PD的栅电极、连接到栅极截止电压端子VSS的第一电极、以及连接到输出端子OUTPUT的第二电极。
将理解的是，虽然在图3中各个晶体管被示出为n型晶体管，但是在其他实施例中，可以使用p型晶体管。在p型晶体管的情况下，用于打开晶体管的电压是低电平电压，并且用于关闭晶体管的电压是高电平电压。
还将理解的是，在其中栅极驱动电路200被实现为GOA的实施例中，各个晶体管被形成为薄膜晶体管。在薄膜晶体管的情况下，源电极和漏电极可互换地使用。
图4A和4B是分别示意性示出如图2所示的栅极驱动电路200在正向扫描模式和反向扫描模式下的驱动方法的时序图。为了便于描述，假定栅极驱动电路200包括8个级(n＝8)，尽管其他数目的级是可能的。相应地，存在8个栅极线GL1，GL2，...，GL8，如图4A和4B所示。
如上文所述，栅极驱动电路200被配置成响应于第一扫描开始信号STV_F到8个级中的最先两个级(ST1和ST2)的输入端子INPUT 的施加而工作在正向扫描模式。在这种情况下，栅极信号依次输出到栅极线GL1，GL2，...，GL8，如图4A所示。
参照图4A，第一时钟信号CLK1、第二时钟信号CLK2、第三时钟信号CLK3和第四时钟信号CLK4中的每个是以2H的周期周期性重复的脉冲信号，其中H是水平扫描周期，在该水平扫描周期期间栅极信号处于作为栅极导通电压的高电平。
第一时钟信号CLK1、第二时钟信号CLK2、第三时钟信号CLK3和第四时钟信号CLK4具有第一时序型式。具体地，第一时钟信号CLK1和第三时钟信号CLK3具有180°的相位差，第二时钟信号CLK2和第四时钟信号CLK4具有180°的相位差，并且第一时钟信号CLK1在相位上领先第四时钟信号CLK4 90°。另外，第一扫描开始信号STV_F是具有1.5H的脉冲宽度的脉冲信号，并且第一扫描开始信号STV_F的上升沿与第三时钟信号CLK3的上升沿同步。
如上文所述，栅极驱动电路200被配置成响应于第二扫描开始信号STV_R到8个级中的最后两个级(ST8和ST7)的复位端子的施加而工作在反向扫描模式。在这种情况下，栅极信号依次输出到栅极线GL8，GL7，...，GL1，如图4B所示。
在反向扫描模式下，第一时钟信号CLK1、第二时钟信号CLK2、第三时钟信号CLK3和第四时钟信号CLK4具有第二时序型式。第二时序型式不同于第一时序型式。
参照图4B，第一时钟信号CLK1和第三时钟信号CLK3具有180°的相位差，第二时钟信号CLK2和第四时钟信号CLK4具有180°的相位差，并且第一时钟信号CLK1在相位上落后第四时钟信号CLK4 90°。另外，第二扫描开始信号STV_R是具有1.5H的脉冲宽度的脉冲信号，并且第二扫描开始信号STV_R的上升沿与第二时钟信号CLK2的上升沿同步。
下面将参照图2、图3、图5A、5B、5C和5D以及图6A和6B描述根据本发明实施例的栅极驱动电路200的操作。
图5A、5B、5C和5D是分别示意性示出如图2所示的栅极驱动电路200的第一级ST1、第二级ST2、第三级ST3和第四级ST4在正向扫描模式下的操作的时序图。每一级的操作包括5个阶段P1、P2、P3、P4和P5。
下面描述第一级ST1的操作。
在阶段P1，第一扫描开始信号STV_F的高电平被施加到输入端子INPUT，以使得第一晶体管M1被打开，以经由第二时钟端子CLKB’将第四时钟信号CLK4供给到第一节点PU。在阶段P1的后半段，第四时钟信号CLK4的高电平向第一电容器C1充电，以使得第六晶体管M6和第八晶体管M8被打开以经由栅极截止电压端子VSS将栅极截止电压供给到第二节点PD_CN和第三节点PD，并且第三晶体管M3被打开以准备经由输出端子OUTPUT向栅极线GL1输出高电平。
在阶段P2，第一时钟信号CLK1的高电平被施加到第三时钟端子CLK，并且跨第一电容器C1的电压维持第三晶体管M3处于打开状态，以使得第一时钟信号CLK1的高电平经由第三晶体管M3供给到输出端子OUTPUT，并且输出到栅极线GL1。
在阶段P3，第三级ST3输出的高电平(GL3)被施加到第一级ST1的复位端子RESET，以使得第四晶体管M4被打开以经由栅极截止电压端子VSS将栅极截止电压供给到输出端子OUTPUT，从而将输出到栅极线GL1的栅极信号拉低到低电平。同时，第二晶体管M2被打开以经由第四时钟端子CLK’将第二时钟信号CLK2供给到第一节点PU。在阶段P3的后半段，第二时钟信号CLK2的低电平供给到第一节点PU，以使得第一电容器C1放电。
在阶段P4，各晶体管处于关闭状态，以使得输出端子OUTPUT被悬浮在低电平。输出到栅极线GL1的栅极信号处于低电平。
在阶段P5，第三时钟信号CLK3的高电平被施加到第一时钟端子CLKB，以使得第九晶体管M9和第五晶体管M5被打开，以将第三时钟信号CLK3的高电平供给到第二节点PD_CN和第三节点PD。由于第三节点PD处于高电平，所以第十晶体管M10被打开以使第一电容器C1放电，并且第十一晶体管M11被打开以保持经由输出端子OUTPUT输出到栅极线GL1的栅极信号处于低电平。
下面描述第二级ST2的操作。
在阶段P1，第一扫描开始信号STV_F的高电平被施加到输入端子INPUT，以使得第一晶体管M1被打开，以经由第二时钟端子CLKB’将第一时钟信号CLK1供给到第一节点PU。在阶段P1的后半段，第一时钟信号CLK1的高电平向第一电容器C1充电，以使得第六晶体管 M6和第八晶体管M8被打开以经由栅极截止电压端子VSS将栅极截止电压供给到第二节点PD_CN和第三节点PD，并且第三晶体管M3被打开以准备经由输出端子OUTPUT向栅极线GL2输出高电平。
在阶段P2，第二时钟信号CLK2的高电平被施加到第三时钟端子CLK，并且跨第一电容器C1的电压维持第三晶体管M3处于打开状态，以使得第二时钟信号CLK2的高电平经由第三晶体管M3供给到输出端子OUTPUT，并且输出到栅极线GL2。
在阶段P3，第四级ST4输出的高电平(GL4)被施加到第二级ST2的复位端子RESET，以使得第四晶体管M4被打开以经由栅极截止电压端子VSS将栅极截止电压供给到输出端子OUTPUT，从而将输出到栅极线GL2的栅极信号拉低到低电平。同时，第二晶体管M2被打开以经由第四时钟端子CLK’将第三时钟信号CLK3供给到第一节点PU。在阶段P3的后半段，第三时钟信号CLK3的低电平供给到第一节点PU，以使得第一电容器C1放电。
在阶段P4，各晶体管处于关闭状态，以使得输出端子OUTPUT被悬浮在低电平。输出到栅极线GL2的栅极信号处于低电平。
在阶段P5，第四时钟信号CLK4的高电平被施加到第一时钟端子CLKB，以使得第九晶体管M9和第五晶体管M5被打开，以将第四时钟信号CLK4的高电平供给到第二节点PD_CN和第三节点PD。由于第三节点PD处于高电平，所以第十晶体管M10被打开以使第一电容器C1放电，并且第十一晶体管M11被打开以保持经由输出端子OUTPUT输出到栅极线GL2的栅极信号处于低电平。
下面描述第三级ST3的操作。
在阶段P1，第一级ST1输出的高电平被施加到输入端子INPUT，以使得第一晶体管M1被打开，以经由第二时钟端子CLKB’将第二时钟信号CLK2供给到第一节点PU。在阶段P1的后半段，第二时钟信号CLK2的高电平向第一电容器C1充电，以使得第六晶体管M6和第八晶体管M8被打开以经由栅极截止电压端子VSS将栅极截止电压供给到第二节点PD_CN和第三节点PD，并且第三晶体管M3被打开以准备经由输出端子OUTPUT向栅极线GL3输出高电平。
在阶段P2，第三时钟信号CLK3的高电平被施加到第三时钟端子CLK，并且跨第一电容器C1的电压维持第三晶体管M3处于打开状态， 以使得第三时钟信号CLK3的高电平经由第三晶体管M3供给到输出端子OUTPUT，并且输出到栅极线GL3。
在阶段P3，第五级ST5输出的高电平(GL5)被施加到第三级ST3的复位端子RESET，以使得第四晶体管M4被打开以经由栅极截止电压端子VSS将栅极截止电压供给到输出端子OUTPUT，从而将输出到栅极线GL3的栅极信号拉低到低电平。同时，第二晶体管M2被打开以经由第四时钟端子CLK’将第四时钟信号CLK4供给到第一节点PU。在阶段P3的后半段，第四时钟信号CLK4的低电平供给到第一节点PU，以使得第一电容器C1放电。
在阶段P4，各晶体管处于关闭状态，以使得输出端子OUTPUT被悬浮在低电平。输出到栅极线GL3的栅极信号处于低电平。
在阶段P5，第一时钟信号CLK1的高电平被施加到第一时钟端子CLKB，以使得第九晶体管M9和第五晶体管M5被打开，以将第一时钟信号CLK1的高电平供给到第二节点PD_CN和第三节点PD。由于第三节点PD处于高电平，所以第十晶体管M10被打开以使第一电容器C1放电，并且第十一晶体管M11被打开以保持经由输出端子OUTPUT输出到栅极线GL3的栅极信号处于低电平。
下面描述第四级ST4的操作。
在阶段P1，第二级ST2输出的高电平被施加到输入端子INPUT，以使得第一晶体管M1被打开，以经由第二时钟端子CLKB’将第三时钟信号CLK3供给到第一节点PU。在阶段P1的后半段，第三时钟信号CLK3的高电平向第一电容器C1充电，以使得第六晶体管M6和第八晶体管M8被打开以经由栅极截止电压端子VSS将栅极截止电压供给到第二节点PD_CN和第三节点PD，并且第三晶体管M3被打开以准备经由输出端子OUTPUT向栅极线GL4输出高电平。
在阶段P2，第四时钟信号CLK4的高电平被施加到第三时钟端子CLK，并且跨第一电容器C1的电压维持第三晶体管M3处于打开状态，以使得第四时钟信号CLK4的高电平经由第三晶体管M3供给到输出端子OUTPUT，并且输出到栅极线GL4。
在阶段P3，第六级ST6输出的高电平(GL6)被施加到第四级ST4的复位端子RESET，以使得第四晶体管M4被打开以经由栅极截止电压端子VSS将栅极截止电压供给到输出端子OUTPUT，从而将输出到 栅极线GL4的栅极信号拉低到低电平。同时，第二晶体管M2被打开以经由第四时钟端子CLK’将第一时钟信号CLK1供给到第一节点PU。在阶段P3的后半段，第一时钟信号CLK1的低电平供给到第一节点PU，以使得第一电容器C1放电。
在阶段P4，各晶体管处于关闭状态，以使得输出端子OUTPUT被悬浮在低电平。输出到栅极线GL4的栅极信号处于低电平。
在阶段P5，第二时钟信号CLK2的高电平被施加到第一时钟端子CLKB，以使得第九晶体管M9和第五晶体管M5被打开，以将第二时钟信号CLK2的高电平供给到第二节点PD_CN和第三节点PD。由于第三节点PD处于高电平，所以第十晶体管M10被打开以使第一电容器C1放电，并且第十一晶体管M11被打开以保持经由输出端子OUTPUT输出到栅极线GL4的栅极信号处于低电平。
为了简单起见，后续级的操作的描述被省略。将理解的是，虽然在上文的实施例中第一扫描开始信号STV_F被描述为具有1.5H的脉冲宽度，但是在其他实施例中，第一扫描开始信号STV_F可以具有1H的脉冲宽度。
图6A和6B是分别示意性示出如图2所示的栅极驱动电路200(n＝8)的第八级和第七级在反向扫描模式下的操作的时序图。每一级的操作包括5个阶段P1、P2、P3、P4和P5。
下面描述第八级ST8的操作。
在阶段P1，STV_R的高电平被施加到复位端子RESET，以使得第二晶体管M2被打开，以经由第四时钟端子CLK’将第一时钟信号CLK1供给到第一节点PU。在阶段P1的后半段，第一时钟信号CLK1的高电平向第一电容器C1充电，以使得第六晶体管M6和第八晶体管M8被打开以经由栅极截止电压端子VSS将栅极截止电压供给到第二节点PD_CN和第三节点PD，并且第三晶体管M3被打开以准备经由输出端子OUTPUT向栅极线GL8输出高电平。
在阶段P2，第四时钟信号CLK4的高电平被施加到第三时钟端子CLK，并且跨第一电容器C1的电压维持第三晶体管M3处于打开状态，以使得第四时钟信号CLK4的高电平经由第三晶体管M3供给到输出端子OUTPUT，并且输出到栅极线GL8。
在阶段P3，第六级ST6输出的高电平(GL6)被施加到第八级ST8 的输入端子INPUT，以使得第七晶体管M7被打开以经由栅极截止电压端子VSS将栅极截止电压供给到输出端子OUTPUT，从而将输出到栅极线GL8的栅极信号拉低到低电平。同时，第一晶体管M1被打开以经由第二时钟端子CLKB’将第三时钟信号CLK3供给到第一节点PU。在阶段P3的后半段，第三时钟信号CLK3的低电平供给到第一节点PU，以使得第一电容器C1放电。
在阶段P4，各晶体管处于关闭状态，以使得输出端子OUTPUT被悬浮在低电平。输出到栅极线GL8的栅极信号处于低电平。
在阶段P5，第二时钟信号CLK2的高电平被施加到第一时钟端子CLKB，以使得第九晶体管M9和第五晶体管M5被打开，以将第二时钟信号CLK2的高电平供给到第二节点PD_CN和第三节点PD。由于第三节点PD处于高电平，所以第十晶体管M10被打开以使第一电容器C1放电，并且第十一晶体管M11被打开以保持经由输出端子OUTPUT输出到栅极线GL8的栅极信号处于低电平。
下面描述第七级ST7的操作。
在阶段P1，STV_R的高电平被施加到复位端子RESET，以使得第二晶体管M2被打开，以经由第四时钟端子CLK’将第四时钟信号CLK4供给到第一节点PU。在阶段P1的后半段，第四时钟信号CLK4的高电平向第一电容器C1充电，以使得第六晶体管M6和第八晶体管M8被打开以经由栅极截止电压端子VSS将栅极截止电压供给到第二节点PD_CN和第三节点PD，并且第三晶体管M3被打开以准备经由输出端子OUTPUT向栅极线GL7输出高电平。
在阶段P2，第三时钟信号CLK3的高电平被施加到第三时钟端子CLK，并且跨第一电容器C1的电压维持第三晶体管M3处于打开状态，以使得第三时钟信号CLK3的高电平经由第三晶体管M3供给到输出端子OUTPUT，并且输出到栅极线GL7。
在阶段P3，第五级ST5输出的高电平(GL5)被施加到第七级ST7的输入端子INPUT，以使得第七晶体管M7被打开以经由栅极截止电压端子VSS将栅极截止电压供给到输出端子OUTPUT，从而将输出到栅极线GL7的栅极信号拉低到低电平。同时，第一晶体管M1被打开以经由第二时钟端子CLKB’将第二时钟信号CLK2供给到第一节点PU。在阶段P3的后半段，第二时钟信号CLK2的低电平供给到第一节 点PU，以使得第一电容器C1放电。
在阶段P4，各晶体管处于关闭状态，以使得输出端子OUTPUT被悬浮在低电平。输出到栅极线GL7的栅极信号处于低电平。
在阶段P5，第一时钟信号CLK1的高电平被施加到第一时钟端子CLKB，以使得第九晶体管M9和第五晶体管M5被打开，以将第一时钟信号CLK1的高电平供给到第二节点PD_CN和第三节点PD。由于第三节点PD处于高电平，所以第十晶体管M10被打开以使第一电容器C1放电，并且第十一晶体管M11被打开以保持经由输出端子OUTPUT输出到栅极线GL7的栅极信号处于低电平。
为了简单起见，后续级的操作的描述被省略。将理解的是，虽然在上文的实施例中第二扫描开始信号STV_R被描述为具有1.5H的脉冲宽度，但是在其他实施例中，第二扫描开始信号STV_R可以具有1H的脉冲宽度。
根据本发明的实施例，可以通过利用第一扫描开始信号STV_F和第二扫描开始信号STV_R并通过改变时钟信号的时序来使得栅极驱动电路能够实现正向扫描和反向扫描，而不需要附加的信号线。
鉴于前面的描述并结合阅读附图，对前述本发明的示例性实施例的各种修改和改动对于相关领域的技术人员可以变得显而易见。任何和所有修改仍将落入本发明的非限制性和示例性实施例的范围内。此外，属于本发明的这些实施例所属领域的技术人员，在得益于前面的描述和相关附图所给出的教导后，将会想到在此描述的本发明的其他实施例。
因此，应当理解，本发明的实施例并不限于所公开的特定实施例，并且修改和其他的实施例也意图被包含在所附权利要求书的范围内。尽管此处使用了特定术语，但是它们仅在通用和描述性意义上使用，而非为了限制的目的。

Claims (19)

  1. 一种栅极驱动电路，包括：
    顺序布置的n个级，其中n是大于或等于4的整数，
    其中，所述n个级被划分为包括所述n个级中的第4k+1个级的第一级组、包括所述n个级中的第4k+2个级的第二级组、包括所述n个级中的第4k+3个级的第三级组和包括所述n个级中的第4(k+1)个级的第四级组，其中k是大于或等于0的整数，
    其中，第一级组、第二级组、第三级组和第四级组被配置成接收第一时钟信号、第二时钟信号、第三时钟信号和第四时钟信号的相应不同组合，
    其中，第一级组的级与第三级组的级彼此级联，并且第二级组的级与第四级组的级彼此级联，并且
    其中，所述n个级中的最先两个级被配置成接收第一扫描开始信号，并且所述n个级中的最后两个级被配置成接收第二扫描开始信号。
  2. 根据权利要求1所述的栅极驱动电路，还包括：
    传送所述第一时钟信号的第一时钟线、传送所述第二时钟信号的第二时钟线、传送所述第三时钟信号的第三时钟线、以及传送所述第四时钟信号的第四时钟线，
    其中，所述n个级中的每个包括第一时钟端子、第二时钟端子、第三时钟端子和第四时钟端子，
    其中，所述第一时钟线连接到所述第一级组的每个级的第三时钟端子、所述第二级组的每个级的第二时钟端子、所述第三级组的每个级的第一时钟端子、以及所述第四级组的每个级的第四时钟端子；
    其中，所述第二时钟线连接到所述第一级组的每个级的第四时钟端子、所述第二级组的每个级的第三时钟端子、所述第三级组的每个级的第二时钟端子、以及所述第四级组的每个级的第一时钟端子；
    其中，所述第三时钟线连接到所述第一级组的每个级的第一时钟端子、所述第二级组的每个级的第四时钟端子、所述第三级组的每个级的第三时钟端子、以及所述第四级组的每个级的第二时钟端子；并且
    其中，所述第四时钟线连接到所述第一级组的每个级的第二时钟 端子、所述第二级组的每个级的第一时钟端子、所述第三级组的每个级的第四时钟端子、以及所述第四级组的每个级的第三时钟端子。
  3. 根据权利要求2所述的栅极驱动电路，还包括：
    传送所述第一扫描开始信号的第一扫描开始信号线和传送所述第二扫描开始信号的第二扫描开始信号线，
    其中，所述n个级中的每个还包括输入端子、输出端子、复位端子、以及被配置成接收栅极截止电压的栅极截止电压端子，
    其中，第一级组的每个级的输出端子连接到第三级组的相应下一个级的输入端子，并且第三级组的每个级的输出端子连接到第一级组的相应前一个级的复位端子和第一级组的相应下一个级的输入端子，
    其中，第二级组的每个级的输出端子连接到第四级组的相应下一个级的输入端子，并且第四级组的每个级的输出端子连接到第二级组的相应前一个级的复位端子和第二级组的相应下一个级的输入端子，并且
    其中，所述n个级中的最先两个级的输入端子连接到所述第一扫描开始信号线，并且所述n个级中的最后两个级的复位端子连接到所述第二扫描开始信号线。
  4. 根据权利要求3所述的栅极驱动电路，其中，所述n个级中的每个包括：
    第一节点；
    缓冲部，可操作用于基于施加到所述输入端子的信号和施加到所述复位端子的信号而选择性地将施加到所述第二时钟端子的信号或施加到所述第四时钟端子的信号供给到所述第一节点；
    充电部，可操作用于基于所述缓冲部供给到所述第一节点处的信号进行充电；
    上拉部，可操作用于基于所述第一节点处的电压而选择性地将施加到所述第三时钟端子的信号供给到所述输出端子；
    下拉部，可操作用于基于施加到所述输入端子的信号和施加到所述复位端子的信号而选择性地将施加到所述栅极截止电压端子的信号供给到所述输出端子；以及
    保持部，可操作用于基于施加到所述第一时钟端子的信号而保持施加到所述栅极截止电压端子的信号到所述输出端子的供给。
  5. 根据权利要求4所述的栅极驱动电路，其中，所述缓冲部包括第一晶体管和第二晶体管，其中所述第一晶体管包括连接到所述输入端子的栅电极、连接到所述第一节点的第一电极、以及连接到所述第二时钟端子的第二电极，并且所述第二晶体管包括连接到所述复位端子的栅电极、连接到所述第四时钟端子的第一电极、以及连接到所述第一节点的第二电极。
  6. 根据权利要求5所述的栅极驱动电路，其中，所述充电部包括第一电容器，其中所述第一电容器包括连接到所述第一节点的第一端子和连接到所述输出端子的第二端子。
  7. 根据权利要求6所述的栅极驱动电路，其中，所述上拉部包括第三晶体管，其中所述第三晶体管包括连接到所述第一节点的栅电极、连接到所述输出端子的第一电极、以及连接到所述第三时钟端子的第二电极。
  8. 根据权利要求7所述的栅极驱动电路，其中，所述下拉部包括第四晶体管和第七晶体管，其中所述第四晶体管包括连接到所述复位端子的栅电极、连接到所述栅极截止电压端子的第一电极、以及连接到所述输出端子的第二电极，并且所述第七晶体管包括连接到所述输入端子的栅电极、连接到所述栅极截止电压端子的第一电极、以及连接到所述输出端子的第二电极。
  9. 根据权利要求8所述的栅极驱动电路，其中，所述n个级中的每个还包括第二节点和第三节点，并且其中，所述保持部包括第五晶体管、第九晶体管、第十晶体管和第十一晶体管，其中所述第五晶体管包括连接到所述第二节点的栅电极、连接到所述第三节点的第一电极、以及连接到所述第一时钟端子的第二电极，所述第九晶体管包括连接到所述第一时钟端子的栅电极、连接到所述第二节点的第一电极、以及连接到所述第一时钟端子的第二电极，所述第十晶体管包括连接到所述第三节点的栅电极、连接到所述栅极截止电压端子的第一电极、以及连接到所述第一节点的第二电极，并且所述第十一晶体管包括连接到所述第三节点的栅电极、连接到所述栅极截止电压端子的第一电极、以及连接到所述输出端子的第二电极。
  10. 根据权利要求9所述的栅极驱动电路，其中，所述缓冲部还包括第六晶体管和第八晶体管，其中所述第六晶体管包括连接到所述第 一节点的栅电极、连接到所述栅极截止电压端子的第一电极、以及连接到所述第三节点的第二电极，并且所述第八晶体管包括连接到所述第一节点的栅电极、连接到所述栅极截止电压端子的第一电极、以及连接到所述第二节点的第二电极。
  11. 根据权利要求3所述的栅极驱动电路，其中，所述栅极驱动电路被配置成响应于所述第一扫描开始信号到所述n个级中的最先两个级的输入端子的施加而工作在正向扫描模式。
  12. 根据权利要求11所述的栅极驱动电路，其中，所述第一时钟信号、第二时钟信号、第三时钟信号和第四时钟信号中的每个是以2H的周期周期性重复的脉冲信号，其中，H是水平扫描周期，所述第一时钟信号和第三时钟信号具有180°的相位差，所述第二时钟信号和第四时钟信号具有180°的相位差，并且所述第一时钟信号在相位上领先所述第四时钟信号90°。
  13. 根据权利要求12所述的栅极驱动电路，其中，所述第一扫描开始信号是具有1.5H或1H的脉冲宽度的脉冲信号，并且所述第一扫描开始信号的上升沿与所述第三时钟信号的上升沿同步。
  14. 根据权利要求3所述的栅极驱动电路，其中，所述栅极驱动电路被配置成响应于所述第二扫描开始信号到所述n个级中的最后两个级的复位端子的施加而工作在反向扫描模式。
  15. 根据权利要求14所述的栅极驱动电路，其中，所述第一时钟信号、第二时钟信号、第三时钟信号和第四时钟信号中的每个是以2H的周期周期性重复的脉冲信号，其中，H是水平扫描周期，所述第一时钟信号和第三时钟信号具有180°的相位差，所述第二时钟信号和第四时钟信号具有180°的相位差，并且所述第一时钟信号在相位上落后所述第四时钟信号90°。
  16. 根据权利要求15所述的栅极驱动电路，其中，所述第二扫描开始信号是具有1.5H或1H的脉冲宽度的脉冲信号，并且所述第二扫描开始信号的上升沿与所述第二时钟信号的上升沿同步。
  17. 一种阵列基板，包括：
    显示区，包括多个栅极线和与所述多个栅极线彼此相交的多个数据线；以及
    根据权利要求1-16中任一项所述的栅极驱动电路，其中，所述栅 极驱动电路形成在所述阵列基板的除所述显示区之外的外围区中，并且被配置成向所述多个栅极线供给栅极信号。
  18. 一种显示面板，包括根据权利要求17所述的阵列基板。
  19. 一种驱动根据权利要求18所述的显示面板的方法，包括：
    通过向所述栅极驱动电路供给第一时钟信号、第二时钟信号、第三时钟信号、第四时钟信号和第一扫描开始信号，驱动所述显示面板在正向扫描模式下操作，其中，所述第一时钟信号、第二时钟信号、第三时钟信号和所述第四时钟信号中的每个是以2H的周期周期性重复的脉冲信号，H是水平扫描周期，所述第一时钟信号和第三时钟信号具有180°的相位差，所述第二时钟信号和第四时钟信号具有180°的相位差，所述第一时钟信号在相位上领先所述第四时钟信号90°，所述第一扫描开始信号是具有1.5H或1H的脉冲宽度的脉冲信号，并且所述第一扫描开始信号的上升沿与所述第三时钟信号的上升沿同步；并且
    通过向所述栅极驱动电路供给第一时钟信号、第二时钟信号、第三时钟信号、第四时钟信号和第二扫描开始信号，驱动所述显示面板在反向扫描模式下操作，其中，所述第一时钟信号、第二时钟信号、第三时钟信号和所述第四时钟信号中的每个是以2H的周期周期性重复的脉冲信号，H是水平扫描周期，所述第一时钟信号和第三时钟信号具有180°的相位差，所述第二时钟信号和第四时钟信号具有180°的相位差，所述第一时钟信号在相位上落后所述第四时钟信号90°，所述第二扫描开始信号是具有1.5H或1H的脉冲宽度的脉冲信号，并且所述第二扫描开始信号的上升沿与所述第二时钟信号的上升沿同步。
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