WO2019223336A1 - 显示装置、栅极驱动电路、移位寄存器及其控制方法 - Google Patents

显示装置、栅极驱动电路、移位寄存器及其控制方法 Download PDF

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Publication number
WO2019223336A1
WO2019223336A1 PCT/CN2019/070993 CN2019070993W WO2019223336A1 WO 2019223336 A1 WO2019223336 A1 WO 2019223336A1 CN 2019070993 W CN2019070993 W CN 2019070993W WO 2019223336 A1 WO2019223336 A1 WO 2019223336A1
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Prior art keywords
node
control
signal
terminal
transistor
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PCT/CN2019/070993
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English (en)
French (fr)
Inventor
胡祖权
张振宇
杨海鹏
戴珂
Original Assignee
京东方科技集团股份有限公司
合肥京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/473,076 priority Critical patent/US11443682B2/en
Publication of WO2019223336A1 publication Critical patent/WO2019223336A1/zh
Priority to US17/809,234 priority patent/US11645969B2/en
Priority to US18/181,625 priority patent/US11996030B2/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/16—Determination of a pixel data signal depending on the signal applied in the previous frame
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G09G3/3241—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror
    • G09G3/325—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror the data current flowing through the driving transistor during a setting phase, e.g. by using a switch for connecting the driving transistor to the data driver

Definitions

  • Embodiments of the present disclosure relate to a shift register, a gate driving circuit, a display device, and a control method of the shift register.
  • AMOLED active matrix organic light emitting diode
  • Some embodiments of the present disclosure provide a shift register including a first shift register unit and a second shift register unit.
  • the first shift register unit and a first node, a first signal input terminal, and a first clock signal
  • the second shift register unit is electrically connected to the first node, the second signal input terminal, the second clock signal terminal, and the second signal output terminal, and the first shift register unit is electrically connected to the first signal output terminal.
  • the bit register unit is configured to write a first control signal to the first node under the control of a first input signal provided by the first signal input terminal, and write the first control signal under the control of the voltage of the first node.
  • the first clock signal provided by the first clock signal terminal is written into the first signal output terminal;
  • the second shift register unit is configured to be under the control of a second input signal provided by the second signal input terminal Write a second control signal into the first node, and write a second clock signal provided by the second clock signal terminal into the second signal output terminal under the control of the voltage of the first node;
  • Two phases The frame includes a first frame and a second frame. During the first frame time, the first clock signal and the first input signal are pulse signals, and the second clock signal and the second input signal are DC signal; within the second frame time, the first clock signal and the first input signal are DC signals, and the second clock signal and the second input signal are pulse signals.
  • the first shift register unit includes a first input circuit and a first output circuit
  • the second shift register unit includes a second input circuit and a second An output circuit
  • the first input circuit is respectively connected to the first signal input terminal and the first node
  • the first input circuit is used for controlling a first input signal provided at the first signal input terminal Writing the first input signal into the first node
  • the first output circuit is connected to the first node, the first clock signal terminal, and the first signal output terminal
  • the first An output circuit is used to write the voltage of the first clock signal terminal to the first signal output terminal under the control of the voltage of the first node
  • the second input circuit and the second signal input terminal are respectively Connected to the first node
  • the second input circuit is configured to write the second input signal to the first node under the control of a second input signal provided by the second signal input terminal
  • the Second output circuit Do not connect with the first node, the second clock signal terminal, and the second signal output terminal.
  • the second output circuit is configured
  • the first shift register unit further includes a first control circuit
  • the second shift register unit further includes a second control circuit
  • the first control The circuit is respectively connected to a first power terminal, the first node, a first reset signal terminal, a third power terminal and the first signal output terminal
  • the first control circuit is configured to provide the first power terminal Controlling the voltage of the first signal output terminal and the first node under the control of the first control voltage and the first reset voltage provided by the first reset signal terminal
  • the second control circuit is respectively connected with the first Two power terminals, the first node, the second reset signal terminal, the third power terminal, and the second signal output terminal are connected, and the second control circuit is used for the first terminal provided at the second power terminal.
  • the first control voltage and the second control voltage both have a high level.
  • the first control circuit includes a first pull-down control circuit and a first pull-down circuit, and the first pull-down control circuit is respectively connected to the first node.
  • the first pull-down control circuit is respectively connected to the first node and the first pull-down circuit.
  • the second node, the third power terminal, and the first signal output terminal are connected, and are configured to output the first node and the first signal under the control of the voltage of the second node. Terminal for discharge treatment.
  • the first pull-down control circuit is further connected to the first power supply terminal and the third power supply terminal, respectively, and the first pull-down control circuit is used for Write the first control voltage to the second node under the control of the first control voltage, and write the voltage of the third power supply terminal to the second node under the control of the voltage of the first node Second node.
  • the first control circuit further includes a first reset circuit, and the first reset circuit is respectively connected to the first reset signal terminal and the third power supply terminal. Connected to the first node, the first reset circuit is configured to write the voltage of the third power terminal to the first node under the control of the first reset voltage.
  • the first pull-down circuit is further connected to the third node and the second signal output terminal, and the first pull-down circuit is further configured to Discharge processing is performed on the third node and the second signal output terminal under the control of the voltage of the second node.
  • the second control circuit includes a second pull-down control circuit and a second pull-down circuit, and the second pull-down control circuit is connected to the first node and the third node, respectively.
  • the nodes are connected and configured to control the level of the third node under the control of the voltage of the first node, and the second pull-down circuit is respectively connected to the first node and the third node
  • the third power supply terminal is connected to the second signal output terminal, and is configured to discharge the first node and the second signal output terminal under the control of the voltage of the third node.
  • the second pull-down control circuit is also connected to the second power supply terminal and the third power supply terminal, respectively, and the second pull-down control circuit is used for Write the second control voltage to the third node under the control of the second control voltage, and write the voltage of the third power supply terminal to the third node under the control of the voltage of the first node node.
  • the second control circuit further includes a second reset circuit, and the second reset circuit is respectively connected to the second reset signal terminal and the third power supply terminal. Connected to the first node, the second reset circuit is configured to write the voltage of the third power supply terminal to the first node under the control of the second reset voltage.
  • the second pull-down circuit is further connected to the second node and the first signal output terminal, and the second pull-down circuit is further configured to Discharging the second node and the first signal output terminal under the control of the voltage of the third node.
  • the first shift register unit further includes a first control circuit
  • the second shift register unit further includes a second control circuit
  • the first control circuit is connected to a first power terminal, the first node, a first reset signal terminal, a third power terminal, and the first signal output terminal, respectively. Controlling the voltage of the first signal output terminal and the first node under the control of a first control voltage provided by a first power supply terminal and a first reset voltage provided by the first reset signal terminal;
  • the second control circuit is respectively connected to the first power terminal, the first node, the second reset signal terminal, the third power terminal, and the second signal output terminal.
  • the second control circuit is used for Controlling the voltage of the second signal output terminal and the first node under the control of a first control voltage provided by the first power supply terminal and a second reset voltage provided by the second reset signal terminal;
  • the first power supply terminal outputs the first control voltage.
  • the first control circuit includes a first pull-down control circuit, a first pull-down circuit, and a first reset circuit,
  • the first pull-down control circuit is respectively connected to the first node and the second node, and is configured to control the level of the second node under the control of the voltage of the first node;
  • the first pull-down circuit is respectively connected to the first node, the second node, the third power terminal, and the first signal output terminal, and is configured to be at a voltage of the second node. Performing discharge processing on the first node and the first signal output terminal under control;
  • the first reset circuit is respectively connected to the first reset signal terminal, the third power supply terminal, and the first node, and the first reset circuit is configured to control all the signals under the control of the first reset voltage.
  • the voltage of the third power supply terminal is written into the first node.
  • the second control circuit includes the first pull-down control circuit, the first pull-down circuit, and a second reset circuit
  • the first pull-down circuit is further connected to the second signal output terminal, and is further configured to perform a discharge process on the second signal output terminal under the control of the voltage of the second node;
  • the second reset circuit is respectively connected to the second reset signal terminal, the third power supply terminal, and the first node, and the second reset circuit is configured to control all the signals under the control of the second reset voltage.
  • the voltage of the third power supply terminal is written into the first node.
  • the first pull-down control circuit is further connected to the first power supply terminal and the third power supply terminal, respectively, and the first pull-down control circuit is used for Write the first control voltage to the second node under the control of the first control voltage, and write the voltage of the third power supply terminal to the second node under the control of the voltage of the first node Second node.
  • the first input circuit includes a first transistor, and a first pole and a control pole of the first transistor are connected to the first signal input terminal to receive the first signal input terminal.
  • the first input signal is used as the first control signal, and a second pole of the first transistor is connected to the first node;
  • the second input circuit includes a second transistor, and the first pole of the second transistor A control electrode is connected to the second signal input terminal to receive the second input signal as the second control signal, and a second electrode of the second transistor is connected to the first node.
  • the first output circuit includes a third transistor and a first capacitor, and a first pole of the third transistor is connected to the first clock signal terminal, so The second electrode of the third transistor is connected to the first signal output terminal, the control electrode of the third transistor is connected to the first node, and the first terminal of the first capacitor is connected to the first node.
  • a second terminal of the first capacitor is connected to the first signal output terminal;
  • the second output circuit includes a fourth transistor and a second capacitor; a first pole of the fourth transistor is connected to the second clock;
  • the signal terminal is connected, the second electrode of the fourth transistor is connected to the second signal output terminal, the control electrode of the fourth transistor is connected to the first node, and the first terminal of the second capacitor is connected to the The first node is connected, and the second terminal of the second capacitor is connected to the second signal output terminal.
  • the first pull-down control circuit includes a seventh transistor and an eighth transistor, and a first electrode and a control electrode of the seventh transistor are connected to the first power source.
  • the second pole of the seventh transistor is connected to the second node, the first pole of the eighth transistor is connected to the third power terminal, and the second pole of the eighth transistor is connected to the The second node is connected, and the control electrode of the eighth transistor is connected to the first node;
  • the first pull-down circuit includes an eleventh transistor and a twelfth transistor, and the first electrode of the eleventh transistor is connected to The first node is connected, the second pole of the eleventh transistor is connected to the third power terminal, the control pole of the eleventh transistor is connected to the second node, and the twelfth transistor is A first electrode is connected to the first signal output terminal, a second electrode of the twelfth transistor is connected to the third power terminal, and a control electrode of the twelfth transistor is connected to the second node
  • the first pull-down circuit further includes a fifteenth transistor and a sixteenth transistor, and a first pole of the fifteenth transistor and the third node Connected, the second pole of the fifteenth transistor is connected to the third power supply terminal, the control pole of the fifteenth transistor is connected to the second node, and the first pole of the sixteenth transistor is connected to all The second signal output terminal is connected, the second pole of the sixteenth transistor is connected to the third power source terminal, and the control pole of the sixteenth transistor is connected to the second node.
  • the first reset circuit includes a fifth transistor, a first pole of the fifth transistor is connected to the first node, and a first A second pole is connected to the third power source terminal, and a control pole of the fifth transistor is connected to the first reset signal terminal.
  • the second pull-down control circuit includes a ninth transistor and a tenth transistor, and a first electrode and a control electrode of the ninth transistor are connected to the second power source terminal.
  • the second pole of the ninth transistor is connected to the third node
  • the first pole of the tenth transistor is connected to the third power terminal
  • the second pole of the tenth transistor is connected to the third node
  • Three nodes are connected, and a control electrode of the tenth transistor is connected to the first node
  • the second pull-down circuit includes a thirteenth transistor and a fourteenth transistor, and a first electrode of the thirteenth transistor is connected to the first node
  • the first node is connected, the second pole of the thirteenth transistor is connected to the third power supply terminal, the control pole of the thirteenth transistor is connected to the third node, and the first node of the fourteenth transistor is connected
  • An electrode is connected to the second signal output terminal, a second electrode of the fourteenth transistor is connected to the third power source terminal
  • the second pull-down circuit further includes a seventeenth transistor and an eighteenth transistor, and a first pole of the seventeenth transistor is connected to the second node A second pole of the seventeenth transistor is connected to the third power terminal, a control pole of the seventeenth transistor is connected to the third node, and a first pole of the eighteenth transistor is connected to the third node A first signal output terminal is connected, a second electrode of the eighteenth transistor is connected to the third power source terminal, and a control electrode of the eighteenth transistor is connected to the third node.
  • the second reset circuit includes a sixth transistor, a first pole of the sixth transistor is connected to the first node, and a first A second pole is connected to the third power source terminal, and a control pole of the sixth transistor is connected to the second reset signal terminal.
  • Some embodiments of the present disclosure further provide a gate driving circuit, which includes a shift register provided by any one of the above embodiments.
  • Some embodiments of the present disclosure further provide a display device including the gate driving circuit according to any one of the above embodiments.
  • Some embodiments of the present disclosure also provide a method for controlling a shift register according to any one of the above embodiments, including: at the first frame time, under the control of the first input signal, passing the first A shift register unit writes a first control signal into the first node, and writes the first clock signal into the first node through the first shift register unit under the control of the voltage of the first node.
  • the first signal output terminal wherein the first clock signal and the first input signal are pulse signals
  • the second signal passes through the second signal.
  • the shift register unit writes a second control signal into the first node, and writes the second clock signal into the first node through the second shift register unit under the control of the voltage of the first node.
  • the second signal output terminal wherein the second clock signal and the second input signal are pulse signals.
  • the first frame time includes a first input phase, a first output phase, and a first discharge phase
  • the second frame time includes a second input Phase, second output phase, and second discharge phase
  • the control method includes: in the first input phase, the first signal input terminal outputs the first input signal, and the first input circuit is in the first input phase; Write the first control signal to the first node under the control of the first input signal; in the first output stage, the first clock signal terminal outputs the first clock signal, and the first The output circuit outputs the first clock signal to the first signal output terminal under the control of the voltage of the first node; in the first discharge phase, the first reset signal terminal outputs the first clock signal A reset voltage, the first power supply terminal outputs the first control voltage, and the voltage of the third power supply terminal is controlled by the first control circuit under the control of the first reset voltage and the first control voltage Minute Do not write the first node and the first signal output terminal; in the second input stage, the second
  • FIG. 1 is a circuit diagram of a pixel circuit
  • FIG. 2 is a schematic diagram of a driving timing of the pixel circuit shown in FIG. 1;
  • 3A is a schematic block diagram of a shift register according to some embodiments of the present disclosure.
  • 3B is a schematic block diagram of another shift register according to some embodiments of the present disclosure.
  • 3C is a schematic block diagram of still another shift register according to some embodiments of the present disclosure.
  • 4A is a schematic block diagram of a shift register according to some embodiments of the present disclosure.
  • 4B is a schematic block diagram of still another shift register according to other embodiments of the present disclosure.
  • 5A is a circuit schematic diagram of a shift register according to some embodiments of the present disclosure.
  • 5B is a circuit schematic diagram of still another shift register according to some embodiments of the present disclosure.
  • FIG. 6 is a schematic diagram of working timing of the shift register shown in FIG. 4A according to some embodiments of the present disclosure
  • FIG. 7 is a structural schematic diagram of a gate driving circuit provided according to some embodiments of the present disclosure.
  • FIG. 8 is a schematic diagram of an operation timing of the gate driving circuit shown in FIG. 7 according to some embodiments of the present disclosure.
  • FIG. 9 is a schematic block diagram of a display device according to some embodiments of the present disclosure.
  • FIG. 10 is a flowchart of a method for controlling a shift register according to some embodiments of the present disclosure.
  • FIG. 11 is a flowchart of another method for controlling a shift register according to some embodiments of the present disclosure.
  • an AMOLED (Active Matrix Organic Light Emitting Diode) pixel circuit can use two sub-pixel circuits to reduce the threshold voltage drift of the driving tube.
  • Each sub-pixel circuit Includes two thin film transistors (driving transistor and data writing transistor) and a capacitor. In adjacent frames, the driving transistors in the two sub-pixel circuits are turned on in turn, thereby reducing the bias time of each driving transistor and reducing the threshold voltage drift of the driving transistor.
  • the existing gate driving circuit cannot achieve the driving timing required for the pixel circuit.
  • the AMOLED pixel circuit can use two sub-pixel circuits to reduce the threshold voltage drift of the driving tube.
  • the two sub-pixel circuits are a first sub-pixel circuit and a second sub-pixel circuit.
  • the first sub-pixel circuit includes a first sub-pixel circuit.
  • the driving transistor T2, the first data writing transistor T1, and the first storage capacitor C1, and the second sub-pixel circuit includes a second driving transistor T2 ', a second data writing transistor T1', and a second storage capacitor C1 '.
  • the first subpixel circuit and the second subpixel circuit work alternately, that is, within a frame time, the first subpixel circuit works, that is, the first driving transistor T2 and the first data write in FIG.
  • the transistor T1 and the first storage capacitor C1 work, and the second sub-pixel circuit does not work at this time, that is, the second driving transistor T2 ′, the second data writing transistor T1 ′, and the second storage capacitor C1 ′ in FIG. 1 do not work.
  • the second sub-pixel circuit works, that is, the second driving transistor T2 ′, the second data writing transistor T1 ′, and the second storage capacitor C1 ′ in FIG. 1 work, and the first sub-pixel circuit does not work. That is, the first driving transistor T2, the first data writing transistor T1, and the first storage capacitor C1 in FIG. 1 do not work.
  • the driving timing of the pixel circuit in FIG. 1 may be as shown in FIG. 2.
  • the first scan signal Vscan_a and the first data signal Vdata_a are at a high level. Therefore, the first data is written into the transistor T1.
  • the first data signal Vdata_a is written into the gate of the first driving transistor T2; at this time, the second scan signal Vscan_b and the second data signal Vdata_b are at a low level, and thus the second data writing transistor T1 'is turned off; Therefore, in a subsequent period of the Nth frame, the first driving transistor T2 is turned on, and the second driving transistor T2 'is turned off and is in a threshold voltage recovery period.
  • the second scan signal Vscan_b and the second data signal Vdata_b are at a high level. Therefore, the second data writing transistor T1 ′ is turned on, and the second data signal Vdata_b is written into the first The gates of the two driving transistors T2 '; at this time, the first scan signal Vscan_a and the first data signal Vdata_a are at a low level, whereby the first data writing transistor T1 is turned off; therefore, at the subsequent time of the N + 1 frame time Segment, the second driving transistor T2 'is turned on, the first driving transistor T2 is turned off and is in a threshold voltage recovery period. In this way, in adjacent frames, the first driving transistor T2 and the second driving transistor T2 'are turned on in turn, which will greatly reduce the bias time of the driving transistor, thereby greatly reducing the threshold voltage drift of the driving transistor.
  • the gate driver circuit GOA Gate Driver On Array
  • the gate driver circuit GOA can also realize the narrow bezel design of the display panel. And production is more and more widely used.
  • the present disclosure proposes a shift register and a control method thereof, a gate driving circuit, and a display device, so that different driving transistors are turned on alternately at different frames, reducing the threshold voltage drift of the driving transistors, and enabling optimization
  • the requirements for driving timing, and the small number of transistors used overall, make the shift register simpler to implement and reduce costs.
  • the first to eighteenth transistors and the like may be field effect transistors.
  • the field effect transistor can be divided into an N-type transistor and a P-type transistor.
  • the embodiments of the present disclosure regard the field-effect transistor as an N-type transistor (for example, an N-type MOS transistor (NMOS)) as The example illustrates the technical solution of the present disclosure in detail.
  • the field effect transistor of the embodiment of the present disclosure is not limited to N-type transistors.
  • P-type transistors for example, P-type MOS transistors (PMOS)
  • PMOS P-type MOS transistors
  • the field effect transistor used in the embodiments of the present disclosure may be a field effect transistor such as a thin film transistor or other switching devices with the same characteristics.
  • the thin film transistor may include an oxide semiconductor thin film transistor, an amorphous silicon thin film transistor, or a polysilicon thin film. Transistors, etc.
  • the source and drain of the field effect transistor can be symmetrical in structure, so the source and drain of the field effect transistor can be indistinguishable in physical structure.
  • one of the first and second poles is directly described, so all or part of the field in the embodiment of the present disclosure is described.
  • the first and second poles of the effect transistor are interchangeable as required.
  • FIG. 3A is a schematic block diagram of a shift register according to some embodiments of the present disclosure
  • FIG. 3B is a schematic block diagram of another shift register according to some embodiments of the present disclosure.
  • the shift register 100 includes a first shift register unit 101 and a second shift register unit 102.
  • the first shift register unit 101 is electrically connected to the first node pu, the first signal input terminal input_a, the first clock signal terminal clk, and the first signal output terminal output_a.
  • the second shift register unit 102 is connected to the first node pu, the first The two signal input terminals input_b, the second clock signal terminal clkb, and the second signal output terminal output_b are electrically connected.
  • the first shift register unit 101 is configured to write the first control signal to the first node pu under the control of the first input signal provided by the first signal input terminal input_a, and to control the voltage of the first node pu
  • the first clock signal provided by the first clock signal terminal clk is written into the first signal output terminal output_a.
  • the second shift register unit 102 is configured to write the second control signal to the first node pu under the control of the second input signal provided by the second signal input terminal input_b, and to write the second control signal under the control of the voltage of the first node pu.
  • the second clock signal provided by the second clock signal terminal clkb is written into the second signal output terminal output_b.
  • any two adjacent frames include a first frame and a second frame.
  • the first clock signal and the first input signal are pulse signals
  • the second clock signal and the second input signal are DC signals
  • the first clock signal and the first input signal are DC signals
  • the second clock signal and the second input signal are pulse signals. That is, in the multi-frame time, the first clock signal terminal clk outputs pulse signals and DC signals alternately, the first signal input terminal input_a outputs pulse signals and DC signals alternately, and accordingly, the second clock signal terminal clkb also alternately outputs DC signal and pulse signal, and the second signal input terminal input_b also outputs DC signal and pulse signal alternately.
  • the first clock signal terminal clk outputs a pulse signal
  • the first signal input terminal input_a outputs a pulse signal
  • the second clock signal terminal clkb outputs a DC signal
  • the second signal input terminal input_b outputs a DC signal.
  • the first clock signal terminal clk outputs a DC signal
  • the first signal input terminal input_a outputs a DC signal
  • the second clock signal terminal clkb outputs a pulse signal
  • the second signal input Input_b output signal where m is a positive integer.
  • the DC signal may be a low-level DC signal.
  • the first shift register unit 101 includes a first input circuit 11, a first output circuit 12, and a first control circuit 13.
  • the first input circuit 11 and the first signal are respectively The input terminal input_a is connected to the first node pu.
  • the first input circuit 11 is used to write the first control signal to the first node pu under the control of the first input signal provided by the first signal input terminal input_a; the first output circuit 12
  • the first node pu, the first clock signal terminal clk, and the first signal output terminal output_a are respectively connected.
  • the first output circuit 12 is configured to control the first clock signal terminal clk to provide a first signal under the control of the voltage of the first node pu.
  • the clock signal is written into the first signal output terminal output_a; the first control circuit 13 is respectively connected to the first power terminal vdd1, the first node pu, the first reset signal terminal rst_a, the third power terminal vss and the first signal output terminal output_a, The first control circuit 13 is configured to control the voltage of the first signal output terminal output_a and the first node pu under the control of the first control voltage provided by the first power supply terminal vdd1 and the first reset voltage provided by the first reset signal terminal rst_a. Line control.
  • the second shift register unit 102 includes a second input circuit 21, a second output circuit 22, and a second control circuit 23.
  • the second input circuit 21 is respectively connected to the second signal input terminal input_b and the first node pu.
  • the second input circuit 21 is configured to write a second control signal under the control of the second input signal provided by the second signal input terminal input_b.
  • the first node pu; the second output circuit 22 is connected to the first node pu, the second clock signal terminal clkb, and the second signal output terminal output_b, respectively.
  • the second output circuit 22 is used to control the voltage of the first node pu under the control of The second clock signal provided by the second clock signal terminal clkb is written into the second signal output terminal output_b; the second control circuit 23 is connected to the second power terminal vdd2, the first node pu, the second reset signal terminal rst_b, and the third power terminal, respectively.
  • vss is connected to the second signal output terminal output_b, and the second control circuit 23 is configured to output the second signal under the control of the second control voltage provided by the second power supply terminal vdd2 and the second reset voltage provided by the second reset signal terminal rst_b.
  • the terminal output_b and the voltage of the first node pu are controlled.
  • the first control signal is a pulse signal and the second control signal is a DC signal; in the second frame time, the first control signal is a DC signal and the second control signal is a pulse signal.
  • the first control signal is a pulse signal
  • the phase, period, and the like of the first control signal are the same as the first input signal, so that, for example, the first control signal may be the first input signal.
  • the second control signal is a pulse signal
  • the phase, period, and the like of the second control signal are the same as the second input signal, so that the second control signal may be the second input signal. It should be noted that the present disclosure is not limited to this.
  • the first control signal may be a high-level DC signal
  • the second control signal may be a low-level DC signal.
  • One control signal may be a low-level DC signal
  • the second control signal may be a high-level DC signal.
  • the first control signal may be written into the first node pu to charge the first node pu, that is, That is, when the first input signal controls the first input circuit 11 to be turned on, the first node pu may be pulled up by the first control signal.
  • the second control signal can be written to the first node pu to charge the first node pu, that is, at the second When the input signal controls the second input circuit 21 to be turned on, the first node pu can be pulled up by the second control signal.
  • the first power terminal vdd1 outputs a first control voltage
  • the second power terminal vdd2 outputs a second control voltage.
  • the second power supply terminal vdd2 outputs a low-level voltage signal
  • the first power supply terminal vdd1 outputs a low-level voltage signal.
  • the first control voltage and the second control voltage may both be high level, and the pulse signal may be a square wave signal with high and low levels.
  • the pulse signal may change from low level to high at time t1 Signal at a level and at a time t2 after the time t (that is, an interval t time between the time t1 and the time t2) and then changes from a high level to a low level.
  • high level and “low level” in this document refer to two logic states represented by a range of potential heights at a certain position, respectively.
  • a high level can specifically refer to a potential that is higher than the common terminal voltage
  • a low level can specifically refer to a potential that is lower than the common terminal voltage
  • the "high level” potential at different positions can be different
  • the "low-level” potentials at different locations may also be different.
  • the specific potential height range can be set as required in specific application scenarios, and this disclosure does not limit this.
  • the level of the first control voltage output from the first power supply terminal vdd1 can be set to a high level while the second power supply
  • the level of the second control voltage output from the terminal vdd2 is set to a low level.
  • the first node pu and the first signal output terminal output_a will be discharged.
  • the first power terminal will be discharged.
  • the level of the first control voltage output by vdd1 is set to a low level
  • the level of the second control voltage output from the second power supply terminal vdd2 is set to a high level.
  • the first node pu and the second signal will be The output terminal output_b is discharged.
  • FIG. 3C is a schematic block diagram of still another shift register according to some embodiments of the present disclosure.
  • the first shift register unit 101 further includes a first input circuit 11, a first output circuit 12, and a first control circuit 31.
  • the first input circuit 11 and the first control circuit 31 respectively A signal input terminal input_a is connected to the first node pu.
  • the first input circuit 11 is used to write a first control signal to the first node pu under the control of the first input signal provided by the first signal input terminal input_a;
  • the first output The circuit 12 is respectively connected to the first node pu, the first clock signal terminal clk, and the first signal output terminal output_a.
  • the first output circuit 12 is configured to control the voltage provided by the first clock signal terminal clk under the control of the voltage of the first node pu.
  • the first clock signal is written into the first signal output terminal output_a; the first control circuit 31 and the first power terminal vdd1, the first node pu, the first reset signal terminal rst_a, the third power terminal vss, and the first signal output terminal output_a, respectively.
  • the first control circuit 31 is configured to control the first signal output terminal output_a and the first node pu under the control of the first control voltage provided by the first power supply terminal vdd1 and the first reset voltage provided by the first reset signal terminal rst_a. Voltage control.
  • the second shift register unit 102 includes a second input circuit 21, a second output circuit 22, and a second control circuit 32.
  • the second input circuit 21 is respectively connected to the second signal input terminal input_b and the first node pu.
  • the second input circuit 21 is configured to write a second control signal under the control of the second input signal provided by the second signal input terminal input_b.
  • the first node pu; the second output circuit 22 is connected to the first node pu, the second clock signal terminal clkb, and the second signal output terminal output_b, respectively.
  • the second output circuit 22 is used to control the voltage of the first node pu under the control of the voltage of the first node pu.
  • the second clock signal provided by the second clock signal terminal clkb is written into the second signal output terminal output_b; the second control circuit 32 is connected to the first power terminal vdd1, the first node pu, the second reset signal terminal rst_b, and the third power terminal, respectively.
  • vss is connected to the second signal output terminal output_b, and the second control circuit 32 is configured to output the second signal under the control of the first control voltage provided by the first power supply terminal vdd1 and the second reset voltage provided by the second reset signal terminal rst_b.
  • the terminal output_b and the voltage of the first node pu are controlled.
  • the first power terminal vdd1 outputs a first control voltage
  • the first control voltage may be a high level
  • the first clock signal output from the first clock signal terminal clk can be set to a square wave with high and low pulses within one frame time.
  • the second clock signal output from the second clock signal terminal clkb is set to a low-level DC signal
  • the second clock signal output from the second clock signal terminal clkb is set to have High-low pulse square wave signals
  • the first clock signal output from the first clock signal terminal clk is set to a low-level DC signal.
  • the signal of the first signal output terminal output_a and the signal of the second signal output terminal output_b can be respectively provided to the first scan signal Vscan_a and the second scan signal Vscan_b in FIG. 1, that is, the first signal
  • the signal at the output terminal output_a corresponds to the first scan signal Vscan_a in FIG. 1
  • the signal at the second signal output terminal output_b corresponds to the second scan signal Vscan_b in FIG. 1.
  • the first output circuit 12 writes the voltage of the first clock signal terminal clk to the first signal output terminal output_a, and the first clock signal output at the first clock signal terminal clk
  • the signal output from the first signal output terminal output_a is high, so that, for example, the first sub-pixel circuit in FIG. 1 (that is, the first data writing transistor T1, the first driving transistor T2, and the first capacitor can be driven.
  • C1 works, and the second output circuit 22 writes the voltage of the second clock signal terminal clkb to the second signal output terminal output_b.
  • the second The signal output terminal output_b always outputs a low-level signal, so that pixel driving cannot be performed.
  • the second sub-pixel circuit in FIG. 1 that is, the second data writing transistor T1 ′, the second driving transistor T2 ′, and the second capacitor cannot be driven.
  • C1 ' work, that is, the second sub-pixel circuit does not work.
  • the driving timing of the Nth frame in FIG. 2 can be implemented to drive the pixel circuit shown in FIG. 1.
  • the second output circuit 22 writes the voltage of the second clock signal terminal clkb to the second signal output terminal output_b.
  • the second clock signal is high, the signal output from the second signal output terminal output_b is high, so that, for example, the second sub-pixel circuit (ie, the second data writing transistor T1 ', the second driving transistor in FIG. 1) can be driven.
  • T2 'and the second capacitor C1') work, and the first output circuit 12 writes the voltage of the first clock signal terminal clk to the first signal output terminal output_a, because the first clock signal output from the first clock signal terminal clk is low Level, so that the first signal output terminal output_a always outputs a low-level signal, so that pixel driving cannot be performed.
  • the first sub-pixel circuit in FIG. 1 that is, the first data writing transistor T1 and the first driving transistor cannot be driven.
  • T2 and the first capacitor C1) work, that is, the first sub-pixel circuit does not work.
  • the driving timing of the (N + 1) -th frame in FIG. 2 can be realized to drive the pixel circuit shown in FIG. 1.
  • the first shift register unit 101 and the second shift register unit 102 can alternately perform pixel driving, realize a driving timing required for a pixel circuit employing two sets of driving designs, and are easy to implement.
  • FIG. 4A is a schematic block diagram of a shift register according to other embodiments of the present disclosure.
  • the shift register shown in FIG. 4A is an example of the shift register shown in FIG. 3B.
  • the first control circuit 13 includes a first reset circuit 14, a first pull-down control circuit 15, and a first pull-down circuit 16.
  • the first reset circuit 14 is configured to reset the first node pu under the control of the first reset signal terminal rst_a. As shown in FIG. 4A, the first reset circuit 14 is connected to the first reset signal terminal rst_a, the third power supply terminal vss, and the first node pu, respectively. The first reset circuit 14 is used for the first reset signal terminal rst_a provided. The voltage of the third power supply terminal vss is written into the first node pu under the control of the reset voltage.
  • the first pull-down control circuit 15 is respectively connected to the first node pu and the second node pd1, and is configured to control the level of the second node pd1 under the control of the voltage of the first node pu. As shown in FIG. 4A, the first pull-down control circuit 15 is also connected to the first power terminal vdd1 and the third power terminal vss, respectively. The first pull-down control circuit 15 is used for a first control voltage provided at the first power terminal vdd1. The first control voltage is written into the second node pd1 under the control of the control, and the voltage of the third power supply terminal vss is written into the second node pd1 under the control of the voltage of the first node pu.
  • the first pull-down circuit 16 is connected to the second node pd1, the first node pu, the third power terminal vss, and the first signal output terminal output_a, respectively.
  • the first pull-down circuit 16 is used for the second node Under the control of the voltage of pd1, the first node pu and the first signal output terminal output_a are discharged.
  • the second control circuit 23 includes a second reset circuit 24, a second pull-down control circuit 25, and a second pull-down circuit 26.
  • the second reset circuit 24 is configured to reset the first node pu under the control of the second reset signal terminal rst_b. As shown in FIG. 4A, the second reset circuit 24 is connected to the second reset signal terminal rst_b, the third power supply terminal vss, and the first node pu, respectively. The second reset circuit 24 is used for the second reset signal terminal rst_b provided by The voltage of the third power supply terminal vss is written into the first node pu under the control of the reset voltage.
  • the second pull-down control circuit 25 is respectively connected to the first node pu and the third node pd2, and is configured to control the level of the third node pd2 under the control of the voltage of the first node pu. As shown in FIG. 4A, the second pull-down control circuit 25 is also connected to the second power supply terminal vdd2 and the third power supply terminal vss, respectively. The second pull-down control circuit 25 is used to control the second control voltage provided by the second power supply terminal vdd2. The second control voltage is written into the third node pd2, and the voltage of the third power supply terminal vss is written into the third node pd2 under the control of the voltage of the first node pu.
  • the second pull-down circuit 26 is connected to the third node pd2, the first node pu, the third power terminal vss, and the second signal output terminal output_b, respectively.
  • the second pull-down circuit 26 is used for the third node pd2. Under the control of the voltage, the first node pu and the second signal output terminal output_b are discharged.
  • the first pull-down circuit 16 is further connected to the third node pd2 and the second signal output terminal output_b, and the first pull-down circuit 16 is also used to control the voltage of the second node pd1.
  • the third node pd2 and the second signal output terminal output_b perform discharge processing;
  • the second pull-down circuit 26 is also connected to the second node pd1 and the first signal output terminal output_a, and the second pull-down circuit 26 is also used for voltage at the third node pd2 Discharge processing is performed on the second node pd1 and the first signal output terminal output_a under the control of.
  • the level of the first control voltage output from the first power supply terminal vdd1 is set to a high level, while the second control output from the second power supply terminal vdd2 is set to a high level.
  • the voltage level is set to a low level.
  • the first node pu and the first signal output terminal output_a are discharged, and the second signal output terminal output_b is also discharged.
  • the level of the first control voltage output from the first power supply terminal vdd1 is set to a low level, and the second control output from the second power supply terminal vdd2 is set at the same time.
  • the voltage level is set to a high level.
  • the first node pu and the second signal output terminal output_b are discharged, and the first signal output terminal output_a is also discharged.
  • FIG. 4B is a schematic block diagram of another type of shift register according to other embodiments of the present disclosure.
  • the shift register shown in FIG. 4B is an example of the shift register shown in FIG. 3C.
  • the first control circuit 31 includes a first pull-down control circuit 34, a first pull-down circuit 35, and a first reset circuit 33.
  • the first pull-down control circuit 34 is respectively connected to the first node pu and the second node pd1, and is configured to control the level of the second node pd1 under the control of the voltage of the first node pu. As shown in FIG. 4B, the first pull-down control circuit 34 is also connected to the first power terminal vdd1 and the third power terminal vss, respectively. The first pull-down control circuit 34 is used for a first control voltage provided at the first power terminal vdd1. The first control voltage is written into the second node pd1 under the control of the control, and the voltage of the third power supply terminal vss is written into the second node pd1 under the control of the voltage of the first node pu.
  • the first pull-down circuit 35 is connected to the first node pu, the second node pd1, the third power terminal vss, and the first signal output terminal output_a, and is configured to be connected to the second node pd1. Under the control of the voltage, the first node pu and the first signal output terminal output_a are discharged.
  • the first reset circuit 33 is connected to the first reset signal terminal rst_a, the third power supply terminal vss, and the first node pu, respectively.
  • the first reset circuit 33 is configured to provide the first reset signal terminal rst_a
  • the voltage of the third power supply terminal vss is written into the first node pu under the control of the first reset voltage.
  • the second control circuit 32 includes a first pull-down control circuit 34, a first pull-down circuit 35, and a second reset circuit 36, that is, in this example, the first control circuit 31 and The second control circuit 32 can share the first pull-down control circuit 34 and the first pull-down circuit 35, thereby further saving the number of transistors and saving costs.
  • the first pull-down circuit 34 is also connected to the second signal output terminal output_a, and is also configured to perform a discharge process on the second signal output terminal output_a under the control of the voltage of the second node pd1. .
  • the second reset circuit 36 is connected to the second reset signal terminal rst_b, the third power supply terminal vss, and the first node pu, respectively.
  • the second reset circuit 36 is used to control the second reset voltage provided at the second reset signal terminal rst_b.
  • the voltage of the third power supply terminal vss is written into the first node pu.
  • the "first node” is a pull-up node
  • the "second node” and “third node” are both pull-down nodes.
  • the term “pull-up” means charging a node or an electrode of a transistor so that the node or the electrode The absolute value of the level is increased to achieve the operation of the corresponding transistor (for example, turn on); “pulling down” means discharging a node or an electrode of a transistor so that the absolute value of the level of the node or the electrode Lowered, thereby enabling operation (eg, off) of the corresponding transistor.
  • pulse-up means discharging a node or an electrode of a transistor so that the absolute value of the level of the node or the electrode is reduced, thereby realizing the corresponding transistor.
  • Operation (such as turning on); “pull-down” means charging a node or an electrode of a transistor so that the absolute value of the level of the node or the electrode increases, thereby realizing the operation of the corresponding transistor (such as turning off) .
  • the first frame time in any two adjacent frames includes the first input phase, the first output phase, and the first discharge phase
  • the second frame time in any two adjacent frames includes the second input phase, the second Output stage and second discharge stage.
  • the working process of the shift register 100 is as follows:
  • the first signal input terminal input_a outputs the first input signal
  • the first input circuit 11 is controlled by the first input signal to the first The node pu writes the first input signal.
  • the first clock signal terminal clk outputs a first clock signal, and at this time the first clock signal has a first level, and the first output circuit 12 is controlled by the voltage of the first node pu to the first The signal output terminal output_a outputs a first clock signal. It should be noted that at this time, the voltage signal of the first node pu is greater than the first input signal.
  • the first reset signal terminal rst_a outputs a first reset voltage
  • the first power supply terminal vdd1 outputs a first control voltage
  • the first reset circuit 14 of the first control circuit 13 is controlled by the first reset voltage to the first One node pu outputs the voltage from the third power supply terminal vss.
  • the first pull-down control circuit 15 of the first control circuit 13 outputs the first control voltage to the second node pd1 under the control of the first control voltage.
  • the first pull-down circuit 16 of 13 outputs the voltage from the third power supply terminal vss to the first node pu and the first signal output terminal output_a under the control of the second node pd1, respectively.
  • the second signal input terminal input_b outputs the second input signal
  • the second input circuit 21 is controlled by the second input signal to the first node. pu writes the second input signal.
  • the second clock signal terminal clkb outputs a second clock signal, and at this time the second clock signal has a first level, and the second output circuit 22 is controlled by the voltage of the first node pu to the second The signal output terminal input_b outputs a second clock signal. It should be noted that at this time, the voltage signal of the first node pu is greater than the second input signal.
  • the second reset signal terminal rst_b outputs a second reset voltage
  • the second power supply terminal vdd2 outputs a second control voltage
  • the second reset circuit 24 of the second control circuit 23 is controlled by the second reset voltage to the first One node pu outputs the voltage from the third power supply terminal vss.
  • the second pull-down control circuit 25 of the second control circuit 23 outputs the second control voltage to the third node pd2 under the control of the second control voltage.
  • the second control circuit 23 The second pull-down circuit 26 under the control of the third node pd2 outputs the voltage from the third power supply terminal vss to the first node pu and the second signal output terminal output_b, respectively.
  • the first frame time includes a first intermediate stage, and the first intermediate stage is between the first output stage and the first discharge stage.
  • the first clock signal terminal clk outputs a first clock signal
  • the first node pu holds the first input signal
  • the first output circuit 12 is at the first node Under the control of pu
  • a first clock signal having a second level is output to the first signal output terminal input_a.
  • the second frame time includes a second intermediate stage, and the second intermediate stage is between the second output stage and the second discharge stage.
  • the second clock signal terminal clkb outputs a second clock signal, and at this time the second clock signal has a second level, the first node pu holds the second input signal, and the second output circuit 22 is at the first node Under the control of pu, a second clock signal having a second level is output to the second signal output terminal input_b.
  • the first level, the level of the first input signal, the level of the second input signal, the level of the first reset voltage, the level of the second reset voltage, and the first control voltage Both the level of and the level of the second control voltage can be high, and the level of the voltage at the third power supply terminal vss and the second level can be low.
  • the working process of the shift register 100 may include:
  • the first input signal output from the first signal input terminal input_a has a high level
  • the first input circuit 11 is turned on
  • the first input signal is written into the first node pu
  • the first output circuit 12 and the second
  • the output circuit 22 is turned on under the control of the first node pu. Therefore, the first signal output terminal output_a outputs a first clock signal
  • the second signal output terminal output_b outputs a second clock signal.
  • Both the clock signal and the second clock signal output from the second clock signal terminal clkb have a low level, that is, the first signal output terminal output_a and the second signal output terminal output_b output a signal with a low level.
  • the second input signal output from the second signal input terminal input_b has a low level, so the second input circuit 21 is turned off. Because the level of the first node pu is high, under the control of the first node pu, the first pull-down control circuit 15 writes the voltage of the third power supply terminal vss to the second node pd1, and the second pull-down control circuit 25 Write the voltage of the third power supply terminal vss to the third node pd2. Both the first reset voltage output from the first reset signal terminal rst_a and the second reset voltage output from the second reset signal terminal rst_b are, for example, low-level voltages. Therefore, the first reset circuit 14 and the second reset circuit 24 are turned off. Thus, in the first input stage, the first node pu is charged to a high level (for example, the first input signal), and the first signal output terminal output_a and the second signal output terminal output_b output signals having a low level.
  • a high level for example, the first input signal
  • the first input signal outputted from the first signal input terminal input_a and the second input signal outputted from the second signal input terminal input_b have, for example, low levels.
  • the first input circuit 11 and the second input circuit 21 is turned off, but due to the capacitance retention of the first output circuit 12 and the second output circuit 22, the first output circuit 12 and the second output circuit 22 continue to be turned on, and the first output circuit 12 outputs a first clock signal to the first signal
  • the output terminal output_a that is, the first signal output terminal output_a outputs the first clock signal. Because the first clock signal output by the first clock signal terminal clk has a high level, therefore, the first signal output terminal output_a outputs a signal with a high level. .
  • the second output circuit 22 outputs the second clock signal to the second signal output terminal output_b, that is, the second signal output terminal output_b outputs the second clock signal, and the second clock signal terminal clkb outputs the first clock signal.
  • the two clock signals have a low level, so the second signal output terminal output_b outputs a signal with a low level.
  • the voltage of the first node pu further increases, that is, the voltage signal at the first node pu at this time is greater than the first input signal, and thus at the first Under the control of the node pu, the first pull-down control circuit 15 writes the voltage of the third power supply terminal vss to the second node pd1, and the second pull-down control circuit 25 writes the voltage of the third power supply terminal vss to the third node pd2.
  • the first reset voltage output from the first reset signal terminal rst_a and the second reset voltage output from the second reset signal terminal rst_b are both low-level voltages. Therefore, the first reset circuit 14 and the second reset circuit 24 are turned off.
  • the first input signal output from the first signal input terminal input_a and the second input signal output from the second signal input terminal input_b have, for example, a low level.
  • the first input circuit 11 and the second input circuit 21 is turned off, but due to the capacitance retaining function of the first output circuit 12 and the second output circuit 22, the first output circuit 12 and the second output circuit 22 continue to be turned on, because the first clock signal output from the first clock signal terminal clk and The second clock signal output from the second clock signal terminal clkb has a low level.
  • the first signal output terminal output_a outputs the first clock signal and the second signal output terminal output_b outputs the second clock signal, that is, the first signal
  • the output terminal output_a and the second signal output terminal output_b each output a signal having a low level. Since the pu point of the first node is still high (for example, the first input signal), the second node pd1 and the third node pd2 remain at the voltage of the third power supply terminal vss. Both the first reset voltage output from the first reset signal terminal rst_a and the second reset voltage output from the second reset signal terminal rst_b are low-level voltages. Therefore, the first reset circuit 14 and the second reset circuit 24 are turned off.
  • the first reset voltage output from the first reset signal terminal rst_a has a high level
  • the first reset circuit 14 is turned on
  • the first node pu is discharged to a low level, that is, the voltage of the first node pu is pulled down
  • the voltage to the third power supply terminal vss so the first output circuit 12 and the second output circuit 22 are turned off.
  • the first pull-down control circuit 15 Since the first control voltage has a high level, the first pull-down control circuit 15 writes the first control voltage into the second Node pd1, that is, the second node pd1 is written with a high-level voltage, and the first pull-down circuit 16 is turned on, so that the first node pu, the first signal output terminal output_a, and the second signal output terminal output_b are discharged to low.
  • the level, that is, the voltage of the first node pu, the first signal output terminal output_a, and the second signal output terminal output_b is pulled down to the third power supply terminal vss. Because the second control voltage has a low level, the potential of the third node pd2 is still low, and the second pull-down circuit 26 is turned off.
  • the second reset voltage output from the second reset signal terminal rst_b is a low-level voltage, and the second reset circuit 24 is turned off.
  • the working process of the shift register 100 may include:
  • the second input signal output from the second signal input terminal input_b has a high level
  • the second input circuit 21 is turned on
  • the second input signal is written into the first node pu
  • the first output circuit 12 and the second The output circuit 22 is turned on under the control of the first node pu. Therefore, the first signal output terminal output_a outputs a first clock signal
  • the second signal output terminal output_b outputs a second clock signal.
  • Both the clock signal and the second clock signal output from the second clock signal terminal clkb have a low level, that is, the first signal output terminal output_a and the second signal output terminal output_b output a signal with a low level.
  • the first input signal output from the first signal input terminal input_a has a low level, so the first input circuit 11 is turned off. Because the level of the first node pu is high, under the control of the first node pu, the first pull-down control circuit 15 writes the voltage of the third power supply terminal vss to the second node pd1, and the second pull-down control circuit 25 Write the voltage of the third power supply terminal vss to the third node pd2.
  • Both the first reset voltage output from the first reset signal terminal rst_a and the second reset voltage output from the second reset signal terminal rst_b are, for example, low-level voltages. Therefore, the first reset circuit 14 and the second reset circuit 24 are turned off. Therefore, in the second input stage, the first node pu is charged to a high level (for example, a second input signal), and the first signal output terminal output_a and the second signal output terminal output_b output signals having a low level.
  • the first input signal output from the first signal input terminal input_a and the second input signal output from the second signal input terminal input_b have, for example, a low level.
  • the first input circuit 11 and the second input circuit 21 is turned off, but due to the capacitance retention of the first output circuit 12 and the second output circuit 22, the first output circuit 12 and the second output circuit 22 continue to be turned on, and the second output circuit 22 outputs a second clock signal to the second signal
  • the output terminal output_b that is, the second signal output terminal output_b outputs a second clock signal, because the second clock signal output by the second clock signal terminal clkb has a high level, therefore, the second signal output terminal output_b outputs a signal with a high level .
  • the first output circuit 12 outputs the first clock signal to the first signal output terminal output_a, that is, the first signal output terminal output_a outputs the first clock signal, and the first clock signal terminal clk outputs
  • the first clock signal has a low level, so the first signal output terminal output_a outputs a signal with a low level.
  • the voltage of the first node pu further increases, that is, the voltage signal at the first node pu at this time is greater than the first input signal, and thus at the first Under the control of the node pu, the first pull-down control circuit 15 writes the voltage of the third power supply terminal vss to the second node pd1, and the second pull-down control circuit 25 writes the voltage of the third power supply terminal vss to the third node pd2.
  • Both the first reset voltage output from the first reset signal terminal rst_a and the second reset voltage output from the second reset signal terminal rst_b are low-level voltages. Therefore, the first reset circuit 14 and the second reset circuit 24 are turned off.
  • both the first input signal outputted from the first signal input terminal input_a and the second input signal outputted from the second signal input terminal input_b have low levels.
  • the first input circuit 11 and the second input circuit 21 Is turned off, but due to the capacitance retention of the first output circuit 12 and the second output circuit 22, the first output circuit 12 and the second output circuit 22 continue to be turned on, because the first clock signal and the first clock signal output from the first clock signal terminal clk
  • the second clock signal output from the two clock signal terminals clkb has a low level.
  • the first signal output terminal output_a outputs the first clock signal
  • the second signal output terminal output_b outputs the second clock signal, that is, the first signal output Both the terminal output_a and the second signal output terminal output_b output signals having a low level. Since the pu point of the first node is still high (for example, the second input signal), the second node pd1 and the third node pd2 remain at the voltage of the third power supply terminal vss. Both the first reset voltage output from the first reset signal terminal rst_a and the second reset voltage output from the second reset signal terminal rst_b are low-level voltages. Therefore, the first reset circuit 14 and the second reset circuit 24 are turned off.
  • the first reset voltage output from the second reset signal terminal rst_b has a high level
  • the second reset circuit 24 is turned on
  • the first node pu is discharged to a low level, that is, the voltage of the first node pu is pulled down
  • the voltage to the third power supply terminal vss so the first output circuit 12 and the second output circuit 22 are turned off.
  • the second pull-down control circuit 25 Since the second control voltage has a high level, the second pull-down control circuit 25 writes the second control voltage to the third node pd2, that is, the third node pd2 is written with a high-level voltage, and the second pull-down circuit 26 is turned on, so that the first node pu, the first signal output terminal output_a, and the second signal output terminal output_b are discharged to a low level That is, the first node pu, the first signal output terminal output_a and the second signal output terminal output_b are pulled down to the voltage of the third power supply terminal vss. Because the first control voltage has a low level, the second node pd1 is still at a low level, and the first pull-down circuit 16 is turned off. The first reset voltage output from the first reset signal terminal rst_a is a low-level voltage, and the first reset circuit 14 is turned off.
  • the first shift register unit can be made. 101 and the second shift register unit 102 alternately perform pixel driving in different frames, thereby realizing the pixel driving timing in FIG. 2.
  • FIG. 5A is a circuit schematic diagram of a shift register according to some embodiments of the present disclosure. The circuit structure of the shift register according to some embodiments of the present disclosure will be described in detail below with reference to FIG. 5A.
  • FIG. 5A is a circuit structure of the shift register shown in FIG. 4A.
  • the first input circuit 11 includes a first transistor M1, and a first pole and a control pole of the first transistor M1 are connected to a first signal input terminal input_a to receive the first input signal as the first control signal.
  • the second electrode of the first transistor M1 is connected to the first node pu;
  • the second input circuit 21 includes a second transistor M2, and the first and control electrodes of the second transistor M2 are connected to the second signal input terminal input_b to receive the second input
  • the signal is used as the second control signal, and the second pole of the second transistor M2 is connected to the first node pu.
  • the first output circuit 12 includes a third transistor M3 and a first capacitor C11, a first pole of the third transistor M3 is connected to the first clock signal terminal clk, and a second pole of the third transistor M3 is connected to
  • the first signal output terminal output_a is connected
  • the control electrode of the third transistor M3 is connected to the first node pu
  • the first terminal of the first capacitor C11 is connected to the first node pu
  • the second terminal of the first capacitor C11 is output to the first signal
  • the second output circuit 22 includes a fourth transistor M4 and a second capacitor C22.
  • the first pole of the fourth transistor M4 is connected to the second clock signal terminal clkb
  • the second pole of the fourth transistor M4 is connected to the second signal output.
  • the terminal output_b is connected, the control electrode of the fourth transistor M4 is connected to the first node pu, the first terminal of the second capacitor C22 is connected to the first node pu, and the second terminal of the second capacitor C22 is connected to the second signal output terminal output_b.
  • the first reset circuit 14 includes a fifth transistor M5, a first pole of the fifth transistor M5 is connected to the first node pu, a second pole of the fifth transistor M5 is connected to the third power supply terminal vss, and a fifth The control pole of the transistor M5 is connected to the first reset signal terminal rst_a; the second reset circuit 24 includes a sixth transistor M6, the first pole of the sixth transistor M6 is connected to the first node pu, and the second pole of the sixth transistor M6 is connected to the first node pu.
  • the three power supply terminals vss are connected, and the control electrode of the sixth transistor M6 is connected to the second reset signal terminal rst_b.
  • the first pull-down control circuit 15 includes a seventh transistor M7 and an eighth transistor M8.
  • the first electrode and the control electrode of the seventh transistor M7 are connected to the first power terminal vdd1, and the second of the seventh transistor M7 is Electrode is connected to the second node pd1, the first electrode of the eighth transistor M8 is connected to the third power supply terminal vss, the second electrode of the eighth transistor M8 is connected to the second node pd1, and the control electrode of the eighth transistor M8 is connected to the first node pu is connected;
  • the second pull-down control circuit 25 includes a ninth transistor M9 and a tenth transistor M10, a first pole and a control pole of the ninth transistor M9 are connected to the second power terminal vdd2, and a second pole of the ninth transistor M9 is connected to the third The node pd2 is connected, the first pole of the tenth transistor M10 is connected to the third power terminal vss, the second pole of the tenth transistor M10 is connected
  • the first pull-down circuit 16 includes an eleventh transistor M11 and a twelfth transistor M12, a first pole of the eleventh transistor M11 is connected to the first node pu, and a second pole of the eleventh transistor M11 Connected to the third power supply terminal vss, the control electrode of the eleventh transistor M11 is connected to the second node pd1, the first electrode of the twelfth transistor M12 is connected to the first signal output terminal output_a, and the second electrode of the twelfth transistor M12 Connected to the third power terminal vss, the control electrode of the twelfth transistor M12 is connected to the second node pd1;
  • the second pull-down circuit 26 includes a thirteenth transistor M13 and a fourteenth transistor M14, and a first electrode of the thirteenth transistor M13 Connected to the first node pu, the second electrode of the thirteenth transistor M13 is connected to the third power terminal vss, the control electrode of the thirteenth transistor M
  • the first pull-down circuit 16 further includes a fifteenth transistor M15 and a sixteenth transistor M16, a first pole of the fifteenth transistor M15 is connected to the third node pd2, and a second of the fifteenth transistor M15 is Electrode is connected to the third power terminal vss, the control electrode of the fifteenth transistor M15 is connected to the second node pd1, the first electrode of the sixteenth transistor M16 is connected to the second signal output terminal output_b, and the second of the sixteenth transistor M16 is Is connected to the third power supply terminal vss, and the control electrode of the sixteenth transistor M16 is connected to the second node pd1; the second pull-down circuit 26 further includes a seventeenth transistor M17 and an eighteenth transistor M18, One pole is connected to the second node pd1, the second pole of the seventeenth transistor M17 is connected to the third power supply terminal vss, the control pole of the seventeenth transistor M17 is connected to the third node pd2,
  • FIG. 5B is a circuit schematic diagram of another shift register according to some embodiments of the present disclosure, and FIG. 5B is a circuit structure of the shift register shown in FIG. 4B.
  • the shift register shown in FIG. 4B may not include the ninth transistor M9, the tenth transistor M10, the thirteenth transistor M13, the fourteenth transistor M14, The fifteenth transistor M15, the seventeenth transistor M17, and the eighteenth transistor M18.
  • the shift register shown in FIG. 5B may include first to eighth transistors M1 to M8, an eleventh transistor M11, a twelfth transistor M12, a sixteenth transistor M16, a first capacitor C11, and a second capacitor C22.
  • the connection methods of the transistors M1 to eighth transistor M8, the eleventh transistor M11, the twelfth transistor M12, the sixteenth transistor M16, the first capacitor C11, and the second capacitor C22 are the same as those shown in FIG. 5A.
  • the first input circuit 11 includes a first transistor M1, and a first pole and a control pole of the first transistor M1 are connected to the first signal input terminal input_a to receive the first input signal as the first control signal.
  • the second electrode of the first transistor M1 is connected to the first node pu;
  • the second input circuit 21 includes a second transistor M2, and the first and control electrodes of the second transistor M2 are connected to the second signal input terminal input_b to receive the second input
  • the signal is used as the second control signal, and the second pole of the second transistor M2 is connected to the first node pu.
  • the first output circuit 12 includes a third transistor M3 and a first capacitor C11, a first pole of the third transistor M3 is connected to the first clock signal terminal clk, and a second pole of the third transistor M3 is connected to the first
  • the signal output terminal output_a is connected, the control electrode of the third transistor M3 is connected to the first node pu, the first terminal of the first capacitor C11 is connected to the first node pu, and the second terminal of the first capacitor C11 is connected to the first signal output terminal output_a
  • the second output circuit 22 includes a fourth transistor M4 and a second capacitor C22.
  • the first pole of the fourth transistor M4 is connected to the second clock signal terminal clkb, and the second pole of the fourth transistor M4 is connected to the second signal output terminal output_b.
  • the control electrode of the fourth transistor M4 is connected to the first node pu, the first terminal of the second capacitor C22 is connected to the first node pu, and the second terminal of the second capacitor C22 is connected to the second signal output terminal output_b.
  • the first reset circuit 33 includes a fifth transistor M5, a first pole of the fifth transistor M5 is connected to the first node pu, a second pole of the fifth transistor M5 is connected to the third power supply terminal vss, and a fifth The control pole of the transistor M5 is connected to the first reset signal terminal rst_a;
  • the second reset circuit 36 includes a sixth transistor M6, the first pole of the sixth transistor M6 is connected to the first node pu, and the second pole of the sixth transistor M6 is connected to the first The three power supply terminals vss are connected, and the control electrode of the sixth transistor M6 is connected to the second reset signal terminal rst_b.
  • the first pull-down control circuit 34 includes a seventh transistor M7 and an eighth transistor M8.
  • the first and control electrodes of the seventh transistor M7 are connected to the first power terminal vdd1, and the second of the seventh transistor M7 is Electrode is connected to the second node pd1, the first electrode of the eighth transistor M8 is connected to the third power supply terminal vss, the second electrode of the eighth transistor M8 is connected to the second node pd1, and the control electrode of the eighth transistor M8 is connected to the first node pu connected.
  • the first pull-down circuit 35 includes an eleventh transistor M11, a twelfth transistor M12, and a sixteenth transistor M16.
  • the first pole of the eleventh transistor M11 is connected to the first node pu.
  • the second pole of the transistor M11 is connected to the third power terminal vss
  • the control pole of the eleventh transistor M11 is connected to the second node pd1
  • the first pole of the twelfth transistor M12 is connected to the first signal output terminal output_a
  • the second pole of the transistor M12 is connected to the third power terminal vss
  • the control pole of the twelfth transistor M12 is connected to the second node pd1
  • the first pole of the sixteenth transistor M16 is connected to the second signal output terminal output_b
  • the sixteenth The second electrode of the transistor M16 is connected to the third power supply terminal vss
  • the control electrode of the sixteenth transistor M16 is connected to the second node pd1.
  • the second reset circuit 36 includes a sixth transistor M6, the first pole of the sixth transistor M6 is connected to the first node pu, the second pole of the sixth transistor M6 is connected to the third power terminal vss, and the sixth The control electrode of the transistor M6 is connected to the second reset signal terminal rst_b.
  • control electrode of the transistor may refer to the gate
  • first electrode of the transistor may refer to the drain
  • second electrode of the transistor may refer to the source
  • the first control voltage is a high-level voltage
  • the second control voltage is a low-level voltage
  • the first clock signal is a pulse signal
  • the second clock signal is a low-level DC signal.
  • the timing chart in FIG. 5 describes the working process of the shift register shown in FIG. 5A in detail.
  • vdd1, vdd2, input_a, input_b, clk, clkb, rst_a, rst_b, etc. are used to indicate both the corresponding signal end and the corresponding signal.
  • the following embodiments are the same, and will not be described again.
  • the seventh transistor M7 Since the first control voltage vdd1 is a high-level voltage, the seventh transistor M7 is always turned on within one frame time, and the second control voltage vdd2 is a low-level voltage, so the ninth transistor M9 is always turned off within one frame time.
  • the time period t1 corresponds to the first input stage.
  • the first input signal input_a has a high level
  • the second input signal input_b has a high level
  • the first clock signal clk has a high level
  • the signal clkb, the first reset voltage rst_a, and the second reset voltage rst_b all have a low level.
  • the first transistor M1 is turned on, and the first input signal input_a is written to the first node pu
  • the third transistor M3 and the fourth transistor M4 are turned on, so that the first signal output terminal output_a outputs the first clock signal clk, and the second signal output terminal output_b outputs the second clock signal clkb
  • the first clock signal clk and the second clock signal clkb are low-level signals
  • the first signal output terminal output_a and the second signal output terminal output_b output low-level signals. Because the second input signal input_b has a low level, the second transistor M2 is turned off.
  • the eighth transistor M8 and the tenth transistor M10 are turned on, the second node pd1 is pulled to a low voltage (that is, the voltage of the third power supply terminal vss), and the third node pd2 Is pulled to a low level voltage (ie, the voltage of the third power supply terminal vss). Since the second node pd1 and the third node pd2 are pulled to the voltage of the third power supply terminal vss, the eleventh to eighteenth transistors M11 to M18 are all turned off.
  • the fifth transistor M5 and the sixth transistor M6 are turned off. Therefore, in the first input stage, the first node pu can be charged to the first input signal, the third transistor M3 and the fourth transistor M4 are turned on, and the output of the first signal output terminal output_a and the second signal output terminal output_b has Low-level signals.
  • the seventh transistor M7 and the eighth transistor M8 are both turned on. Since the seventh transistor M7 charges the second node pd1, the eighth transistor M8 discharges the second node pd1.
  • the two-node pd1 can be pulled to a low-level voltage, which can be achieved by appropriately setting the channel width ratio of the seventh transistor M7 and the eighth transistor M8.
  • W (M8) of the eight transistor M8 is much larger than the channel width W (M7) of the seventh transistor M7, so that the discharge speed of the second node pd1 when the eighth transistor M8 is turned on is much greater than that when the seventh transistor M7 is turned on.
  • the charging speed of the second node pd1 so whether the seventh transistor M7 is turned on or not, as long as the eighth transistor M8 is turned on, the second node pd1 can be pulled to a low voltage.
  • the time period t2 corresponds to the first output stage.
  • the first clock signal clk has a high level
  • the signal clkb, the first reset voltage rst_a, and the second reset voltage rst_b all have a low level.
  • the first transistor M1 and the second transistor M2 are turned off, but due to the holding effect of the first capacitor C11 and the second capacitor C22, the third The transistor M3 and the fourth transistor M4 continue to be turned on.
  • the third transistor M3 outputs a high level signal to the first signal output terminal output_a, that is, the first signal output terminal output_a outputs a high level.
  • the potential of the first node pu is further pulled up, and at this time, the potential peak of the first node pu becomes approximately twice the original value.
  • the fourth transistor M4 since the fourth transistor M4 is turned on and the second clock signal clkb still has a low level, the second signal output terminal output_b still outputs a low level signal. Because the discharge speed of the eighth transistor M8 is much faster than the discharge speed of the seventh transistor M7, the potential of the second node pd1 is still low.
  • the tenth transistor M10 is turned on, and the second control voltage vdd2 has a low level, so the potential of the third node pd2 is still low. Since the potentials of the second node pd1 and the third node pd2 are both low, the eleventh to eighteenth transistors M11 to M18 are all turned off. Since the first reset voltage rst_a and the second reset voltage rst_b are both low-level voltages, the fifth transistor M5 and the sixth transistor M6 are both turned off.
  • the time period t3 corresponds to the first intermediate stage (or the reset stage of the first signal output terminal output_a).
  • the first clock signal clk, the first input signal input_a, the second input signal input_b, the second clock signal clkb, the first reset voltage rst_a, and the second reset voltage rst_b all have a low level.
  • the first input signal input_a and the second input signal input_b have a low level, so the first transistor M1 and the second transistor M2 are turned off.
  • the third transistor M3 and the fourth transistor M4 continue to be turned on, because the first clock signal clk and the second clock signal clkb both have low levels.
  • the third transistor M3 discharges the potential of the first signal output terminal output_a to a low level, and at the same time the fourth transistor M4 is turned on, and the second clock signal clkb is still written into the second signal output terminal output_b, so that the second signal output terminal output_b remains low.
  • the potential of the first node pu will drop to the original high level, that is, the signal at the first node pu becomes about the first input signal.
  • the potential of the first node pu is still high, so that the potentials of the second node pd1 and the third node pd2 remain low, and therefore, the eleventh to eighteenth transistors M11 to M18 are turned off. Since the first reset voltage rst_a and the second reset voltage rst_b are low-level voltages, the fifth transistor M5 and the sixth transistor M6 are turned off.
  • the time period t4 corresponds to the first discharge phase.
  • the first reset voltage rst_a has a high level
  • the first clock signal clk, the first input signal input_a, the second input signal input_b, the second clock signal clkb, and the second reset voltage rst_b all have a low level. Since the first reset voltage rst_a has a high level, the fifth transistor M5 is turned on, so the first node pu is discharged to a low level, that is, the voltage of the first node pu is pulled down to the voltage of the third power supply terminal vss.
  • the third transistor M3 and the fourth transistor M4 are turned off, and the eighth transistor M8 and the tenth transistor M10 are turned off.
  • the control electrode (ie, the gate) and the first electrode (ie, the source) of the seventh transistor M7 are both connected to the first power terminal vdd1.
  • the first control voltage vdd1 output from the first power terminal vdd1 has a high level. Therefore, the first The seventh transistor M7 is turned on, and the second node pd1 is written to a high level, that is, the first control voltage vdd1.
  • the eleventh transistor M11, the twelfth transistor M12, the fifteenth transistor M15, and the sixteenth transistor M16 are turned on, so that The first node pu, the first signal output terminal output_a, and the second signal output terminal output_b are discharged to a low level. Because the second control voltage vdd2 has a low level, the potential of the third node pd2 is still low, so the thirteenth transistor M13, the fourteenth transistor M14, the seventeenth transistor M17, and the eighteenth transistor M18 remain off. . At this time, the first input signal input_a and the second input signal input_b each have a low level, so the first transistor M1 and the second transistor M2 are turned off. The second reset voltage rst_b is a low-level voltage, so the sixth transistor M6 is turned off.
  • FIG. 2 when the first control voltage vdd1 and the second control voltage vdd2 are alternately high in different frames, and the first clock signal clk and the second clock signal clkb are alternately pulsed in different frames, FIG. 2 can be implemented. Pixel driving timing in.
  • the first clock signal alternates between a pulse signal and a low-level DC signal in different frames.
  • the second clock signal alternates between a low-level DC signal and a pulse signal, which can implement the first shift register.
  • the unit and the second shift register unit alternately perform pixel driving, which meets the driving timing requirements of FIG. 2.
  • the number of transistors used in the shift register as a whole is small, making it easier to implement.
  • the first power supply terminal outputs the first control voltage and the first clock within one frame time (for example, the first frame time) of any two adjacent frames.
  • the signal and the first input signal are pulse signals to make the first shift register unit work.
  • the second power supply terminal outputs the second control.
  • the voltage, the second clock signal, and the second input signal are pulse signals to make the second shift register unit work, so that the first shift register unit and the second shift register unit alternately perform pixel driving, so that two sets of driving designs are implemented.
  • the driving timing required by the pixel circuit is easy to implement.
  • FIG. 7 is a structural schematic diagram of a gate driving circuit provided according to some embodiments of the present disclosure
  • FIG. 8 is a schematic diagram of an operation timing of the gate driving circuit shown in FIG. 7 provided according to some embodiments of the present disclosure.
  • the gate driving circuit includes a plurality of shift registers (for example, SR1, SR2, SR3, and SR4 shown in FIG. 7), and the plurality of shift registers are connected in cascade.
  • Each shift register is a shift register described in any one of the above embodiments. The following describes the gate driving circuit by taking each shift register as an example of the shift register shown in FIG. 4A.
  • a plurality of cascaded shift registers form a plurality of gate driving circuit groups, each gate driving circuit group includes 2P shift registers, and each gate driving circuit group includes 2P
  • the shift register corresponds to 2P clock signal groups. Two clock signals in each clock signal group are respectively provided to the first clock signal terminal clk and the second clock signal terminal clkb of the corresponding shift register, and P is a positive integer. That is, each shift register corresponds to a clock signal group, that is, two clock signals in a clock signal group are transmitted to the first clock signal terminal clk and the second clock corresponding to the shift register shown in FIG. 3-6.
  • the signal terminal clkb that is, a clock signal group includes a first clock signal and a second clock signal. For example, P is a positive integer.
  • the first clock signal output from the first clock signal terminal clk is a pulse signal
  • the second clock signal output from the second clock signal terminal clkb is a low-level DC signal.
  • Each group of gate drives The circuit group includes 2P first clock signal terminals clk, and the 2P first clock signals output by the 2P first clock signal terminals clk are pulse signals. Assuming that the period of the pulse signal is T, then the 2P first clock In the signal, the phase of the i + 1th first clock signal is (T / 2P) cycles later than the phase of the ith first clock signal.
  • the second clock signal output from the second clock signal terminal clkb is a pulse signal
  • the first clock signal output from the first clock signal terminal clk is a low-level DC signal.
  • the pole driving circuit group includes 2P second clock signal terminals clkb, and 2P first clock signals output by 2P second clock signal terminals clkb are pulse signals. Assuming that the period of the pulse signal is T, then, In the clock signal, the phase of the i + 1th second clock signal is (T / 2P) cycles later than the phase of the ith second clock signal. i is a positive integer.
  • the first signal input terminal of each stage shift register is connected to the first signal output terminal of the previous stage shift register, and the second signal input terminal of each stage shift register is connected to the first stage shift register.
  • the second signal output terminal, the first reset signal terminal of each stage shift register is connected to the first signal output terminal of the first stage shift register, and the second reset signal terminal of each stage shift register is connected to the first stage shift register. The second signal output terminal.
  • the first-stage shift register refers to the first-stage shift register of the current-stage shift register
  • the last-stage shift register refers to the last-stage gate drive circuit of the current-stage shift register.
  • the j-stage is used as an example of the current stage.
  • the first-stage shift register of the j-th stage shift register is the (j-1) -th stage shift register
  • the last stage of the j-th stage shift register is the (j-th stage). +1) stage shift register.
  • the first signal input terminal of the j-th shift register is connected to the first signal output terminal of the (j-1) th shift register
  • the second signal input terminal of the j-th shift register is connected to the (j -1) the second signal output terminal of the shift register
  • the first reset signal terminal of the j-th shift register is connected to the first signal output terminal of the (j + 1) -th shift register
  • the j-th shift register The second reset signal terminal of is connected to the second signal output terminal of the (j + 1) th stage shift register.
  • the first signal input terminal of each stage shift register is connected to the first signal output terminal of the previous P stage shift register, and the second signal input terminal of each stage shift register is connected to the front P stage shift register.
  • the second signal output terminal after the first reset signal terminal of each stage shift register is connected, the first signal output terminal of the (P + 1) stage shift register is connected, and the second reset signal terminal of each stage shift register is connected (P A second signal output terminal of the +1) stage shift register.
  • the former P-stage shift register refers to the former P-stage shift register of the current stage shift register
  • the latter (P + 1) stage shift register refers to the latter (P + 1) of the current stage shift register.
  • Stage shift register taking the j-th stage as the current stage as an example, the first P-stage shift register of the j-th stage shift register is the (jP) -stage shift register, and the j-th stage of the shift register after (P + 1) ) Stage shift register is the (j + P + 1) th stage shift register.
  • the first signal input terminal of the j-th shift register is connected to the first signal output terminal of the (jP) stage shift register
  • the second signal input terminal of the j-th shift register is connected to the (jP) stage.
  • the second signal output terminal of the shift register, the first reset signal terminal of the j-th shift register is connected to the first signal output terminal of the (j + P + 1) -th shift register, and the first The two reset signal terminals are connected to the second signal output terminal of the (j + P + 1) -stage shift register.
  • j is an integer greater than P.
  • the first signal input terminal and the second signal of the current-stage shift register can be used.
  • the input terminal is connected to the preset control signal terminal STV.
  • the current stage shift register does not exist (P + 1) stage shift register or the last stage shift register
  • the first reset signal terminal and the second reset signal terminal of the current stage shift register can be connected to a preset reset signal. end.
  • the gate driving circuit includes a first-stage shift register SR1, a second-stage shift register SR2, a third-stage shift register SR3, and a fourth-stage shift register SR4, where each stage of the shift register There are a first signal output terminal output_a and a second signal output terminal output_b.
  • the signals output from the first signal output terminal output_a and the second signal output terminal output_b may correspond to the first scan signal Vscan_a and the first Two scan signals Vscan_b.
  • the gate driving circuit further includes a first clock signal line clk1, a second clock signal line clk2, a third clock signal line clk3, and a fourth clock signal line clk4.
  • the connection modes of the shift registers of each stage and the above-mentioned clock signal lines are as follows and so on.
  • the first clock signal terminal clk of the 4n-3th stage shift register (for example, the first stage shift register SR1) is connected to the first clock signal line clk1, and the 4n-2th stage shift register (for example, the second stage shift register).
  • the first clock signal terminal clk of the bit register SR2) is connected to the second clock signal line clk2, and the first clock signal terminal clk of the 4n-1 stage shift register unit (for example, the third stage shift register SR3) and the third clock signal terminal clk2 are connected.
  • the clock signal line clk3 is connected, and the first clock signal terminal clk of the 4nth stage shift register unit (for example, the fourth stage shift register SR4) is connected to the fourth clock signal line clk4.
  • n is an integer greater than 0.
  • the gate driving circuit further includes a fifth clock signal line clkb1, a sixth clock signal line clkb2, a seventh clock signal line clkb3, and an eighth clock signal line clkb4.
  • the connection modes of the shift registers of each stage and the above-mentioned clock signal lines are as follows and so on.
  • the second clock signal terminal clkb of the 4n-3th stage shift register (for example, the first stage shift register SR1) is connected to the fifth clock signal line clkb1, and the 4n-2 stage shift register (for example, the second stage shift register).
  • the second clock signal terminal clkb of the bit register SR2) is connected to the sixth clock signal line clkb2, and the second clock signal terminal clkb and the seventh of the 4n-1 stage shift register unit (for example, the third stage shift register SR3)
  • the clock signal line clkb3 is connected, and the second clock signal terminal clkb of the 4nth stage shift register unit (for example, the fourth stage shift register SR4) is connected to the eighth clock signal line clkb4.
  • the gate driving circuit further includes a first power supply line vdd1, a second power supply line vdd2, and a third power supply line vss.
  • the first power supply terminal vdd1 of each stage of the shift register is connected to the first power supply line vdd1.
  • the second power supply terminal vdd2 of the shift register of each stage is connected to the second power supply line vdd2, and the third power supply terminal vss of the shift register of each stage is connected to the third power supply line vss.
  • the first signal output terminal output1_a and the second signal output terminal output1_b of the first-stage shift register SR1 are connected to the first signal input terminal input3_a and the second signal input of the third-stage shift register SR3, respectively.
  • Input3_b, the first signal output terminal output2_a and the second signal output terminal output2_b of the second-stage shift register SR2 are respectively connected to the first signal input terminal input4_a and the second signal input terminal input4_b of the fourth-stage shift register SR4; the fourth The first signal output terminal output4_a and the second signal output terminal output4_b of the output of the stage shift register SR4 are respectively connected to the first reset signal terminal rst_a and the second reset signal terminal rst_b of the first stage shift register SR1.
  • the signals output on the first clock signal line clk1, the second clock signal line clk2, the third clock signal line clk3, and the fourth clock signal line clk4 are all pulse signals, and the fifth clock signal line clkb1, the first When the signals output by the six clock signal lines clkb2, the seventh clock signal line clkb3, and the eighth clock signal line clkb4 are low-level DC signals, the first signal output terminal output1_a of the first-stage shift register is shifted to the fourth stage.
  • the first signal output terminal output4_a of the register sequentially outputs the row driving signal, and the second signal output terminal output1_b of the first-stage shift register to the second signal output terminal output4_b of the fourth-stage shift register always output a low-level signal.
  • the signals output on the fifth clock signal line clkb1, the sixth clock signal line clkb2, the seventh clock signal line clkb3, and the eighth clock signal line clkb4 are pulse signals, and the first clock signal line clk1 and the second clock signal
  • the second signal output terminal output1_b of the first-stage shift register to the first The two signal output terminals output4_b sequentially output the row driving signals, and the first signal output terminal output1_a of the first-stage shift register to the first signal output terminal output4_a of the fourth-stage shift register always output low-level signals.
  • the first clock signal of each stage of the shift register alternates into a pulse signal and a low-level DC signal at different frames.
  • the second of each stage of the shift register The clock signal is alternated with a low-level DC signal and a pulse signal.
  • the first shift register unit and the second shift register unit of each stage of the shift register can alternately perform pixel driving driving timing, and the number of transistors used as a whole is smaller. Less, making the gate drive circuit easier to implement.
  • the first shift register unit and the second shift register unit of the multi-stage shift register alternately perform pixel driving to realize a pixel circuit adopting two sets of driving designs.
  • the required drive timing is easy to implement.
  • FIG. 9 is a schematic block diagram of a display device according to some embodiments of the present disclosure.
  • the display device 30 includes a gate driving circuit 20.
  • the gate driving circuit 20 is the gate driving circuit described in any one of the above embodiments of the present disclosure.
  • the display device 30 may be a Liquid Crystal Display (LCD) panel, an LCD TV, a display, an Organic Light-Emitting Diode (OLED) panel, an OLED TV, an electronic paper display device, a mobile phone, a tablet computer, Any product or component having a display function, such as a notebook computer, a digital photo frame, a navigator, etc., is not limited in the embodiments of the present disclosure.
  • LCD Liquid Crystal Display
  • OLED Organic Light-Emitting Diode
  • OLED Organic Light-Emitting Diode
  • FIG. 10 is a flowchart of a method for controlling a shift register according to some embodiments of the present disclosure
  • FIG. 11 is a flowchart of another method of controlling a shift register according to some embodiments of the present disclosure.
  • any two adjacent frames include a first frame and a second frame.
  • the control method of the shift register 100 includes the following operations:
  • each shift register includes a first shift register unit and a second shift register unit.
  • the first shift register unit includes a first input circuit, a first output circuit, and a first control circuit
  • the second shift register unit includes a second input circuit, a second output circuit, and a second control circuit.
  • the first frame time includes a first input phase, a first output phase, and a first discharge phase
  • the second frame time includes a second input phase, a second output phase, and a second discharge phase
  • step S100 includes:
  • the first reset signal terminal In the first discharging stage, the first reset signal terminal outputs a first reset voltage, and the first power terminal outputs a first control voltage. Under the control of the first reset voltage and the first control voltage, the first The voltages of the three power supply terminals are respectively written into the first node and the first signal output terminal.
  • step S3 the first reset voltage has a high level.
  • step S200 includes:
  • the second reset signal terminal In the second discharging phase, the second reset signal terminal outputs a second reset voltage, and the second power terminal outputs a second control voltage. Under the control of the second reset voltage and the second control voltage, the first The voltages of the three power supply terminals are respectively written into the first node and the second signal output terminal.
  • step S6 the second reset voltage has a high level.
  • the first power supply terminal within one frame time (for example, the first frame time) of any two adjacent frames, the first power supply terminal outputs a first control voltage and a first clock The signal and the first input signal are pulse signals to make the first shift register unit work.
  • the second power supply terminal outputs the second control.
  • the voltage, the second clock signal, and the second input signal are pulse signals to make the second shift register unit work, so that the first shift register unit and the second shift register unit alternately perform pixel driving, so that two sets of driving designs are implemented.
  • the driving timing required by the pixel circuit is easy to implement.
  • first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as “first” and “second” may explicitly or implicitly include at least one of the features. In the description of the present disclosure, “multiple” means at least two, e.g., two, three, etc., unless specifically defined otherwise.
  • any process or method description in a flowchart or otherwise described herein can be understood as representing a circuit, segment, or portion of code that includes one or more executable instructions for implementing steps of a custom logic function or process
  • the scope of the preferred embodiments of the present disclosure includes additional implementations in which the functions may be performed out of the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order according to the functions involved, which should It is understood by those skilled in the art to which the embodiments of the present disclosure belong.
  • a sequenced list of executable instructions that can be considered to implement a logical function can be embodied in any computer-readable medium,
  • the instruction execution system, device, or device such as a computer-based system, a system including a processor, or other system that can fetch and execute instructions from the instruction execution system, device, or device), or combine these instruction execution systems, devices, or devices Or equipment.
  • a "computer-readable medium” may be any device that can contain, store, communicate, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device.
  • computer readable media include the following: electrical connections (electronic devices) with one or more wirings, portable computer disk cartridges (magnetic devices), random access memory (RAM), Read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disk read-only memory (CDROM).
  • the computer-readable medium may even be paper or other suitable medium on which the program can be printed, because, for example, by optically scanning the paper or other medium, followed by editing, interpretation, or other suitable Processing to obtain the program electronically and then store it in computer memory.
  • portions of the present disclosure may be implemented in hardware, software, firmware, or a combination thereof.
  • multiple steps or methods may be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system.
  • Discrete logic circuits with logic gates for implementing logic functions on data signals Logic circuits, ASICs with suitable combinational logic gate circuits, programmable gate arrays (PGA), field programmable gate arrays (FPGAs), etc.
  • a person of ordinary skill in the art can understand that all or part of the steps carried by the methods in the foregoing embodiments may be implemented by a program instructing related hardware.
  • the program may be stored in a computer-readable storage medium.
  • the program is When executed, one or a combination of the steps of the method embodiment is included.
  • each functional circuit in each embodiment of the present disclosure may be integrated into one processing circuit, or each circuit may exist separately physically, or two or more circuits may be integrated into one circuit.
  • the above integrated circuit can be implemented in the form of hardware or in the form of software functional circuits. If the integrated circuit is implemented in the form of a software functional circuit and sold or used as an independent product, it may also be stored in a computer-readable storage medium.
  • the aforementioned storage medium may be a read-only memory, a magnetic disk, or an optical disk.

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Abstract

一种显示装置、栅极驱动电路、移位寄存器及其控制方法，移位寄存器(100)的第一移位寄存器单元(101)用于在第一输入信号的控制下将第一控制信号写入第一节点(pu)，在第一节点(pu)的电压的控制下将第一时钟信号写入第一信号输出端(output_a)，移位寄存器(100)的第二移位寄存器单元(102)用于在第二输入信号的控制下将第二控制信号写入第一节点(pu)，在第一节点(pu)的电压的控制下将第二时钟信号写入第二信号输出端(output_b)；第一帧和第二帧相邻，在第一帧内，第一时钟信号和第一输入信号为脉冲信号，第二时钟信号和第二输入信号为直流信号；在第二帧内，第一时钟信号和第一输入信号为直流信号，第二时钟信号和第二输入信号为脉冲信号。

Description

显示装置、栅极驱动电路、移位寄存器及其控制方法
本申请要求于2018年05月25日递交的中国专利申请第201810514974.X号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种移位寄存器、栅极驱动电路、显示装置以及移位寄存器的控制方法。
背景技术
随着显示技术的进步，越来越多的有源矩阵有机发光二极管(Active Matrix Organic Light Emitting Diode,AMOLED)面板进入市场，相对于传统的晶体管液晶显示面板(Thin Film Transistor Liquid Crystal Display,TFT LCD)，AMOLED具有更快的反应速度，更高的对比度，更广的视角以及更薄的模组，因此AMOLED越来越多的受到面板厂商的重视。
发明内容
本公开一些实施例提供一种移位寄存器，包括第一移位寄存单元和第二移位寄存单元，所述第一移位寄存器单元与第一节点、第一信号输入端、第一时钟信号端和第一信号输出端电连接，所述第二移位寄存器单元与所述第一节点、第二信号输入端、第二时钟信号端和第二信号输出端电连接，所述第一移位寄存器单元被配置为在所述第一信号输入端提供的第一输入信号的控制下将第一控制信号写入所述第一节点，并在所述第一节点的电压的控制下将所述第一时钟信号端提供的第一时钟信号写入所述第一信号输出端；所述第二移位寄存器单元被配置为在所述第二信号输入端提供的第二输入信号的控制下将第二控制信号写入所述第一节点，并在所述第一节点的电压的控制下将所述第二时钟信号端提供的第二时钟信号写入所述第二信号输出端；任意两个相邻帧包括第一帧和第二帧，在所述第一帧时间内，所述第一时钟信号和所述第一输入信号为脉冲信号，所述第二时钟信号和所述第二输入信号为直流信号；在所述第二帧时间内，所述第一时钟信号和所述第一输入信号为直流信号，所述第 二时钟信号和所述第二输入信号为脉冲信号。
例如，在本公开一些实施例提供的移位寄存器中，所述第一移位寄存单元包括第一输入电路和第一输出电路，所述第二移位寄存单元包括第二输入电路和第二输出电路，所述第一输入电路分别与所述第一信号输入端和所述第一节点相连，所述第一输入电路用于在所述第一信号输入端提供的第一输入信号的控制下将所述第一输入信号写入所述第一节点；所述第一输出电路分别与所述第一节点、所述第一时钟信号端和所述第一信号输出端相连，所述第一输出电路用于在所述第一节点的电压的控制下将所述第一时钟信号端的电压写入所述第一信号输出端；所述第二输入电路分别与所述第二信号输入端和所述第一节点相连，所述第二输入电路用于在所述第二信号输入端提供的第二输入信号的控制下将所述第二输入信号写入所述第一节点；所述第二输出电路分别与所述第一节点、所述第二时钟信号端和所述第二信号输出端相连，所述第二输出电路用于在所述第一节点的电压的控制下将所述第二时钟信号端的电压写入所述第二信号输出端。
例如，在本公开一些实施例提供的移位寄存器中，所述第一移位寄存器单元还包括第一控制电路，所述第二移位寄存器单元还包括第二控制电路，所述第一控制电路分别与第一电源端、所述第一节点、第一复位信号端、第三电源端和所述第一信号输出端相连，所述第一控制电路用于在所述第一电源端提供的第一控制电压和所述第一复位信号端提供的第一复位电压的控制下对所述第一信号输出端和所述第一节点的电压进行控制；所述第二控制电路分别与第二电源端、所述第一节点、第二复位信号端、所述第三电源端和所述第二信号输出端相连，所述第二控制电路用于在所述第二电源端提供的第二控制电压和所述第二复位信号端提供的第二复位电压的控制下对所述第二信号输出端和所述第一节点的电压进行控制；在所述第一帧时间内，所述第一电源端输出所述第一控制电压，在所述第二帧时间内，所述第二电源端输出所述第二控制电压。
例如，在本公开一些实施例提供的移位寄存器中，所述第一控制电压和所述第二控制电压均具有高电平。
例如，在本公开一些实施例提供的移位寄存器中，所述第一控制电路包括第一下拉控制电路和第一下拉电路，所述第一下拉控制电路分别与所述第一节点和第二节点相连，且被配置为在所述第一节点的电压的控制下，对所述第二 节点的电平进行控制，所述第一下拉电路分别与所述第一节点、所述第二节点、所述第三电源端和所述第一信号输出端相连，且被配置为在所述第二节点的电压的控制下，对所述第一节点和所述第一信号输出端进行放电处理。
例如，在本公开一些实施例提供的移位寄存器中，所述第一下拉控制电路还分别与所述第一电源端和所述第三电源端相连，所述第一下拉控制电路用于在所述第一控制电压的控制下将所述第一控制电压写入所述第二节点，并在所述第一节点的电压的控制下将所述第三电源端的电压写入所述第二节点。
例如，在本公开一些实施例提供的移位寄存器中，所述第一控制电路还包括第一复位电路，所述第一复位电路分别与所述第一复位信号端、所述第三电源端和所述第一节点相连，所述第一复位电路用于在所述第一复位电压的控制下将所述第三电源端的电压写入所述第一节点。
例如，在本公开一些实施例提供的移位寄存器中，所述第一下拉电路还与所述第三节点和所述第二信号输出端相连，所述第一下拉电路还被配置为在所述第二节点的电压的控制下，对所述第三节点和所述第二信号输出端进行放电处理。
例如，在本公开一些实施例提供的移位寄存器中，所述第二控制电路包括第二下拉控制电路和第二下拉电路，所述第二下拉控制电路分别与所述第一节点和第三节点相连，且被配置为在所述第一节点的电压的控制下，对所述第三节点的电平进行控制，所述第二下拉电路分别与所述第一节点、所述第三节点、所述第三电源端和所述第二信号输出端相连，且被配置为在所述第三节点的电压的控制下，对所述第一节点和所述第二信号输出端进行放电处理。
例如，在本公开一些实施例提供的移位寄存器中，所述第二下拉控制电路还分别与所述第二电源端和所述第三电源端相连，所述第二下拉控制电路用于在所述第二控制电压的控制下将所述第二控制电压写入所述第三节点，并在所述第一节点的电压的控制下将所述第三电源端的电压写入所述第三节点。
例如，在本公开一些实施例提供的移位寄存器中，所述第二控制电路还包括第二复位电路，所述第二复位电路分别与所述第二复位信号端、所述第三电源端和所述第一节点相连，所述第二复位电路用于在所述第二复位电压的控制下将所述第三电源端的电压写入所述第一节点。
例如，在本公开一些实施例提供的移位寄存器中，所述第二下拉电路还与所述第二节点和所述第一信号输出端相连，所述第二下拉电路还被配置为在所 述第三节点的电压的控制下，对所述第二节点和所述第一信号输出端进行放电处理。
例如，在本公开一些实施例提供的移位寄存器中，所述第一移位寄存器单元还包括第一控制电路，所述第二移位寄存器单元还包括第二控制电路，
所述第一控制电路分别与第一电源端、所述第一节点、第一复位信号端、第三电源端和所述第一信号输出端相连，所述第一控制电路用于在所述第一电源端提供的第一控制电压和所述第一复位信号端提供的第一复位电压的控制下对所述第一信号输出端和所述第一节点的电压进行控制；
所述第二控制电路分别与所述第一电源端、所述第一节点、第二复位信号端、所述第三电源端和所述第二信号输出端相连，所述第二控制电路用于在所述第一电源端提供的第一控制电压和所述第二复位信号端提供的第二复位电压的控制下对所述第二信号输出端和所述第一节点的电压进行控制；
其中，在所述第一帧时间和所述第二帧时间内，所述第一电源端均输出所述第一控制电压。
例如，在本公开一些实施例提供的移位寄存器中，所述第一控制电路包括第一下拉控制电路、第一下拉电路和第一复位电路，
所述第一下拉控制电路分别与所述第一节点和第二节点相连，且被配置为在所述第一节点的电压的控制下，对所述第二节点的电平进行控制；
所述第一下拉电路分别与所述第一节点、所述第二节点、所述第三电源端和所述第一信号输出端相连，且被配置为在所述第二节点的电压的控制下，对所述第一节点和所述第一信号输出端进行放电处理；
所述第一复位电路分别与所述第一复位信号端、所述第三电源端和所述第一节点相连，所述第一复位电路用于在所述第一复位电压的控制下将所述第三电源端的电压写入所述第一节点。
例如，在本公开一些实施例提供的移位寄存器中，所述第二控制电路包括所述第一下拉控制电路、所述第一下拉电路和第二复位电路，
所述第一下拉电路还与所述第二信号输出端相连，且还被配置为在所述第二节点的电压的控制下，对所述第二信号输出端进行放电处理；
所述第二复位电路分别与所述第二复位信号端、所述第三电源端和所述第一节点相连，所述第二复位电路用于在所述第二复位电压的控制下将所述第三电源端的电压写入所述第一节点。
例如，在本公开一些实施例提供的移位寄存器中，所述第一下拉控制电路还分别与所述第一电源端和所述第三电源端相连，所述第一下拉控制电路用于在所述第一控制电压的控制下将所述第一控制电压写入所述第二节点，并在所述第一节点的电压的控制下将所述第三电源端的电压写入所述第二节点。
例如，在本公开一些实施例提供的移位寄存器中，所述第一输入电路包括第一晶体管，所述第一晶体管的第一极和控制极与所述第一信号输入端相连以接收所述第一输入信号作为所述第一控制信号，所述第一晶体管的第二极与所述第一节点相连；所述第二输入电路包括第二晶体管，所述第二晶体管的第一极和控制极与所述第二信号输入端相连以接收所述第二输入信号作为所述第二控制信号，所述第二晶体管的第二极与所述第一节点相连。
例如，在本公开一些实施例提供的移位寄存器中，所述第一输出电路包括第三晶体管和第一电容，所述第三晶体管的第一极与所述第一时钟信号端相连，所述第三晶体管的第二极与所述第一信号输出端相连，所述第三晶体管的控制极与所述第一节点相连，所述第一电容的第一端与所述第一节点相连，所述第一电容的第二端与所述第一信号输出端相连；所述第二输出电路包括第四晶体管和第二电容，所述第四晶体管的第一极与所述第二时钟信号端相连，所述第四晶体管的第二极与所述第二信号输出端相连，所述第四晶体管的控制极与所述第一节点相连，所述第二电容的第一端与所述第一节点相连，所述第二电容的第二端与所述第二信号输出端相连。
例如，在本公开一些实施例提供的移位寄存器中，所述第一下拉控制电路包括第七晶体管和第八晶体管，所述第七晶体管的第一极和控制极与所述第一电源端相连，所述第七晶体管的第二极与所述第二节点相连，所述第八晶体管的第一极与所述第三电源端相连，所述第八晶体管的第二极与所述第二节点相连，所述第八晶体管的控制极与所述第一节点相连；所述第一下拉电路包括第十一晶体管和第十二晶体管，所述第十一晶体管的第一极与所述第一节点相连，所述第十一晶体管的第二极与所述第三电源端相连，所述第十一晶体管的控制极与所述第二节点相连，所述第十二晶体管的第一极与所述第一信号输出端相连，所述第十二晶体管的第二极与所述第三电源端相连，所述第十二晶体管的控制极与所述第二节点相连。
例如，在本公开一些实施例提供的移位寄存器中，所述第一下拉电路还包括第十五晶体管和第十六晶体管，所述第十五晶体管的第一极与所述第三节点 相连，所述第十五晶体管的第二极与所述第三电源端相连，所述第十五晶体管的控制极与所述第二节点相连，所述第十六晶体管的第一极与所述第二信号输出端相连，所述第十六晶体管的第二极与所述第三电源端相连，所述第十六晶体管的控制极与所述第二节点相连。
例如，在本公开一些实施例提供的移位寄存器中，所述第一复位电路包括第五晶体管，所述第五晶体管的第一极与所述第一节点相连，所述第五晶体管的第二极与所述第三电源端相连，所述第五晶体管的控制极与所述第一复位信号端相连。
例如，在本公开一些实施例提供的移位寄存器中，所述第二下拉控制电路包括第九晶体管和第十晶体管，所述第九晶体管的第一极和控制极与所述第二电源端相连，所述第九晶体管的第二极与所述第三节点相连，所述第十晶体管的第一极与所述第三电源端相连，所述第十晶体管的第二极与所述第三节点相连，所述第十晶体管的控制极与所述第一节点相连；所述第二下拉电路包括第十三晶体管和第十四晶体管，所述第十三晶体管的第一极与所述第一节点相连，所述第十三晶体管的第二极与所述第三电源端相连，所述第十三晶体管的控制极与所述第三节点相连，所述第十四晶体管的第一极与所述第二信号输出端相连，所述第十四晶体管的第二极与所述第三电源端相连，所述第十四晶体管的控制极与所述第三节点相连。
例如，在本公开一些实施例提供的移位寄存器中，所述第二下拉电路还包括第十七晶体管和第十八晶体管，所述第十七晶体管的第一极与所述第二节点相连，所述第十七晶体管的第二极与所述第三电源端相连，所述第十七晶体管的控制极与所述第三节点相连，所述第十八晶体管的第一极与所述第一信号输出端相连，所述第十八晶体管的第二极与所述第三电源端相连，所述第十八晶体管的控制极与所述第三节点相连。
例如，在本公开一些实施例提供的移位寄存器中，所述第二复位电路包括第六晶体管，所述第六晶体管的第一极与所述第一节点相连，所述第六晶体管的第二极与所述第三电源端相连，所述第六晶体管的控制极与所述第二复位信号端相连。
本公开一些实施例还提供一种栅极驱动电路，包括上述任一实施例提供的移位寄存器。
例如，在本公开一些实施例提供的栅极驱动电路中，所述多个级联的移位 寄存器组成多个栅极驱动电路组，每个栅极驱动电路组包括2P个移位寄存器，所述每个栅极驱动电路组中的所述2P个移位寄存器与2P个时钟信号组对应，每个时钟信号组中的两个时钟信号分别提供至相应移位寄存器的第一时钟信号端和第二时钟信号端，当P＝1时，第j级移位寄存器的第一信号输入端连接第(j-1)级移位寄存器的第一信号输出端，所述第j级移位寄存器的第二信号输入端连接所述第(j-1)级移位寄存器的第二信号输出端，所述第j级移位寄存器的第一复位信号端连接第(j+1)级移位寄存器的第一信号输出端，所述第j级移位寄存器的第二复位信号端连接所述第(j+1)级移位寄存器的第二信号输出端；当P大于1时，所述第j级移位寄存器的第一信号输入端连接第(j-P)级移位寄存器的第一信号输出端，所述第j级移位寄存器的第二信号输入端连接所述第(j-P)级移位寄存器的第二信号输出端，所述第j级移位寄存器的第一复位信号端连接第(j+P+1)级移位寄存器的第一信号输出端，所述第j级移位寄存器的第二复位信号端连接所述第(j+P+1)级移位寄存器的第二信号输出端，其中，P为正整数，j为大于P的整数。
本公开一些实施例还提供一种显示装置，包括上述任一实施例所述的栅极驱动电路。
本公开一些实施例还提供一种如上述任一实施例所述的移位寄存器的控制方法，包括：在所述第一帧时间，在所述第一输入信号的控制下，通过所述第一移位寄存器单元将第一控制信号写入所述第一节点，并在所述第一节点的电压的控制下，通过所述第一移位寄存单元将所述第一时钟信号写入所述第一信号输出端，其中，所述第一时钟信号和所述第一输入信号为脉冲信号；在所述第二帧时间，在所述第二输入信号的控制下，通过所述第二移位寄存器单元将第二控制信号写入所述第一节点，并在所述第一节点的电压的控制下，通过所述第二移位寄存单元将所述第二时钟信号写入所述第二信号输出端，其中，所述第二时钟信号和所述第二输入信号为脉冲信号。
例如，在本公开一些实施例提供的移位寄存器的控制方法中，所述第一帧时间包括第一输入阶段、第一输出阶段和第一放电阶段，所述第二帧时间包括第二输入阶段、第二输出阶段和第二放电阶段，所述控制方法包括：在所述第一输入阶段，所述第一信号输入端输出所述第一输入信号，所述第一输入电路在所述第一输入信号的控制下，向所述第一节点写入所述第一控制信号；在所述第一输出阶段，所述第一时钟信号端输出所述第一时钟信号，所述第一输出 电路在所述第一节点的电压的控制下，向所述第一信号输出端输出所述第一时钟信号；在所述第一放电阶段，所述第一复位信号端输出所述第一复位电压，所述第一电源端输出所述第一控制电压，在所述第一复位电压和所述第一控制电压的控制下，通过所述第一控制电路将所述第三电源端的电压分别写入所述第一节点和所述第一信号输出端；在所述第二输入阶段，所述第二信号输入端输出所述第二输入信号，所述第二输入电路在所述第二输入信号的控制下，向所述第一节点写入所述第二控制信号；在所述第二输出阶段，所述第二时钟信号端输出所述第二时钟信号，所述第二输出电路在所述第一节点的电压的控制下，向所述第二信号输出端输出所述第二时钟信号；在所述第二放电阶段，所述第二复位信号端输出所述第二复位电压，所述第二电源端输出所述第二控制电压，在所述第二复位电压和所述第二控制电压的控制下，通过所述第二控制电路将所述第三电源端的电压分别写入所述第一节点和所述第二信号输出端。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种像素电路的电路图；
图2为图1所示的像素电路的驱动时序的示意图；
图3A是根据本公开一些实施例提供的一种移位寄存器的方框示意图；
图3B是根据本公开一些实施例提供的另一种移位寄存器的方框示意图；
图3C是根据本公开一些实施例提供的又一种移位寄存器的方框示意图；
图4A是根据本公开另一些实施例提供的一种移位寄存器的方框示意图；
图4B是根据本公开另一些实施例提供的又一种移位寄存器的方框示意图；
图5A是根据本公开一些实施例提供的一种移位寄存器的电路原理图；
图5B是根据本公开一些实施例提供的又一种移位寄存器的电路原理图；
图6为根据本公开一些实施例提供的图4A所示的移位寄存器的工作时序的示意图；
图7是根据本公开一些实施例提供的一种栅极驱动电路的结构原理图；
图8为根据本公开一些实施例提供的图7所示的栅极驱动电路的工作时序 的示意图；
图9是根据本公开一些实施例提供的一种显示装置的方框示意图；
图10是根据本公开一些实施例提供的一种移位寄存器的控制方法的流程图；以及
图11是根据本公开一些实施例提供的另一种移位寄存器的控制方法的流程图。
具体实施方式
为了使得本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
为了保持本公开实施例的以下说明清楚且简明，本公开省略了部分已知功能和已知部件的详细说明。
针对驱动晶体管的阈值电压漂移的情况，一种AMOLED(Active Matrix Organic Light Emitting Diode,有源矩阵有机发光二极管)像素电路可以采用两个子像素电路，来降低驱动管的阈值电压漂移，每个子像素电路包括两个薄膜晶体管(驱动晶体管和数据写入晶体管)和一个电容。在相邻帧，两个子像素电路中的驱动晶体管轮流开启，从而，降低每个驱动晶体管的偏压时间，降低驱动晶体管的阈值电压漂移。但是，现有栅极驱动电路无法实现该像素电路所需驱动时序。
下面先简单介绍AMOLED像素电路。
如图1所示，AMOLED像素电路可以采用两个子像素电路来降低驱动管的阈值电压漂移，两个子像素电路分别为第一子像素电路和第二子像素电路，第一子像素电路包括第一驱动晶体管T2、第一数据写入晶体管T1和第一存储电容C1，第二子像素电路包括第二驱动晶体管T2'、第二数据写入晶体管T1'和第二存储电容C1'。在多帧时间内，第一子像素电路和第二子像素电路交替工作，即在一帧时间内，第一子像素电路工作，即图1中的第一驱动晶体管T2、第一数据写入晶体管T1和第一存储电容C1工作，这时第二子像素电路则不工作，即图1中的第二驱动晶体管T2'、第二数据写入晶体管T1'和第二存储电容C1'不工作。在另外一帧时间内，第二子像素电路工作，即图1中的第二驱动晶体管T2'、第二数据写入晶体管T1'和第二存储电容C1'工作，第一子像素电路不工作，即图1中的第一驱动晶体管T2、第一数据写入晶体管T1和第一存储电容C1不工作。
图1中像素电路的驱动时序可如图2所示，在第N帧的T1时间段，第一扫描信号Vscan_a和第一数据信号Vdata_a为高电平，由此，第一数据写入晶体管T1开启，第一数据信号Vdata_a被写入第一驱动晶体管T2的栅极；此时第二扫描信号Vscan_b和第二数据信号Vdata_b为低电平，由此，第二数据写入晶体管T1'关闭；因此在第N帧的后续时间段，第一驱动晶体管T2开启，第二驱动晶体管T2'关断并处于阈值电压恢复期。在第N+1帧的T1'时间段，第二扫描信号Vscan_b和第二数据信号Vdata_b为高电平，由此，第二数据写入晶体管T1'开启，第二数据信号Vdata_b被写入第二驱动晶体管T2'的栅极；此时第一扫描信号Vscan_a和第一数据信号Vdata_a为低电平，由此，第一数据写入晶体管T1关闭；因此在第N+1帧时间的后续时间段，第二驱动晶体管T2'开启，第一驱动晶体管T2关断并且处于阈值电压恢复期。如此，在相邻帧，第一驱动管T2和第二驱动晶体管T2'轮流开启，将大大降低驱动晶体管的偏压时间，从而极大的降低了驱动晶体管的阈值电压漂移。
栅极驱动电路GOA(Gate Driver On Array)除了能够省略栅极驱动集成电路(IC)以及对应的绑定(Bonding)工序外，还可实现显示面板的窄边框设计，因此GOA在显示面板的设计和生产中得到越来越广泛的应用。
基于此，本公开提出了一种移位寄存器及其控制方法、栅极驱动电路和显示装置，使得在不同帧时，不同的驱动晶体管交替开启，降低驱动晶体管的阈 值电压漂移，且能够实现优化驱动时序的要求，整体上使用的晶体管的数目较少，使得该移位寄存器实现起来更加简单，同时能够降低成本。
例如，在本公开中，第一晶体管至第十八晶体管等可以为场效应晶体管。按照场效应晶体管的特性，场效应晶体管可以分为N型晶体管和P型晶体管，为了清楚起见，本公开的实施例以场效应晶体管为N型晶体管(例如，N型MOS晶体管(NMOS))为例详细阐述了本公开的技术方案，然而本公开的实施例的场效应晶体管不限于N型晶体管，本领域技术人员还可以根据实际需要利用P型晶体管(例如，P型MOS晶体管(PMOS))实现本公开的实施例中的一个或多个场效应晶体管的功能。
需要说明的是，本公开的实施例中采用的场效应晶体管可以为薄膜晶体管等场效应晶体管或其他特性相同的开关器件，薄膜晶体管可以包括氧化物半导体薄膜晶体管、非晶硅薄膜晶体管或多晶硅薄膜晶体管等。场效应晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在物理结构上可以是没有区别的。在本公开的实施例中，为了区分场效应晶体管，除作为控制极的栅极，直接描述了其中一极为第一极，另一极为第二极，所以本公开的实施例中全部或部分场效应晶体管的第一极和第二极根据需要是可以互换的。
下面参考附图描述本公开实施例的显示装置、栅极驱动电路、移位寄存器及其控制方法。
图3A是根据本公开一些实施例提供的一种移位寄存器的方框示意图，图3B是根据本公开一些实施例提供的另一种移位寄存器的方框示意图。如图3A所示，移位寄存器100包括第一移位寄存单元101和第二移位寄存单元102。第一移位寄存器单元101与第一节点pu、第一信号输入端input_a、第一时钟信号端clk和第一信号输出端output_a电连接，第二移位寄存单元102与第一节点pu、第二信号输入端input_b、第二时钟信号端clkb和第二信号输出端output_b电连接。
例如，第一移位寄存器单元101被配置为在第一信号输入端input_a提供的第一输入信号的控制下将第一控制信号写入第一节点pu，并在第一节点pu的电压的控制下将第一时钟信号端clk提供的第一时钟信号写入第一信号输出端output_a。第二移位寄存单元102被配置为在第二信号输入端input_b提供的第二输入信号的控制下将第二控制信号写入第一节点pu，并在第一节点pu的电压的控制下将第二时钟信号端clkb提供的第二时钟信号写入第二信号输出 端output_b。
例如，任意两个相邻帧包括第一帧和第二帧，在第一帧时间内，第一时钟信号和第一输入信号为脉冲信号，第二时钟信号和第二输入信号为直流信号；在第二帧时间内，第一时钟信号和第一输入信号为直流信号，第二时钟信号和第二输入信号为脉冲信号。也就是说，在多帧时间中，第一时钟信号端clk交替输出脉冲信号和直流信号，第一信号输入端input_a交替输出脉冲信号和直流信号，相应地，第二时钟信号端clkb也交替输出直流信号和脉冲信号，第二信号输入端input_b也交替输出直流信号和脉冲信号。例如，在第2m帧(偶数帧)中，第一时钟信号端clk输出脉冲信号，第一信号输入端input_a输出脉冲信号，第二时钟信号端clkb输出直流信号，第二信号输入端input_b输出直流信号；在第(2m-1)帧(奇数帧)中，第一时钟信号端clk输出直流信号，第一信号输入端input_a输出直流信号，第二时钟信号端clkb输出脉冲信号，第二信号输入端input_b输出信号，其中，m为正整数。
例如，直流信号可以为低电平直流信号。
例如，如图3B所示，在一些实施例中，第一移位寄存单元101包括第一输入电路11、第一输出电路12和第一控制电路13，第一输入电路11分别与第一信号输入端input_a和第一节点pu相连，第一输入电路11用于在第一信号输入端input_a提供的第一输入信号的控制下将第一控制信号写入第一节点pu；第一输出电路12分别与第一节点pu、第一时钟信号端clk和第一信号输出端output_a相连，第一输出电路12用于在第一节点pu的电压的控制下将第一时钟信号端clk提供的第一时钟信号写入第一信号输出端output_a；第一控制电路13分别与第一电源端vdd1、第一节点pu、第一复位信号端rst_a、第三电源端vss和第一信号输出端output_a相连，第一控制电路13用于在第一电源端vdd1提供的第一控制电压和第一复位信号端rst_a提供的第一复位电压的控制下对第一信号输出端output_a和第一节点pu的电压进行控制。
例如，第二移位寄存单元102包括第二输入电路21、第二输出电路22和第二控制电路23。第二输入电路21分别与第二信号输入端input_b和第一节点pu相连，第二输入电路21用于在第二信号输入端input_b提供的第二输入信号的控制下将第二控制信号写入第一节点pu；第二输出电路22分别与第一节点pu、第二时钟信号端clkb和第二信号输出端output_b相连，第二输出电路22用于在第一节点pu的电压的控制下将第二时钟信号端clkb提供的第二时钟信 号写入第二信号输出端output_b；第二控制电路23分别与第二电源端vdd2、第一节点pu、第二复位信号端rst_b、第三电源端vss和第二信号输出端output_b相连，第二控制电路23用于在第二电源端vdd2提供的第二控制电压和第二复位信号端rst_b提供的第二复位电压的控制下对第二信号输出端output_b和第一节点pu的电压进行控制。
例如，在第一帧时间内，第一控制信号为脉冲信号，第二控制信号为直流信号；在第二帧时间内，第一控制信号为直流信号，第二控制信号则为脉冲信号。当第一控制信号为脉冲信号时，第一控制信号的相位、周期等与第一输入信号相同，从而例如第一控制信号可以为第一输入信号。当第二控制信号为脉冲信号时，第二控制信号的相位、周期等与第二输入信号相同，从而第二控制信号可以为第二输入信号。需要说明的是，本公开不限于此，在第一帧时间内，第一控制信号可以为高电平直流信号，第二控制信号可以为低电平直流信号；在第一帧时间内，第一控制信号可以为低电平直流信号，第二控制信号可以为高电平直流信号。在本公开的实施例中，对于第一控制信号，只要在第一输入信号控制第一输入电路11开启时，可以将第一控制信号写入第一节点pu以对第一节点pu进行充电即可，即在第一输入信号控制第一输入电路11开启时，可以通过第一控制信号上拉第一节点pu。另外，对于第二控制信号，只要在第二输入信号控制第二输入电路21开启时，可以将第二控制信号写入第一节点pu以对第一节点pu进行充电即可，即在第二输入信号控制第二输入电路21开启时，可以通过第二控制信号上拉第一节点pu。
例如，在第一帧时间内，第一电源端vdd1输出第一控制电压，在第二帧时间内，第二电源端vdd2输出第二控制电压。在第一帧时间内，第二电源端vdd2输出低电平的电压信号；在第二帧时间内，第一电源端vdd1输出低电平的电压信号。
需要说明的是，第一控制电压和第二控制电压可均为高电平，脉冲信号可为存在高低电平的方波信号，例如，脉冲信号可以是在时刻t1由低电平变为高电平且在t时间后的时刻t2(即时刻t1和时刻t2的间隔t时间)再由高电平变为低电平的信号。
还需说明的是，本文中的“高电平”和“低电平”分别指的是某一位置处由电位高度范围代表的两种逻辑状态。举例来说，高电平可以具体可指代高于公共端电压的电位，低电平可以具体指代低于公共端电压的电位，同时，不同 位置的“高电平”电位可不相同，且不同位置的“低电平”电位也可不相同。可以理解的是，具体的电位高度范围可以在具体应用场景下根据需要进行设置，本公开对此不做限制。
例如，在第一电源端vdd和第二电源端vdd2电平设置上，可以在一帧时间内，第一电源端vdd1输出的第一控制电压的电平设置为高电平，同时第二电源端vdd2输出的第二控制电压的电平设置为低电平，此时将对第一节点pu和第一信号输出端output_a进行放电，在相邻的下一帧时间内，将第一电源端vdd1输出的第一控制电压的电平设置为低电平，同时第二电源端vdd2输出的第二控制电压的电平设置为高电平，此时，将对第一节点pu和第二信号输出端output_b进行放电。
图3C是根据本公开一些实施例提供的又一种移位寄存器的方框示意图。
例如，如图3C所示，在另一些实施例中，第一移位寄存器单元101还包括第一输入电路11、第一输出电路12和第一控制电路31，第一输入电路11分别与第一信号输入端input_a和第一节点pu相连，第一输入电路11用于在第一信号输入端input_a提供的第一输入信号的控制下将第一控制信号写入第一节点pu；第一输出电路12分别与第一节点pu、第一时钟信号端clk和第一信号输出端output_a相连，第一输出电路12用于在第一节点pu的电压的控制下将第一时钟信号端clk提供的第一时钟信号写入第一信号输出端output_a；第一控制电路31分别与第一电源端vdd1、第一节点pu、第一复位信号端rst_a、第三电源端vss和第一信号输出端output_a相连，第一控制电路31用于在第一电源端vdd1提供的第一控制电压和第一复位信号端rst_a提供的第一复位电压的控制下对第一信号输出端output_a和第一节点pu的电压进行控制。
例如，第二移位寄存单元102包括第二输入电路21、第二输出电路22和第二控制电路32。第二输入电路21分别与第二信号输入端input_b和第一节点pu相连，第二输入电路21用于在第二信号输入端input_b提供的第二输入信号的控制下将第二控制信号写入第一节点pu；第二输出电路22分别与第一节点pu、第二时钟信号端clkb和第二信号输出端output_b相连，第二输出电路22用于在第一节点pu的电压的控制下将第二时钟信号端clkb提供的第二时钟信号写入第二信号输出端output_b；第二控制电路32分别与第一电源端vdd1、第一节点pu、第二复位信号端rst_b、第三电源端vss和第二信号输出端output_b相连，第二控制电路32用于在第一电源端vdd1提供的第一控制电压和第二复 位信号端rst_b提供的第二复位电压的控制下对第二信号输出端output_b和第一节点pu的电压进行控制。
例如，在第一帧时间和第二帧时间内，第一电源端vdd1均输出第一控制电压，第一控制电压可为高电平。
另外，在第一时钟信号端clk和第二时钟信号端clkb的电平设置上，可以在一帧时间内，将第一时钟信号端clk输出的第一时钟信号设置为有高低脉冲的方波信号，同时将第二时钟信号端clkb输出的第二时钟信号设置为低电平直流信号，在相邻的下一帧时间内，将第二时钟信号端clkb输出的第二时钟信号设置为有高低脉冲的方波信号，同时将第一时钟信号端clk输出的第一时钟信号设置为低电平直流信号。
由此，在驱动像素时，第一信号输出端output_a的信号和第二信号输出端output_b的信号可分别对应提供至图1中的第一扫描信号Vscan_a和第二扫描信号Vscan_b，即第一信号输出端output_a的信号对应图1中的第一扫描信号Vscan_a，第二信号输出端output_b的信号对应图1中的第二扫描信号Vscan_b。在一帧时间(例如，第一帧时间)内，第一输出电路12将第一时钟信号端clk的电压写入第一信号输出端output_a，在第一时钟信号端clk输出的第一时钟信号为高电平时，第一信号输出端output_a输出的信号为高电平，从而可以驱动例如图1中第一子像素电路(即第一数据写入晶体管T1、第一驱动晶体管T2和第一电容C1)工作，而第二输出电路22将第二时钟信号端clkb的电压写入第二信号输出端output_b，由于第二时钟信号端clkb输出的第二时钟信号为低电平，由此第二信号输出端output_b始终输出低电平的信号，从而无法进行像素驱动，例如不能驱动图1中第二子像素电路(即第二数据写入晶体管T1'、第二驱动晶体管T2'和第二电容C1')进行工作，即第二子像素电路不工作，综上，可实现图2中第N帧的驱动时序以驱动图1所示的像素电路。
在相邻的下一帧时间(例如，第二帧时间)内，第二输出电路22将第二时钟信号端clkb的电压写入第二信号输出端output_b，在第二时钟信号端clkb输出的第二时钟信号为高电平时，第二信号输出端output_b输出的信号为高电平，从而可以驱动例如图1中第二子像素电路(即第二数据写入晶体管T1'、第二驱动晶体管T2'和第二电容C1')工作，而第一输出电路12将第一时钟信号端clk的电压写入第一信号输出端output_a，由于第一时钟信号端clk输出的第一时钟信号为低电平，由此第一信号输出端output_a始终输出低电平的信号， 从而无法进行像素驱动，例如不能驱动图1中第一子像素电路(即第一数据写入晶体管T1、第一驱动晶体管T2和第一电容C1)进行工作，即第一子像素电路不工作，综上，可实现图2中第(N+1)帧的驱动时序以驱动图1所示的像素电路。
由此，第一移位寄存单元101与第二移位寄存单元102能够交替进行像素驱动，实现采用两套驱动设计的像素电路所需的驱动时序，并且易于实现。
图4A是根据本公开另一些实施例提供的一种移位寄存器的方框示意图，图4A所示的移位寄存器为图3B所示的移位寄存器的一个示例。
例如，如图4A所示，在一些实施例中，第一控制电路13包括第一复位电路14、第一下拉控制电路15和第一下拉电路16。
例如，第一复位电路14用于在第一复位信号端rst_a的控制下，对第一节点pu进行复位。如图4A所示，第一复位电路14分别与第一复位信号端rst_a、第三电源端vss和第一节点pu相连，第一复位电路14用于在第一复位信号端rst_a提供的第一复位电压的控制下将第三电源端vss的电压写入第一节点pu。
第一下拉控制电路15分别与第一节点pu和第二节点pd1相连，且被配置为在第一节点pu的电压的控制下，对第二节点pd1的电平进行控制。如图4A所示，第一下拉控制电路15还分别与第一电源端vdd1和第三电源端vss相连，第一下拉控制电路15用于在第一电源端vdd1提供的第一控制电压的控制下将第一控制电压写入第二节点pd1，并在第一节点pu的电压的控制下将第三电源端vss的电压写入第二节点pd1。
如图4A所示，第一下拉电路16分别与第二节点pd1、第一节点pu、第三电源端vss和第一信号输出端output_a相连，第一下拉电路16用于在第二节点pd1的电压的控制下，对第一节点pu和第一信号输出端output_a进行放电处理。
例如，如图4A所示，在一些实施例中，第二控制电路23包括第二复位电路24、第二下拉控制电路25和第二下拉电路26。
例如，第二复位电路24用于在第二复位信号端rst_b的控制下，对第一节点pu进行复位。如图4A所示，第二复位电路24分别与第二复位信号端rst_b、第三电源端vss和第一节点pu相连，第二复位电路24用于在第二复位信号端rst_b提供的第二复位电压的控制下将第三电源端vss的电压写入第一节点pu。
第二下拉控制电路25分别与第一节点pu、第三节点pd2相连，且被配置为在第一节点pu的电压的控制下，对第三节点pd2的电平进行控制。如图4A 所示，第二下拉控制电路25还分别与第二电源端vdd2和第三电源端vss相连，第二下拉控制电路25用于在第二电源端vdd2提供的第二控制电压的控制下将第二控制电压写入第三节点pd2，并在第一节点pu的电压的控制下将第三电源端vss的电压写入第三节点pd2。
如图4A所示，第二下拉电路26分别与第三节点pd2、第一节点pu、第三电源端vss和第二信号输出端output_b相连，第二下拉电路26用于在第三节点pd2的电压的控制下，对第一节点pu和第二信号输出端output_b进行放电处理。
例如，如图4A所示，第一下拉电路16还与第三节点pd2和第二信号输出端output_b相连，第一下拉电路16还用于在第二节点pd1的电压的控制下，对第三节点pd2和第二信号输出端output_b进行放电处理；第二下拉电路26还与第二节点pd1和第一信号输出端output_a相连，第二下拉电路26还用于在第三节点pd2的电压的控制下，对第二节点pd1和第一信号输出端output_a进行放电处理。
也就是说，在一帧时间(例如，第一帧时间)内，将第一电源端vdd1输出的第一控制电压的电平设置为高电平，同时第二电源端vdd2输出的第二控制电压的电平设置为低电平，此时，将对第一节点pu和第一信号输出端output_a进行放电，同时还对第二信号输出端output_b进行放电处理。在相邻的下一帧时间(例如，第二帧时间)内，将第一电源端vdd1输出的第一控制电压的电平设置为低电平，同时第二电源端vdd2输出的第二控制电压的电平设置为高电平，此时，将对第一节点pu和第二信号输出端output_b进行放电，同时还对第一信号输出端output_a进行放电处理。
图4B是根据本公开另一些实施例提供的又一种移位寄存器的方框示意图，图4B所示的移位寄存器为图3C所示的移位寄存器的一个示例。
例如，如图4B所示，第一控制电路31包括第一下拉控制电路34、第一下拉电路35和第一复位电路33。
例如，第一下拉控制电路34分别与第一节点pu和第二节点pd1相连，且被配置为在第一节点pu的电压的控制下，对第二节点pd1的电平进行控制。如图4B所示，第一下拉控制电路34还分别与第一电源端vdd1和第三电源端vss相连，第一下拉控制电路34用于在第一电源端vdd1提供的第一控制电压的控制下将第一控制电压写入第二节点pd1，并在第一节点pu的电压的控制下 将第三电源端vss的电压写入第二节点pd1。
例如，如图4B所示，第一下拉电路35分别与第一节点pu、第二节点pd1、第三电源端vss和第一信号输出端output_a相连，且被配置为在第二节点pd1的电压的控制下，对第一节点pu和第一信号输出端output_a进行放电处理。
例如，如图4B所示，第一复位电路33分别与第一复位信号端rst_a、第三电源端vss和第一节点pu相连，第一复位电路33用于在第一复位信号端rst_a提供的第一复位电压的控制下将第三电源端vss的电压写入第一节点pu。
例如，如图4B所示，第二控制电路32包括第一下拉控制电路34、第一下拉电路35和第二复位电路36，也就是说，在本示例中，第一控制电路31和第二控制电路32可以共用第一下拉控制电路34和第一下拉电路35，从而进一步节省晶体管数量，节省成本。
例如，如图4B所示，第一下拉电路34还与第二信号输出端output_a相连，且还被配置为在第二节点pd1的电压的控制下，对第二信号输出端output_a进行放电处理。
例如，第二复位电路36分别与第二复位信号端rst_b、第三电源端vss和第一节点pu相连，第二复位电路36用于在第二复位信号端rst_b提供的第二复位电压的控制下将第三电源端vss的电压写入第一节点pu。
例如，在一些示例中，“第一节点”为上拉节点，“第二节点”和“第三节点”均为下拉节点。需要说明的是，在本公开的实施例中，例如，当各个电路实现为N型晶体管时，术语“上拉”表示对一个节点或一个晶体管的一个电极进行充电，以使得该节点或该电极的电平的绝对值升高，从而实现相应晶体管的操作(例如导通)；“下拉”表示对一个节点或一个晶体管的一个电极进行放电，以使得该节点或该电极的电平的绝对值降低，从而实现相应晶体管的操作(例如截止)。又例如，当各个电路实现为P型晶体管时，术语“上拉”表示对一个节点或一个晶体管的一个电极进行放电，以使得该节点或该电极的电平的绝对值降低，从而实现相应晶体管的操作(例如导通)；“下拉”表示对一个节点或一个晶体管的一个电极进行充电，以使得该节点或该电极的电平的绝对值升高，从而实现相应晶体管的操作(例如截止)。
例如，任意两个相邻帧中的第一帧时间包括第一输入阶段、第一输出阶段和第一放电阶段，任意两个相邻帧中的第二帧时间包括第二输入阶段、第二输出阶段和第二放电阶段。
下面以图4A所示的移位寄存器为例详细说明移位寄存器的具体电路结构和工作过程。
例如，在一些实施例中，移位寄存器100的工作过程如下：
在任意两个相邻帧中的第一帧时间内，在第一输入阶段，第一信号输入端input_a输出第一输入信号，第一输入电路11在第一输入信号的控制下，向第一节点pu写入第一输入信号。
在第一输出阶段，第一时钟信号端clk输出第一时钟信号，且此时第一时钟信号具有第一电平，第一输出电路12在第一节点pu的电压的控制下，向第一信号输出端output_a输出第一时钟信号。需要说明的是，此时，第一节点pu的电压信号大于第一输入信号。
在第一放电阶段，第一复位信号端rst_a输出第一复位电压，第一电源端vdd1输出第一控制电压，第一控制电路13的第一复位电路14在第一复位电压的控制下向第一节点pu输出来自第三电源端vss的电压，第一控制电路13的第一下拉控制电路15在第一控制电压的控制下，向第二节点pd1输出第一控制电压，第一控制电路13的第一下拉电路16在第二节点pd1的控制下，分别向第一节点pu和第一信号输出端output_a输出来自第三电源端vss的电压。
在任意两个相邻帧的第二帧时间内，在第二输入阶段，第二信号输入端input_b输出第二输入信号，第二输入电路21在第二输入信号的控制下，向第一节点pu写入第二输入信号。
在第二输出阶段，第二时钟信号端clkb输出第二时钟信号，且此时第二时钟信号具有第一电平，第二输出电路22在第一节点pu的电压的控制下，向第二信号输出端input_b输出第二时钟信号。需要说明的是，此时，第一节点pu的电压信号大于第二输入信号。
在第二放电阶段，第二复位信号端rst_b输出第二复位电压，第二电源端vdd2输出第二控制电压，第二控制电路23的第二复位电路24在第二复位电压的控制下向第一节点pu输出来自第三电源端vss的电压，第二控制电路23的第二下拉控制电路25在第二控制电压的控制下，向第三节点pd2输出第二控制电压，第二控制电路23的第二下拉电路26在第三节点pd2的控制下，分别向第一节点pu和第二信号输出端output_b输出来自第三电源端vss的电压。
另外，第一帧时间包括第一中间阶段，第一中间阶段在第一输出阶段与第一放电阶段之间。在第一中间阶段，第一时钟信号端clk输出第一时钟信号， 且此时第一时钟信号具有第二电平，第一节点pu保持第一输入信号，第一输出电路12在第一节点pu的控制下，向第一信号输出端input_a输出具有第二电平的第一时钟信号。第二帧时间包括第二中间阶段，第二中间阶段在第二输出阶段与第二放电阶段之间。在第二中间阶段，第二时钟信号端clkb输出第二时钟信号，且此时第二时钟信号具有第二电平，第一节点pu保持第二输入信号，第二输出电路22在第一节点pu的控制下，向第二信号输出端input_b输出具有第二电平的第二时钟信号。
在本公开的一些具体示例中，第一电平、第一输入信号的电平、第二输入信号的电平、第一复位电压的电平、第二复位电压的电平、第一控制电压的电平和第二控制电压的电平均可为高电平，第三电源端vss的电压的电平和第二电平可为低电平。
例如，假设在一帧时间(例如，第N帧时间)内，第一控制电压的电平为高电平，第二控制电压的电平为低电平，第一时钟信号为脉冲信号，第二时钟信号为低电平直流信号，由此，在第N帧时间内，移位寄存器100的工作过程可以包括：
在第一输入阶段，第一信号输入端input_a输出的第一输入信号具有高电平，第一输入电路11开启，第一输入信号被写入第一节点pu，第一输出电路12和第二输出电路22在第一节点pu的控制下导通，因此，第一信号输出端output_a输出第一时钟信号，第二信号输出端output_b输出第二时钟信号，因第一时钟信号端clk输出的第一时钟信号和第二时钟信号端clkb输出的第二时钟信号均具有低电平，也就是说，第一信号输出端output_a和第二信号输出端output_b输出具有低电平的信号。此时，第二信号输入端input_b输出的第二输入信号具有低电平，因此第二输入电路21关断。因第一节点pu的电平为高电平，在第一节点pu的控制下，第一下拉控制电路15将第三电源端vss的电压写入第二节点pd1，第二下拉控制电路25将第三电源端vss的电压写入第三节点pd2。第一复位信号端rst_a输出的第一复位电压和第二复位信号端rst_b输出的第二复位电压均为例如低电平电压，因此，第一复位电路14和第二复位电路24关断。由此，在第一输入阶段，第一节点pu充电至高电平(例如，第一输入信号)，第一信号输出端output_a和第二信号输出端output_b输出具有低电平的信号。
在第一输出阶段，第一信号输入端input_a输出的第一输入信号和第二信 号输入端input_b输出的第二输入信号例如均具有低电平，此时第一输入电路11和第二输入电路21关断，但是由于第一输出电路12和第二输出电路22的电容保持作用，第一输出电路12和第二输出电路22继续开启，第一输出电路12输出第一时钟信号至第一信号输出端output_a，即第一信号输出端output_a输出第一时钟信号，因第一时钟信号端clk输出的第一时钟信号具有高电平，因此，第一信号输出端output_a输出具有高电平的信号。同时，由于第二输出电路22开启，第二输出电路22输出第二时钟信号至第二信号输出端output_b，即第二信号输出端output_b输出第二时钟信号，第二时钟信号端clkb输出的第二时钟信号具有低电平，因此第二信号输出端output_b输出具有低电平的信号。由于第一输出电路12和第二输出电路22的电容自举作用，第一节点pu的电压进一步升高，即此时第一节点pu处的电压信号大于第一输入信号，由此在第一节点pu控制下，第一下拉控制电路15将第三电源端vss的电压写入第二节点pd1，第二下拉控制电路25将第三电源端vss的电压写入第三节点pd2。并且，第一复位信号端rst_a输出的第一复位电压和第二复位信号端rst_b输出的第二复位电压均为低电平电压，因此，第一复位电路14和第二复位电路24关断。
在第一中间阶段，第一信号输入端input_a输出的第一输入信号和第二信号输入端input_b输出的第二输入信号均具有例如低电平，此时第一输入电路11和第二输入电路21关断，但是由于第一输出电路12和第二输出电路22的电容保持作用，第一输出电路12和第二输出电路22继续开启，因第一时钟信号端clk输出的第一时钟信号和第二时钟信号端clkb输出的第二时钟信号均具有低电平，由于第一信号输出端output_a输出第一时钟信号，第二信号输出端output_b输出第二时钟信号，也就是说，第一信号输出端output_a和第二信号输出端output_b均输出具有低电平的信号。由于第一节点pu点仍为高电平(例如，第一输入信号)，因此第二节点pd1和第三节点pd2仍保持为第三电源端vss的电压。第一复位信号端rst_a输出的第一复位电压和第二复位信号端rst_b输出的第二复位电压均为低电平电压，因此，第一复位电路14和第二复位电路24关断。
在第一放电阶段，第一复位信号端rst_a输出的第一复位电压具有高电平，第一复位电路14开启，第一节点pu被放电至低电平，即第一节点pu的电压被下拉至第三电源端vss的电压，因此第一输出电路12和第二输出电路22关 断，由于第一控制电压具有高电平，第一下拉控制电路15将第一控制电压写入第二节点pd1，也就是说，第二节点pd1被写入高电平电压，第一下拉电路16导通，使得第一节点pu、第一信号输出端output_a和第二信号输出端output_b放电至低电平，即第一节点pu、第一信号输出端output_a和第二信号输出端output_b被下拉至第三电源端vss的电压。因第二控制电压具有低电平，因此第三节点pd2的电位仍为低电平，第二下拉电路26关断。第二复位信号端rst_b输出的第二复位电压为低电平电压，第二复位电路24关断。
又例如，在相邻的下一帧时间(例如，第N+1帧时间)内，第一控制电压的电平为低电平，第二控制电压的电平为高电平，第一时钟信号为低电平直流信号，第二时钟信号为脉冲信号，由此，在第N+1帧时间内，移位寄存器100的工作过程可以包括：
在第二输入阶段，第二信号输入端input_b输出的第二输入信号具有高电平，第二输入电路21开启，第二输入信号被写入第一节点pu，第一输出电路12和第二输出电路22在第一节点pu的控制下导通，因此，第一信号输出端output_a输出第一时钟信号，第二信号输出端output_b输出第二时钟信号，因第一时钟信号端clk输出的第一时钟信号和第二时钟信号端clkb输出的第二时钟信号均具有低电平，也就是说，第一信号输出端output_a和第二信号输出端output_b输出具有低电平的信号。此时，第一信号输入端input_a输出的第一输入信号具有低电平，因此第一输入电路11关断。因第一节点pu的电平为高电平，在第一节点pu的控制下，第一下拉控制电路15将第三电源端vss的电压写入第二节点pd1，第二下拉控制电路25将第三电源端vss的电压写入第三节点pd2。第一复位信号端rst_a输出的第一复位电压和第二复位信号端rst_b输出的第二复位电压均为例如低电平电压，因此，第一复位电路14和第二复位电路24关断。由此，在第二输入阶段，第一节点pu充电至高电平(例如，第二输入信号)，第一信号输出端output_a和第二信号输出端output_b输出具有低电平的信号。
在第二输出阶段，第一信号输入端input_a输出的第一输入信号和第二信号输入端input_b输出的第二输入信号例如均具有低电平，此时第一输入电路11和第二输入电路21关断，但是由于第一输出电路12和第二输出电路22的电容保持作用，第一输出电路12和第二输出电路22继续开启，第二输出电路22输出第二时钟信号至第二信号输出端output_b，即第二信号输出端output_b 输出第二时钟信号，因第二时钟信号端clkb输出的第二时钟信号具有高电平，因此，第二信号输出端output_b输出具有高电平的信号。同时，由于第一输出电路12开启，第一输出电路12输出第一时钟信号至第一信号输出端output_a，即第一信号输出端output_a输出第一时钟信号，且第一时钟信号端clk输出的第一时钟信号具有低电平，因此第一信号输出端output_a输出具有低电平的信号。由于第一输出电路12和第二输出电路22的电容自举作用，第一节点pu的电压进一步升高，即此时第一节点pu处的电压信号大于第一输入信号，由此在第一节点pu控制下，第一下拉控制电路15将第三电源端vss的电压写入第二节点pd1，第二下拉控制电路25将第三电源端vss的电压写入第三节点pd2。第一复位信号端rst_a输出的第一复位电压和第二复位信号端rst_b输出的第二复位电压均为低电平电压，因此，第一复位电路14和第二复位电路24关断。
在第二中间阶段，第一信号输入端input_a输出的第一输入信号和第二信号输入端input_b输出的第二输入信号均具有低电平，此时第一输入电路11和第二输入电路21关断，但是由于第一输出电路12和第二输出电路22的电容保持作用，第一输出电路12和第二输出电路22继续开启，因第一时钟信号端clk输出的第一时钟信号和第二时钟信号端clkb输出的第二时钟信号均具有低电平，由于第一信号输出端output_a输出第一时钟信号，第二信号输出端output_b输出第二时钟信号，也就是说，第一信号输出端output_a和第二信号输出端output_b均输出具有低电平的信号。由于第一节点pu点仍为高电平(例如，第二输入信号)，因此第二节点pd1和第三节点pd2仍保持为第三电源端vss的电压。第一复位信号端rst_a输出的第一复位电压和第二复位信号端rst_b输出的第二复位电压均为低电平电压，因此，第一复位电路14和第二复位电路24关断。
在第二放电阶段，第二复位信号端rst_b输出的第一复位电压具有高电平，第二复位电路24开启，第一节点pu被放电至低电平，即第一节点pu的电压被下拉至第三电源端vss的电压，因此第一输出电路12和第二输出电路22关断，由于第二控制电压具有高电平，第二下拉控制电路25将第二控制电压写入第三节点pd2，也就是说，第三节点pd2被写入高电平电压，第二下拉电路26导通，使得第一节点pu、第一信号输出端output_a和第二信号输出端output_b放电至低电平，即第一节点pu、第一信号输出端output_a和第二信号输出端 output_b被下拉至第三电源端vss的电压。因第一控制电压具有低电平，因此第二节点pd1仍为低电平，第一下拉电路16关断。第一复位信号端rst_a输出的第一复位电压为低电平电压，第一复位电路14关断。
因此，在第一控制电压、第二控制电压在不同帧交替为高电平电压，同时配合第一时钟信号和第二时钟信号在不同帧交替为脉冲信号时，能够使得第一移位寄存单元101与第二移位寄存单元102在不同帧交替进行像素驱动，进而实现图2中的像素驱动时序。
图5A是根据本公开一些实施例提供的一种移位寄存器的电路原理图。下面结合附图5A对本公开一些实施例的移位寄存器的电路结构进行详细描述。图5A为图4A所示的移位寄存器的电路结构。
例如，如图5A所示，第一输入电路11包括第一晶体管M1，第一晶体管M1的第一极和控制极与第一信号输入端input_a相连以接收第一输入信号作为第一控制信号，第一晶体管M1的第二极与第一节点pu相连；第二输入电路21包括第二晶体管M2，第二晶体管M2的第一极和控制极与第二信号输入端input_b相连以接收第二输入信号作为第二控制信号，第二晶体管M2的第二极与第一节点pu相连。
例如，如图5A所示，第一输出电路12包括第三晶体管M3和第一电容C11，第三晶体管M3的第一极与第一时钟信号端clk相连，第三晶体管M3的第二极与第一信号输出端output_a相连，第三晶体管M3的控制极与第一节点pu相连，第一电容C11的第一端与第一节点pu相连，第一电容C11的第二端与第一信号输出端output_a相连；第二输出电路22包括第四晶体管M4和第二电容C22，第四晶体管M4的第一极与第二时钟信号端clkb相连，第四晶体管M4的第二极与第二信号输出端output_b相连，第四晶体管M4的控制极与第一节点pu相连，第二电容C22的第一端与第一节点pu相连，第二电容C22的第二端与第二信号输出端output_b相连。
如图5A所示，第一复位电路14包括第五晶体管M5，第五晶体管M5的第一极与第一节点pu相连，第五晶体管M5的第二极与第三电源端vss相连，第五晶体管M5的控制极与第一复位信号端rst_a相连；第二复位电路24包括第六晶体管M6，第六晶体管M6的第一极与第一节点pu相连，第六晶体管M6的第二极与第三电源端vss相连，第六晶体管M6的控制极与第二复位信号端rst_b相连。
如图5A所示，第一下拉控制电路15包括第七晶体管M7和第八晶体管M8，第七晶体管M7的第一极和控制极与第一电源端vdd1相连，第七晶体管M7的第二极与第二节点pd1相连，第八晶体管M8的第一极与第三电源端vss相连，第八晶体管M8的第二极与第二节点pd1相连，第八晶体管M8的控制极与第一节点pu相连；第二下拉控制电路25包括第九晶体管M9和第十晶体管M10，第九晶体管M9的第一极和控制极与第二电源端vdd2相连，第九晶体管M9的第二极与第三节点pd2相连，第十晶体管M10的第一极与第三电源端vss相连，第十晶体管M10的第二极与第三节点pd2相连，第十晶体管M10的控制极与第一节点pu相连。
如图5A所示，第一下拉电路16包括第十一晶体管M11和第十二晶体管M12，第十一晶体管M11的第一极与第一节点pu相连，第十一晶体管M11的第二极与第三电源端vss相连，第十一晶体管M11的控制极与第二节点pd1相连，第十二晶体管M12的第一极与第一信号输出端output_a相连，第十二晶体管M12的第二极与第三电源端vss相连，第十二晶体管M12的控制极与第二节点pd1相连；第二下拉电路26包括第十三晶体管M13和第十四晶体管M14，第十三晶体管M13的第一极与第一节点pu相连，第十三晶体管M13的第二极与第三电源端vss相连，第十三晶体管M13的控制极与第三节点pd2相连，第十四晶体管M14的第一极与第二信号输出端output_b相连，第十四晶体管M14的第二极与第三电源端vss相连，第十四晶体管M14的控制极与第三节点pd2相连。
如图5A所示，第一下拉电路16还包括第十五晶体管M15和第十六晶体管M16，第十五晶体管M15的第一极与第三节点pd2相连，第十五晶体管M15的第二极与第三电源端vss相连，第十五晶体管M15的控制极与第二节点pd1相连，第十六晶体管M16的第一极与第二信号输出端output_b相连，第十六晶体管M16的第二极与第三电源端vss相连，第十六晶体管M16的控制极与第二节点pd1相连；第二下拉电路26还包括第十七晶体管M17和第十八晶体管M18，第十七晶体管M17的第一极与第二节点pd1相连，第十七晶体管M17的第二极与第三电源端vss相连，第十七晶体管M17的控制极与第三节点pd2相连，第十八晶体管M18的第一极与第一信号输出端output_a相连，第十八晶体管M18的第二极与第三电源端vss相连，第十八晶体管M18的控制极与第三节点pd2相连。
图5B是根据本公开一些实施例提供的又一种移位寄存器的电路原理图，图5B为图4B所示的移位寄存器的电路结构。
与图5A所示的移位寄存器相比，图4B所示的移位寄存器可以不包括图5A所示的第九晶体管M9、第十晶体管M10、第十三晶体管M13、第十四晶体管M14、第十五晶体管M15、第十七晶体管M17和第十八晶体管M18。图5B所示的移位寄存器可以包括第一晶体管M1至第八晶体管M8、第十一晶体管M11、第十二晶体管M12、第十六晶体管M16、第电容C11和第二电容C22，且第一晶体管M1至第八晶体管M8、第十一晶体管M11、第十二晶体管M12、第十六晶体管M16、第电容C11和第二电容C22的连接方式与图5A所示相同。
例如，如图5B所示，第一输入电路11包括第一晶体管M1，第一晶体管M1的第一极和控制极与第一信号输入端input_a相连以接收第一输入信号作为第一控制信号，第一晶体管M1的第二极与第一节点pu相连；第二输入电路21包括第二晶体管M2，第二晶体管M2的第一极和控制极与第二信号输入端input_b相连以接收第二输入信号作为第二控制信号，第二晶体管M2的第二极与第一节点pu相连。
如图5B所示，第一输出电路12包括第三晶体管M3和第一电容C11，第三晶体管M3的第一极与第一时钟信号端clk相连，第三晶体管M3的第二极与第一信号输出端output_a相连，第三晶体管M3的控制极与第一节点pu相连，第一电容C11的第一端与第一节点pu相连，第一电容C11的第二端与第一信号输出端output_a相连；第二输出电路22包括第四晶体管M4和第二电容C22，第四晶体管M4的第一极与第二时钟信号端clkb相连，第四晶体管M4的第二极与第二信号输出端output_b相连，第四晶体管M4的控制极与第一节点pu相连，第二电容C22的第一端与第一节点pu相连，第二电容C22的第二端与第二信号输出端output_b相连。
如图5B所示，第一复位电路33包括第五晶体管M5，第五晶体管M5的第一极与第一节点pu相连，第五晶体管M5的第二极与第三电源端vss相连，第五晶体管M5的控制极与第一复位信号端rst_a相连；第二复位电路36包括第六晶体管M6，第六晶体管M6的第一极与第一节点pu相连，第六晶体管M6的第二极与第三电源端vss相连，第六晶体管M6的控制极与第二复位信号端rst_b相连。
如图5B所示，第一下拉控制电路34包括第七晶体管M7和第八晶体管 M8，第七晶体管M7的第一极和控制极与第一电源端vdd1相连，第七晶体管M7的第二极与第二节点pd1相连，第八晶体管M8的第一极与第三电源端vss相连，第八晶体管M8的第二极与第二节点pd1相连，第八晶体管M8的控制极与第一节点pu相连。
如图5B所示，第一下拉电路35包括第十一晶体管M11、第十二晶体管M12和第十六晶体管M16，第十一晶体管M11的第一极与第一节点pu相连，第十一晶体管M11的第二极与第三电源端vss相连，第十一晶体管M11的控制极与第二节点pd1相连，第十二晶体管M12的第一极与第一信号输出端output_a相连，第十二晶体管M12的第二极与第三电源端vss相连，第十二晶体管M12的控制极与第二节点pd1相连，第十六晶体管M16的第一极与第二信号输出端output_b相连，第十六晶体管M16的第二极与第三电源端vss相连，第十六晶体管M16的控制极与第二节点pd1相连。
如图5B所示，第二复位电路36包括第六晶体管M6，第六晶体管M6的第一极与第一节点pu相连，第六晶体管M6的第二极与第三电源端vss相连，第六晶体管M6的控制极与第二复位信号端rst_b相连。
需要说明的是，晶体管的控制极可指栅极，晶体管的第一极可指漏极，晶体管的第二极可指源极。
假设在一帧时间内，第一控制电压为高电平电压，第二控制电压为低电平电压，第一时钟信号为脉冲信号，第二时钟信号为低电平直流信号，下面结合图6的时序图详细描述图5A所示的移位寄存器的工作过程。在图6中以及下面的描述中，vdd1、vdd2、input_a、input_b、clk、clkb、rst_a、rst_b等既用于表示相应的信号端，也用于表示相应的信号。以下各实施例与此相同，不再赘述。
由于第一控制电压vdd1为高电平电压，因此第七晶体管M7在一帧时间内始终开启，而第二控制电压vdd2为低电平电压，因此第九晶体管M9在一帧时间内始终关闭。
例如，如图5A和图6所示，t1时间段对应第一输入阶段，在t1时间段，第一输入信号input_a具有高电平，第二输入信号input_b、第一时钟信号clk、第二时钟信号clkb、第一复位电压rst_a、第二复位电压rst_b均具有低电平，因第一输入信号input_a具有高电平，因此第一晶体管M1开启，第一输入信号input_a被写入第一节点pu、第一电容C11和第二电容C22，因此，第三晶 体管M3和第四晶体管M4开启，从而第一信号输出端output_a输出第一时钟信号clk，第二信号输出端output_b输出第二时钟信号clkb，由于第一时钟信号clk、第二时钟信号clkb均为低电平信号，因此第一信号输出端output_a和第二信号输出端output_b输出低电平信号。因第二输入信号input_b具有低电平，因此第二晶体管M2关断。另外，因为第一节点pu为高电平，因此第八晶体管M8和第十晶体管M10开启，第二节点pd1被拉至低电平电压(即第三电源端vss的电压)，第三节点pd2被拉至低电平电压(即第三电源端vss的电压)。由于第二节点pd1和第三节点pd2被拉至第三电源端vss的电压，因此，第十一晶体管M11至第十八晶体管M18均关断。另外，由于第一复位电压rst_a、第二复位电压rst_b均为低电平电压，因此第五晶体管M5和第六晶体管M6关断。由此，在第一输入阶段，可实现将第一节点pu充电至第一输入信号，第三晶体管M3和第四晶体管M4开启，且第一信号输出端output_a和第二信号输出端output_b输出具有低电平的信号。
可以理解的是，在t1时间段，第七晶体管M7和第八晶体管M8均开启，由于第七晶体管M7对第二节点pd1进行充电，第八晶体管M8对第二节点pd1进行放电，为了使第二节点pd1能被拉至低电平电压，可通过适当设置第七晶体管M7和第八晶体管M8的沟道宽度比值实现。例如，可适当设置第七晶体管M7和第八晶体管M8的沟道宽度比值,使得W(M8)>>W(M7)(例如W(M7):W(M8)＝1:5)，即第八晶体管M8的沟道宽度W(M8)远大于第七晶体管M7的沟道宽度W(M7),这样第八晶体管M8开启时对第二节点pd1的放电速度远大于第七晶体管M7开启时对第二节点pd1的充电速度，故无论第七晶体管M7是否开启，只要第八晶体管M8开启，第二节点pd1即可被拉至低电平电压。同理，可以对第九晶体管M9和第十晶体管M10的沟道宽度比值做类似设置，使得W(M10)>>W(M9)(例如W(M9):W(M10)＝1:5)，即第十晶体管M10的沟道宽度W(M10)远大于第九晶体管M9的沟道宽度W(M9)，使得第十晶体管M10开启时对第三节点pd2的放电速度远大于第九晶体管M9开启时对第三节点pd2点的充电速度，故无论第九晶体管M9是否开启，只要第十晶体管M10开启，第三节点pd2即被拉至低电平电压。
例如，如图5A和图6所示，t2时间段对应第一输出阶段，在t2时间段，第一时钟信号clk具有高电平，第一输入信号input_a、第二输入信号input_b、第二时钟信clkb、第一复位电压rst_a、第二复位电压rst_b均具有低电平。此 时，由于第一输入信号input_a和第二输入信号input_b为低电平，因此第一晶体管M1、第二晶体管M2关断，但是由于第一电容C11和第二电容C22的保持作用，第三晶体管M3和第四晶体管M4继续开启，因第一时钟信号clk具有高电平，因此第三晶体管M3输出高电平信号至第一信号输出端output_a，即第一信号输出端output_a输出高电平信号，由于第一电容C11的自举作用，因此第一节点pu的电位进一步被拉高，此时第一节点pu的电位峰值近似变为原来的2倍值。同时，由于第四晶体管M4开启，且第二时钟信号clkb仍具有低电平，因此第二信号输出端output_b仍输出低电平信号。因第八晶体管M8的放电速度远大于第七晶体管M7的放电速度，因此第二节点pd1的电位仍为低电平。第十晶体管M10开启，第二控制电压vdd2具有低电平，故第三节点pd2的电位仍为低电平。由于第二节点pd1和第三节点pd2的电位均为低电平，因此，第十一晶体管M11至第十八晶体管M18均关断。由于第一复位电压rst_a、第二复位电压rst_b均为低电平电压，因此，第五晶体管M5和第六晶体管M6均关断。
例如，如图5A和图6所示，t3时间段对应第一中间阶段(或者称第一信号输出端output_a复位阶段)。在t3时间段，第一时钟信号clk、第一输入信号input_a、第二输入信号input_b、第二时钟信号clkb、第一复位电压rst_a、第二复位电压rst_b均具有低电平。此时第一输入信号input_a和第二输入信号input_b具有低电平，因此第一晶体管M1和第二晶体管M2关断。由于第一电容C11和第二电容C22的保持作用，第三晶体管M3和第四晶体管M4继续开启，因第一时钟信号clk和第二时钟信号clkb均具有低电平，此时，由于第三晶体管M3的反向放电将第一信号输出端output_a的电位放电至低电平，同时第四晶体管M4开启，第二时钟信号clkb仍被写入第二信号输出端output_b，使得第二信号输出端output_b维持低电平。此时，在第一电容C11的自举作用下，第一节点pu的电位将下降到原来高电平的水平，即第一节点pu处的信号变约为第一输入信号。第一节点pu的电位仍为高电平，从而第二节点pd1和第三节点pd2的电位仍保持为低电平，因此，第十一晶体管M11至第十八晶体管M18均关断。由于第一复位电压rst_a、第二复位电压rst_b均为低电平电压，因此，第五晶体管M5和第六晶体管M6关断。
例如，如图5A和图6所示，t4时间段对应第一放电阶段。在t4时间段，第一复位电压rst_a具有高电平，第一时钟信号clk、第一输入信号input_a、 第二输入信号input_b、第二时钟信号clkb、第二复位电压rst_b均具有低电平。由于第一复位电压rst_a具有高电平，因此第五晶体管M5开启，故第一节点pu被放电至低电平，即第一节点pu的电压被下拉至第三电源端vss的电压，因此第三晶体管M3和第四晶体管M4关断，第八晶体管M8和第十晶体管M10关断。第七晶体管M7的控制极(即栅极)和第一极(即源极)均与第一电源端vdd1相连，第一电源端vdd1输出的第一控制电压vdd1具有高电平，因此，第七晶体管M7开启，第二节点pd1被写入高电平，即第一控制电压vdd1，故第十一晶体管M11、第十二晶体管M12、第十五晶体管M15和第十六晶体管M16开启，使得第一节点pu、第一信号输出端output_a和第二信号输出端output_b放电至低电平。因第二控制电压vdd2具有低电平，第三节点pd2的电位仍为低电平，因此第十三晶体管M13、第十四晶体管M14、第十七晶体管M17和第十八晶体管M18保持关断。此时，第一输入信号input_a和第二输入信号input_b均具有低电平，因此第一晶体管M1和第二晶体管M2关断。第二复位电压rst_b为低电平电压，因此第六晶体管M6关断。
由以上4个时间段(即t1时间段至t4时间段)的时序分析知道，图6的驱动时序在第一控制电压vdd1具有高电平，且第一时钟信号clk为脉冲时信号时，可以实现图2中第N帧时间的驱动时序；同理分析可以得到，在第二控制电压vdd2具有高电平，且第二时钟信号clkb为脉冲信号时，可以实现图2中第N+1帧时间的驱动时序。由此，在第一控制电压vdd1、第二控制电压vdd2在不同帧交替为高电平，同时配合第一时钟信号clk、第二时钟信号clkb在不同帧交替为脉冲信号时，能够实现图2中的像素驱动时序。
基于上述实施例，在不同帧时，第一时钟信号交替为脉冲信号和低电平直流信号，对应地，第二时钟信号交替为低电平直流信号和脉冲信号，能够实现第一移位寄存单元与第二移位寄存单元交替进行像素驱动，满足图2的驱动时序要求。另外，该移位寄存器整体上使用的晶体管数目较少，使得实现起来更加简单。
综上，根据本公开一些实施例提供的移位寄存器，在任意两个相邻帧的其中一帧时间(例如，第一帧时间)内，第一电源端输出第一控制电压，第一时钟信号和第一输入信号为脉冲信号，以使第一移位寄存单元工作，在任意两个相邻帧的另一帧时间(例如，第二帧时间)内，第二电源端输出第二控制电压，第二时钟信号和第二输入信号为脉冲信号，以使第二移位寄存单元工作，从而 第一移位寄存单元与第二移位寄存单元交替进行像素驱动，实现采用两套驱动设计的像素电路所需的驱动时序，并且易于实现。
本公开一些实施例还提供一种栅极驱动电路。图7是根据本公开一些实施例提供的一种栅极驱动电路的结构原理图，图8为根据本公开一些实施例提供的图7所示的栅极驱动电路的工作时序的示意图。
例如，如图7所示，栅极驱动电路包括多个移位寄存器(例如，图7所示的SR1、SR2、SR3和SR4)，多个移位寄存器级联连接。每个移位寄存器均为上述任一实施例所述的移位寄存器。下面以每个移位寄存器为图4A所示的移位寄存器为例说明栅极驱动电路。
根据本公开的一些实施例，多个级联的移位寄存器组成多个栅极驱动电路组，每个栅极驱动电路组包括2P个移位寄存器，每组栅极驱动电路组中的2P个移位寄存器与2P个时钟信号组对应，每个时钟信号组中的两个时钟信号分别提供至相应移位寄存器的第一时钟信号端clk和第二时钟信号端clkb，P为正整数。也就是说，每个移位寄存器对应一个时钟信号组，即一个时钟信号组中的两个时钟信号传输至对应图3-6所示的移位寄存器的第一时钟信号端clk和第二时钟信号端clkb，也就是说，一个时钟信号组包括一个第一时钟信号和一个第二时钟信号。例如，P为正整数。
例如，在第N帧时间内，第一时钟信号端clk输出的第一时钟信号为脉冲信号，且第二时钟信号端clkb输出的第二时钟信号为低电平直流信号，每组栅极驱动电路组包括2P个第一时钟信号端clk，且2P个第一时钟信号端clk输出的2P个第一时钟信号均为脉冲信号，假设脉冲信号的周期为T，那么，在2P个第一时钟信号中，第i+1个第一时钟信号的相位比第i个第一时钟信号的相位晚(T/2P)个周期。在相邻的第N+1帧时间内，第二时钟信号端clkb输出的第二时钟信号为脉冲信号，第一时钟信号端clk输出的第一时钟信号为低电平直流信号，每组栅极驱动电路组包括2P个第二时钟信号端clkb，且2P个第二时钟信号端clkb输出的2P个第一时钟信号为脉冲信号，假设脉冲信号的周期为T，那么，在2P个第二时钟信号中，第i+1个第二时钟信号的相位比第i个第二时钟信号的相位晚(T/2P)个周期。i为正整数。
当P＝1时，每级移位寄存器的第一信号输入端连接前1级移位寄存器的第一信号输出端，每级移位寄存器的第二信号输入端连接前1级移位寄存器的第二信号输出端，每级移位寄存器的第一复位信号端连接后1级移位寄存器的第 一信号输出端，每级移位寄存器的第二复位信号端连接后1级移位寄存器的第二信号输出端。
需要说明的是，前1级移位寄存器是指当前级移位寄存器的前1级移位寄存器，后1级移位寄存器是指当前级移位寄存器的后1级栅极驱动电路，以第j级作为当前级为例，第j级移位寄存器的前1级移位寄存器为第(j-1)级移位寄存器，第j级移位寄存器的后1级移位寄存器为第(j+1)级移位寄存器。也就是说，第j级移位寄存器的第一信号输入端连接第(j-1)级移位寄存器的第一信号输出端，第j级移位寄存器的第二信号输入端连接第(j-1)级移位寄存器的第二信号输出端，第j级移位寄存器的第一复位信号端连接第(j+1)级移位寄存器的第一信号输出端，第j级移位寄存器的第二复位信号端连接第(j+1)级移位寄存器的第二信号输出端。
当P大于1时，每级移位寄存器的第一信号输入端连接前P级移位寄存器的第一信号输出端，每级移位寄存器的第二信号输入端连接前P级移位寄存器的第二信号输出端，每级移位寄存器的第一复位信号端连接后(P+1)级移位寄存器的第一信号输出端，每级移位寄存器的第二复位信号端连接后(P+1)级移位寄存器的第二信号输出端。
需要说明的是，前P级移位寄存器是指当前级移位寄存器的前P级移位寄存器，后(P+1)级移位寄存器是指当前级移位寄存器的后(P+1)级移位寄存器，以第j级作为当前级为例，第j级移位寄存器的前P级移位寄存器为第(j-P)级移位寄存器，第j级移位寄存器的后(P+1)级移位寄存器为第(j+P+1)级移位寄存器。也就是说，第j级移位寄存器的第一信号输入端连接第(j-P)级移位寄存器的第一信号输出端，第j级移位寄存器的第二信号输入端连接第(j-P)级移位寄存器的第二信号输出端，第j级移位寄存器的第一复位信号端连接第(j+P+1)级移位寄存器的第一信号输出端，第j级移位寄存器的第二复位信号端连接第(j+P+1)级移位寄存器的第二信号输出端。
例如，j为大于P的整数。
可以理解的是，如图7所示，当前级移位寄存器不存在前P级移位寄存器或前1级移位寄存器时，可将当前级移位寄存器的第一信号输入端和第二信号输入端连接预设控制信号端STV。当前级移位寄存器不存在后(P+1)级移位寄存器或后1级移位寄存器时，可将当前级移位寄存器的第一复位信号端和第二复位信号端连接预设复位信号端。
下面结合图7和图8以4个时钟信号组为例进行详细说明，即P＝2。
如图7所示，栅极驱动电路包括第一级移位寄存器SR1、第二级移位寄存器SR2、第三级移位寄存器SR3和第四级移位寄存器SR4，其中，每级移位寄存器有第一信号输出端output_a和第二信号输出端output_b，在驱动像素时，第一信号输出端output_a和第二信号输出端output_b输出的信号可分别对应图2中的第一扫描信号Vscan_a和第二扫描信号Vscan_b。
例如，如图7所示，栅极驱动电路还包括第一时钟信号线clk1、第二时钟信号线clk2、第三时钟信号线clk3和第四时钟信号线clk4。各级移位寄存器与上述各时钟信号线的连接方式如下并以此类推。第4n-3级移位寄存器(例如，第一级移位寄存器SR1)的第一时钟信号端clk和第一时钟信号线clk1连接，第4n-2级移位寄存器(例如，第二级移位寄存器SR2)的第一时钟信号端clk和第二时钟信号线clk2连接，第4n-1级移位寄存器单元(例如，第三级移位寄存器SR3)的第一时钟信号端clk和第三时钟信号线clk3连接，第4n级移位寄存器单元(例如，第四级移位寄存器SR4)的第一时钟信号端clk和第四时钟信号线clk4连接。这里，n为大于0的整数。
例如，如图7所示，栅极驱动电路还包括第五时钟信号线clkb1、第六时钟信号线clkb2、第七时钟信号线clkb3和第八时钟信号线clkb4。各级移位寄存器与上述各时钟信号线的连接方式如下并以此类推。第4n-3级移位寄存器(例如，第一级移位寄存器SR1)的第二时钟信号端clkb和第五时钟信号线clkb1连接，第4n-2级移位寄存器(例如，第二级移位寄存器SR2)的第二时钟信号端clkb和第六时钟信号线clkb2连接，第4n-1级移位寄存器单元(例如，第三级移位寄存器SR3)的第二时钟信号端clkb和第七时钟信号线clkb3连接，第4n级移位寄存器单元(例如，第四级移位寄存器SR4)的第二时钟信号端clkb和第八时钟信号线clkb4连接。
例如，如图7所示，栅极驱动电路还包括第一电源线vdd1、第二电源线vdd2和第三电源线vss，每级移位寄存器的第一电源端vdd1与第一电源线vdd1连接，每级移位寄存器的第二电源端vdd2与第二电源线vdd2连接，每级移位寄存器的第三电源端vss与第三电源线vss连接。
并且，如图7所示，第一级移位寄存器SR1的第一信号输出端output1_a和第二信号输出端output1_b分别连接第三级移位寄存器SR3的第一信号输入端input3_a和第二信号输入端input3_b,第二级移位寄存器SR2的第一信号输 出端output2_a和第二信号输出端output2_b分别连接第四级移位寄存器SR4的第一信号输入端input4_a和第二信号输入端input4_b；第四级移位寄存器SR4的输出第一信号输出端output4_a和第二信号输出端output4_b分别连接到第一级移位寄存器SR1的第一复位信号端rst_a和第二复位信号端rst_b。
如图8所示，在第一时钟信号线clk1、第二时钟信号线clk2、第三时钟信号线clk3和第四时钟信号线clk4输出的信号均为脉冲信号，第五时钟信号线clkb1、第六时钟信号线clkb2、第七时钟信号线clkb3和第八时钟信号线clkb4输出的信号均为低电平直流信号时，第一级移位寄存器的第一信号输出端output1_a至第四级移位寄存器的第一信号输出端output4_a依次输出行驱动信号，而第一级移位寄存器的第二信号输出端output1_b至第四级移位寄存器的第二信号输出端output4_b则始终输出低电平信号。同理，在第五时钟信号线clkb1、第六时钟信号线clkb2、第七时钟信号线clkb3和第八时钟信号线clkb4输出的信号均为脉冲信号，第一时钟信号线clk1、第二时钟信号线clk2、第三时钟信号线clk3和第四时钟信号线clk4输出的信号均为低电平直流信号时，第一级移位寄存器的第二信号输出端output1_b至第四级移位寄存器的第二信号输出端output4_b依次输出行驱动信号，而第一级移位寄存器的第一信号输出端output1_a至第四级移位寄存器的第一信号输出端output4_a则始终输出低电平信号。
由此，通过上述移位寄存器的级联结构，在不同帧时，每级移位寄存器的第一时钟信号交替为脉冲信号和低电平直流信号，对应地，每级移位寄存器的第二时钟信号交替为低电平直流信号和脉冲信号，能够实现每级移位寄存器的第一移位寄存单元与第二移位寄存单元交替进行像素驱动的驱动时序，且整体上使用的晶体管数目较少，使得栅极驱动电路实现起来更加简单。
综上，根据本公开一些实施例提供的栅极驱动电路，通过多级移位寄存器的第一移位寄存单元与第二移位寄存单元交替进行像素驱动，实现采用两套驱动设计的像素电路所需的驱动时序，且易于实现。
本公开一些实施例还提供一种显示装置。图9是根据本公开一些实施例提供的一种显示装置的方框示意图。例如，如图9所示，显示装置30包括栅极驱动电路20，栅极驱动电路20为本公开上面任一实施例所述的栅极驱动电路。
例如，显示装置30可以为液晶显示(Liquid Crystal Display,LCD)面板、LCD电视、显示器、有机发光二极管(Organic Light-Emitting Diode,OLED) 面板、OLED电视、电子纸显示装置、手机、平板电脑、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本公开的实施例对此不作限制。显示装置30的技术效果可以参考上述实施例中关于移位寄存器100和栅极驱动电路20的相应描述，这里不再赘述。
本公开一些实施例还提供一种移位寄存器的控制方法。图10是根据本公开一些实施例提供的一种移位寄存器的控制方法的流程图，图11是根据本公开一些实施例提供的另一种移位寄存器的控制方法的流程图。
例如，任意两个相邻帧包括第一帧和第二帧。如图10所示，该移位寄存器100的控制方法包括如下操作：
S100：在第一帧时间，在第一输入信号的控制下，通过第一移位寄存器单元将第一控制信号写入第一节点，并在第一节点的电压的控制下，通过第一移位寄存单元将第一时钟信号写入第一信号输出端，其中，第一时钟信号和第一输入信号为脉冲信号；
S200：在第二帧时间，在第二输入信号的控制下，通过第二移位寄存器单元将第二控制信号写入第一节点，并在第一节点的电压的控制下，通过第二移位寄存单元将第二时钟信号写入第二信号输出端，其中，第二时钟信号和第二输入信号为脉冲信号。
例如，每个移位寄存器包括第一移位寄存单元和第二移位寄存单元。第一移位寄存单元包括第一输入电路、第一输出电路和第一控制电路，第二移位寄存单元包括第二输入电路、第二输出电路和第二控制电路。
下面以每个移位寄存器为图4A所示的移位寄存器为例说明移位寄存器的控制方法。
例如，第一帧时间包括第一输入阶段、第一输出阶段和第一放电阶段，第二帧时间包括第二输入阶段、第二输出阶段和第二放电阶段。
例如，如图11所示，步骤S100包括：
S1：在第一输入阶段，第一信号输入端输出第一输入信号，第一输入电路在第一输入信号的控制下，向第一节点写入第一控制信号；
S2：在第一输出阶段，第一时钟信号端输出第一时钟信号，第一输出电路在第一节点的电压的控制下，向第一信号输出端输出第一时钟信号；
S3：在第一放电阶段，第一复位信号端输出第一复位电压，第一电源端输出第一控制电压，在第一复位电压和第一控制电压的控制下，通过第一控制电 路将第三电源端的电压分别写入第一节点和第一信号输出端。
例如，在步骤S3中，第一复位电压具有高电平。
例如，如图11所示，步骤S200包括：
S4：在第二输入阶段，第二信号输入端输出第二输入信号，第二输入电路在第二输入信号的控制下，向第一节点写入第二控制信号；
S5：在第二输出阶段，第二时钟信号端输出第二时钟信号，第二输出电路在第一节点的电压的控制下，向第二信号输出端输出第二时钟信号；
S6：在第二放电阶段，第二复位信号端输出第二复位电压，第二电源端输出第二控制电压，在第二复位电压和第二控制电压的控制下，通过第二控制电路将第三电源端的电压分别写入第一节点和第二信号输出端。
例如，在步骤S6中，第二复位电压具有高电平。
需要说明的是，关于步骤S1-S6的详细说明可以参考上述移位寄存器的实施例中的相关描述，重复之处在此不再赘述。
根据本公开一些实施例提出的移位寄存器的控制方法，在任意两个相邻帧的其中一帧时间(例如，第一帧时间)内，第一电源端输出第一控制电压，第一时钟信号和第一输入信号为脉冲信号，以使第一移位寄存单元工作，在任意两个相邻帧的另一帧时间(例如，第二帧时间)内，第二电源端输出第二控制电压，第二时钟信号和第二输入信号为脉冲信号，以使第二移位寄存单元工作，从而第一移位寄存单元与第二移位寄存单元交替进行像素驱动，实现采用两套驱动设计的像素电路所需的驱动时序，并且易于实现。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。在本公开的描述中，“多 个”的含义是至少两个，例如两个，三个等，除非另有明确具体的限定。
流程图中或在此以其他方式描述的任何过程或方法描述可以被理解为，表示包括一个或更多个用于实现定制逻辑功能或过程的步骤的可执行指令的代码的电路、片段或部分，并且本公开的优选实施方式的范围包括另外的实现，其中可以不按所示出或讨论的顺序，包括根据所涉及的功能按基本同时的方式或按相反的顺序，来执行功能，这应被本公开的实施例所属技术领域的技术人员所理解。
在流程图中表示或在此以其他方式描述的逻辑和/或步骤，例如，可以被认为是用于实现逻辑功能的可执行指令的定序列表，可以具体实现在任何计算机可读介质中，以供指令执行系统、装置或设备(如基于计算机的系统、包括处理器的系统或其他可以从指令执行系统、装置或设备取指令并执行指令的系统)使用，或结合这些指令执行系统、装置或设备而使用。就本说明书而言，"计算机可读介质"可以是任何可以包含、存储、通信、传播或传输程序以供指令执行系统、装置或设备或结合这些指令执行系统、装置或设备而使用的装置。计算机可读介质的更具体的示例(非穷尽性列表)包括以下：具有一个或多个布线的电连接部(电子装置)，便携式计算机盘盒(磁装置)，随机存取存储器(RAM)，只读存储器(ROM)，可擦除可编辑只读存储器(EPROM或闪速存储器)，光纤装置，以及便携式光盘只读存储器(CDROM)。另外，计算机可读介质甚至可以是可在其上打印所述程序的纸或其他合适的介质，因为可以例如通过对纸或其他介质进行光学扫描，接着进行编辑、解译或必要时以其他合适方式进行处理来以电子方式获得所述程序，然后将其存储在计算机存储器中。
应当理解，本公开的各部分可以用硬件、软件、固件或它们的组合来实现。在上述实施方式中，多个步骤或方法可以用存储在存储器中且由合适的指令执行系统执行的软件或固件来实现。如，如果用硬件来实现和在另一实施方式中一样，可用本领域公知的下列技术中的任一项或他们的组合来实现：具有用于对数据信号实现逻辑功能的逻辑门电路的离散逻辑电路，具有合适的组合逻辑门电路的专用集成电路，可编程门阵列(PGA)，现场可编程门阵列(FPGA)等。
本技术领域的普通技术人员可以理解实现上述实施例方法携带的全部或部分步骤是可以通过程序来指令相关的硬件完成，所述的程序可以存储于一种 计算机可读存储介质中，该程序在执行时，包括方法实施例的步骤之一或其组合。
此外，在本公开各个实施例中的各功能电路可以集成在一个处理电路中，也可以是各个电路单独物理存在，也可以两个或两个以上电路集成在一个电路中。上述集成的电路既可以采用硬件的形式实现，也可以采用软件功能电路的形式实现。所述集成的电路如果以软件功能电路的形式实现并作为独立的产品销售或使用时，也可以存储在一个计算机可读取存储介质中。
上述提到的存储介质可以是只读存储器，磁盘或光盘等。尽管上面已经示出和描述了本公开的实施例，可以理解的是，上述实施例是示例性的，不能理解为对本公开的限制，本领域的普通技术人员在本公开的范围内可以对上述实施例进行变化、修改、替换和变型。
对于本公开，还有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本发明的实施例的附图中，层或结构的厚度和尺寸被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (29)

  1. 一种移位寄存器，包括第一移位寄存单元和第二移位寄存单元，
    其中，所述第一移位寄存器单元与第一节点、第一信号输入端、第一时钟信号端和第一信号输出端电连接，所述第二移位寄存器单元与所述第一节点、第二信号输入端、第二时钟信号端和第二信号输出端电连接，
    所述第一移位寄存器单元被配置为在所述第一信号输入端提供的第一输入信号的控制下将第一控制信号写入所述第一节点，并在所述第一节点的电压的控制下将所述第一时钟信号端提供的第一时钟信号写入所述第一信号输出端；
    所述第二移位寄存器单元被配置为在所述第二信号输入端提供的第二输入信号的控制下将第二控制信号写入所述第一节点，并在所述第一节点的电压的控制下将所述第二时钟信号端提供的第二时钟信号写入所述第二信号输出端；
    任意两个相邻帧包括第一帧和第二帧，
    在所述第一帧时间内，所述第一时钟信号和所述第一输入信号为脉冲信号，所述第二时钟信号和所述第二输入信号为直流信号；
    在所述第二帧时间内，所述第一时钟信号和所述第一输入信号为直流信号，所述第二时钟信号和所述第二输入信号为脉冲信号。
  2. 根据权利要求1所述的移位寄存器，其中，
    所述第一移位寄存单元包括第一输入电路和第一输出电路，所述第二移位寄存单元包括第二输入电路和第二输出电路，
    所述第一输入电路分别与所述第一信号输入端和所述第一节点相连，所述第一输入电路用于在所述第一信号输入端提供的第一输入信号的控制下将所述第一控制信号写入所述第一节点；
    所述第一输出电路分别与所述第一节点、所述第一时钟信号端和所述第一信号输出端相连，所述第一输出电路用于在所述第一节点的电压的控制下将所述第一时钟信号写入所述第一信号输出端；
    所述第二输入电路分别与所述第二信号输入端和所述第一节点相连，所述第二输入电路用于在所述第二信号输入端提供的第二输入信号的控制下将所述第二控制信号写入所述第一节点；
    所述第二输出电路分别与所述第一节点、所述第二时钟信号端和所述第二信号输出端相连，所述第二输出电路用于在所述第一节点的电压的控制下将所述第二时钟信号写入所述第二信号输出端。
  3. 根据权利要求2所述的移位寄存器，其中，所述第一移位寄存器单元还包括第一控制电路，所述第二移位寄存器单元还包括第二控制电路，
    所述第一控制电路分别与第一电源端、所述第一节点、第一复位信号端、第三电源端和所述第一信号输出端相连，所述第一控制电路用于在所述第一电源端提供的第一控制电压和所述第一复位信号端提供的第一复位电压的控制下对所述第一信号输出端和所述第一节点的电压进行控制；
    所述第二控制电路分别与第二电源端、所述第一节点、第二复位信号端、所述第三电源端和所述第二信号输出端相连，所述第二控制电路用于在所述第二电源端提供的第二控制电压和所述第二复位信号端提供的第二复位电压的控制下对所述第二信号输出端和所述第一节点的电压进行控制；
    其中，在所述第一帧时间内，所述第一电源端输出所述第一控制电压，在所述第二帧时间内，所述第二电源端输出所述第二控制电压。
  4. 根据权利要求3所述的移位寄存器，其中，所述第一控制电压和所述第二控制电压均具有高电平。
  5. 根据权利要求3或4所述的移位寄存器，其中，所述第一控制电路包括第一下拉控制电路和第一下拉电路，
    所述第一下拉控制电路分别与所述第一节点和第二节点相连，且被配置为在所述第一节点的电压的控制下，对所述第二节点的电平进行控制，
    所述第一下拉电路分别与所述第一节点、所述第二节点、所述第三电源端和所述第一信号输出端相连，且被配置为在所述第二节点的电压的控制下，对所述第一节点和所述第一信号输出端进行放电处理。
  6. 根据权利要求5所述的移位寄存器，其中，
    所述第一下拉控制电路还分别与所述第一电源端和所述第三电源端相连，所述第一下拉控制电路用于在所述第一控制电压的控制下将所述第一控制电压写入所述第二节点，并在所述第一节点的电压的控制下将所述第三电源端的电压写入所述第二节点。
  7. 根据权利要求5或6所述的移位寄存器，其中，所述第一控制电路还包括第一复位电路，
    所述第一复位电路分别与所述第一复位信号端、所述第三电源端和所述第一节点相连，所述第一复位电路用于在所述第一复位电压的控制下将所述第三电源端的电压写入所述第一节点。
  8. 根据权利要求5-7任一项所述的移位寄存器，其中，所述第一下拉电路还与第三节点和所述第二信号输出端相连，所述第一下拉电路还被配置为在所述第二节点的电压的控制下，对所述第三节点和所述第二信号输出端进行放电处理。
  9. 根据权利要求3-8任一项所述的移位寄存器，其中，所述第二控制电路包括第二下拉控制电路和第二下拉电路，
    所述第二下拉控制电路分别与所述第一节点和第三节点相连，且被配置为在所述第一节点的电压的控制下，对所述第三节点的电平进行控制，
    所述第二下拉电路分别与所述第一节点、所述第三节点、所述第三电源端和所述第二信号输出端相连，且被配置为在所述第三节点的电压的控制下，对所述第一节点和所述第二信号输出端进行放电处理。
  10. 根据权利要求9所述的移位寄存器，其中，所述第二下拉控制电路还分别与所述第二电源端和所述第三电源端相连，所述第二下拉控制电路用于在所述第二控制电压的控制下将所述第二控制电压写入所述第三节点，并在所述第一节点的电压的控制下将所述第三电源端的电压写入所述第三节点。
  11. 根据权利要求9或10所述的移位寄存器，其中，所述第二控制电路还包括第二复位电路，
    所述第二复位电路分别与所述第二复位信号端、所述第三电源端和所述第一节点相连，所述第二复位电路用于在所述第二复位电压的控制下将所述第三电源端的电压写入所述第一节点。
  12. 根据权利要求9-11任一项所述的移位寄存器，其中，所述第二下拉电路还与所述第二节点和所述第一信号输出端相连，所述第二下拉电路还被配置为在所述第三节点的电压的控制下，对所述第二节点和所述第一信号输出端进行放电处理。
  13. 根据权利要求2所述的移位寄存器，其中，所述第一移位寄存器单元还包括第一控制电路，所述第二移位寄存器单元还包括第二控制电路，
    所述第一控制电路分别与第一电源端、所述第一节点、第一复位信号端、第三电源端和所述第一信号输出端相连，所述第一控制电路用于在所述第一电 源端提供的第一控制电压和所述第一复位信号端提供的第一复位电压的控制下对所述第一信号输出端和所述第一节点的电压进行控制；
    所述第二控制电路分别与所述第一电源端、所述第一节点、第二复位信号端、所述第三电源端和所述第二信号输出端相连，所述第二控制电路用于在所述第一电源端提供的第一控制电压和所述第二复位信号端提供的第二复位电压的控制下对所述第二信号输出端和所述第一节点的电压进行控制；
    其中，在所述第一帧时间和所述第二帧时间内，所述第一电源端均输出所述第一控制电压。
  14. 根据权利要求13所述的移位寄存器，其中，所述第一控制电路包括第一下拉控制电路、第一下拉电路和第一复位电路，
    所述第一下拉控制电路分别与所述第一节点和第二节点相连，且被配置为在所述第一节点的电压的控制下，对所述第二节点的电平进行控制；
    所述第一下拉电路分别与所述第一节点、所述第二节点、所述第三电源端和所述第一信号输出端相连，且被配置为在所述第二节点的电压的控制下，对所述第一节点和所述第一信号输出端进行放电处理；
    所述第一复位电路分别与所述第一复位信号端、所述第三电源端和所述第一节点相连，所述第一复位电路用于在所述第一复位电压的控制下将所述第三电源端的电压写入所述第一节点。
  15. 根据权利要求14所述的移位寄存器，其中，所述第二控制电路包括所述第一下拉控制电路、所述第一下拉电路和第二复位电路，
    所述第一下拉电路还与所述第二信号输出端相连，且还被配置为在所述第二节点的电压的控制下，对所述第二信号输出端进行放电处理；
    所述第二复位电路分别与所述第二复位信号端、所述第三电源端和所述第一节点相连，所述第二复位电路用于在所述第二复位电压的控制下将所述第三电源端的电压写入所述第一节点。
  16. 根据权利要求14或15所述的移位寄存器，其中，
    所述第一下拉控制电路还分别与所述第一电源端和所述第三电源端相连，所述第一下拉控制电路用于在所述第一控制电压的控制下将所述第一控制电压写入所述第二节点，并在所述第一节点的电压的控制下将所述第三电源端的电压写入所述第二节点。
  17. 根据权利要求2-16中任一项所述的移位寄存器，其中，
    所述第一输入电路包括第一晶体管，所述第一晶体管的第一极和控制极与所述第一信号输入端相连以接收所述第一输入信号作为所述第一控制信号，所述第一晶体管的第二极与所述第一节点相连；
    所述第二输入电路包括第二晶体管，所述第二晶体管的第一极和控制极与所述第二信号输入端相连以接收所述第二输入信号作为所述第二控制信号，所述第二晶体管的第二极与所述第一节点相连。
  18. 根据权利要求2-17中任一项所述的移位寄存器，其中，
    所述第一输出电路包括第三晶体管和第一电容，所述第三晶体管的第一极与所述第一时钟信号端相连，所述第三晶体管的第二极与所述第一信号输出端相连，所述第三晶体管的控制极与所述第一节点相连，所述第一电容的第一端与所述第一节点相连，所述第一电容的第二端与所述第一信号输出端相连；
    所述第二输出电路包括第四晶体管和第二电容，所述第四晶体管的第一极与所述第二时钟信号端相连，所述第四晶体管的第二极与所述第二信号输出端相连，所述第四晶体管的控制极与所述第一节点相连，所述第二电容的第一端与所述第一节点相连，所述第二电容的第二端与所述第二信号输出端相连。
  19. 根据权利要求5-8任一项所述的移位寄存器，其中，
    所述第一下拉控制电路包括第七晶体管和第八晶体管，所述第七晶体管的第一极和控制极与所述第一电源端相连，所述第七晶体管的第二极与所述第二节点相连，所述第八晶体管的第一极与所述第三电源端相连，所述第八晶体管的第二极与所述第二节点相连，所述第八晶体管的控制极与所述第一节点相连；
    所述第一下拉电路包括第十一晶体管和第十二晶体管，所述第十一晶体管的第一极与所述第一节点相连，所述第十一晶体管的第二极与所述第三电源端相连，所述第十一晶体管的控制极与所述第二节点相连，所述第十二晶体管的第一极与所述第一信号输出端相连，所述第十二晶体管的第二极与所述第三电源端相连，所述第十二晶体管的控制极与所述第二节点相连。
  20. 根据权利要求19所述的移位寄存器，其中，
    所述第一下拉电路还包括第十五晶体管和第十六晶体管，所述第十五晶体管的第一极与第三节点相连，所述第十五晶体管的第二极与所述第三电源端相连，所述第十五晶体管的控制极与所述第二节点相连，所述第十六晶体管的第一极与所述第二信号输出端相连，所述第十六晶体管的第二极与所述第三电源 端相连，所述第十六晶体管的控制极与所述第二节点相连。
  21. 根据权利要求7或14-16任一项所述的移位寄存器，其中，
    所述第一复位电路包括第五晶体管，所述第五晶体管的第一极与所述第一节点相连，所述第五晶体管的第二极与所述第三电源端相连，所述第五晶体管的控制极与所述第一复位信号端相连。
  22. 根据权利要求9-12所述的移位寄存器，其中，
    所述第二下拉控制电路包括第九晶体管和第十晶体管，所述第九晶体管的第一极和控制极与所述第二电源端相连，所述第九晶体管的第二极与所述第三节点相连，所述第十晶体管的第一极与所述第三电源端相连，所述第十晶体管的第二极与所述第三节点相连，所述第十晶体管的控制极与所述第一节点相连；
    所述第二下拉电路包括第十三晶体管和第十四晶体管，所述第十三晶体管的第一极与所述第一节点相连，所述第十三晶体管的第二极与所述第三电源端相连，所述第十三晶体管的控制极与所述第三节点相连，所述第十四晶体管的第一极与所述第二信号输出端相连，所述第十四晶体管的第二极与所述第三电源端相连，所述第十四晶体管的控制极与所述第三节点相连。
  23. 根据权利要求22所述的移位寄存器，其中，
    所述第二下拉电路还包括第十七晶体管和第十八晶体管，所述第十七晶体管的第一极与所述第二节点相连，所述第十七晶体管的第二极与所述第三电源端相连，所述第十七晶体管的控制极与所述第三节点相连，所述第十八晶体管的第一极与所述第一信号输出端相连，所述第十八晶体管的第二极与所述第三电源端相连，所述第十八晶体管的控制极与所述第三节点相连。
  24. 根据权利要求11或15所述的移位寄存器，所述第二复位电路包括第六晶体管，所述第六晶体管的第一极与所述第一节点相连，所述第六晶体管的第二极与所述第三电源端相连，所述第六晶体管的控制极与所述第二复位信号端相连。
  25. 一种栅极驱动电路，包括多个级联的如权利要求1-24中任一项所述的移位寄存器。
  26. 根据权利要求25所述的栅极驱动电路，其中，所述多个级联的移位寄存器组成多个栅极驱动电路组，每个栅极驱动电路组包括2P个移位寄存器，所述每个栅极驱动电路组中的所述2P个移位寄存器与2P个时钟信号组对应， 每个时钟信号组中的两个时钟信号分别提供至相应移位寄存器的第一时钟信号端和第二时钟信号端，
    当P＝1时，第j级移位寄存器的第一信号输入端连接第(j-1)级移位寄存器的第一信号输出端，所述第j级移位寄存器的第二信号输入端连接所述第(j-1)级移位寄存器的第二信号输出端，所述第j级移位寄存器的第一复位信号端连接第(j+1)级移位寄存器的第一信号输出端，所述第j级移位寄存器的第二复位信号端连接所述第(j+1)级移位寄存器的第二信号输出端；
    当P大于1时，所述第j级移位寄存器的第一信号输入端连接第(j-P)级移位寄存器的第一信号输出端，所述第j级移位寄存器的第二信号输入端连接所述第(j-P)级移位寄存器的第二信号输出端，所述第j级移位寄存器的第一复位信号端连接第(j+P+1)级移位寄存器的第一信号输出端，所述第j级移位寄存器的第二复位信号端连接所述第(j+P+1)级移位寄存器的第二信号输出端，
    其中，P为正整数，j为大于P的整数。
  27. 一种显示装置，包括根据权利要求25或26所述的栅极驱动电路。
  28. 一种如权利要求1-24中任一项所述的移位寄存器的控制方法，包括：
    在所述第一帧时间，在所述第一输入信号的控制下，通过所述第一移位寄存器单元将第一控制信号写入所述第一节点，并在所述第一节点的电压的控制下，通过所述第一移位寄存单元将所述第一时钟信号写入所述第一信号输出端，其中，所述第一时钟信号和所述第一输入信号为脉冲信号；
    在所述第二帧时间，在所述第二输入信号的控制下，通过所述第二移位寄存器单元将第二控制信号写入所述第一节点，并在所述第一节点的电压的控制下，通过所述第二移位寄存单元将所述第二时钟信号写入所述第二信号输出端，其中，所述第二时钟信号和所述第二输入信号为脉冲信号。
  29. 一种如权利要求3-12所述的移位寄存器的控制方法，
    其中，所述第一帧时间包括第一输入阶段、第一输出阶段和第一放电阶段，所述第二帧时间包括第二输入阶段、第二输出阶段和第二放电阶段，
    所述控制方法包括：
    在所述第一输入阶段，所述第一信号输入端输出所述第一输入信号，所述第一输入电路在所述第一输入信号的控制下，向所述第一节点写入所述第一控制信号；
    在所述第一输出阶段，所述第一时钟信号端输出所述第一时钟信号，所述第一输出电路在所述第一节点的电压的控制下，向所述第一信号输出端输出所述第一时钟信号；
    在所述第一放电阶段，所述第一复位信号端输出所述第一复位电压，所述第一电源端输出所述第一控制电压，在所述第一复位电压和所述第一控制电压的控制下，通过所述第一控制电路将所述第三电源端的电压分别写入所述第一节点和所述第一信号输出端；
    在所述第二输入阶段，所述第二信号输入端输出所述第二输入信号，所述第二输入电路在所述第二输入信号的控制下，向所述第一节点写入所述第二控制信号；
    在所述第二输出阶段，所述第二时钟信号端输出所述第二时钟信号，所述第二输出电路在所述第一节点的电压的控制下，向所述第二信号输出端输出所述第二时钟信号；
    在所述第二放电阶段，所述第二复位信号端输出所述第二复位电压，所述第二电源端输出所述第二控制电压，在所述第二复位电压和所述第二控制电压的控制下，通过所述第二控制电路将所述第三电源端的电压分别写入所述第一节点和所述第二信号输出端。
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