WO2020083275A1 - 移位寄存器单元、栅极驱动电路、显示装置及驱动方法 - Google Patents

移位寄存器单元、栅极驱动电路、显示装置及驱动方法 Download PDF

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Publication number
WO2020083275A1
WO2020083275A1 PCT/CN2019/112498 CN2019112498W WO2020083275A1 WO 2020083275 A1 WO2020083275 A1 WO 2020083275A1 CN 2019112498 W CN2019112498 W CN 2019112498W WO 2020083275 A1 WO2020083275 A1 WO 2020083275A1
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WIPO (PCT)
Prior art keywords
pull
transistor
signal
coupled
node
Prior art date
Application number
PCT/CN2019/112498
Other languages
English (en)
French (fr)
Inventor
冯雪欢
李永谦
袁粲
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to JP2020560439A priority Critical patent/JP7561626B2/ja
Priority to US16/652,165 priority patent/US11410608B2/en
Priority to EP19861294.7A priority patent/EP3872801A4/en
Publication of WO2020083275A1 publication Critical patent/WO2020083275A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/06—Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a shift register unit, a gate driving circuit, a display device, and a driving method.
  • OLED Organic Light Emitting Diode
  • GOA Gate Driver Array
  • the embodiments of the present disclosure provide a shift register and its driving method, a gate driving circuit and its driving method, and a display device.
  • a shift register unit includes a blanking input circuit, a display input circuit, an output circuit, and a first control circuit.
  • the blanking input circuit is configured to provide a blanking input signal to the pull-up control node and a blanking pull-up signal to the pull-up node.
  • the display input circuit is configured to provide a display pull-up signal to the pull-up node according to the display input signal.
  • the output circuit is configured to provide the output signal to the shift signal output terminal and the pixel signal output terminal under the control of the voltage of the pull-up node.
  • the first control circuit is configured to couple the shift signal output terminal to the pixel signal output terminal according to the display input signal.
  • the first control circuit includes a first transistor.
  • the control electrode of the first transistor is coupled to the display input signal terminal to receive the display input signal
  • the first electrode of the first transistor is coupled to the shift signal output terminal
  • the second electrode of the first transistor is coupled to the pixel signal output terminal.
  • the shift register unit further includes a second control circuit.
  • the second control circuit is configured to couple the shift signal output terminal to the pixel signal output terminal under the control of the first clock signal.
  • the second control circuit includes a second transistor.
  • the control electrode of the second transistor is coupled to the first clock signal terminal to receive the first clock signal, the first electrode of the second transistor is coupled to the shift signal output terminal, and the second electrode of the second transistor is coupled to the pixel signal output terminal Pick up.
  • the blanking input circuit includes a charging sub-circuit, a storage sub-circuit, and an isolation sub-circuit.
  • the charging sub-circuit is configured to provide the blanking input signal to the pull-up control node according to the second clock signal.
  • the storage subcircuit is configured to store the blanking input signal provided by the charging subcircuit.
  • the isolation sub-circuit is configured to provide a blanking pull-up signal to the pull-up node under the control of the voltage of the pull-up control node and the first clock signal.
  • the charging sub-circuit includes a third transistor, the control electrode of the third transistor and the second clock signal terminal are coupled to receive the second clock signal, the first electrode of the third transistor and the blanking input signal terminal Coupled to receive the blanking input signal, the second electrode of the third transistor is coupled to the pull-up control node.
  • the storage subcircuit includes a first capacitor, a first pole of the first capacitor is coupled to the pull-up control node, and a second pole of the first capacitor is coupled to the first voltage terminal to receive the first voltage.
  • the isolating sub-circuit includes a fourth transistor and a fifth transistor, the control electrode of the fourth transistor is coupled to the pull-up control node, the first electrode of the fourth transistor and the third clock signal terminal are coupled to receive the third clock signal as blanking Pull-up signal, the second electrode of the fourth transistor is coupled to the first electrode of the fifth transistor, the control electrode of the fifth transistor is coupled to the first clock signal terminal to receive the first clock signal, and the second electrode of the fifth transistor It is coupled to the pull-up node.
  • the display input circuit includes a sixth transistor.
  • the control electrode of the sixth transistor is coupled to the display input signal terminal to receive the display input signal
  • the first electrode of the sixth transistor and the second voltage terminal are coupled to receive the second voltage as the display pull-up signal
  • the second of the sixth transistor The pole and the pull-up node are coupled.
  • the output circuit includes a seventh transistor, an eighth transistor, and a second capacitor.
  • the control electrode of the seventh transistor is coupled to the pull-up node, the first electrode of the seventh transistor and the fourth clock signal terminal are coupled to receive the fourth clock signal as an output signal, and the second electrode of the seventh transistor and the shift signal are output ⁇ coupled.
  • the control electrode of the eighth transistor is coupled to the pull-up node, the first electrode of the eighth transistor and the fourth clock signal terminal are coupled to receive the fourth clock signal as an output signal, and the second electrode of the eighth transistor and the pixel signal output terminal Coupling.
  • the first electrode of the second capacitor is coupled to the pull-up node, and the second electrode of the second capacitor is coupled to the second electrode of the seventh transistor.
  • the shift register unit further includes a pull-down circuit, a first pull-down control circuit, a second pull-down control circuit, and a reset circuit.
  • the pull-down circuit is configured to perform noise reduction on the pull-up node, the shift signal output terminal, and the pixel signal output terminal under the control of the voltage of the pull-down node.
  • the first pull-down control circuit is configured to control the voltage of the pull-down node under the control of the voltage of the pull-up node.
  • the second pull-down control circuit is configured to control the voltage of the pull-down node under the control of the blanking pull-down control signal and the display pull-down control signal.
  • the reset circuit is configured to reset the pull-up node under the control of the blanking reset signal and the display reset signal.
  • the pull-down circuit includes a ninth transistor, a tenth transistor, and an eleventh transistor.
  • the control electrode of the ninth transistor is coupled to the pull-down node, the first electrode of the ninth transistor is coupled to the pull-up node, and the second electrode of the ninth transistor is coupled to the first voltage terminal to receive the first voltage.
  • the control electrode of the tenth transistor is coupled to the pull-down node, the first electrode of the tenth transistor is coupled to the shift signal output terminal, and the second electrode of the tenth transistor is coupled to the first voltage terminal to receive the first voltage.
  • the control electrode of the eleventh transistor is coupled to the pull-down node, the first electrode of the eleventh transistor is coupled to the pixel signal output terminal, and the second electrode of the eleventh transistor is coupled to the third voltage terminal to receive the third voltage.
  • the first pull-down control circuit includes a twelfth transistor, a thirteenth transistor, and a fourteenth transistor.
  • the control electrode and the first electrode of the twelfth transistor are coupled to the fourth voltage terminal to receive the fourth voltage, and the second electrode of the twelfth transistor is coupled to the pull-down node.
  • the control electrode and the first electrode of the thirteenth transistor are coupled to the fifth voltage terminal to receive the fifth voltage, and the second electrode of the thirteenth transistor is coupled to the pull-down node.
  • the control electrode of the fourteenth transistor is coupled to the pull-up node, the first electrode of the fourteenth transistor is coupled to the pull-down node, and the second electrode of the fourteenth transistor is coupled to the first voltage terminal to receive the first voltage.
  • the second pull-down control circuit includes a fifteenth transistor and a sixteenth transistor.
  • the control electrode of the fifteenth transistor is coupled to the first clock signal terminal to receive the first clock signal as a blanking pull-down control signal, the first electrode of the fifteenth transistor is coupled to the pull-down node, and the second electrode of the fifteenth transistor
  • the first voltage terminal is coupled to receive the first voltage.
  • the control electrode of the sixteenth transistor is coupled to the display input signal terminal to receive the display input signal as a display pull-down control signal, the first electrode of the sixteenth transistor is coupled to the pull-down node, and the second electrode of the sixteenth transistor is coupled to the first The voltage terminal is coupled to receive the first voltage.
  • the reset circuit includes a seventeenth transistor and an eighteenth transistor.
  • the control electrode of the seventeenth transistor is coupled to the second clock signal terminal to receive the second clock signal as a blanking reset signal, the first electrode of the seventeenth transistor is coupled to the pull-up node, the second of the seventeenth transistor The pole and the first voltage terminal are coupled to receive the first voltage.
  • the control electrode of the eighteenth transistor is coupled to the display reset signal terminal to receive the display reset signal, the first electrode of the eighteenth transistor is coupled to the pull-up node, and the second electrode of the eighteenth transistor is coupled to the first voltage terminal To receive the first voltage.
  • the shift register unit further includes a load capacitance and a load resistance.
  • One end of the load capacitor is coupled to the pixel signal output end, and the other end is grounded.
  • One end of the load resistor is coupled to the pixel signal output end, and the other end is grounded.
  • a gate drive circuit includes a plurality of cascaded shift register units as provided in the first aspect of the present disclosure.
  • the shift signal output terminal of the nth stage shift register unit provides a blanking input signal to the n + 1th stage shift register unit.
  • the shift signal output terminal of the nth stage shift register unit provides a display input signal to the n + 2th stage shift register unit.
  • n is an integer greater than 0.
  • the gate driving circuit further includes a first subclock signal line, a second subclock signal line, a third subclock signal line, and a fourth subclock signal line.
  • the first sub-clock signal line provides the fourth clock signal to the 4n-3 stage shift register unit as an output signal
  • the second sub-clock signal line provides the fourth clock signal to the 4n-2 stage shift register unit as an output signal.
  • the third subclock signal line provides the fourth clock signal to the 4n-1th stage shift register unit as an output signal
  • the fourth subclock signal line provides the fourth clock signal to the 4nth stage shift register unit as the output signal.
  • the gate driving circuit further includes a fifth subclock signal line, a sixth subclock signal line, and a seventh subclock signal line.
  • the fifth sub-clock signal line provides a second clock signal to the shift register unit of the 2n-1th stage, and a third clock signal to the shift register unit of the 2n-1th stage as a blanking pull-up signal.
  • the sixth sub-clock signal line provides a third clock signal as a blanking pull-up signal to the 2n-1th stage shift register unit, and provides a second clock signal terminal to the 2nth stage shift register unit.
  • the seventh sub-clock signal line provides the first clock signal to the shift register units at all levels.
  • the shift signal output terminal of the n + 3 stage shift register unit provides a display reset signal to the nth stage shift register unit.
  • a display device includes a gate driving circuit as provided in the second aspect of the present disclosure.
  • a method for driving a shift register unit as provided in the first aspect of the present disclosure includes: the blanking input circuit provides the blanking input signal to the pull-up control node; the display input circuit provides the display pull-up signal to the pull-up node in response to the display input signal, wherein, under the control of the display input signal, the first The control circuit couples the shift signal output terminal to the pixel signal output terminal; the output circuit outputs the display output signal under the control of the voltage of the pull-up node; the blanking input circuit controls the voltage of the pull-up control node and the first clock signal The blanking pull-up signal is provided to the pull-up node; and the output circuit outputs the blanking output signal under the control of the voltage of the pull-up node.
  • the method further includes: the second control circuit couples the shift signal output terminal to the pixel signal output terminal under the control of the first clock signal.
  • FIG. 1 shows a schematic block diagram of a shift register unit according to an embodiment of the present disclosure
  • FIG. 2 shows a schematic block diagram of a blanking input circuit according to an embodiment of the present disclosure
  • FIG. 3 shows a schematic block diagram of a shift register unit according to an embodiment of the present disclosure
  • FIG. 4 shows a schematic block diagram of a shift register unit according to an embodiment of the present disclosure
  • FIG. 5 shows a schematic block diagram of a shift register unit according to an embodiment of the present disclosure
  • FIG. 6 shows an exemplary circuit diagram of a shift register unit according to an embodiment of the present disclosure
  • FIG. 7 shows an exemplary circuit diagram of a shift register unit according to an embodiment of the present disclosure
  • FIG. 8 shows a schematic diagram of a gate driving circuit according to an embodiment of the present disclosure
  • FIG. 10 shows a schematic flowchart of a method for driving a mobile register unit according to an embodiment of the present disclosure.
  • the gate drive circuit is usually integrated in an integrated circuit IC.
  • the area of the chip in integrated circuit IC design is the main factor affecting the cost of the chip.
  • the gate drive circuit includes a detection circuit, a display circuit, and a connection circuit (or gate circuit) that outputs a composite pulse of both.
  • the structure of this type of circuit is very complicated, and it is difficult to meet the requirements of high resolution and narrow border.
  • an external compensation can also be provided by providing a sensing transistor.
  • the gate driving circuit composed of the shift register unit needs to provide drive signals for the scanning transistor and the sensing transistor to the sub-pixel units in the display panel, respectively.
  • a scan driving signal for scanning transistors is provided in a display period (Display) of one frame
  • a sensing driving signal for sensing transistors is provided in a blanking period (Blank) of one frame.
  • one frame includes a display period and a blanking period that are sequentially performed.
  • the gate driving circuit outputs a display output signal, which can be used to drive the scanning transistor in the display panel to perform scanning from the first row to the last row.
  • the gate driving circuit outputs a blanking output signal, which can be used to drive a sensing transistor in a row of sub-pixel units in the display panel to complete the external compensation of the row of sub-pixel units .
  • the gate drive circuit When the gate drive circuit is driven at a high frequency, since the data writing time is very short, the gate line can be precharged so that there is overlap between multiple output waveforms, thereby increasing the data writing time. However, in the high-level writing stage, coupling noise is easily generated at the output of each shift register unit in the gate drive circuit.
  • the embodiments of the present disclosure provide a shift register unit and its driving method, a gate driving circuit and its driving method, and a display device.
  • the embodiments and examples of the present disclosure will be described in detail below with reference to the drawings.
  • FIG. 1 shows a schematic block diagram of a shift register unit according to an embodiment of the present disclosure.
  • the shift register unit 10 may include a blanking input circuit 100, a display input circuit 200, an output circuit 300 and a first control circuit 400.
  • the blanking input circuit 100 may provide a blanking input signal to the pull-up control node H (not shown in FIG. 1, see FIG. 2, which will be described in detail below) to control the voltage of the pull-up control node H.
  • the blanking input circuit 100 may also provide a blanking pull-up signal to the pull-up node Q to control the voltage of the pull-up node Q.
  • the blanking input circuit 100 may be coupled to the blanking input signal terminal STU1 to receive the blanking input signal, to the first clock signal terminal CLKA to receive the first clock signal, and the second clock signal terminal CLKB is coupled to receive the second clock signal, and is coupled to the third clock signal terminal CLKC to receive the third clock signal.
  • the third clock signal can be used as a blanking pull-up signal.
  • the blanking input circuit 100 may provide the blanking input signal to the pull-up control node H under the control of the second clock signal.
  • the blanking input circuit 100 may also provide the blanking pull-up signal to the pull-up node Q under the control of the voltage of the pull-up control node H and the first clock signal.
  • the blanking input circuit 100 may receive the blanking input signal and store the blanking input signal in the display period of one frame, and provide the pull-up node Q according to the blanking input signal during the blanking period of this frame. Blanking the pull-up signal.
  • the blanking input circuit 100 can also receive a blanking input signal and store the blanking input signal in a blanking period of one frame, and provide a blanking pull-up at the node Q according to the blanking input signal in the blanking period of the next frame. signal.
  • FIG. 2 shows a schematic block diagram of a blanking input circuit according to an embodiment of the present disclosure.
  • the blanking input circuit 100 may include a charging sub-circuit 110, a storage sub-circuit 120 and an isolation sub-circuit 130.
  • the charging sub-circuit 110 may provide the blanking input signal to the pull-up control node H under the control of the second clock signal to control the voltage of the pull-up control node H.
  • the charging sub-circuit 110 may be coupled to the second clock signal terminal CLKB to receive the second clock signal, and coupled to the blanking input signal terminal STU1 to receive the blanking input signal.
  • the storage sub-circuit 120 may store the blanking input signal provided by the charging sub-circuit.
  • the memory sub-circuit 120 may be coupled to the pull-up control node H and coupled to the first voltage terminal VGL1 (not shown) to receive the first voltage.
  • the memory sub-circuit 120 may charge the pull-up control node H to a high potential. Thus, the high level of the pull-up control node H is maintained until the blanking period of the frame.
  • the first voltage terminal VGL1 may provide a DC low-level signal, that is, the first voltage is a low level.
  • the isolation sub-circuit 130 may provide a blanking pull-up signal to the pull-up node Q under the control of the voltage of the pull-up control node H and the first clock signal to control the voltage of the pull-up node Q.
  • the isolation sub-circuit 130 may be coupled to the first clock signal terminal CLKA to receive the first clock signal, and coupled to the third clock signal terminal CLKC to receive the third clock signal as a blanking pull-up signal.
  • the isolation sub-circuit 130 is provided between the pull-up node Q and the pull-up control node H, the pull-up node Q and the pull-up control node H can be prevented from affecting each other.
  • the isolation sub-circuit 130 may disconnect the connection between the pull-up node Q and the third clock signal terminal CLKC under the control of the first clock signal. During this period, the high-level blanking pull-up signal does not affect the voltage of the pull-up node Q.
  • the display input circuit 200 may provide a display pull-up signal to the pull-up node Q under the control of the display input signal.
  • the display input circuit 200 may be coupled to the display input signal terminal STU2 to receive the display input signal, and coupled to the second voltage terminal VDD to receive the second voltage as a display pull-up signal.
  • the second voltage terminal VDD may provide a DC high-level signal, that is, the second voltage is a high level.
  • the output circuit 300 may provide the output signal to the shift signal output terminal CR and the pixel signal output terminal OUT under the control of the voltage of the pull-up node Q.
  • the output circuit 300 may be coupled to the fourth clock signal terminal CLKD to receive the fourth clock signal as an output signal.
  • the output signal may include a display output signal and a blanking output signal.
  • the output circuit 300 may output the display output signal to the shift signal output under the control of the voltage of the pull-up node Q Terminal CR and pixel signal output terminal OUT.
  • the display output signal output from the shift signal output terminal CR can be used for scanning shift of the shift register unit at the upper and lower stages.
  • the display output signal output from the pixel signal output terminal OUT can be used to drive the sub-pixel unit in the display panel for scanning display.
  • the output circuit 300 may output the blanking output signal to the shift signal output terminal CR and the pixel signal output terminal OUT under the control of the voltage of the pull-up node Q.
  • the blanking output signal output from the shift signal output terminal CR can be used for the blanking input signal of the shift register unit of the next stage (to be described in detail below).
  • the blanking output signal output from the pixel signal output terminal OUT can be used to control the transistor in the sub-pixel unit in the display panel.
  • the first control circuit 400 may couple the shift signal output terminal CR to the pixel signal output terminal OUT under the control of the display input signal.
  • the first control circuit 400 may be coupled to the display input signal terminal STU2 to receive the display input signal.
  • the first control circuit 400 couples the shift signal output terminal CR and the pixel signal output terminal OUT under the control of the display input signal, whereby the load capacitance and load resistance on the pixel signal output terminal OUT side can be ( (Not shown) Regulates the shift signal output terminal CR.
  • the load capacitor may be a separately provided capacitor or a parasitic capacitor on a line coupled to the pixel signal output terminal OUT.
  • the load resistance may be a separately provided resistance, or may be a parasitic resistance on a line coupled to the pixel signal output terminal OUT.
  • the voltage of the pull-up node Q can be controlled by the blanking input circuit 100 and the display input circuit 200 at different periods, and the blanking input circuit 100 and the display input circuit 200 are shared
  • the same output circuit 300 realizes the output of both the display output signal and the blanking output signal.
  • the first control circuit 400 can control the shift signal output terminal CR of the output circuit 300 to be coupled to the pixel signal output terminal OUT, so as to reduce the noise generated by the shift signal output terminal CR during the high-voltage writing process.
  • FIG. 3 shows a schematic block diagram of a shift register unit according to an embodiment of the present disclosure.
  • the shift register unit 15 may include a blanking input circuit 100, a display input circuit 200, an output circuit 300, a first control circuit 400, a pull-down circuit 500, a first pull-down control circuit 600, and a second pull-down control Circuit 700 and reset circuit 800.
  • the blanking input circuit 100, the display input circuit 200, the output circuit 300, and the first control circuit 400 have been described in detail above, and will not be repeated here.
  • the pull-down circuit 500 may perform noise reduction on the pull-up node Q, the shift signal output terminal CR, and the pixel signal output terminal OUT under the control of the voltage of the pull-down node QB.
  • the pull-down circuit 500 may be coupled to the first voltage terminal VGL1 to receive the first voltage and coupled to the third voltage terminal VGL2 to receive the third voltage.
  • the pull-down circuit 500 may control the voltage of the pull-up node Q and the shift signal output terminal CR through the first voltage of the first voltage terminal VGL1 under the control of the voltage of the pull-down node QB, and through the third voltage terminal VGL2 controls the voltage of the pixel signal output terminal OUT.
  • the pull-down circuit 500 can reduce the noise of the pull-up node Q, the shift signal output terminal CR, and the pixel signal output terminal OUT.
  • the third voltage terminal VGL2 may provide a DC low-level signal, that is, the third voltage is a low level.
  • the first pull-down control circuit 600 can control the voltage of the pull-down node QB under the control of the voltage of the pull-up node Q.
  • the first pull-down control circuit 600 may be coupled to the first voltage terminal VGL1 to receive the first voltage, and coupled to the fourth voltage terminal VDD_A to receive the fourth voltage.
  • the first pull-down control circuit 600 may pull the voltage of the pull-down node QB to a low level by a first voltage (for example, a low level).
  • the first pull-down control circuit 600 may charge the pull-down node QB with a fourth voltage (for example, a high level) to pull the pull-down node QB to a high level.
  • a fourth voltage for example, a high level
  • the first pull-down control circuit 600 may also be coupled to the fifth voltage terminal VDD_B to receive the fifth voltage (eg, high level).
  • the fourth voltage terminal VDD_A and the fifth voltage terminal VDD_B may be configured to alternately provide a high level, that is, when the fourth voltage terminal VDD_A provides a high level, the fifth voltage terminal VDD_B provides a low level, and the fourth voltage terminal VDD_A When a low level is provided, the fifth voltage terminal VDD_B provides a high level.
  • the first pull-down control circuit 600 may charge the pull-down node QB with a fourth voltage or a fifth voltage to pull the pull-down node QB to a high level .
  • the second pull-down control circuit 700 can control the voltage of the pull-down node QB under the control of the blanking pull-down control signal.
  • the second pull-down control circuit 700 may be coupled to the first clock signal terminal CLKA to receive the first clock signal as a blanking pull-down control signal, and coupled to the first voltage terminal VGL1 to receive the first voltage.
  • the second pull-down control circuit 700 may be turned on in response to the first clock signal, so that the pull-down node QB may be pulled to a low level through the first voltage terminal VGL1.
  • the second pull-down control circuit 700 may also be coupled to other signal terminals to receive the blanking pull-down control signal, which is not limited in the present disclosure.
  • the second pull-down control circuit 700 can also control the voltage of the pull-down node QB under the control of displaying the pull-down control signal.
  • the second pull-down control circuit 700 may be connected to the display input signal terminal STU2 to receive the display input signal as a display pull-down control signal, and coupled to the first voltage terminal VGL1 to receive the first voltage.
  • the display input signal is also provided to the second pull-down control circuit 700, so that The pull-down node QB is pulled down to a low level through the first voltage terminal VGL1.
  • the second pull-down control circuit 700 may also be coupled to other signal terminals to receive the display pull-down control signal, which is not limited in the present disclosure.
  • the reset circuit 800 can reset the pull-up node Q under the control of the blanking reset signal.
  • the reset circuit 800 may be coupled to the second clock signal terminal CLKB to receive the second clock signal as a blanking reset signal, and coupled to the first voltage terminal VGL1 to receive the first voltage. It should be noted that, in the embodiment of the present disclosure, the reset circuit 800 may also be coupled to other signal terminals to receive a blanking reset signal, which is not limited in the present disclosure.
  • the reset circuit 800 can also reset the pull-up node Q under the control of the display reset signal.
  • the reset circuit 800 may be coupled to the display reset signal terminal STD to receive the display reset signal, and coupled to the first voltage terminal VGL1 to receive the first voltage.
  • FIG. 4 shows a schematic block diagram of a shift register unit according to another embodiment of the present disclosure.
  • the shift register unit 20 may include a blanking input circuit 100, a display input circuit 200, an output circuit 300, a first control circuit 400, and a second control circuit 420.
  • the blanking input circuit 100, the display input circuit 200, the output circuit 300, and the first control circuit 400 have been described above, and will not be repeated here.
  • the second control circuit 420 may couple the shift signal output terminal CR to the pixel signal output terminal OUT under the control of the first clock signal.
  • the second control circuit 420 may be coupled to the first clock signal terminal CLKA to receive the first clock signal.
  • the second control circuit 420 may couple the shift signal output terminal CR and the pixel signal output terminal OUT under the control of the first clock signal, thereby passing the load capacitance and load resistance on the pixel signal output terminal OUT side (Not shown) Regulates the shift signal output terminal CR.
  • the isolation sub-circuit 130 may control the connection between the pull-up node Q and the third clock signal terminal CLKC according to the first clock signal.
  • the load capacitance and The load resistor processes the voltage noise at the shift signal output terminal CR. In this way, the noise of the shift signal output terminal CR during high-voltage writing can be effectively reduced.
  • FIG. 5 shows an exemplary circuit diagram of a shift register unit according to an embodiment of the present disclosure.
  • the shift register 25 may include a blanking input circuit 100, a display input circuit 200, an output circuit 300, a first control circuit 400, a second control circuit 420, a pull-down circuit 500, and a first pull-down control circuit 600 2.
  • the second pull-down control circuit 700 and the reset circuit 800 Each circuit is described in detail above and will not be repeated here.
  • the shift register unit may further include a load capacitance and a load resistance (not shown).
  • One end of the load capacitor is coupled to the pixel signal output end, and the other end is grounded.
  • One end of the load resistor is coupled to the pixel signal output end, and the other end is grounded.
  • the load capacitor may be a separately provided capacitor, or may be a parasitic capacitor on a line coupled to the pixel signal output terminal OUT.
  • the load resistance may be a separately provided resistance, or may be a parasitic resistance on a line coupled to the pixel signal output terminal OUT.
  • FIG. 6 shows an exemplary circuit diagram of a shift register unit according to an embodiment of the present disclosure.
  • the shift register unit is, for example, the shift register unit 15 shown in FIG. 3.
  • the shift register unit may include a first transistor M1 to a seventeenth transistor M17, a first capacitor C1 and a second capacitor C2, and a load capacitor C L and a load resistor R L.
  • transistors used in the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other switching devices with the same characteristics.
  • the thin film transistor is taken as an example for description.
  • the source and drain of the transistor used here may be symmetrical in structure, so the source and drain may be indistinguishable in structure.
  • the gate of the transistor can be referred to as the gate.
  • transistors can be divided into N-type and P-type transistors according to their characteristics.
  • the on-voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltage), and the off-voltage is a high-level voltage (for example, 5V, 10V or other suitable Voltage).
  • the on-voltage is a high-level voltage (for example, 5V, 10V or other suitable voltage)
  • the off-voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable Voltage).
  • the transistors used in the shift register unit 10 provided in the embodiments of the present disclosure are all described using N-type transistors (eg, NMOS transistors) as an example.
  • N-type transistors eg, NMOS transistors
  • Embodiments of the present disclosure include, but are not limited to, for example, at least part of the transistors in the shift register unit 10 may also use P-type transistors (eg, PMOS transistors).
  • the charging sub-circuit 110 in the blanking input circuit 100 may include a third transistor M3.
  • the gate of the third transistor M3 is coupled to the second clock signal terminal CLKB to receive the second clock signal
  • the first electrode of the third transistor M3 is coupled to the blanking input signal terminal STU1 to receive the blanking input signal
  • the third transistor The second pole of M3 is coupled to the pull-up control node H.
  • the third transistor M3 when the second clock signal is at a high level, the third transistor M3 is turned on, so that the blanking input signal can be provided to the pull-up control node H to charge it.
  • the storage sub-circuit 120 in the blanking input circuit 100 may include a first capacitor C1.
  • the first terminal of the first capacitor C1 is coupled to the pull-up control node H, and the second terminal of the first capacitor C1 is coupled to the first voltage terminal VGL1 to receive the first voltage.
  • the voltage of the pull-up control node H can be maintained by setting the first capacitor C1.
  • the third transistor M3 may charge the pull-up control node H to a high level, and the first capacitor C1 may maintain the high level of the pull-up control node H to the erasing of the frame Hidden period.
  • the isolation sub-circuit 130 in the blanking input circuit 100 may include a fourth transistor M4 and a fifth transistor M5.
  • the gate of the fourth transistor M4 is coupled to the pull-up control node H.
  • the first electrode of the fourth transistor M4 is coupled to the third clock signal terminal CLKC to receive the third clock signal as a blanking pull-up signal.
  • the fourth transistor M4 The second electrode of M4 is coupled to the first electrode of the fifth transistor M5.
  • the gate of the fifth transistor M5 is coupled to the first clock signal terminal CLKA to receive the first clock signal, and the second electrode of the fifth transistor M5 is coupled to the pull-up node Q.
  • the fourth transistor M4 may be turned on under the control of the voltage of the pull-up control node H, and when the first clock signal is at a high level, the fifth transistor M5 is turned on, Therefore, the third clock signal can charge the pull-up node Q through the fourth transistor M4 and the fifth transistor M5.
  • the display input circuit 200 may include a sixth transistor M6.
  • the gate of the sixth transistor M6 is coupled to the display input signal terminal STU2 to receive the display input signal
  • the first electrode of the sixth transistor M6 and the second voltage terminal VDD are coupled to receive the second voltage as the display pull-up signal
  • the sixth The second electrode of the transistor M6 is coupled to the pull-up node Q.
  • the sixth transistor M6 may be turned on under the control of the display input signal, thereby charging the pull-up node Q with the second voltage.
  • the output circuit 300 may include a seventh transistor M7, an eighth transistor M8, and a second capacitor.
  • the gate of the seventh transistor M7 is coupled to the pull-up node Q, the first electrode of the seventh transistor M7 and the fourth clock signal terminal CLKD are coupled to receive the fourth clock signal as an output signal, and the second electrode of the seventh transistor M7 It is coupled to the shift signal output terminal CR.
  • the gate of the eighth transistor M8 is coupled to the pull-up node Q, the first pole of the eighth transistor M8 and the fourth clock signal terminal CLKD are coupled to receive the fourth clock signal as an output signal, and the second pole of the eighth transistor M8 It is coupled to the pixel signal output terminal OUT.
  • the first electrode of the second capacitor C2 is coupled to the pull-up node Q, and the second electrode of the second capacitor C2 is coupled to the second electrode of the seventh transistor M7.
  • the seventh transistor M7 and the eighth transistor M8 are turned on, so that the fourth clock signal can be output as an output signal to the shift signal output terminal CR and the pixel, respectively Signal output terminal OUT.
  • the first control circuit 400 may include a first transistor M1.
  • the gate of the first transistor M1 is coupled to the display input signal terminal STU2 to receive the display input signal
  • the first electrode of the first transistor M1 is coupled to the shift signal output terminal CR
  • the second electrode of the first transistor M1 is coupled.
  • the pull-down circuit 500 may include a ninth transistor M9, a tenth transistor M10, and an eleventh transistor M11.
  • the gate of the ninth transistor M9 is coupled to the pull-down node QB, the first pole of the ninth transistor M9 is coupled to the pull-up node Q, and the second pole of the ninth transistor M9 is coupled to the first voltage terminal VGL1 to receive the first Voltage.
  • the gate of the tenth transistor M10 is coupled to the pull-down node QB, the first electrode of the tenth transistor M10 is coupled to the shift signal output terminal CR, and the second electrode of the tenth transistor M10 is coupled to the first voltage terminal VGL1 to receive First voltage.
  • the gate of the eleventh transistor M11 is coupled to the pull-down node QB, the first pole of the eleventh transistor M11 is coupled to the pixel signal output terminal OUT, and the second pole of the eleventh transistor M11 is coupled to the third voltage terminal VGL2 To receive the third voltage.
  • the first pull-down control circuit 600 may include a twelfth transistor M12, a thirteenth transistor M13, and a fourteenth transistor M14.
  • the gate and the first electrode of the twelfth transistor M12 are coupled to the fourth voltage terminal VDD_A to receive the fourth voltage, and the second electrode of the twelfth transistor M12 is coupled to the pull-down node QB.
  • the gate and first pole of the thirteenth transistor M13 are coupled to the fifth voltage terminal VDD_B to receive the fifth voltage, and the second pole of the thirteenth transistor M13 is coupled to the pull-down node QB.
  • the gate of the fourteenth transistor M14 is connected to the pull-up node Q, the first pole of the fourteenth transistor M14 is coupled to the pull-down node QB, and the second pole of the fourteenth transistor M14 is coupled to the first voltage terminal VGL1 to receive First voltage.
  • the fourth voltage terminal VDD_A and the fifth voltage terminal VDD_B may be configured to alternately provide a high level. That is, when the fourth voltage terminal VDD_A provides a high level, the fifth voltage terminal VDD_B provides a low level, and when the fourth voltage terminal VDD_A provides a low level, the fifth voltage terminal VDD_B provides a high level. Therefore, only one of the twelfth transistor M12 and the thirteenth transistor M13 is in an on state. This can avoid performance drift caused by long-term transistor turn-on.
  • the fourth voltage can charge the pull-down node QB when the twelfth transistor M12 is turned on, or the fifth voltage can charge the pull-down node QB when the thirteenth transistor M13 is turned on, thereby pulling up the voltage of the pull-down node QB To high level.
  • the fourteenth transistor M14 is turned on.
  • the fourteenth transistor M14 and the twelfth transistor M12 can be configured (for example, the size ratio of the two, the threshold voltage, etc.) in M14 and M12 ( M13)
  • the voltage of the pull-down node QB can be pulled down to a low level, which can keep the ninth transistor M9, the tenth transistor M10, and the eleventh transistor M11 off.
  • the ninth transistor M9 and the tenth transistor M10 in the pull-down circuit 500 are turned on, so that the pull-up node Q and the shift signal can be output using the first voltage terminal VGL1
  • the terminal CR is pulled down to reduce the noise of the pull-up node Q and the shift signal output terminal CR.
  • the eleventh transistor M11 is also turned on, so that the third signal terminal VGL2 can be used to pull down the pixel signal output terminal OUT to reduce the noise of the pixel signal output terminal OUT.
  • the first voltage and the third voltage may be different, for example, the first voltage is set to -10V, and the third voltage is set to -6V.
  • the third voltage terminal VGL2 may not be provided, and the second electrode of the eleventh transistor M11 may be coupled to the first voltage terminal VGL1 to receive the first voltage, which is not limited in the embodiments of the present disclosure .
  • the second pull-down control circuit 700 may include a fifteenth transistor M15 and a sixteenth transistor M16.
  • the gate of the fifteenth transistor M15 is coupled to the first clock signal terminal CLKA to receive the first clock signal as a blanking pull-down control signal, the first pole of the fifteenth transistor M15 is coupled to the pull-down node QB, and the fifteenth transistor The second pole of M15 is coupled to the first voltage terminal VGL1 to receive the first voltage.
  • the fifteenth transistor M15 when the first clock signal is at a high level, the fifteenth transistor M15 is turned on, so that the pull-down node QB can be pulled down using the first voltage terminal VGL1. In this way, the influence of the pull-down node QB on the pull-up node Q can be reduced during the blanking period of one frame, so that the blanking input circuit 100 charges the pull-up node Q more fully.
  • the gate of the sixteenth transistor M16 is coupled to the display input signal terminal STU2 to receive the display input signal as a display pull-down control signal
  • the first pole of the sixteenth transistor M16 is coupled to the pull-down node QB
  • the first The two poles are coupled to the first voltage terminal VGL1 to receive the first voltage.
  • the sixteenth transistor M16 when the display input signal is at a high level, the sixteenth transistor M16 is turned on, so that the pull-down node QB can be pulled down using the first voltage terminal VGL1. In this way, the influence of the pull-down node QB on the pull-up node Q can be reduced during the display period of one frame, so that the display input circuit 200 charges the pull-up node Q more fully.
  • the reset circuit 800 may include a seventeenth transistor M17 and an eighteenth transistor M18.
  • the gate of the seventeenth transistor M17 is coupled to the second clock signal terminal CLKB to receive the second clock signal as a blanking reset signal, the first pole of the seventeenth transistor M17 is coupled to the pull-up node Q, the seventeenth The second electrode of the transistor M17 is coupled to the first voltage terminal VGL1 to receive the first voltage. For example, when the second clock signal is at a high level, the seventeenth transistor M17 is turned on, so that the pull-up node Q can be reset using the first voltage terminal VGL1.
  • the gate of the eighteenth transistor M18 is coupled to the display reset signal terminal STD to receive the display reset signal, the first pole of the eighteenth transistor M18 is coupled to the pull-up node Q, and the second pole of the eighteenth transistor M18 is coupled to the first A voltage terminal VGL1 is coupled to receive the first voltage. For example, when the display reset signal is at a high level, the eighteenth transistor M18 is turned on, so that the pull-up node Q can be reset using the first voltage terminal VGL1.
  • L is the load capacitance C is coupled to one end of the pixel signal output terminal and ground.
  • One end of the load resistor RL is coupled to the pixel signal output end, and the other end is grounded.
  • the voltage at the pull-up control node H can be maintained by the first capacitor C1, and the voltage at the pull-up node Q can be maintained by the second capacitor C2.
  • At least one of the first capacitor C1, the second capacitor C2 and the load capacitor C L may be a capacitor device manufactured by a process, for example, a capacitor electrode is realized by making a dedicated capacitor electrode, and each electrode of the capacitor may pass through a metal layer , Semiconductor layer (such as doped polysilicon) and so on.
  • at least one of the first capacitor C1, the second capacitor C2, and the load capacitor C L may also be realized by a parasitic capacitance between each device.
  • the connection method of at least one of the first capacitor C1, the second capacitor C2, and the load capacitor C L is not limited to the method described above, and may be other suitable connection methods.
  • the shift register unit is, for example, the shift register unit 25 shown in FIG. 5, in which the blanking input circuit 100, the display input circuit 200, the output circuit 300, the first control circuit 400, the pull-down circuit 500, the first pull-down control circuit
  • the circuit structure of 600, the second pull-down control circuit 700, the reset circuit 800, the load capacitance and the load resistance (not shown) is the same as the circuit structure of the corresponding circuit in FIG. 6, which will not be repeated here.
  • the second control circuit 420 may include a second transistor M2.
  • the gate of the second transistor M2 is coupled to the first clock signal terminal CLKA to receive the first clock signal, the first electrode of the second transistor M2 is coupled to the shift signal output terminal CR, and the second electrode of the second transistor M2 It is coupled to the pixel signal output terminal OUT.
  • the embodiments of the present disclosure also provide a gate driving circuit constituted by a shift register unit.
  • FIG. 8 shows a schematic diagram of a gate driving circuit according to an embodiment of the present disclosure.
  • the gate driving circuit 30 may include a plurality of cascaded shift register units, wherein any one or more shift register units may adopt the shift register unit 10, the shift register unit 15, the shift provided by the embodiment of the present disclosure
  • Only the first four stages of shift register units (A1, A2, A3, and A4) of the gate driving circuit 30 are schematically shown in FIG. 5. It can be understood that when the shift register unit in the gate driving circuit is the shift register units 10 and 20, the display reset signal terminal STD is not provided.
  • the gate driving circuit 30 further includes a first sub-clock signal line CLK_1, a second sub-clock signal line CLK_2, a third sub-clock signal line CLK_3, and a fourth sub-clock signal line CLK_4.
  • the first sub-clock signal line provides a fourth clock signal to the shift register unit of the 4n-3th stage (eg, the 1st stage, the 5th stage, the 9th stage, etc.).
  • the second sub-clock signal line provides a fourth clock signal to the shift register unit of the 4n-2th stage (eg, the second stage, the sixth stage, the tenth stage, etc.).
  • the third sub-clock signal line provides a fourth clock signal to the shift register unit of the 4n-1th stage (e.g., 3rd stage, 7th stage, 11th stage, etc.).
  • the fourth sub-clock signal line provides a fourth clock signal to the shift register unit of the 4nth stage (eg, the 4th stage, the 8th stage, the 12th stage, etc.).
  • the fourth clock signal serves as an outputtable signal.
  • the shift register unit may include the fourth clock signal terminal CLKD.
  • the fourth clock signal terminal CLKD of the shift register unit of the 4n-3 stage is coupled to the first sub-clock signal line CLK_1, and the fourth clock signal terminal CLKD of the shift register unit of the 4n-2 stage is The second sub-clock signal line CLK_2 is coupled, the fourth clock signal terminal CLKD of the 4n-1th stage shift register unit and the third sub-clock signal line CLK_3 are coupled, and the fourth clock signal terminal of the 4nth stage shift register unit CLKD is coupled to the fourth sub-clock signal line CLK_4.
  • n is an integer greater than 0.
  • the gate driving circuit 30 may further include a fifth sub-clock signal line CLK_5 and a sixth sub-clock signal line CLK_6.
  • the fifth sub-clock signal line provides the second clock signal to the shift register unit of the 2n-1th stage (eg, 1st stage, 3rd stage, 5th stage, etc.) and to the 2nth stage (eg, 2nd stage, (4th stage, 8th stage, etc.)
  • the shift register unit provides a third clock signal.
  • the sixth sub-clock signal line provides a third clock signal to the shift register unit of the 2n-1th stage and a second clock signal to the shift register unit of the 2nth stage.
  • the third clock signal may be used as a blanking pull-up signal.
  • the shift register unit may include the second clock signal terminal CLKB and the third clock signal terminal CLKC.
  • the second clock signal terminal CLKB of the 2n-1th stage shift register unit is coupled to the fifth sub-clock signal line CLK_5, and the third clock signal terminal CLKC is coupled to the sixth sub-clock signal line CLK_6.
  • the second clock signal terminal CLKB of the 2n-th shift register unit is coupled to the sixth sub-clock signal line CLK_6, and the third clock signal terminal CLKC is coupled to the fifth sub-clock signal line CLK_5.
  • n is an integer greater than 0.
  • the gate driving circuit 30 may further include a seventh sub-clock signal line CLK_7, and the seventh sub-clock signal line provides the first clock signal to the shift register units at all levels.
  • the first clock signal terminal CLKA of each stage of the shift register unit is coupled to the seventh sub-clock signal line CLK_7.
  • the blanking input signal terminal STU1 and the display input signal terminal STU2 of the first-stage shift register unit A1 and the display input signal terminal STU2 of the second-stage shift register unit A2 are all the same as the input signal line STU (Not shown) Coupling, for example to receive trigger signal STV.
  • the shift signal output terminal of the nth-stage shift register unit provides a blanking input signal to the n + 1th-stage shift register unit.
  • the blanking input signal terminal STU1 of the shift register unit of the n + 1th stage and the shift signal output terminal CR of the shift register unit of the nth stage are coupled.
  • the shift signal output terminal CR of the first-stage shift register unit A1 is coupled to the blanking input signal terminal STU1 of the second-stage shift register unit A2.
  • the shift signal output terminal CR of the second-stage shift register unit A2 is coupled to the blanking input signal terminal STU1 of the third-stage shift register unit A3.
  • the shift signal output terminal CR of the third-stage shift register unit A3 is coupled to the blanking input signal terminal STU1 of the fourth-stage shift register unit A4.
  • the shift signal output terminal of the nth stage shift register unit provides a display input signal to the n + 2th stage shift register unit.
  • the display input signal terminal STU2 of the n + 2th stage shift register unit and the shift signal output terminal CR of the nth stage shift register unit are coupled.
  • the shift signal output terminal CR of the first-stage shift register unit A1 is coupled to the display input signal terminal STU2 of the third-stage shift register unit A3.
  • the shift signal output terminal CR of the second-stage shift register unit A2 is coupled to the display input signal terminal STU2 of the fourth-stage shift register unit A4.
  • the shift signal output terminal of the n + 3th stage shift register unit provides a display reset signal to the nth stage shift register unit.
  • the display reset signal terminal STD of the nth stage shift register unit and the shift signal output terminal CR of the n + 3th stage shift register unit are coupled.
  • n is an integer greater than 0.
  • the display reset signal terminal STD of the shift register unit A1 of the first stage is coupled to the shift signal output terminal CR of the shift register unit A4 of the fourth stage.
  • the display reset signal terminal STD of the last three-stage shift register unit may be coupled to the shift signal output terminal of the dummy shift register unit, or the display reset signal line STD (not shown) or respectively Connect other appropriate signal lines.
  • FIG. 8 only schematically illustrates the connection relationship between the shift register units, rather than limiting it, and there may be other appropriate connections not shown.
  • FIG. 9 shows a timing diagram of signals during the operation of the gate driving circuit 30 shown in FIG. 8.
  • Q ⁇ 1> and Q ⁇ 2> represent the voltages of the pull-up nodes Q in the first-stage shift register unit A1 and the second-stage shift register unit A2 in the gate drive circuit 30, respectively.
  • OUT ⁇ 1>, OUT ⁇ 2>, OUT ⁇ 3> and OUT ⁇ 4> respectively represent the first-stage shift register unit A1, the second-stage shift register unit A2, and the third-stage shift in the gate drive circuit 30
  • 1F, 2F, 3F, and 4F represent the first frame, the second frame, the third frame, and the fourth frame, respectively.
  • Display represents the display period in one frame
  • Blank represents the blanking period in one frame.
  • the signal voltage in the signal timing diagram shown in FIG. 9 is only schematic and does not represent the real voltage value. Furthermore, in the example, the first voltage VGL1 is a low level, the second voltage VDD is a high level, and the third voltage VGL2 is a low level.
  • the shift register unit in the gate driving circuit 30 shown in FIG. 8 may adopt the shift register unit shown in FIGS. 5 and 6.
  • the fifth sub-clock signal line CLK_5 and the sixth sub-clock signal line CLK_6 both provide high levels. Since the second clock signal terminal CLKB and the third clock signal terminal CLKC in the shift register units at all levels are alternately connected to the fifth sub-clock signal line CLK_5 and the sixth sub-clock signal line CLK_6, each shift register unit The third transistor M3 and the seventeenth transistor M17 are both turned on. At this time, the blanking input signal terminal STU provides a low level. Thus, the pull-up control node H and the pull-up node Q in each stage of the shift register unit can be reset to achieve a global reset. At this time, the voltages of the pull-up control node H and the pull-up node Q are both low level.
  • the first frame 1F starts, the signal provided by the sixth sub-clock signal line CLK_6 becomes low level, and the signal provided by the fifth sub-clock signal line CLK_5 continues to maintain high level.
  • the thirteenth transistor M13 Since the fifth voltage terminal VDD_B provides a high level, the thirteenth transistor M13 is turned on, so that the pull-down node QB is charged to a high level.
  • the high level of the pull-down node QB causes the ninth transistor M9 to be turned on, thereby pulling down the pull-up node Q to a low level.
  • the blanking input signal terminal STU1 and the display input signal terminal STU2 of the first-stage shift register unit A1 are connected to the input signal line STU, so the blanking input signal terminal STU1 and the display input signal terminal STU2 are both Input high level.
  • the sixth transistor M6 is turned on, and the high-level signal of the second voltage terminal VDD can charge the pull-up node Q ⁇ 1> through the sixth transistor M6, so that the pull-up node Q is pulled up to a high level and is used by the second capacitor C2 storage.
  • the second clock signal terminal CLKB connected thereto is also a high level, so the third transistor M3 is turned on, and the pull-up control node H ⁇ 1> is charged to a high level
  • the level is stored by the first capacitor C1.
  • the sixteenth transistor M16 is turned on due to the high level of the display input signal terminal STU2, so that the pull-down node QB can be assisted in pull-down.
  • the fifth sub-clock signal line CLK_5 provides a low level, so that the second clock signal terminal CLKB is a low level, and the third transistor M3 is turned off.
  • the voltage of the pull-up node Q ⁇ 1> is high level, so that the seventh transistor M7 and the eighth transistor M8 are turned on.
  • the fourth clock signal terminal CLKD connected thereto is a low-level signal.
  • both the shift signal output terminal CR and the pixel signal output terminal OUT output low-level signals.
  • the pull-down node QB can be pulled low by the fourteenth transistor M14, thereby turning off the tenth transistor M10 and the eleventh transistor M11 .
  • the display input signal terminal STU2 keeps providing a high level, and the first transistor M1 is turned on.
  • the shift signal output terminal CR is coupled to the pixel signal output terminal OUT.
  • the voltage at the shift signal output terminal CR is subjected to noise reduction processing through the load capacitor C L and the load resistor R L coupled to the pixel signal output terminal OUT.
  • the voltage of the shift signal output terminal CR can be stabilized, and the noise of the shift signal output terminal CR can be effectively reduced.
  • the high-level signal is provided to the fourth clock signal terminal CLKD through the first sub-clock signal line CLK_1, so that the voltage of the pull-up node Q ⁇ 1> is further pulled up due to the bootstrap effect.
  • the seventh transistor M7 and the eighth transistor M8 remain turned on, so that both the shift signal output terminal CR and the pixel signal output terminal OUT output high-level signals.
  • the high-level signal output from the shift signal output terminal CR can be used for scanning shift of the upper and lower shift register units, and the high-level signal output from the pixel signal output terminal OUT can be used to drive the The sub-pixel unit performs display.
  • a low-level signal is provided to the fourth clock signal terminal CLKD through the first sub-clock signal line CLK_1, so that both the shift signal output terminal CR and the pixel signal output terminal OUT can pass through the fourth clock signal terminal CLKD Discharge, thereby completing the reset of the shift signal output terminal CR and the pixel signal output terminal OUT. Since the shift signal output terminal CR and the pixel signal output terminal OUT are reset to a low level, the voltage of the pull-up node Q ⁇ 1> will drop by an amplitude due to the coupling effect between the transistors.
  • the shift signal output terminal CR of the fourth-stage shift register unit A4 outputs a high level, so that the display reset signal terminal STD of the first-stage shift register unit A1 is also a high-level signal.
  • the eighteen transistor M18 is turned on, the pull-up node Q ⁇ 1> is pulled down to a low level, and the reset of the pull-up node Q ⁇ 1> is completed.
  • the voltage change of the first-stage pull-up node Q exhibits a “tower shape”.
  • the shift signal output terminal CR and the pixel signal output terminal OUT are at a high level, the voltage of the pull-up node Q rises due to the bootstrap effect.
  • the shift signal output terminal CR and the pixel signal output terminal OUT are discharged through the seventh transistor M7 and the eighth transistor M8, respectively, the current flowing through the transistor can be greater and the discharge speed is faster.
  • the eighth transistor M8 and the seventh transistor M7 can adopt smaller sizes. Transistor to reduce the layout area occupied by the shift register unit.
  • the fifth transistor M5 In the display period of the first frame described above, since the first clock signal terminal CLKA (connected to the seventh sub-clock signal line CLK_7) has been kept at a low level, the fifth transistor M5 remains turned off. The fifth transistor M5 can isolate the influence of the high level pre-stored at the pull-up control node H on the pull-up node Q in the display period.
  • the first-stage shift register unit drives the sub-pixels in the first row of the display panel to complete the display, and so on, and the second- and third-stage shift register units drive the sub-pixel units in the display panel row by row to complete a frame Display driver. At this point, the display period of the first frame ends.
  • the display reset signal line STD can provide a display reset signal to the display service signal terminal of the last three-stage shift register unit during the display period Display of each frame, so that the corresponding eighteenth transistor M18 is turned on, thereby pulling up Node Q.
  • the pull-up control node H maintains the high level of the display period due to the storage of the first capacitor C1.
  • the first clock signal terminal CLKA (connected to the seventh sub-clock signal line CLK_7) and the third clock signal terminal CLKC (connected to the sixth sub-clock signal line CLK_6) input high-level signals, the fourth transistor M4 and the first The five transistor M5 is turned on. Therefore, the high level of the third clock signal terminal CLKC can charge the pull-up node Q ⁇ 1> and pull the pull-up node Q ⁇ 1> to a high level.
  • the fourteenth transistor M14 is turned on under the control of the pull-up node Q ⁇ 1>, so that the pull-down node QB is pulled down to a low level.
  • the fifteenth transistor M15 is also turned on under the control of the first clock signal terminal CLKA, and can further pull down the pull-down node QB.
  • the second transistor M2 since the first clock signal terminal CLKA provides a high level, the second transistor M2 is turned on. Thereby, the second transistor M2 can couple the shift signal output terminal CR to the pixel signal output terminal OUT, so that the shift signal can be output to the shift signal through the load capacitance C L and the load resistance R L coupled to the pixel signal output terminal OUT
  • the signal at the terminal CR is subjected to noise reduction processing.
  • the voltage of the shift signal output terminal CR can be stabilized, and the noise of the shift signal output terminal CR can be effectively reduced.
  • a low-level signal is input to the first clock signal terminal CLKA, and the fifth transistor M5 is turned off.
  • the fourth clock signal terminal CLKD (connected to the first sub-clock signal line CLK_1) inputs a high-level signal, and the voltage of the pull-up node Q ⁇ 1> is further pulled up due to the bootstrap effect.
  • the seventh transistor M7 and the eighth transistor M8 is turned on, and the high-level signal input from the fourth clock signal terminal CLKD can be output to the shift signal output terminal CR and the pixel signal output terminal OUT.
  • the blanking input signal terminal STU1 of the second-stage shift register unit A2 is connected to the first-stage shift register
  • the shift signal output terminal CR of unit A1 is connected, so the third transistor M3 in the second-stage shift register unit A2 is turned on, so that the pull-up control node H ⁇ 2> in the second-stage shift register unit A2 is Pull up to high level.
  • the sixth sub-clock signal line CLK_6 inputs a low-level signal.
  • the fourth clock signal terminal CLKD of the first-stage shift register unit A1 (connected to the first sub-clock signal line CLK_1) continues to input a high level, so the shift signal output terminal CR and the pixel signal output terminal OUT keep output high Ping signal.
  • the first clock signal terminal CLKA (connected to the seventh sub-clock signal line CLK_7) is at a low level, and the fifth transistor M5 remains off, so that the pull-up node Q ⁇ 1> can be prevented from passing through the fifth transistor M5 leakage.
  • the fifth sub-clock signal line CLK_5 inputs a high-level signal. Since the second clock signal terminal CLKB of the odd-numbered shift register unit is connected to the fifth sub-clock signal line CLK_5, the The reset of the pull-up control node H and the pull-up node Q in all odd-stage shift register units.
  • the gate driving circuit 30 repeats the same operation as the display period of the first frame, which will not be repeated here.
  • the third clock signal terminal CLKC is connected to the fifth sub-clock signal line CLK_5.
  • both the first clock signal terminal CLKA and the third clock signal terminal CLKC of the second-stage shift register unit A2 input high-level signals, and the fourth transistor M4 and the fifth transistor M5 are turned on.
  • the high level input from the third clock signal terminal CLKC can charge the pull-up node Q ⁇ 2> and pull the pull-up node Q ⁇ 2> to a high level.
  • the shift signal output terminal CR and the pixel signal output terminal OUT output a high-level signal
  • the sixth sub-clock signal line CLK_6 inputs a high-level signal. Since the second clock signal terminal CLKB of the even-numbered shift register unit is connected to the sixth sub-clock signal line CLK_6, the pull-up control node H and the pull-up node Q in all even-numbered shift register units can be completed Reset.
  • the blanking output signal output by the gate driving circuit can be used to drive the sensing transistor in the sub-pixel unit in the display panel.
  • the driving signal is sequentially provided line by line.
  • the gate driving circuit outputs a driving signal for the sub-pixel unit of the first row of the display panel.
  • the gate driving circuit outputs a driving signal for the sub-pixel unit of the second row of the display panel, and so on, to complete the row-by-row sequential compensation.
  • the embodiments of the present disclosure also provide a display device.
  • the display device may include the gate driving circuit 30 according to an embodiment of the present disclosure.
  • the display device may be any product or component with a display function such as a liquid crystal panel, an LCD TV, a display, an OLED panel, an OLED TV, an electronic paper display device, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigator, etc. .
  • the embodiments of the present disclosure also provide a method for driving a shift register unit and a gate driving circuit.
  • FIG. 10 shows a schematic flowchart of a method for driving a shift register unit according to an embodiment of the present disclosure.
  • the shift register unit may be any applicable shift register unit based on an embodiment of the present disclosure, such as at least one of shift register unit 10, shift register unit 15, shift register unit 20, and shift register unit 25.
  • the blanking input circuit 100 may provide the blanking input signal to the pull-up control node H in response to the second clock signal.
  • the blanking input circuit 100 may store the voltage of the pull-up control node H.
  • the display input circuit 200 may provide a display pull-up signal to the pull-up node Q in response to the display input signal.
  • the first control circuit 400 may couple the shift signal output terminal CR to the pixel signal output terminal OUT.
  • the voltage of the shift signal output terminal CR can be subjected to noise reduction processing through the load capacitor C L and the load resistor R L coupled to the pixel signal output terminal OUT, thereby stabilizing the voltage of the shift signal output terminal CR and effectively Reduce the noise of the shift signal output terminal CR.
  • the output circuit 300 may output a display output signal under the control of the voltage of the pull-up node Q.
  • the display output signal can be used to drive the sub-pixel unit in the display panel for display.
  • steps 920 and 930 may be performed during the display period of one frame.
  • the blanking input circuit 100 may provide the blanking pull-up signal to the pull-up node Q under the control of the voltage of the pull-up control node H and the first clock signal.
  • the second control circuit 420 may couple the shift signal output terminal CR to the pixel signal output terminal OUT under the control of the first clock signal. Therefore, the voltage at the shift signal output terminal CR can be subjected to noise reduction processing through the load capacitor C L and the load resistor R L coupled to the pixel signal output terminal OUT, thereby stabilizing the voltage at the shift signal output terminal CR, Effectively reduce the noise of the shift signal output terminal CR.
  • the output circuit 300 may output a blanking output signal under the control of the voltage of the pull-up node Q.
  • the blanking output signal can be used to drive the sub-pixel unit in the display panel for external compensation.
  • step 910 may be performed during the blanking period of one frame, and step 940 and step 950 may be performed during the blanking period of the next frame.
  • step 910 may be performed during the display period of one frame, and 940 and 950 may be performed during the blanking period of the same frame.

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Abstract

本公开的实施例提供了移位寄存器单元、栅极驱动电路、显示装置及驱动方法。移位寄存器单元包括消隐输入电路、显示输入电路、输出电路和第一控制电路。消隐输入电路将消隐输入信号提供到上拉控制节点并将消隐上拉信号提供到上拉节点。显示输入电路响应于显示输入信号将显示上拉信号提供到上拉节点。输出电路在上拉节点的电压的控制下，将输出信号输出至移位信号输出端和像素信号输出端。第一控制电路响应于显示输入信号将移位信号输出端耦接到像素信号输出端。

Description

移位寄存器单元、栅极驱动电路、显示装置及驱动方法
相关申请的交叉引用
本申请要求于2018年10月25日递交的申请号为201811246431.0的中国专利申请的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开涉及显示技术领域，具体地，涉及移位寄存器单元、栅极驱动电路、显示装置及驱动方法。
背景技术
随着显示技术的进步，相对于传统的液晶显示(Liquid Crystal Display，LCD)装置，新一代的有机发光二极管(Organic Light Emitting Diode，OLED)显示装置具有更低的制造成本，更快的反应速度，更高的对比度，更广的视角，更大的工作温度范围，不需要背光单元，色彩鲜艳及轻薄等优点，因此OLED显示技术成为当前发展最快的显示技术。
为了提高OLED面板的工艺集成度并降低成本，通常采用阵列基板行驱动(Gate Driver on Array，简称GOA)技术而将薄膜晶体管(TFT)的栅极驱动电路集成在显示面板的阵列基板上以形成对显示面板的扫描驱动。这种利用GOA技术而集成在阵列基板上的栅极驱动电路也称为GOA单元或移位寄存器单元。采用GOA电路的显示装置由于省去了绑定驱动电路的部分，可以从材料成本和制作工艺两方面降低成本。
发明内容
本公开的实施例提供了移位寄存器及其驱动方法、栅极驱动电路及其驱动方法、以及显示装置。
根据本公开的第一方面，提供了一种移位寄存器单元。移位寄存器单 元包括消隐输入电路、显示输入电路、输出电路和第一控制电路。消隐输入电路被配置为将消隐输入信号提供到上拉控制节点以及将消隐上拉信号提供到上拉节点。显示输入电路被配置为根据显示输入信号将显示上拉信号提供到上拉节点。输出电路被配置为在上拉节点的电压的控制下，将输出信号提供至移位信号输出端和像素信号输出端。第一控制电路被配置为根据显示输入信号将移位信号输出端耦接到像素信号输出端。
在本公开的实施例中，第一控制电路包括第一晶体管。第一晶体管的控制极和显示输入信号端耦接以接收显示输入信号，第一晶体管的第一极和移位信号输出端耦接，第一晶体管的第二极和像素信号输出端耦接。
在本公开的实施例中，移位寄存器单元还包括第二控制电路。第二控制电路被配置为在第一时钟信号的控制下，将移位信号输出端耦接到像素信号输出端。
在本公开的实施例中，第二控制电路包括第二晶体管。第二晶体管的控制极和第一时钟信号端耦接以接收第一时钟信号，第二晶体管的第一极和移位信号输出端耦接，第二晶体管的第二极和像素信号输出端耦接。
在本公开的实施例中，消隐输入电路包括充电子电路、存储子电路和隔离子电路。充电子电路被配置为根据第二时钟信号将消隐输入信号提供到上拉控制节点。存储子电路被配置为存储充电子电路提供的消隐输入信号。隔离子电路被配置为在上拉控制节点的电压和第一时钟信号的控制下，将消隐上拉信号提供到上拉节点。
在本公开的实施例中，充电子电路包括第三晶体管，第三晶体管的控制极和第二时钟信号端耦接以接收第二时钟信号，第三晶体管的第一极和消隐输入信号端耦接以接收消隐输入信号，第三晶体管的第二极和上拉控制节点耦接。存储子电路包括第一电容，第一电容的第一极和上拉控制节点耦接，第一电容的第二极和第一电压端耦接以接收第一电压。隔离子电路包括第四晶体管和第五晶体管，第四晶体管的控制极和上拉控制节点耦接，第四晶体管的第一极和第三时钟信号端耦接以接收第三时钟信号作为消隐上拉信号，第四晶体管的第二极和第五晶体管的第一极耦接，第五晶 体管的控制极和第一时钟信号端耦接以接收第一时钟信号，第五晶体管的第二极和上拉节点耦接。
在本公开的实施例中，显示输入电路包括第六晶体管。第六晶体管的控制极和显示输入信号端耦接以接收显示输入信号，第六晶体管的第一极和第二电压端耦接以接收第二电压作为显示上拉信号，第六晶体管的第二极和上拉节点耦接。
在本公开的实施例中，输出电路包括第七晶体管、第八晶体管和第二电容。第七晶体管的控制极和上拉节点耦接，第七晶体管的第一极和第四时钟信号端耦接以接收第四时钟信号作为输出信号，第七晶体管的第二极和移位信号输出端耦接。第八晶体管的控制极和上拉节点耦接，第八晶体管的第一极和第四时钟信号端耦接以接收第四时钟信号作为输出信号，第八晶体管的第二极和像素信号输出端耦接。第二电容的第一极和上拉节点耦接，第二电容的第二极和第七晶体管的第二极耦接。
在本公开的实施例中，移位寄存器单元还包括下拉电路、第一下拉控制电路、第二下拉控制电路和复位电路。下拉电路被配置为在下拉节点的电压的控制下，对上拉节点、移位信号输出端和像素信号输出端进行降噪。第一下拉控制电路被配置为在上拉节点的电压的控制下，对下拉节点的电压进行控制。第二下拉控制电路被配置为在消隐下拉控制信号和显示下拉控制信号的控制下，对下拉节点的电压进行控制。复位电路被配置为在消隐复位信号和显示复位信号的控制下对上拉节点进行复位。
在本公开的实施例中，下拉电路包括第九晶体管、第十晶体管和第十一晶体管。第九晶体管的控制极和下拉节点耦接，第九晶体管的第一极和上拉节点耦接，第九晶体管的第二极和第一电压端耦接以接收第一电压。第十晶体管的控制极和下拉节点耦接，第十晶体管的第一极和移位信号输出端耦接，第十晶体管的第二极和第一电压端耦接以接收第一电压。第十一晶体管的控制极和下拉节点耦接，第十一晶体管的第一极和像素信号输出端耦接，第十一晶体管的第二极和第三电压端耦接以接收第三电压。
在本公开的实施例中，第一下拉控制电路包括第十二晶体管、第十三 晶体管和第十四晶体管。第十二晶体管的控制极和第一极与第四电压端耦接以接收第四电压，第十二晶体管的第二极和下拉节点耦接。第十三晶体管的控制极和第一极与第五电压端耦接以接收第五电压，第十三晶体管的第二极和下拉节点耦接。第十四晶体管的控制极和上拉节点耦接，第十四晶体管的第一极和下拉节点耦接，第十四晶体管的第二极和第一电压端耦接以接收第一电压。
在本公开的实施例中，第二下拉控制电路包括第十五晶体管和第十六晶体管。第十五晶体管的控制极和第一时钟信号端耦接以接收第一时钟信号作为消隐下拉控制信号，第十五晶体管的第一极和下拉节点耦接，第十五晶体管的第二极和第一电压端耦接以接收第一电压。第十六晶体管的控制极和显示输入信号端耦接以接收显示输入信号作为显示下拉控制信号，第十六晶体管的第一极和下拉节点耦接，第十六晶体管的第二极和第一电压端耦接以接收第一电压。
在本公开的实施例中，复位电路包括第十七晶体管和第十八晶体管。第十七晶体管的控制极和第二时钟信号端耦接以接收第二时钟信号并作为消隐复位信号，第十七晶体管的第一极和上拉节点耦接，第十七晶体管的第二极和第一电压端耦接以接收第一电压。第十八晶体管的控制极和显示复位信号端耦接以接收显示复位信号，第十八晶体管的第一极和上拉节点耦接，第十八晶体管的第二极和第一电压端耦接以接收第一电压。
在本公开的实施例中，移位寄存器单元还包括负载电容和负载电阻。负载电容的一端耦接像素信号输出端，另一端接地。负载电阻的一端耦接像素信号输出端，另一端接地。
根据本公开的第二方面，提供了一种栅极驱动电路。栅极驱动电路包括多个级联的如本公开的第一方面提供的移位寄存器单元。第n级移位寄存器单元的移位信号输出端向第n+1级移位寄存器单元提供消隐输入信号。第n级移位寄存器单元的移位信号输出端向第n+2级移位寄存器单元提供显示输入信号。n为大于0的整数。
在本公开的实施例中，栅极驱动电路还包括第一子时钟信号线、第二 子时钟信号线、第三子时钟信号线和第四子时钟信号线。第一子时钟信号线向第4n-3级移位寄存器单元提供第四时钟信号作为输出信号，第二子时钟信号线向第4n-2级移位寄存器单元提供第四时钟信号作为输出信号，第三子时钟信号线向第4n-1级移位寄存器单元提供第四时钟信号作为输出信号，第四子时钟信号线向第4n级移位寄存器单元提供第四时钟信号作为输出信号。
在本公开的实施例中，栅极驱动电路还包括第五子时钟信号线、第六子时钟信号线和第七子时钟信号线。第五子时钟信号线向第2n-1级移位寄存器单元提供第二时钟信号，以及向第2n级移位寄存器单元提供第三时钟信号作为消隐上拉信号。第六子时钟信号线向第2n-1级移位寄存器单元提供第三时钟信号作为消隐上拉信号，以及向第2n级移位寄存器单元提供第二时钟信号端。第七子时钟信号线向各级移位寄存器单元提供第一时钟信号。
在本公开的实施例中，n+3级移位寄存器单元的移位信号输出端向第n级移位寄存器单元提供显示复位信号。
根据本公开的第三方面，提供了一种显示装置。显示装置包括如本公开的第二方面提供的栅极驱动电路。
根据本公开的第四方面，提供了一种用于驱动如本公开的第一方面提供的移位寄存器单元的方法。方法包括：消隐输入电路将消隐输入信号提供到上拉控制节点；显示输入电路响应于显示输入信号将显示上拉信号提供到上拉节点，其中，在显示输入信号的控制下，第一控制电路将移位信号输出端耦接到像素信号输出端；输出电路在上拉节点的电压的控制下输出显示输出信号；消隐输入电路在上拉控制节点的电压和第一时钟信号的控制下将消隐上拉信号提供到上拉节点；以及输出电路在上拉节点的电压的控制下输出消隐输出信号。
在本公开的实施例中，方法进一步包括：第二控制电路在第一时钟信号的控制下将移位信号输出端耦接到像素信号输出端。
附图说明
为了更清楚地说明本公开的技术方案，下面将对实施例的附图进行简单说明。应当知道，以下描述的附图仅仅是本公开的一些实施例，而非对本公开的限制，其中：
图1示出了根据本公开的实施例的移位寄存器单元的示意性框图；
图2示出了根据本公开的实施例的消隐输入电路的示意性框图；
图3示出了根据本公开的实施例的移位寄存器单元的示意性框图；
图4示出了根据本公开的实施例的移位寄存器单元的示意性框图；
图5示出了根据本公开的实施例的移位寄存器单元的示意性框图；
图6示出了根据本公开的实施例的移位寄存器单元的示例性电路图；
图7示出了根据本公开的实施例的移位寄存器单元的示例性电路图；
图8示出了根据本公开的实施例的栅极驱动电路的示意图；
图9示出了根据本公开的实施例的栅极驱动电路的工作过程中各信号的时序图；以及
图10示出了根据本公开的实施例的用于驱动移动寄存器单元的方法的示意性流程图。
具体实施方式
为使本公开实施例的技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指 出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在显示领域，特别是有机发光二极管OLED显示技术中，栅极驱动电路通常都集成在集成电路IC中。集成电路IC设计中芯片的面积是影响芯片成本的主要因素。通常，栅极驱动电路包括检测电路、显示电路和输出两者复合脉冲的连接电路(或门电路)。此类电路结构非常复杂，难以满足高分辨率窄边框的要求。
在对OLED显示面板中的子像素单元进行补偿时，除了在子像素单元中设置像素补偿电路进行内部补偿外，还可以通过设置感测晶体管进行外部补偿。在进行外部补偿时，由移位寄存器单元构成的栅极驱动电路需要向显示面板中的子像素单元分别提供用于扫描晶体管和感测晶体管的驱动信号。例如，在一帧的显示时段(Display)提供用于扫描晶体管的扫描驱动信号，在一帧的消隐时段(Blank)提供用于感测晶体管的感测驱动信号。
在本公开的实施例中，“一帧”、“每帧”或“某一帧”包括依次进行的显示时段和消隐时段。例如，在显示时段中，栅极驱动电路输出显示输出信号，该显示输出信号可以用于驱动显示面板中的扫描晶体管，以进行从第一行到最后一行的扫描。在消隐时段中，栅极驱动电路输出消隐输出信号，该消隐输出信号可以用于驱动显示面板中的某一行子像素单元中的感测晶体管，以完成该行子像素单元的外部补偿。
在高频率驱动栅极驱动电路时，由于数据写入时间很短，所以可对栅极线预充电以使多个输出波形之间存在交叠，从而提高数据写入时间。然而，在高电平写入阶段，栅极驱动电路中的各移位寄存器单元的输出端容易产生耦合噪声。
本公开的实施例提供了移位寄存器单元及其驱动方法、栅极驱动电路及其驱动方法、以及显示装置。下面结合附图对本公开的实施例及其示例进 行详细说明。
图1示出了根据本公开的实施例的移位寄存器单元的示意性框图。如图1所示，移位寄存器单元10可包括消隐输入电路100、显示输入电路200、输出电路300和第一控制电路400。
消隐输入电路100可将消隐输入信号提供到上拉控制节点H(图1中未示出，参见图2，将在下文中详细描述)，以控制上拉控制节点H的电压。消隐输入电路100还可将消隐上拉信号提供到上拉节点Q，以控制上拉节点Q的电压。
在一些实施例中，消隐输入电路100可与消隐输入信号端STU1耦接以接收消隐输入信号，与第一时钟信号端CLKA耦接以接收第一时钟信号，与第二时钟信号端CLKB耦接以接收第二时钟信号，以及与第三时钟信号端CLKC耦接以接收第三时钟信号。第三时钟信号可作为消隐上拉信号。
例如，消隐输入电路100可在第二时钟信号的控制下，将消隐输入信号提供到上拉控制节点H。消隐输入电路100还可以在上拉控制节点H的电压和第一时钟信号的控制下，将消隐上拉信号提供到上拉节点Q。
在示例性实施例中，消隐输入电路100可以在一帧的显示时段接收消隐输入信号并存储消隐输入信号，并在这一帧的消隐时段根据消隐输入信号向上拉节点Q提供消隐上拉信号。此外，消隐输入电路100还可以在一帧的消隐时段接收消隐输入信号并存储消隐输入信号，并在下一帧的消隐时段根据消隐输入信号向上拉节点Q提供消隐上拉信号。
图2示出了根据本公开的实施例的消隐输入电路的示意性框图。如图2所示，消隐输入电路100可包括充电子电路110、存储子电路120和隔离子电路130。
充电子电路110可在第二时钟信号的控制下，将消隐输入信号提供到上拉控制节点H，以控制上拉控制节点H的电压。例如，充电子电路110可与第二时钟信号端CLKB耦接以接收第二时钟信号，以及与消隐输入信号端STU1耦接以接收消隐输入信号。
存储子电路120可存储充电子电路提供的消隐输入信号。例如，存储子 电路120可与上拉控制节点H耦接，以及与第一电压端VGL1耦接(未示出)以接收第一电压。在实施例中，在一帧的显示时段中，存储子电路120可将上拉控制节点H充电至高电位。从而使得上拉控制节点H的高电平一直保持至该帧的消隐时段。
在本公开的实施例中，第一电压端VGL1可提供直流低电平信号，即第一电压为低电平。
隔离子电路130可在上拉控制节点H的电压和第一时钟信号的控制下，将消隐上拉信号提供到上拉节点Q，以控制上拉节点Q的电压。例如，隔离子电路130可与第一时钟信号端CLKA耦接以接收第一时钟信号，与第三时钟信号端CLKC耦接以接收第三时钟信号并作为消隐上拉信号。
由于隔离子电路130设置在上拉节点Q和上拉控制节点H之间，所以可以防止上拉节点Q与上拉控制节点H相互影响。在实施例中，例如在消隐时段，隔离子电路130可在第一时钟信号的控制下，断开上拉节点Q与第三时钟信号端CLKC之间的连接。在此期间，高电平的消隐上拉信号不影响上拉节点Q的电压。
如图1所示，显示输入电路200可在显示输入信号的控制下将显示上拉信号提供到上拉节点Q。例如，显示输入电路200可与显示输入信号端STU2耦接以接收显示输入信号，以及与第二电压端VDD耦接以接收第二电压并作为显示上拉信号。
在本公开的实施例中，第二电压端VDD可提供直流高电平信号，即第二电压为高电平。
输出电路300可在上拉节点Q的电压的控制下，将输出信号提供至移位信号输出端CR和像素信号输出端OUT。例如，输出电路300可与第四时钟信号端CLKD耦接以接收第四时钟信号并作为输出信号。
在实施例中，输出信号可以包括显示输出信号和消隐输出信号，在一帧的显示时段中，输出电路300可在上拉节点Q的电压的控制下将显示输出信号输出至移位信号输出端CR和像素信号输出端OUT。从移位信号输出端CR输出的显示输出信号可以用于上下级移位寄存器单元的扫描移位。 从像素信号输出端OUT输出的显示输出信号可以用于驱动显示面板中的子像素单元进行扫描显示。在一帧的消隐时段中，输出电路300可在上拉节点Q的电压的控制下将消隐输出信号输出至移位信号输出端CR和像素信号输出端OUT。从移位信号输出端CR输出的消隐输出信号可以用于下一级移位寄存器单元的消隐输入信号(将在下文中详细描述)。从像素信号输出端OUT输出的消隐输出信号可以用于控制显示面板中的子像素单元中的晶体管。
此外，第一控制电路400可在显示输入信号的控制下，将移位信号输出端CR耦接到像素信号输出端OUT。例如，第一控制电路400可与显示输入信号端STU2耦接以接收显示输入信号。在实施例中，第一控制电路400在显示输入信号的控制下使移位信号输出端CR与像素信号输出端OUT耦接，由此可通过像素信号输出端OUT侧的负载电容和负载电阻(未示出)对移位信号输出端CR进行稳压。负载电容可以是单独设置的电容，也可以是与像素信号输出端OUT耦接的线路上的寄生电容。负载电阻可以是单独设置的电阻，也可以是与像素信号输出端OUT耦接的线路上的寄生电阻。在显示阶段对上拉节点Q写入高电压时，移位信号输出端CR耦接到与像素信号输出端OUT耦接的负载电容和负载电阻，由此利用负载电容和负载电阻的滤波作用减少移位信号输出端CR处的信号的噪声。以此方式，可以有效地降低高压写入过程中移位信号输出端CR的噪声。
根据本公开的实施例提供的移位寄存器单元10，可以实现在不同时段通过消隐输入电路100和显示输入电路200分别控制上拉节点Q的电压，消隐输入电路100和显示输入电路200共用同一个输出电路300以实现显示输出信号和消隐输出信号两者的输出。此外，第一控制电路400可控制输出电路300的移位信号输出端CR耦接到像素信号输出端OUT，以降低高压写入过程中移位信号输出端CR产生的噪声。
图3示出了根据本公开的实施例的移位寄存器单元的示意性框图。如图3所示，移位寄存器单元15可包括消隐输入电路100、显示输入电路200、输出电路300、第一控制电路400、下拉电路500、第一下拉控制电路600、 第二下拉控制电路700和复位电路800。其中，消隐输入电路100、显示输入电路200、输出电路300、第一控制电路400已在上文中详细描述，在此不再赘述。
在实施例中，下拉电路500可在下拉节点QB的电压的控制下，对上拉节点Q、移位信号输出端CR和像素信号输出端OUT进行降噪。例如，下拉电路500可与第一电压端VGL1耦接以接收第一电压，与第三电压端VGL2耦接以接收第三电压。在实施例中，下拉电路500可在下拉节点QB的电压的控制下，通过第一电压端VGL1的第一电压控制上拉节点Q和移位信号输出端CR的电压，以及通过第三电压端VGL2控制像素信号输出端OUT的电压。由此，下拉电路500可降低上拉节点Q、移位信号输出端CR和像素信号输出端OUT的噪声。
在本公开的实施例中，第三电压端VGL2可提供直流低电平信号，即第三电压为低电平。
第一下拉控制电路600可在上拉节点Q的电压的控制下，对下拉节点QB的电压进行控制。例如，第一下拉控制电路600可与第一电压端VGL1耦接以接收第一电压，与第四电压端VDD_A耦接以接收第四电压。在实施例中，当上拉节点Q处于高电平时，第一下拉控制电路600可以通过第一电压(例如为低电平)将下拉节点QB的电压下拉至低电平。当上拉节点Q的电压处于低电平时，第一下拉控制电路600可以利用第四电压(例如为高电平)对下拉节点QB进行充电，以将下拉节点QB上拉至高电平。
在另一个示例中，第一下拉控制电路600还可以和第五电压端VDD_B耦接以接收第五电压(例如为高电平)。例如，第四电压端VDD_A和第五电压端VDD_B可以被配置为交替提供高电平，即第四电压端VDD_A提供高电平时，第五电压端VDD_B提供低电平，而第四电压端VDD_A提供低电平时，第五电压端VDD_B提供高电平。在实施例中，当上拉节点Q的电压处于低电平时，第一下拉控制电路600可以利用第四电压或第五电压对下拉节点QB进行充电，以将下拉节点QB上拉至高电平。
第二下拉控制电路700可在消隐下拉控制信号的控制下，对下拉节点 QB的电压进行控制。例如，第二下拉控制电路700可与第一时钟信号端CLKA耦接以接收第一时钟信号并作为消隐下拉控制信号，以及与第一电压端VGL1耦接以接收第一电压。在实施例中，在一帧的消隐时段中，第二下拉控制电路700可以响应于第一时钟信号而导通，从而可以通过第一电压端VGL1将下拉节点QB下拉至低电平。采用这种方式可以使得在消隐时段中，降低下拉节点QB对上拉节点Q的影响，使得消隐输入电路100对上拉节点Q的充电更充分。需要说明的是，在本公开的实施例中，第二下拉控制电路700还可以与其它信号端耦接以接收消隐下拉控制信号，本公开对此不作限定。
此外，第二下拉控制电路700还可在显示下拉控制信号的控制下，对下拉节点QB的电压进行控制。例如，第二下拉控制电路700可与显示输入信号端STU2连接以接收显示输入信号并作为显示下拉控制信号，以及与第一电压端VGL1耦接以接收第一电压。在实施例中，在一帧的显示时段中，在将显示输入信号提供至显示输入电路200对上拉节点Q充电的同时，将该显示输入信号也提供至第二下拉控制电路700，从而可以通过第一电压端VGL1将下拉节点QB下拉至低电平。采用这种方式可以使得在显示时段中，降低下拉节点QB对上拉节点Q的影响，使得显示输入电路200对上拉节点Q的充电更充分。需要说明的是，在本公开的实施例中，第二下拉控制电路700还可以与其它信号端耦接以接收显示下拉控制信号，本公开对此不作限定。
另一方面，复位电路800可在消隐复位信号的控制下对上拉节点Q进行复位。例如，复位电路800可与第二时钟信号端CLKB耦接以接收第二时钟信号并作为消隐复位信号，以及与第一电压端VGL1耦接以接收第一电压。需要说明的是，在本公开的实施例中，复位电路800还可以与其它信号端耦接以接收消隐复位信号，本公开对此不作限定。
此外，复位电路800还可在显示复位信号的控制下对上拉节点Q进行复位。例如，复位电路800可与显示复位信号端STD耦接以接收显示复位信号，以及与第一电压端VGL1耦接以接收第一电压。
本领域技术人员可以理解，尽管图3中的移位寄存器单元10示出了下拉电路500、第一下拉控制电路600，第二下拉控制电路700和复位电路800，然而上述示例并不能限制本公开的保护范围。在实际应用中，技术人员可以根据情况选择使用或不使用上述各电路中的一个或多个，基于前述各电路的各种组合变型均不脱离本公开的原理，对此不再赘述。
图4示出了根据本公开的另一实施例的移位寄存器单元的示意性框图。如图4所示，移位寄存器单元20可包括消隐输入电路100、显示输入电路200、输出电路300、第一控制电路400和第二控制电路420。上文中已对消隐输入电路100、显示输入电路200、输出电路300和第一控制电路400进行描述，在此不再赘述。
第二控制电路420可在第一时钟信号的控制下，将移位信号输出端CR耦接到像素信号输出端OUT。例如，第二控制电路420可与第一时钟信号端CLKA耦接以接收第一时钟信号。在实施例中，第二控制电路420可在第一时钟信号的控制下使移位信号输出端CR与像素信号输出端OUT耦接，由此通过像素信号输出端OUT侧的负载电容和负载电阻(未示出)对移位信号输出端CR进行稳压。在实施例中，例如在消隐时段，隔离子电路130可根据第一时钟信号控制上拉节点Q与第三时钟信号端CLKC的连接。由此，在根据第一时钟信号控制上拉节点Q与第三时钟信号端CLKC连接的过程期间，在消隐上拉信号对上拉节点Q进行高电压写入过程中，可通过负载电容和负载电阻对移位信号输出端CR处的电压噪声进行处理。以此方式，可以有效地降低高压写入过程中移位信号输出端CR的噪声。
相应地，图5示出了根据本公开的实施例的移位寄存器单元的示例性电路图。如图5所示，移位寄存器25可包括消隐输入电路100、显示输入电路200、输出电路300、第一控制电路400、第二控制电路420、下拉电路500、第一下拉控制电路600、第二下拉控制电路700和复位电路800。各电路均在上文中详细描述，在此不再赘述。
在本公开的实施例中，移位寄存器单元还可包括负载电容和负载电阻(未示出)。负载电容的一端耦接像素信号输出端，另一端接地。负载电阻 的一端耦接像素信号输出端，另一端接地。如上所述，负载电容可以是单独设置的电容，也可以是与像素信号输出端OUT耦接的线路上的寄生电容。负载电阻可以是单独设置的电阻，也可以是与像素信号输出端OUT耦接的线路上的寄生电阻。
以下通过示例电路结构来对本公开提供的移位寄存器单元进行描述。
图6示出了根据本公开的实施例的移位寄存器单元的示例性电路图。移位寄存器单元例如是图3中所示的移位寄存器单元15。如图6所示，移位寄存器单元可包括第一晶体管M1至第十七晶体管M17、第一电容C1和第二电容C2、以及负载电容C L和负载电阻R L。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其它特性相同的开关器件。本公开的实施例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。晶体管的栅极可被称为控制极。此外，按照晶体管的特性区分可以将晶体管分为N型和P型晶体管。当晶体管为P型晶体管时，导通电压为低电平电压(例如，0V、-5V、-10V或其它合适的电压)，关断电压为高电平电压(例如，5V、10V或其它合适的电压)。当晶体管为N型晶体管时，导通电压为高电平电压(例如，5V、10V或其它合适的电压)，关断电压为低电平电压(例如，0V、-5V、-10V或其它合适的电压)。
另外，需要说明的是，本公开的实施例中提供的移位寄存器单元10中采用的晶体管均是以N型晶体管(例如，NMOS晶体管)为例进行说明的。本公开的实施例包括但不限于此，例如移位寄存器单元10中的至少部分晶体管也可以采用P型晶体管(例如，PMOS晶体管)。
如图6所示，消隐输入电路100中的充电子电路110可包括第三晶体管M3。第三晶体管M3的栅极和第二时钟信号端CLKB耦接以接收第二时钟信号，第三晶体管M3的第一极和消隐输入信号端STU1耦接以接收消隐输入信号，第三晶体管M3的第二极和上拉控制节点H耦接。在实施例中， 当第二时钟信号为高电平时，第三晶体管M3导通，从而可以将消隐输入信号提供到上拉控制节点H以对其进行充电。
消隐输入电路100中的存储子电路120可包括第一电容C1。第一电容C1的第一端和上拉控制节点H耦接，第一电容C1的第二端和第一电压端VGL1耦接以接收第一电压。通过设置第一电容C1可以保持上拉控制节点H的电压。在实施例中，在一帧的显示时段中，第三晶体管M3可将上拉控制节点H充电至高电平，第一电容C1可以将上拉控制节点H的高电平保持至该帧的消隐时段。
消隐输入电路100中的隔离子电路130可包括第四晶体管M4和第五晶体管M5。第四晶体管M4的栅极和上拉控制节点H耦接，第四晶体管M4的第一极和第三时钟信号端CLKC耦接以接收第三时钟信号并作为消隐上拉信号，第四晶体管M4的第二极和第五晶体管M5的第一极耦接。第五晶体管M5的栅极和第一时钟信号端CLKA耦接以接收第一时钟信号，第五晶体管M5的第二极和上拉节点Q耦接。在实施例中，在一帧的消隐时段中，第四晶体管M4可在上拉控制节点H的电压的控制下导通，当第一时钟信号为高电平时，第五晶体管M5导通，因此第三时钟信号可以通过第四晶体管M4和第五晶体管M5对上拉节点Q进行充电。
显示输入电路200可包括第六晶体管M6。第六晶体管M6的栅极和显示输入信号端STU2耦接以接收显示输入信号，第六晶体管M6的第一极和第二电压端VDD耦接以接收第二电压作为显示上拉信号，第六晶体管M6的第二极和上拉节点Q耦接。在实施例中，在一帧的显示时段中，第六晶体管M6可在显示输入信号的控制下导通，从而利用第二电压对上拉节点Q进行充电。
输出电路300可包括第七晶体管M7、第八晶体管M8和第二电容。第七晶体管M7的栅极和上拉节点Q耦接，第七晶体管M7的第一极和第四时钟信号端CLKD耦接以接收第四时钟信号作为输出信号，第七晶体管M7的第二极和移位信号输出端CR耦接。第八晶体管M8的栅极和上拉节点Q耦接，第八晶体管M8的第一极和第四时钟信号端CLKD耦接以接收 第四时钟信号作为输出信号，第八晶体管M8的第二极和像素信号输出端OUT耦接。第二电容C2的第一极和上拉节点Q耦接，第二电容C2的第二极和第七晶体管M7的第二极耦接。在实施例中，在上拉节点Q的电压为高电平时，第七晶体管M7和第八晶体管M8导通，从而可以将第四时钟信号作为输出信号分别输出至移位信号输出端CR和像素信号输出端OUT。
第一控制电路400可包括第一晶体管M1。第一晶体管M1的栅极和显示输入信号端STU2耦接以接收显示输入信号，第一晶体管M1的第一极和移位信号输出端CR耦接，第一晶体管M1的第二极和像素信号输出端OUT耦接。
下拉电路500可包括第九晶体管M9、第十晶体管M10和第十一晶体管M11。第九晶体管M9的栅极和下拉节点QB耦接，第九晶体管M9的第一极和上拉节点Q耦接，第九晶体管M9的第二极和第一电压端VGL1耦接以接收第一电压。第十晶体管M10的栅极和下拉节点QB耦接，第十晶体管M10的第一极和移位信号输出端CR耦接，第十晶体管M10的第二极和第一电压端VGL1耦接以接收第一电压。第十一晶体管M11的栅极和下拉节点QB耦接，第十一晶体管M11的第一极和像素信号输出端OUT耦接，第十一晶体管M11的第二极和第三电压端VGL2耦接以接收第三电压。
第一下拉控制电路600可包括第十二晶体管M12、第十三晶体管M13和第十四晶体管M14。第十二晶体管M12的栅极和第一极与第四电压端VDD_A耦接以接收第四电压，第十二晶体管M12的第二极和下拉节点QB耦接。第十三晶体管M13的栅极和第一极与第五电压端VDD_B耦接以接收第五电压，第十三晶体管M13的第二极和下拉节点QB耦接。第十四晶体管M14的栅极和上拉节点Q连接，第十四晶体管M14的第一极和下拉节点QB耦接，第十四晶体管M14的第二极和第一电压端VGL1耦接以接收第一电压。
在实施例中，第四电压端VDD_A和第五电压端VDD_B可以被配置为交替提供高电平。也就是说，第四电压端VDD_A提供高电平时，第五电 压端VDD_B提供低电平，而第四电压端VDD_A提供低电平时，第五电压端VDD_B提供高电平。因此，第十二晶体管M12和第十三晶体管M13中只有一个晶体管处于导通状态。这样可以避免晶体管长期导通引起的性能漂移。当第十二晶体管M12导通时第四电压可以对下拉节点QB进行充电，或者当第十三晶体管M13导通时第五电压可以对下拉节点QB进行充电，从而将下拉节点QB的电压上拉至高电平。当上拉节点Q的电压为高电平时，第十四晶体管M14导通。例如，在晶体管的设计上，可以将第十四晶体管M14与第十二晶体管M12(或第十三晶体管M13)配置为(例如对二者的尺寸比、阈值电压等配置)在M14和M12(M13)均导通时，下拉节点QB的电压可以被下拉至低电平，该低电平可以使得第九晶体管M9、第十晶体管M10以及第十一晶体管M11保持关断。
另一方面，当下拉节点QB的电压为高电平时，下拉电路500中的第九晶体管M9和第十晶体管M10导通，从而可以利用第一电压端VGL1对上拉节点Q和移位信号输出端CR进行下拉，以降低上拉节点Q和移位信号输出端CR的噪声。此外，当下拉节点QB的电压为高电平时，第十一晶体管M11也导通，从而可以利用第三电压端VGL2对像素信号输出端OUT进行下拉，以降低像素信号输出端OUT的噪声。
在示例中，第一电压和第三电压可以不同，例如第一电压设置为-10V，第三电压设置为-6V。在另一示例中，也可以不设置第三电压端VGL2，而将第十一晶体管M11的第二极和第一电压端VGL1耦接以接收第一电压，本公开的实施例对此不作限定。
如图6所示，第二下拉控制电路700可包括第十五晶体管M15和第十六晶体管M16。
第十五晶体管M15的栅极和第一时钟信号端CLKA耦接以接收第一时钟信号作为消隐下拉控制信号，第十五晶体管M15的第一极和下拉节点QB耦接，第十五晶体管M15的第二极和第一电压端VGL1耦接以接收第一电压。在实施例中，当第一时钟信号为高电平时，第十五晶体管M15导通，从而可以利用第一电压端VGL1对下拉节点QB进行下拉。采用这种 方式可以使得在一帧的消隐时段中，降低下拉节点QB对上拉节点Q的影响，使得消隐输入电路100对上拉节点Q的充电更充分。
第十六晶体管M16的栅极和显示输入信号端STU2耦接以接收显示输入信号作为显示下拉控制信号，第十六晶体管M16的第一极和下拉节点QB耦接，第十六晶体管M16的第二极和第一电压端VGL1耦接以接收第一电压。在实施例中，当显示输入信号为高电平时，第十六晶体管M16导通，从而可以利用第一电压端VGL1对下拉节点QB进行下拉。采用这种方式可以使得在一帧的显示时段中，降低下拉节点QB对上拉节点Q的影响，使得显示输入电路200对上拉节点Q的充电更充分。
如图6所示，复位电路800可包括第十七晶体管M17和第十八晶体管M18。
第十七晶体管M17的栅极和第二时钟信号端CLKB耦接以接收第二时钟信号并作为消隐复位信号，第十七晶体管M17的第一极和上拉节点Q耦接，第十七晶体管M17的第二极和第一电压端VGL1耦接以接收第一电压。例如，当第二时钟信号为高电平时，第十七晶体管M17导通，从而可以利用第一电压端VGL1对上拉节点Q进行复位。
第十八晶体管M18的栅极和显示复位信号端STD耦接以接收显示复位信号，第十八晶体管M18的第一极和上拉节点Q耦接，第十八晶体管M18的第二极和第一电压端VGL1耦接以接收第一电压。例如，当显示复位信号为高电平时，第十八晶体管M18导通，从而可以利用第一电压端VGL1对上拉节点Q进行复位。
此外，负载电容C L的一端耦接像素信号输出端，另一端接地。负载电阻R L的一端耦接像素信号输出端，另一端接地。
如前所述，在本公开的实施例提供的移位寄存器单元中，可以利用第一电容C1维持上拉控制节点H处的电压，利用第二电容C2维持上拉节点Q处的电压。第一电容C1、第二电容C2和负载电容中C L的至少一者可以是通过工艺制程制作的电容器件，例如通过制作专门的电容电极来实现电容器件，该电容的各个电极可以通过金属层、半导体层(例如掺杂多晶硅) 等实现。此外，第一电容C1、第二电容C2和负载电容C L中的至少一者也可以通过各个器件之间的寄生电容实现。此外，第一电容C1、第二电容C2和负载电容C L中的至少一者的连接方式不局限于上面描述的方式，也可以为其他适用的连接方式。
图7示出了根据本公开的实施例的移位寄存器单元的示例性电路图。移位寄存器单元例如是图5中所示的移位寄存器单元25，其中消隐输入电路100、显示输入电路200、输出电路300、第一控制电路400、下拉电路500、第一下拉控制电路600、第二下拉控制电路700、复位电路800、负载电容和负载电阻(未示出)的电路结构与图6中相应电路的电路结构相同，在此不再赘述。
如图7所示，第二控制电路420可包括第二晶体管M2。第二晶体管M2的栅极和第一时钟信号端CLKA耦接以接收所述第一时钟信号，第二晶体管M2的第一极和移位信号输出端CR耦接，第二晶体管的第二极和像素信号输出端OUT耦接。
本公开的实施例还提供了由移位寄存器单元构成的栅极驱动电路。
图8示出了根据本公开的实施例的栅极驱动电路的示意图。栅极驱动电路30可包括多个级联的移位寄存器单元，其中任意一个或多个移位寄存器单元可以采用本公开的实施例提供的移位寄存器单元10、移位寄存器单元15、移位寄存器单元20或移位寄存器单元25的结构或其变型。需要说明的是，图5中仅示意性的示出了栅极驱动电路30的前四级移位寄存器单元(A1、A2、A3和A4)。可以理解，栅极驱动电路中的移位寄存器单元是移位寄存器单元10和20的情况下，不具有显示复位信号端STD。
如图8所示，栅极驱动电路30还包括第一子时钟信号线CLK_1、第二子时钟信号线CLK_2、第三子时钟信号线CLK_3和第四子时钟信号线CLK_4。第一子时钟信号线向第4n-3级(例如，第1级、第5级、第9级等)移位寄存器单元提供第四时钟信号。第二子时钟信号线向第4n-2级(例如，第2级、第6级、第10级等)移位寄存器单元提供第四时钟信号。第三子时钟信号线向第4n-1级(例如，第3级、第7级、第11级等)移位 寄存器单元提供第四时钟信号。第四子时钟信号线向第4n级(例如，第4级、第8级、第12级等)移位寄存器单元提供第四时钟信号。在实施例中，第四时钟信号作为可输出信号。
在实施例中，如上所述，移位寄存器单元可包括第四时钟信号端CLKD。如图8所示，第4n-3级移位寄存器单元的第四时钟信号端CLKD和第一子时钟信号线CLK_1耦接，第4n-2级移位寄存器单元的第四时钟信号端CLKD和第二子时钟信号线CLK_2耦接，第4n-1级移位寄存器单元的第四时钟信号端CLKD和第三子时钟信号线CLK_3耦接，第4n级移位寄存器单元的第四时钟信号端CLKD和第四子时钟信号线CLK_4耦接。n为大于0的整数。
如图8所示，栅极驱动电路30还可以包括第五子时钟信号线CLK_5和第六子时钟信号线CLK_6。第五子时钟信号线向第2n-1级(例如，第1级、第3级、第5级等)移位寄存器单元提供第二时钟信号，以及向第2n级(例如，第2级、第4级、第8级等)移位寄存器单元提供第三时钟信号。第六子时钟信号线向第2n-1级移位寄存器单元提供第三时钟信号，以及向第2n级移位寄存器单元提供第二时钟信号。在实施例中，第三时钟信号可作为消隐上拉信号。
在实施例中，如上所述，移位寄存器单元可包括第二时钟信号端CLKB和第三时钟信号端CLKC。如图8所示，第2n-1级移位寄存器单元的第二时钟信号端CLKB和第五子时钟信号线CLK_5耦接，第三时钟信号端CLKC和第六子时钟信号线CLK_6耦接。第2n级移位寄存器单元的第二时钟信号端CLKB和第六子时钟信号线CLK_6耦接，第三时钟信号端CLKC和第五子时钟信号线CLK_5耦接。n为大于0的整数。
另外，栅极驱动电路30还可以包括第七子时钟信号线CLK_7，第七子时钟信号线向各级移位寄存器单元提供第一时钟信号。在实施例中，每一级移位寄存器单元的第一时钟信号端CLKA均和第七子时钟信号线CLK_7耦接。
在本公开的实施例中，第一级移位寄存器单元A1的消隐输入信号端 STU1和显示输入信号端STU2以及第二级移位寄存器单元A2的显示输入信号端STU2均和输入信号线STU(未示出)耦接，例如接收触发信号STV。
此外，第n级移位寄存器单元的移位信号输出端向第n+1级移位寄存器单元提供消隐输入信号。例如，第n+1级移位寄存器单元的消隐输入信号端STU1和第n级移位寄存器单元的移位信号输出端CR耦接。如图所示，第1级移位寄存器单元A1的移位信号输出端CR耦接第2级移位寄存器单元A2的消隐输入信号端STU1。第2级移位寄存器单元A2的移位信号输出端CR耦接第3级移位寄存器单元A3的消隐输入信号端STU1。第3级移位寄存器单元A3的移位信号输出端CR耦接第4级移位寄存器单元A4的消隐输入信号端STU1。
第n级移位寄存器单元的移位信号输出端向第n+2级移位寄存器单元提供显示输入信号。例如，第n+2级移位寄存器单元的显示输入信号端STU2和第n级移位寄存器单元的移位信号输出端CR耦接。如图所示，第1级移位寄存器单元A1的移位信号输出端CR耦接第3级移位寄存器单元A3的显示输入信号端STU2。第2级移位寄存器单元A2的移位信号输出端CR耦接第4级移位寄存器单元A4的显示输入信号端STU2。
第n+3级移位寄存器单元的移位信号输出端向第n级移位寄存器单元提供显示复位信号。例如，除了最后三级移位寄存器单元外，第n级移位寄存器单元的显示复位信号端STD和第n+3级移位寄存器单元的移位信号输出端CR耦接。n为大于0的整数。如图所示，第1级移位寄存器单元A1的显示复位信号端STD耦接第4级移位寄存器单元A4的移位信号输出端CR。在一些实施例中，最后三级移位寄存器单元的显示复位信号端STD可耦接虚设(dummy)移位寄存器单元的移位信号输出端，或者显示复位信号线STD(未示出)或分别连接其它适当的信号线。
可以理解，图8仅是示意性地示出各移位寄存器单元之间的连接关系，而非对其进行限定，还可存在其它未示出的适当连接。
以下结合图9详细描述图8所示的栅极驱动电路30的工作过程。
图9示出了图8所示的栅极驱动电路30的工作过程中各信号的时序图。 在图9中，Q<1>和Q<2>分别表示栅极驱动电路30中第一级移位寄存器单元A1和第二级移位寄存器单元A2中的上拉节点Q的电压。OUT<1>、OUT<2>、OUT<3>和OUT<4>分别表示栅极驱动电路30中的第一级移位寄存器单元A1、第二级移位寄存器单元A2、第三级移位寄存器单元A3以及第四级移位寄存器单元A4中相应的像素信号输出端OUT。1F、2F、3F和4F分别表示第一帧、第二帧、第三帧以及第四帧。Display表示一帧中的显示时段，Blank表示一帧中的消隐时段。需要说明的是，由于每一级移位寄存器单元中的移位信号输出端CR和像素信号输出端OUT的电压相同，所以在图9中未示出移位信号输出端CR。
可理解的是，图9所示的信号时序图中的信号电压只是示意性的，不代表真实电压值。此外，在示例中，第一电压VGL1是低电平，第二电压VDD是高电平，第三电压VGL2是低电平。
下面结合图9中的信号时序图，对图8中所示的栅极驱动电路30的工作过程进行说明。例如，图8中所示的栅极驱动电路30中的移位寄存器单元可以采用图5和图6中所示的移位寄存器单元。
在第一帧1F开始前，第五子时钟信号线CLK_5和第六子时钟信号线CLK_6均提供高电平。由于各级移位寄存器单元中的第二时钟信号端CLKB和第三时钟信号端CLKC交替与第五子时钟信号线CLK_5和第六子时钟信号线CLK_6连接，所以每一级移位寄存器单元中的第三晶体管M3和第十七晶体管M17均导通。此时，消隐输入信号端STU提供低电平。由此，可以对每一级移位寄存器单元中的上拉控制节点H和上拉节点Q进行复位，以实现全局复位。此时，上拉控制节点H和上拉节点Q的电压均为低电平。
然后，第一帧1F开始，第六子时钟信号线CLK_6提供的信号变为低电平，第五子时钟信号线CLK_5提供的信号继续保持高电平。
由于第五电压端VDD_B提供高电平，第十三晶体管M13导通，使得下拉节点QB被充电至高电平。下拉节点QB的高电平使得第九晶体管M9导通，从而将上拉节点Q下拉至低电平。
在第一帧1F的显示时段Display中，对第一级的移位寄存器单元A1的工作过程描述如下。
在第一阶段1中，第一级移位寄存器单元A1的消隐输入信号端STU1和显示输入信号端STU2均与输入信号线STU连接，因此消隐输入信号端STU1和显示输入信号端STU2均输入高电平。第六晶体管M6导通，第二电压端VDD的高电平信号可以通过第六晶体管M6对上拉节点Q<1>进行充电，使得上拉节点Q被上拉至高电平并被第二电容C2存储。开始时，由于第五子时钟信号线CLK_5输入高电平，与其连接的第二时钟信号端CLKB也为高电平，所以第三晶体管M3导通，上拉控制节点H<1>被充电至高电平并被第一电容C1存储。第十六晶体管M16由于显示输入信号端STU2的高电平而导通，从而可以对下拉节点QB进行辅助下拉。
然后，第五子时钟信号线CLK_5提供低电平，使得第二时钟信号端CLKB为低电平，第三晶体管M3关断。如上描述的，上拉节点Q<1>的电压为高电平，使得第七晶体管M7和第八晶体管M8导通。由于第一子时钟信号线CLK_1提供低电平信号，因此与其连接的第四时钟信号端CLKD为低电平信号。由此，移位信号输出端CR和像素信号输出端OUT均输出低电平信号。
在上拉节点Q<1>被写入高电平的瞬间，可通过第十四晶体管M14将下拉节点QB拉低为低电平，由此使得第十晶体管M10和第十一晶体管M11断开。此时，显示输入信号端STU2保持提供高电平，第一晶体管M1导通。将移位信号输出端CR耦接到像素信号输出端OUT。通过与像素信号输出端OUT耦接的负载电容C L和负载电阻R L对移位信号输出端CR处的电压进行降噪处理。由此，可使移位信号输出端CR的电压稳定，有效降低移位信号输出端CR的噪声。
在第二阶段2中，通过第一子时钟信号线CLK_1向第四时钟信号端CLKD提供高电平信号，使得上拉节点Q<1>的电压由于自举效应而进一步被拉高。第七晶体管M7和第八晶体管M8保持导通，从而移位信号输出端CR和像素信号输出端OUT均输出高电平信号。例如，从移位信号输出 端CR输出的高电平信号可以用于上下级移位寄存器单元的扫描移位，而从像素信号输出端OUT输出的高电平信号可以用于驱动显示面板中的子像素单元进行显示。
在第三阶段3中，通过第一子时钟信号线CLK_1向第四时钟信号端CLKD提供低电平信号，使得移位信号输出端CR和像素信号输出端OUT均可以通过第四时钟信号端CLKD放电，从而完成移位信号输出端CR和像素信号输出端OUT的复位。由于移位信号输出端CR和像素信号输出端OUT被复位至低电平，通过晶体管之间的耦合作用，上拉节点Q<1>的电压会下降一个幅度。此外，由于第一级移位寄存器单元A1的显示复位信号端STD和第四级移位寄存器单元的移位信号输出端CR连接，此时第四级移位寄存器单元的移位信号输出端CR还未输出高电平信号，所以不会对上拉节点Q<1>进行下拉，使得上拉节点Q<1>可以保持在一个较高的电平。
在第四阶段4中，第四级移位寄存器单元A4的移位信号输出端CR输出高电平，使得第一级移位寄存器单元A1的显示复位信号端STD也为高电平信号，第十八晶体管M18导通，上拉节点Q<1>被下拉至低电平，完成对上拉节点Q<1>的复位。
通过上述过程，第一级的上拉节点Q的电压变化呈现“塔状”。当移位信号输出端CR和像素信号输出端OUT处于高电平时，上拉节点Q的电压由于自举效应而升高。由此，移位信号输出端CR和像素信号输出端OUT在分别通过第七晶体管M7和第八晶体管M8放电时，流过晶体管的电流可以更大，放电速度更快。此外，由于移位信号输出端CR和像素信号输出端OUT处积累的电荷可以分别通过第七晶体管M7和第八晶体管M8进行放电，因此第八晶体管M8和第七晶体管M7可以采用尺寸较小的晶体管，以减小移位寄存器单元占用的版图面积。
在上述第一帧的显示时段中，由于第一时钟信号端CLKA(与第七子时钟信号线CLK_7连接)一直保持低电平，所以第五晶体管M5保持关断。第五晶体管M5可以隔离上拉控制节点H处预存的高电平对显示时段的上 拉节点Q的影响。
第一级移位寄存器单元驱动显示面板中第一行的子像素完成显示后，依次类推，第二级、第三级等移位寄存器单元逐行驱动显示面板中的子像素单元完成一帧的显示驱动。至此，第一帧的显示时段结束。
此外，显示复位信号线STD可以在每帧的显示时段Display向最后三级移位寄存器单元的显示服务信号端提供显示复位信号，以使得相应的第十八晶体管M18导通，从而拉低上拉节点Q。
在第一帧1F的消隐时段Blank中，对第一级移位寄存器单元A1的工作过程描述如下。
在第五阶段5中，上拉控制节点H由于第一电容C1的存储而保持显示时段的高电平。此时，第一时钟信号端CLKA(与第七子时钟信号线CLK_7连接)和第三时钟信号端CLKC(与第六子时钟信号线CLK_6连接)输入高电平信号，第四晶体管M4和第五晶体管M5导通。因此，第三时钟信号端CLKC的高电平可以对上拉节点Q<1>进行充电，将上拉节点Q<1>上拉至高电平。第十四晶体管M14在上拉节点Q<1>的控制下导通，使得下拉节点QB被下拉至低电平。第十五晶体管M15在第一时钟信号端CLKA的控制下也导通，可以进一步对下拉节点QB进行下拉。
在实施例中，在由于第一时钟信号端CLKA提供高电平，第二晶体管M2导通。由此，第二晶体管M2可将移位信号输出端CR耦接到像素信号输出端OUT，从而可通过与像素信号输出端OUT耦接的负载电容C L和负载电阻R L对移位信号输出端CR处的信号进行降噪处理。由此，可使移位信号输出端CR的电压稳定，有效降低移位信号输出端CR的噪声。
在第六阶段6中，第一时钟信号端CLKA输入低电平信号，第五晶体管M5关断。第四时钟信号端CLKD(与第一子时钟信号线CLK_1连接)输入高电平信号，上拉节点Q<1>的电压由于自举效应而进一步被拉高，第七晶体管M7和第八晶体管M8导通，第四时钟信号端CLKD输入的高电平信号可以输出至移位信号输出端CR和像素信号输出端OUT。
此外，由于第二级移位寄存器单元A2的第二时钟信号端CLKB与第六 子时钟信号线CLK_6连接，第二级移位寄存器单元A2的消隐输入信号端STU1与第一级移位寄存器单元A1的移位信号输出端CR连接，所以第二级移位寄存器单元A2中的第三晶体管M3导通，从而使得第二级移位寄存器单元A2中的上拉控制节点H<2>被上拉至高电平。
在第二级移位寄存器单元中的上拉控制节点H<2>被充分写入高电平后，在第七阶段7中，第六子时钟信号线CLK_6输入低电平信号。同时第一级移位寄存器单元A1的第四时钟信号端CLKD(与第一子时钟信号线CLK_1连接)持续输入高电平，所以移位信号输出端CR和像素信号输出端OUT保持输出高电平信号。在此过程中，第一时钟信号端CLKA(与第七子时钟信号线CLK_7连接)处于低电平，第五晶体管M5保持关断状态，所以可以避免上拉节点Q<1>通过第五晶体管M5漏电。
在第八阶段8中，第五子时钟信号线CLK_5输入高电平信号，由于奇数级的移位寄存器单元的第二时钟信号端CLKB均和第五子时钟信号线CLK_5连接，所以可以完成对所有奇数级移位寄存器单元中的上拉控制节点H和上拉节点Q的复位。
如图9所示，在第二帧2F的显示时段Display中，栅极驱动电路30重复和第一帧的显示时段相同的操作，这里不再赘述。
在第二帧2F的消隐时段Blank中，对于第二级移位寄存器单元A2，第三时钟信号端CLKC与第五子时钟信号线CLK_5连接。在消隐时段开始时，第二级移位寄存器单元A2的第一时钟信号端CLKA和第三时钟信号端CLKC均输入高电平信号，第四晶体管M4和第五晶体管M5导通。第三时钟信号端CLKC输入的高电平可以对上拉节点Q<2>进行充电，将上拉节点Q<2>上拉至高电平。然后在第二子时钟信号线CLK_2输入高电平信号时，移位信号输出端CR和像素信号输出端OUT输出高电平信号，同时对第三级移位寄存器单元中的上拉控制节点H<3>进行充电。在第二帧消隐时段的最后阶段，第六子时钟信号线CLK_6输入高电平信号。由于偶数级的移位寄存器单元的第二时钟信号端CLKB均和第六子时钟信号线CLK_6连接，所以可以完成对所有偶数级移位寄存器单元中的上拉控制节 点H和上拉节点Q的复位。
然后，在第三帧、第四帧、第五帧等更多阶段中对栅极驱动电路的驱动可以参考上述描述，这里不再赘述。
如上所述，在每一帧的消隐时段，栅极驱动电路输出的消隐输出信号可用于驱动显示面板中子像素单元中的感测晶体管。如图所示，该驱动信号是逐行顺序提供的。例如，在第一帧的消隐时段，栅极驱动电路输出用于显示面板第一行子像素单元的驱动信号。在第二帧的消隐时段，栅极驱动电路输出用于显示面板第二行子像素单元的驱动信号，依次类推，完成逐行顺序补偿。
另一方面，本公开的实施例还提供显示装置。显示装置可包括根据本公开实施例的栅极驱动电路30。在实施例中，显示装置可以为液晶面板、液晶电视、显示器、OLED面板、OLED电视、电子纸显示装置、手机、平板电脑、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
此外，本公开的实施例还提供了用于驱动移位寄存器单元和栅极驱动电路的方法。
图10示出了根据本公开的实施例的用于驱动移位寄存器单元的方法的示意性流程图。移位寄存器单元可以是基于本公开实施例的任何可适用的移位寄存器单元，例如移位寄存器单元10、移位寄存器单元15、移位寄存器单元20和移位寄存器单元25中的至少一个。
如图10所示，在方法中，在步骤910，消隐输入电路100可响应于第二时钟信号将消隐输入信号提供到上拉控制节点H。在实施例中，消隐输入电路100可存储上拉控制节点H的电压。
在步骤920，显示输入电路200可响应于显示输入信号将显示上拉信号提供到上拉节点Q。在显示输入信号的控制下，第一控制电路400可将移位信号输出端CR耦接到像素信号输出端OUT。由此，可通过与像素信号输出端OUT耦接的负载电容C L和负载电阻R L对移位信号输出端CR的电压进行降噪处理，从而使移位信号输出端CR的电压稳定，有效降低移位 信号输出端CR的噪声。
在步骤930，输出电路300可在上拉节点Q的电压的控制下输出显示输出信号。例如，显示输出信号可以用于驱动显示面板中的子像素单元进行显示。
在实施例中，步骤920和步骤930可在一帧的显示时段期间进行。
在步骤940，消隐输入电路100可在上拉控制节点H的电压和第一时钟信号的控制下将消隐上拉信号提供到上拉节点Q。
在实施例中，第二控制电路420可在第一时钟信号的控制下，将移位信号输出端CR耦接到像素信号输出端OUT。由此，可通过与像素信号输出端OUT耦接的负载电容C L和负载电阻R L对移位信号输出端CR处的电压进行降噪处理，从而使移位信号输出端CR的电压稳定，有效降低移位信号输出端CR的噪声。
在步骤950，输出电路300可在上拉节点Q的电压的控制下输出消隐输出信号。例如，消隐输出信号可以用于驱动显示面板中的子像素单元进行外部补偿。
在实施例中，步骤910可在一帧的消隐时段期间进行，步骤940和步骤950可在下一帧的消隐时段期间进行。此外，在其它实施例中，例如对于栅极驱动电路中的第一级移位寄存器单元，步骤910可在一帧的显示时段期间进行，940和950可在同一帧的消隐时段期间进行。
本领域技术人员可以理解，以上各步骤虽然按顺序描述，但并不构成对方法顺序的限定，本公开实施例也可以以任何其它合适顺序实施。
以上对本公开的若干实施方式进行了详细描述，但本公开的保护范围并不限于此。显然，对于本领域的普通技术人员来说，在不脱离本公开的精神和范围的情况下，可以对本公开的实施例进行各种修改、替换或变形。本公开的保护范围由所附权利要求限定。

Claims (21)

  1. 一种移位寄存器单元，包括消隐输入电路、显示输入电路、输出电路和第一控制电路；
    其中，所述消隐输入电路被配置为将消隐输入信号提供到上拉控制节点以及将消隐上拉信号提供到上拉节点；
    所述显示输入电路被配置为根据显示输入信号将显示上拉信号提供到所述上拉节点；
    所述输出电路被配置为在所述上拉节点的电压的控制下，将输出信号提供至移位信号输出端和像素信号输出端；
    所述第一控制电路被配置为根据所述显示输入信号将所述移位信号输出端耦接到所述像素信号输出端。
  2. 根据权利要求1所述的移位寄存器单元，其中，所述第一控制电路包括第一晶体管；
    所述第一晶体管的控制极和显示输入信号端耦接以接收所述显示输入信号，所述第一晶体管的第一极和所述移位信号输出端耦接，所述第一晶体管的第二极和所述像素信号输出端耦接。
  3. 根据权利要求1或2所述的移位寄存器单元，其中，所述移位寄存器单元还包括第二控制电路；
    其中，所述第二控制电路被配置为在第一时钟信号的控制下，将所述移位信号输出端耦接到所述像素信号输出端。
  4. 根据权利要求3所述的移位寄存器单元，其中，所述第二控制电路包括第二晶体管；
    所述第二晶体管的控制极和第一时钟信号端耦接以接收所述第一时钟信号，所述第二晶体管的第一极和所述移位信号输出端耦接，所述第二晶体管的第二极和所述像素信号输出端耦接。
  5. 根据权利要求1所述的移位寄存器单元，其中，所述消隐输入电路包括：
    充电子电路，被配置为根据第二时钟信号将所述消隐输入信号提供到所述上拉控制节点；
    存储子电路，被配置为存储所述充电子电路提供的所述消隐输入信号；
    隔离子电路，被配置为在所述上拉控制节点的电压和第一时钟信号的控制下，将所述消隐上拉信号提供到所述上拉节点。
  6. 根据权利要求5所述的移位寄存器单元，其中，
    所述充电子电路包括第三晶体管，所述第三晶体管的控制极和第二时钟信号端耦接以接收所述第二时钟信号，所述第三晶体管的第一极和消隐输入信号端耦接以接收所述消隐输入信号，所述第三晶体管的第二极和所述上拉控制节点耦接；
    所述存储子电路包括第一电容，所述第一电容的第一极和所述上拉控制节点耦接，所述第一电容的第二极和第一电压端耦接以接收第一电压；
    所述隔离子电路包括第四晶体管和第五晶体管，所述第四晶体管的控制极和所述上拉控制节点耦接，所述第四晶体管的第一极和第三时钟信号端耦接以接收第三时钟信号作为所述消隐上拉信号，所述第四晶体管的第二极和所述第五晶体管的第一极耦接，所述第五晶体管的控制极和第一时钟信号端耦接以接收所述第一时钟信号，所述第五晶体管的第二极和所述上拉节点耦接。
  7. 根据权利要求1至6中任一项所述的移位寄存器单元，其中，所述显示输入电路包括第六晶体管；
    所述第六晶体管的控制极和显示输入信号端耦接以接收所述显示输入信号，所述第六晶体管的第一极和第二电压端耦接以接收第二电压作为所述显示上拉信号，所述第六晶体管的第二极和所述上拉节点耦接。
  8. 根据权利要求1至7中任一项所述的移位寄存器单元，其中，所述输出电路包括第七晶体管、第八晶体管和第二电容；
    所述第七晶体管的控制极和所述上拉节点耦接，所述第七晶体管的第一极和第四时钟信号端耦接以接收第四时钟信号作为所述输出信号，所述第七晶体管的第二极和所述移位信号输出端耦接；
    所述第八晶体管的控制极和所述上拉节点耦接，所述第八晶体管的第一极和所述第四时钟信号端耦接以接收所述第四时钟信号作为所述输出信号，所述第八晶体管的第二极和所述像素信号输出端耦接；
    所述第二电容的第一极和所述上拉节点耦接，所述第二电容的第二极和所述第七晶体管的第二极耦接。
  9. 根据权利要求1至8中任一项所述的移位寄存器单元，还包括下拉电路、第一下拉控制电路、第二下拉控制电路和复位电路；其中，
    所述下拉电路被配置为在下拉节点的电压的控制下，对所述上拉节点、所述移位信号输出端和所述像素信号输出端进行降噪；
    所述第一下拉控制电路被配置为在所述上拉节点的电压的控制下，对所述下拉节点的电压进行控制；
    所述第二下拉控制电路被配置为在消隐下拉控制信号和显示下拉控制信号的控制下，对所述下拉节点的电压进行控制；
    所述复位电路被配置为在消隐复位信号和显示复位信号的控制下对所述上拉节点进行复位。
  10. 根据权利要求9所述的移位寄存器单元，其中，所述下拉电路包括包括第九晶体管、第十晶体管和第十一晶体管；
    所述第九晶体管的控制极和所述下拉节点耦接，所述第九晶体管的第一极和所述上拉节点耦接，所述第九晶体管的第二极和第一电压端耦接以接收第一电压；
    所述第十晶体管的控制极和所述下拉节点耦接，所述第十晶体管的第一极和所述移位信号输出端耦接，所述第十晶体管的第二极和所述第一电压端耦接以接收所述第一电压；
    所述第十一晶体管的控制极和所述下拉节点耦接，所述第十一晶体管的第一极和所述像素信号输出端耦接，所述第十一晶体管的第二极和第三电压端耦接以接收第三电压。
  11. 根据权利要求9或10所述的移位寄存器单元，其中，所述第一下拉控制电路包括第十二晶体管、第十三晶体管和第十四晶体管；
    所述第十二晶体管的控制极和第一极与第四电压端耦接以接收第四电压，所述第十二晶体管的第二极和所述下拉节点耦接；
    所述第十三晶体管的控制极和第一极与第五电压端耦接以接收第五电压，所述第十三晶体管的第二极和所述下拉节点耦接；
    所述第十四晶体管的控制极和所述上拉节点耦接，所述第十四晶体管的第一极和所述下拉节点耦接，所述第十四晶体管的第二极和第一电压端耦接以接收第一电压。
  12. 根据权利要求9至11中任一项所述的移位寄存器单元，其中，所述第二下拉控制电路包括第十五晶体管和第十六晶体管；
    所述第十五晶体管的控制极和第一时钟信号端耦接以接收所述第一时钟信号作为所述消隐下拉控制信号，所述第十五晶体管的第一极和所述下拉节点耦接，所述第十五晶体管的第二极和第一电压端耦接以接收第一电压；
    所述第十六晶体管的控制极和显示输入信号端耦接以接收所述显示输入信号作为所述显示下拉控制信号，所述第十六晶体管的第一极和所述下拉节点耦接，所述第十六晶体管的第二极和第一电压端耦接以接收第一电压。
  13. 根据权利要求9至12中任一项所述的移位寄存器单元，其中，所述复位电路包括第十七晶体管和第十八晶体管；
    所述第十七晶体管的控制极和第二时钟信号端耦接以接收第二时钟信号并作为所述消隐复位信号，所述第十七晶体管的第一极和所述上拉节点耦接，所述第十七晶体管的第二极和第一电压端耦接以接收第一电压。
    所述第十八晶体管的控制极和显示复位信号端耦接以接收所述显示复位信号，所述第十八晶体管的第一极和所述上拉节点耦接，所述第十八晶体管的第二极和第一电压端耦接以接收第一电压。
  14. 根据权利要求1至8中任一项所述的移位寄存器单元，还包括负载电容和负载电阻；
    其中，所述负载电容的一端耦接所述像素信号输出端，另一端接地；
    所述负载电阻的一端耦接所述像素信号输出端，另一端接地。
  15. 一种栅极驱动电路，包括多个级联的如权利要求1至14中任一项所述的移位寄存器单元；
    其中，第n级移位寄存器单元的移位信号输出端向第n+1级移位寄存器单元提供消隐输入信号；以及
    第n级移位寄存器单元的移位信号输出端向第n+2级移位寄存器单元提供显示输入信号；
    n为大于0的整数。
  16. 根据权利要求15所述的栅极驱动电路，还包括第一子时钟信号线、第二子时钟信号线、第三子时钟信号线和第四子时钟信号线；其中，
    所述第一子时钟信号线向第4n-3级移位寄存器单元提供第四时钟信号作为输出信号；
    所述第二子时钟信号线向第4n-2级移位寄存器单元提供第四时钟信号作为输出信号；
    所述第三子时钟信号线向第4n-1级移位寄存器单元提供第四时钟信号作为输出信号；
    所述第四子时钟信号线向第4n级移位寄存器单元提供第四时钟信号作为输出信号。
  17. 根据权利要求16所述的栅极驱动电路，还包括第五子时钟信号线、第六子时钟信号线和第七子时钟信号线；其中，
    所述第五子时钟信号线向第2n-1级移位寄存器单元提供第二时钟信号，以及向第2n级移位寄存器单元提供第三时钟信号作为消隐上拉信号；
    所述第六子时钟信号线向第2n-1级移位寄存器单元提供第三时钟信号作为消隐上拉信号，以及向第2n级移位寄存器单元提供第二时钟信号；
    所述第七子时钟信号线向各级移位寄存器单元提供第一时钟信号。
  18. 根据权利要求15至17中任一项所述的栅极驱动电路，其中，
    第n+3级移位寄存器单元的移位信号输出端向第n级移位寄存器单元提供显示复位信号。
  19. 一种显示装置，包括如权利要求15至18中任一项所述的栅极驱动电路。
  20. 一种用于驱动如权利要求1至14中任一项所述的移位寄存器单元的方法，包括：
    消隐输入电路将消隐输入信号提供到上拉控制节点；
    显示输入电路响应于显示输入信号将显示上拉信号提供到上拉节点，其中，在所述显示输入信号的控制下，第一控制电路将移位信号输出端耦接到像素信号输出端；
    输出电路在所述上拉节点的电压的控制下输出显示输出信号；
    消隐输入电路在所述上拉控制节点的电压和第一时钟信号的控制下将消隐上拉信号提供到所述上拉节点；以及
    所述输出电路在所述上拉节点的电压的控制下输出消隐输出信号。
  21. 根据权利要求20所述的方法，其中，所述移位寄存器单元进一步包括第二控制电路，所述第二控制电路被配置为在第一时钟信号的控制下，将所述移位信号输出端耦接到所述像素信号输出端；其中，所述方法进一步包括：
    第二控制电路在第一时钟信号的控制下将所述移位信号输出端耦接到所述像素信号输出端。
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