WO2020142923A1 - 移位寄存器及其驱动方法、栅极驱动电路和显示装置 - Google Patents

移位寄存器及其驱动方法、栅极驱动电路和显示装置 Download PDF

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Publication number
WO2020142923A1
WO2020142923A1 PCT/CN2019/070966 CN2019070966W WO2020142923A1 WO 2020142923 A1 WO2020142923 A1 WO 2020142923A1 CN 2019070966 W CN2019070966 W CN 2019070966W WO 2020142923 A1 WO2020142923 A1 WO 2020142923A1
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WIPO (PCT)
Prior art keywords
transistor
coupled
pull
node
electrode
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PCT/CN2019/070966
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English (en)
French (fr)
Inventor
冯雪欢
李永谦
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to JP2020558455A priority Critical patent/JP7395503B2/ja
Priority to US16/645,733 priority patent/US11302257B2/en
Priority to EP19856464.3A priority patent/EP3910639A4/en
Priority to CN201980000039.4A priority patent/CN111684528B/zh
Priority to PCT/CN2019/070966 priority patent/WO2020142923A1/zh
Priority to CN202210593799.4A priority patent/CN115064127A/zh
Publication of WO2020142923A1 publication Critical patent/WO2020142923A1/zh
Priority to JP2023200958A priority patent/JP2024020569A/ja

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a shift register and a driving method thereof, a gate driving circuit, and a display device.
  • OLED Organic Light Emitting Diode
  • the array substrate row drive (Gate Driver On Array, GOA for short) technology is generally used to integrate the gate drive circuit of the thin film transistor (TFT) on the array substrate of the display panel to form Scan driver for the display panel.
  • This gate drive circuit integrated on the array substrate using GOA technology is also called a GOA unit or a shift register.
  • the display device adopting the GOA circuit can reduce the cost from both the material cost and the manufacturing process because the part of the binding drive circuit is omitted.
  • the embodiments of the present disclosure provide a shift register and a driving method thereof, a gate driving circuit, and a display device.
  • a shift register may include a blanking input circuit, a blanking control circuit, a blanking pull-down circuit, and a shift register circuit.
  • the blanking input circuit may provide the blanking input signal from the blanking input signal terminal to the first control node according to the second clock signal from the second clock signal terminal.
  • the blanking control circuit may provide the first clock signal from the first clock signal terminal to the second control node according to the voltage of the first control node, and maintain the voltage difference between the first control node and the second control node.
  • the blanking pull-down circuit may provide the voltage of the second control node to the pull-down node according to the first clock signal.
  • the shift register circuit is configured to provide a shift signal via the shift signal output terminal according to the voltage of the pull-down node, and provide a first drive signal via the first drive signal output terminal.
  • the blanking control circuit may include a second transistor and a first capacitor.
  • the control electrode of the second transistor is coupled to the first control node
  • the first electrode of the second transistor is coupled to the first clock signal terminal
  • the second electrode of the second transistor is coupled to the second control node.
  • the first capacitor is coupled between the first control node and the second control node.
  • the blanking input circuit may include a first transistor.
  • the control electrode of the first transistor is coupled to the second clock signal terminal, the first electrode of the first transistor is coupled to the blanking input signal terminal, and the second electrode of the first transistor is coupled to the first control node.
  • the blanking pull-down circuit may include a third transistor.
  • the control electrode of the third transistor is coupled to the first clock signal terminal, the first electrode of the third transistor is coupled to the second control node, and the second electrode of the third transistor is coupled to the pull-down node.
  • the shift register may further include a display input circuit and an output circuit.
  • the display input circuit may provide the first voltage from the first voltage terminal to the pull-down node according to the display input signal from the display input signal terminal.
  • the output circuit may output the shift signal from the shift signal output terminal according to the voltage of the pull-down node, and output the first drive signal from the first drive signal output terminal.
  • the display input circuit may include a fourth transistor.
  • the control electrode of the fourth transistor is coupled to the display input signal terminal, the first electrode of the fourth transistor is coupled to the first voltage terminal, and the second electrode of the fourth transistor is coupled to the pull-down node.
  • the output circuit may include a nineteenth transistor, a twenty-second transistor, and a second capacitor.
  • the control electrode of the nineteenth transistor is coupled to the pull-down node, the first electrode of the nineteenth transistor and the fourth clock signal terminal are coupled to receive the fourth clock signal, the second electrode of the nineteenth transistor and the output terminal of the shift signal Coupling.
  • the control electrode of the twenty-second transistor is coupled to the pull-down node, the first electrode of the twenty-second transistor is coupled to the fourth clock signal terminal to receive the fourth clock signal, and the second electrode of the twenty-second transistor is coupled to the first The driving signal output terminal is coupled.
  • the second capacitor is coupled between the pull-down node and the shift signal output terminal.
  • the shift register circuit may further include a first control circuit, a pull-up circuit, and a second control circuit.
  • the first control circuit may control the voltage of the pull-up node according to the voltage of the pull-down node.
  • the pull-up circuit may provide the second voltage from the second voltage terminal to the pull-down node, the shift signal output terminal, and the drive signal output terminal according to the voltage of the pull-up node.
  • the second control circuit may control the voltage of the pull-up node according to the first clock signal and the voltage of the first control node, and control the voltage of the pull-up node according to the display input signal.
  • the pull-up node may include a first pull-up node.
  • the first control circuit may include a seventh transistor and an eighth transistor.
  • the control electrode of the seventh transistor is coupled to the first electrode and the third voltage terminal, and the second electrode of the seventh transistor is coupled to the first pull-up node.
  • the control electrode of the eighth transistor is coupled to the pull-down node, the first electrode of the eighth transistor is coupled to the first pull-up node, and the second electrode of the eighth transistor is coupled to the second voltage terminal.
  • the pull-up circuit may include a ninth transistor, a twentieth transistor, and a twenty-third transistor.
  • the control electrode of the ninth transistor is coupled to the first pull-up node, the first electrode of the ninth transistor is coupled to the pull-down node, and the second electrode of the ninth transistor is coupled to the second voltage terminal.
  • the control electrode of the twentieth transistor is coupled to the first pull-up node, the first electrode of the twentieth transistor is coupled to the shift signal output terminal, and the second electrode of the twentieth transistor is coupled to the second voltage terminal.
  • the control electrode of the twenty-third transistor is coupled to the first pull-up node, the first electrode of the twenty-third transistor is coupled to the first drive signal output terminal, and the second electrode and the second voltage terminal of the twenty-third transistor Coupling.
  • the second control circuit may include a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor.
  • the control electrode of the thirteenth transistor is coupled to the first clock signal terminal, and the first electrode of the thirteenth transistor is coupled to the first pull-up node.
  • the control electrode of the fourteenth transistor is coupled to the first control node, the first electrode of the fourteenth transistor is coupled to the second electrode of the thirteenth transistor, and the second electrode of the fourteenth transistor is coupled to the second voltage terminal .
  • the control electrode of the fifteenth transistor is coupled to the display input signal terminal, the first electrode of the fifteenth transistor is coupled to the first pull-up node, and the second electrode of the fifteenth transistor is coupled to the second voltage terminal.
  • the pull-up node may further include a second pull-up node.
  • the first control circuit also includes a tenth transistor and an eleventh transistor.
  • the control electrode of the tenth transistor is coupled to the first electrode and the fourth voltage terminal, and the second electrode of the tenth transistor is coupled to the second pull-up node.
  • the control electrode of the eleventh transistor is coupled to the pull-down node, the first electrode of the eleventh transistor is coupled to the second pull-up node, and the second electrode of the eleventh transistor is coupled to the second voltage terminal.
  • the pull-up circuit may further include a twelfth transistor, a twenty-first transistor, and a twenty-fourth transistor.
  • the control electrode of the twelfth transistor is coupled to the second pull-up node, the first electrode of the twelfth transistor is coupled to the pull-down node, and the second electrode of the twelfth transistor is coupled to the second voltage terminal.
  • the control electrode of the twenty-first transistor is coupled to the second pull-up node, the first electrode of the twenty-first transistor is coupled to the output terminal of the shift signal, and the second electrode of the twenty-first transistor is coupled to the second voltage terminal .
  • the control pole of the twenty-fourth transistor is coupled to the second pull-up node, the first pole of the twenty-fourth transistor is coupled to the first drive signal output terminal, and the second pole of the twenty-fourth transistor is coupled to the second voltage terminal Coupling.
  • the second control circuit may further include a sixteenth transistor, a seventeenth transistor, and an eighteenth transistor.
  • the control electrode of the sixteenth transistor is coupled to the first clock signal terminal, and the first electrode of the sixteenth transistor is coupled to the second pull-up node.
  • the control electrode of the seventeenth transistor is coupled to the first control node, the first electrode of the seventeenth transistor is coupled to the second electrode of the sixteenth transistor, and the second electrode of the seventeenth transistor is coupled to the second voltage terminal .
  • the control electrode of the eighteenth transistor is coupled to the display input signal terminal, the first electrode of the eighteenth transistor is coupled to the second pull-up node, and the second electrode of the eighteenth transistor is coupled to the second voltage terminal.
  • the reset circuit may include a fifth transistor and a sixth transistor.
  • the control electrode of the fifth transistor is coupled to the blanking reset signal terminal, the first electrode of the fifth transistor is coupled to the pull-down node, and the second electrode of the fifth transistor is coupled to the second voltage terminal.
  • the control electrode of the sixth transistor is coupled to the display reset signal terminal, the first electrode of the sixth transistor is coupled to the pull-down node, and the second electrode of the sixth transistor is coupled to the second voltage terminal.
  • the output circuit may further include a twenty-fifth transistor and a third capacitor.
  • the control electrode of the twenty-fifth transistor is coupled to the pull-down node
  • the first electrode of the twenty-fifth transistor and the fifth clock signal terminal are coupled to receive the fifth clock signal
  • the second electrode of the twenty-fifth transistor and the second The driving signal output terminal is coupled.
  • the third capacitor is coupled between the pull-down node and the second driving signal output terminal.
  • the pull-up circuit may further include a twenty-sixth transistor and a twenty-seventh transistor.
  • the control electrode of the twenty-sixth transistor is coupled to the first pull-up node, the first electrode of the twenty-sixth transistor is coupled to the second drive signal output terminal, and the second electrode and the second voltage terminal of the twenty-sixth transistor Coupling.
  • the control pole of the twenty-seventh transistor is coupled to the second pull-up node, the first pole of the twenty-seventh transistor is coupled to the second drive signal output terminal, and the second pole of the twenty-seventh transistor is coupled to the second voltage terminal Coupling.
  • a gate driving circuit may include N cascaded shift registers as provided in the first aspect of the present disclosure, a first sub-clock signal line and a second sub-clock signal line.
  • the blanking input signal terminal of the i+1th-stage shift register is coupled to the shift signal output terminal of the i-th stage shift register.
  • the first clock signal terminal of the shift register at each level is coupled to the first sub-clock signal line.
  • the second clock signal terminal of the shift register at each level is coupled to the second sub-clock signal line.
  • the gate driving circuit may further include a blanking reset signal line, a first sub-clock signal line, and a second sub-clock signal line.
  • the display input signal terminal of the i+2th stage shift register is coupled to the shift signal output terminal of the ith stage shift register.
  • the blanking reset signal terminal of each level of shift register is coupled to the blanking reset signal line.
  • the display reset signal terminal of the i-th shift register is coupled to the shift signal output terminal of the i+3th shift register.
  • the gate driving circuit may further include a seventh sub-clock signal line, an eighth sub-clock signal line, a ninth sub-clock signal line, and a tenth sub-clock signal line.
  • the fifth clock signal terminal of the 4i-3 stage shift register is coupled to the seventh sub-clock signal line.
  • the fifth clock signal terminal of the 4i-2th stage shift register is coupled to the eighth subclock signal line.
  • the fifth clock signal terminal of the shift register of the 4i-1th stage is coupled to the ninth sub-clock signal line.
  • the fifth clock signal terminal of the shift register of the 4ith stage is coupled to the tenth sub-clock signal line.
  • a display device includes the gate driving circuit provided according to the second aspect of the present disclosure.
  • FIG. 1 shows a schematic block diagram of a shift register according to an embodiment of the present disclosure
  • FIG. 2 shows a schematic block diagram of a shift register according to an embodiment of the present disclosure
  • FIG. 3 shows an exemplary circuit diagram of a shift register according to an embodiment of the present disclosure
  • FIG. 6 shows an exemplary circuit diagram of a shift register according to another embodiment of the present disclosure.
  • FIG. 7 shows a schematic diagram of a gate driving circuit according to an embodiment of the present disclosure
  • FIG. 8 shows a timing diagram of signals during operation of the gate driving circuit according to an embodiment of the present disclosure.
  • FIG. 9 shows a schematic flowchart of a method for driving a shift register according to an embodiment of the present disclosure.
  • the gate drive circuit In the display field, especially in organic light-emitting diode OLED display technology, the gate drive circuit is usually integrated in an integrated circuit IC.
  • the area of the chip in the IC design is the main factor affecting the cost of the chip.
  • the gate drive circuit includes a detection circuit, a display circuit, and a connection circuit (or gate circuit) that outputs a composite pulse of both. This type of circuit structure is very complicated, and it is difficult to meet the requirements of high resolution and narrow border.
  • the gate drive circuit formed by the shift register needs to provide drive signals for the scan transistor and the sense transistor to the sub-pixels in the display panel, respectively.
  • a scan driving signal for scanning transistors is provided in a display period (Display) of one frame
  • a sensing driving signal for sensing transistors is provided in a blanking period (Blank) of one frame.
  • “one frame”, “each frame”, or “a certain frame” includes a display period and a blanking period that are sequentially performed.
  • the gate drive circuit outputs a display output signal, which can be used to drive the scan transistors in the display panel to scan from the first row to the last row, so that the display panel performs display.
  • the gate driving circuit outputs a blanking output signal, which can be used to drive a sensing transistor in a row of sub-pixels in the display panel to sense the driving current of the row of sub-pixels, based on The sensed drive current is compensated. .
  • the embodiments of the present disclosure provide a shift register and a driving method thereof, a gate driving circuit, and a display device.
  • the embodiments and examples of the present disclosure will be described in detail below with reference to the drawings.
  • FIG. 1 shows a schematic block diagram of a shift register according to an embodiment of the present disclosure.
  • the shift register 10 may include a blanking input circuit 100, a blanking control circuit 200, a blanking pull-down circuit 300, and a shift register circuit 1000.
  • the blanking input circuit 100 may provide the blanking input signal STU1 from the blanking input signal terminal to the first control node H according to the second clock signal CLKB from the second clock signal terminal to control the first Control the voltage of node H.
  • the blanking input circuit 100 may be coupled to the second clock signal terminal to receive the second clock signal CLKB, and to the blanking input signal terminal to receive the blanking input signal STU1.
  • the blanking pull-down circuit 300 may provide the voltage of the second control node N to the pull-down node Q according to the first clock signal CLKA to control the voltage of the pull-down node Q.
  • the blanking pull-down circuit 300 may be coupled to the first clock signal terminal to receive the first clock signal CLKA.
  • the blanking control circuit 200 can maintain the voltage difference between the first control node H and the second control node N, when the voltage of the second control node N changes, the voltage of the first control node H also corresponds The ground clock is changed so that the first clock signal CLKA can be supplied to the second control node N without loss.
  • the blanking pull-down circuit 300 may provide the first clock signal CLKA (ie, the voltage of the second control node N) to the pull-down node Q without loss. Thereby, the threshold voltage loss of the transistor when the pull-down node Q is written to a low potential during the blanking period can be eliminated.
  • the blanking control circuit 200 and the blanking pull-down circuit 300 are provided between the first control node H and the pull-down node Q, it is possible to prevent the voltages of the first control node H and the second control node N from the voltage of the pull-down node Q Make an impact.
  • the shift register circuit 1000 can provide a shift signal through the shift signal output terminal and a first drive signal through the first drive signal output terminal under the control of the pull-down node Q.
  • the shift signal can be used for scanning shift of the upper and lower shift register units, for example.
  • the driving signal may be used to drive the scanning transistor in the display panel to drive the display panel for display.
  • the shift signal can also be used for scanning shift of the upper and lower shift register units, for example.
  • the driving signal may be used to drive the sensing transistors in the sub-pixels in the display panel to perform external compensation of the sub-pixels in the row.
  • FIG. 2 shows a schematic block diagram of a shift register according to another embodiment of the present disclosure.
  • the shift register 20 may include a blanking input circuit 100, a blanking control circuit 200, a blanking pull-down circuit 300, and a shift register circuit 1000.
  • the shift register circuit 1000 may include a display input circuit 400 and an output circuit 500.
  • the shift register circuit 1000 may further include a first control circuit 600, a pull-up circuit 700, and a second control circuit 800.
  • the shift register circuit 1000 may further include a reset circuit 900.
  • the shift register circuit 1000 includes a display input circuit 400, an output circuit 500, a first control circuit 600, a pull-up circuit 700, a second control circuit 800, and a reset circuit 900.
  • the blanking input circuit 100, the blanking control circuit 200, and the blanking pull-down circuit 300 have been described in detail above, and will not be repeated here. The following mainly describes each partial circuit in the shift register circuit 1000.
  • the display input circuit 400 may provide the first voltage V1 from the first voltage terminal to the pull-down node Q according to the display input signal STU2 from the display input signal terminal to control the voltage of the pull-down node Q.
  • the display input circuit 400 may be coupled to the display input signal terminal to receive the display input signal STU2 and coupled to the first voltage terminal to receive the first voltage V1.
  • the first voltage terminal may provide a DC low-level signal, that is, the first voltage V1 is a low level.
  • the output circuit 500 may output a shift signal from the shift signal output terminal CR according to the voltage of the pull-down node Q, and output a first drive signal from the first drive signal output terminal OUT1.
  • the output circuit 500 may be coupled to the fourth clock signal terminal to receive the fourth clock signal CLKD.
  • the output circuit 500 may provide the fourth clock signal CLKD to the shift signal output terminal CR according to the voltage of the pull-down node Q to output the fourth clock signal CLKD as the shift signal, and provide the fourth clock signal CLKD to the first driving signal
  • the output terminal OUT1 outputs the fourth clock signal CLKD as the first driving signal.
  • the output circuit 500 may also output the second driving signal from the second driving signal output terminal OUT2 according to the voltage of the pull-down node Q.
  • the output circuit 500 may be coupled to the fifth clock signal terminal to receive the fifth clock signal CLKE.
  • the output circuit 500 may also provide the fifth clock signal CLKE to the second driving signal output terminal OUT2 according to the voltage of the pull-down node Q to output the fifth clock signal CLKE as the second output signal.
  • the number of driving signal output terminals is not limited to two, and may be more than two.
  • the output circuit may output a corresponding driving signal according to a corresponding clock signal.
  • the shift signal and the corresponding driving signal may also be collectively referred to as the display output signal
  • the blanking output signal the shift signal and the corresponding driving signal may also be collectively referred to as the blanking output signal.
  • the first control circuit 600 may control the voltage of the pull-up node QB according to the voltage of the pull-down node Q.
  • the first control circuit 600 may be coupled to the second voltage terminal to receive the second voltage V2 and coupled to the third voltage terminal to receive the third voltage V3.
  • the second voltage terminal may provide a DC high-level signal, that is, the second voltage V2 is a high level.
  • the first control circuit 600 may control the voltage of the pull-up node QB according to the second voltage V2 and the third voltage V3 under the control of the voltage of the pull-down node Q.
  • the first control circuit 600 may also be coupled to the fourth voltage terminal to receive the fourth voltage V4.
  • the third voltage terminal and the fourth voltage terminal may alternately provide a DC low-level signal, for example, one of the third voltage V3 and the fourth voltage V4 is a low level, and the other is a high level.
  • the first control circuit 600 may control the voltage of the pull-up node QB according to the second voltage V2 and the third voltage V3 (or the fourth voltage) under the control of the voltage of the pull-down node Q.
  • the pull-up circuit 700 may provide the second voltage V2 from the second voltage terminal to the pull-down node Q, the shift signal output terminal CR, the first drive signal output terminal OUT1, and the second drive signal output terminal according to the voltage of the pull-up node QB OUT2.
  • the pull-up circuit 700 may be coupled to the second voltage terminal to receive the second voltage V2.
  • the pull-up circuit 700 reduces the noise at each terminal by pulling up the pull-down node Q, the shift signal output terminal CR, and the corresponding drive signal output terminal.
  • the second control circuit 800 may control the voltage of the pull-up node QB according to the first clock signal CLKA and the voltage of the first control node H.
  • the second control circuit 800 may be coupled to the first clock signal terminal to receive the first clock signal CLKA, and coupled to the second voltage terminal to receive the second voltage.
  • the second control circuit 800 may provide the second voltage to the pull-up node QB under the control of the first clock signal CLKA and the voltage of the first control node H.
  • the second control circuit 800 can also control the voltage of the pull-up node QB according to the display input signal STU2.
  • the second control circuit 800 may be coupled to the display input signal terminal to receive the display input signal STU2.
  • the second control circuit 800 may provide the second voltage to the pull-up node QB under the control of the display input signal STU.
  • the second control circuit 800 can pull up the pull-up node QB.
  • the reset circuit 900 may reset the pull-down node Q according to the blanking reset signal TRST from the blanking reset signal terminal, and reset the pull-down node Q according to the display reset signal STD from the display reset signal terminal.
  • the reset circuit 900 may be coupled to the blanking reset signal terminal to receive the blanking reset signal TRST, coupled to the display reset signal terminal to receive the display reset signal STD, and coupled to the second voltage terminal to receive the second voltage V2 .
  • the reset circuit 900 may provide the second voltage V2 to the pull-down node Q according to the blanking reset signal TRST, and provide the second voltage V2 to the pull-down node Q according to the display reset signal STD.
  • the shift register circuit 1000 in FIG. 2 shows the display input circuit 400, the output circuit 500, the first control circuit 600, the pull-up circuit 700, the second control circuit 800, and the reset circuit 900
  • the above examples do not limit the protection scope of the present disclosure.
  • technicians can choose to use or not use one or more of the above circuits according to the situation.
  • Various combinations and modifications based on the foregoing circuits do not deviate from the principles of the present disclosure and will not be repeated here.
  • FIG. 3 shows an exemplary circuit diagram of a shift register according to an embodiment of the present disclosure.
  • the shift register is, for example, the shift register 20 shown in FIG. 2.
  • the shift register may include a first transistor M1 to a twenty-seventh transistor M27, and a first capacitor C1 to a third capacitor C3.
  • all the transistors used in the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other switching devices with the same characteristics.
  • thin film transistors are used as examples.
  • the source and drain of the transistor used here may be symmetrical in structure, so the source and drain may be indistinguishable in structure.
  • the gate of the transistor can be referred to as the gate.
  • the transistors can be divided into N-type and P-type transistors according to their characteristics.
  • the on-voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltage), and the off-voltage is a high-level voltage (for example, 5V, 10V or other suitable voltage) Voltage).
  • the on-voltage is a high-level voltage (for example, 5V, 10V or other suitable voltage)
  • the off-voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable Voltage).
  • the transistors used in the shift register provided in the embodiments of the present disclosure are all described using P-type transistors as an example. Embodiments of the present disclosure include but are not limited to this. For example, at least part of the transistors in the shift register may also use N-type transistors, and change the potential of the corresponding voltage (first voltage, second voltage, etc.).
  • the pull-up node QB may include at least one of a first pull-up node QB_A and a second pull-up node QB_B.
  • FIG. 3 shows a case where the pull-up node QB includes both the first pull-up node QB_A and the second pull-up node QB_B. It can be understood that the pull-up node QB may also include only one of the first pull-up node QB_A and the second pull-up node QB_B, and the associated circuit only needs to be adjusted accordingly.
  • the blanking input circuit 100 includes a first transistor M1.
  • the control electrode of the first transistor M1 and the second clock signal terminal are coupled to receive the second clock signal CLKB
  • the first electrode of the first transistor M1 and the blanking input signal terminal are coupled to receive the blanking input signal STU1
  • the first transistor The second pole of M1 is coupled to the first control node H.
  • the first transistor M1 when the second clock signal CLKB is low, the first transistor M1 is turned on, so that a blanking input signal can be provided to the first control node H to control the voltage of the first control node H.
  • the blanking control circuit 200 includes a second transistor M2 and a first capacitor C1.
  • the control electrode of the second transistor M2 is coupled to the first control node H, the first electrode of the second transistor M2 and the first clock signal terminal are coupled to receive the first clock signal CLKA, the second electrode of the second transistor M2 and the first Two control nodes N are coupled.
  • the first terminal of the first capacitor is coupled to the first control node H, and the second terminal of the first capacitor is coupled to the second control node N.
  • the second transistor M2 when the voltage of the first control node H is at a low level, the second transistor M2 is turned on to provide the first clock signal CLKA to the second control node N to control the voltage of the second control node N.
  • the voltage of the second control node N changes, since the first capacitor C1 maintains the voltage difference between the first control node H and the second control node N, the voltage of the first control node H also changes accordingly.
  • the blanking pull-down circuit 300 includes a third transistor M3.
  • the control electrode of the third transistor M3 is coupled to the first clock signal terminal to receive the first clock signal CLKA, the first electrode of the third transistor M3 is coupled to the second control node N, and the second electrode of the third transistor M3 is pulled down Node Q is coupled.
  • the third transistor M3 when the first clock signal CLKA is at a low level, the third transistor M3 is turned on to provide the voltage of the second control node N to the pull-down node Q.
  • the display input circuit 400 includes a fourth transistor M4.
  • the control electrode of the fourth transistor M4 is coupled to the display input signal terminal to receive the display input signal STU2, the first electrode of the fourth transistor M4 and the first voltage terminal are coupled to receive the first voltage V1, and the second terminal of the fourth transistor M4 The pole and the pull-down node Q are coupled.
  • the fourth transistor M4 when the display input signal STU2 is at a low level, the fourth transistor M4 is turned on to provide the first voltage V1 to the pull-down node Q, so that the voltage of the pull-down node Q is at a low level.
  • the output circuit 500 includes a nineteenth transistor M19, a twenty-second transistor M22, and a second capacitor C2.
  • the control electrode of the nineteenth transistor M19 is coupled to the pull-down node Q
  • the first electrode of the nineteenth transistor M19 and the fourth clock signal terminal are coupled to receive the fourth clock signal CLKD
  • the second electrode of the nineteenth transistor M19 and The shift signal output terminal CR is coupled.
  • the control electrode of the twenty-second transistor M22 is coupled to the pull-down node Q
  • the first electrode of the twenty-second transistor M22 and the fourth clock signal terminal are coupled to receive the fourth clock signal CLKD
  • the two poles and the first driving signal output terminal are coupled to OUT1.
  • the first terminal of the second capacitor C2 is coupled to the pull-down node Q
  • the second terminal of the second capacitor C2 is coupled to the shift signal output terminal CR.
  • the output circuit 500 may further include a twenty-fifth transistor M25 and a third capacitor C3.
  • the control electrode of the twenty-fifth transistor M25 is coupled to the pull-down node Q.
  • the first electrode of the twenty-fifth transistor M25 and the fifth clock signal terminal are coupled to receive the fifth clock signal CLKE.
  • the two poles are coupled to the second driving signal output terminal OUT2.
  • the first terminal of the third capacitor C3 is coupled to the pull-down node Q, and the second terminal of the third capacitor C3 is coupled to the second driving signal output terminal OUT2.
  • the nineteenth transistor M19, the twenty-second transistor M22, and the twenty-fifth transistor M25 are turned on to provide the fourth clock signal CLKD to the shift signal output terminal CR
  • the first driving signal output terminal is coupled to OUT1
  • the fifth clock signal CLKE is provided to the second driving signal output terminal OUT2.
  • the first control circuit 600 includes a seventh transistor M7, an eighth transistor M8, a tenth transistor M10, and an eleventh transistor M11.
  • the control electrode of the seventh transistor M7 is coupled to the first electrode and the third voltage terminal to receive the third voltage V3, and the second electrode of the seventh transistor M7 is coupled to the first pull-up node QB_A.
  • the control electrode of the eighth transistor M8 is coupled to the pull-down node Q, the first electrode of the eighth transistor M8 is coupled to the first pull-up node QB_A, and the second electrode of the eighth transistor M8 is coupled to the second voltage terminal to receive the first Two voltage V2.
  • the control electrode and the first electrode of the tenth transistor M10 are coupled to the fourth voltage terminal V4, and the second electrode of the tenth transistor M10 is coupled to the second pull-up node QB_B.
  • the control electrode of the eleventh transistor M11 is coupled to the pull-down node Q, the first electrode of the eleventh transistor M11 is coupled to the second pull-up node QB_B, and the second electrode of the eleventh transistor M11 is coupled to the second voltage terminal V2 Connected to receive the second voltage V2.
  • the first control circuit 600 may include a seventh transistor M7 and an eighth transistor M8 (or a tenth transistor M10 And the eleventh transistor M11).
  • the specific circuit structure is similar and will not be repeated here.
  • the third voltage terminal V3 and the fourth voltage terminal V4 may be configured to alternately provide a low level. That is, when the third voltage terminal V3 provides a high level, the fourth voltage terminal V4 provides a low level, and the tenth transistor M10 is turned on. When the third voltage terminal V3 provides a low level, the fourth voltage terminal V4 provides a high level, and the seventh transistor M7 is turned on. Therefore, only one of the seventh transistor M7 and the tenth transistor M10 is in an on state. This can avoid performance drift caused by long-term transistor turn-on.
  • the third voltage can charge the first pull-up node QB_A when the seventh transistor M7 is turned on, and the second voltage can charge the second pull-up node QB_B when the tenth transistor M10 is turned on, thereby pulling the first pull-up node QB_B
  • the voltage of the node QB_A or the second pull-up node QB_B is controlled to a low level.
  • the eighth transistor M8 and the eleventh transistor M11 are turned on.
  • the seventh transistor M7 and the eighth transistor M8 can be configured (for example, the size ratio of the two, the threshold voltage, etc.).
  • the first pull-up node QB_A The voltage of can be pulled up to a high level, which can keep the twentieth transistor M20, the twenty-third transistor M23, and the twenty-sixth transistor M26 off.
  • the tenth transistor M10 and the eleventh transistor M11 can be configured (for example, the size ratio of the two, the threshold voltage, etc.).
  • the voltage of the second pull-up node QB_B can be It is pulled up to a high level, which can keep the twenty-first transistor M21, the twenty-fourth transistor M24, and the twenty-seventh transistor M27 off.
  • the pull-up circuit 700 includes a ninth transistor M9, a twentieth transistor M20, a twenty-third transistor M23, a twelfth transistor M12, a twenty-first transistor M21, a twenty-fourth transistor M24, a Twenty-six transistor M26 and twenty-seven transistor M27.
  • the control electrode of the ninth transistor M9 is coupled to the first pull-up node QB_A, the first electrode of the ninth transistor M9 is coupled to the pull-down node Q, and the second electrode of the ninth transistor M9 is coupled to the second voltage terminal V2.
  • the control electrode of the twentieth transistor M20 is coupled to the first pull-up node QB_A, the first electrode of the twentieth transistor M20 is coupled to the shift signal output terminal CR, the second electrode of the twentieth transistor M20 and the second voltage The terminal V2 is coupled.
  • the control electrode of the twenty-third transistor M23 is coupled to the first pull-up node QB_A, the first electrode of the twenty-third transistor M23 is coupled to the first drive signal output terminal OUT1, and the second electrode of the twenty-third transistor M23 It is coupled to the second voltage terminal V2.
  • the control pole of the twenty-sixth transistor M26 is coupled to the first pull-up node QB_A, the first pole of the twenty-sixth transistor is coupled to the second drive signal output terminal OUT2, and the second pole of the twenty-sixth transistor is coupled to the first The two voltage terminals V2 are coupled.
  • the ninth transistor M9, the twentieth transistor M20, the twenty-third transistor M23, and the twenty-sixth transistor are turned on to pull down the node Q ,
  • the shift signal output terminal CR, the first drive signal output terminal OUT1 and the second drive signal output terminal OUT2 are pulled up.
  • the control electrode of the twelfth transistor M12 is coupled to the second pull-up node QB_B, the first electrode of the twelfth transistor M12 is coupled to the pull-down node Q, and the second electrode of the twelfth transistor M12 is coupled to the second voltage terminal V2 Pick up.
  • the control electrode of the twenty-first transistor M21 is coupled to the second pull-up node QB_B, the first electrode of the twenty-first transistor M21 is coupled to the shift signal output terminal CR, and the second electrode of the twenty-first transistor M21 is The second voltage terminal V2 is coupled.
  • the control pole of the twenty-fourth transistor M24 is coupled to the second pull-up node QB_B, the first pole of the twenty-fourth transistor M24 is coupled to the first drive signal output terminal OUT1, and the second pole of the twenty-fourth transistor M24 It is coupled to the second voltage terminal V2.
  • the control pole of the twenty-seventh transistor M27 is coupled to the second pull-up node QB_B, the first pole of the twenty-seventh transistor is coupled to the second drive signal output terminal OUT2, the second pole of the twenty-seventh transistor and the second The two voltage terminals V2 are coupled.
  • the twelfth transistor M12, the twenty-first transistor M21, the twenty-fourth transistor M24, and the twenty-seventh transistor M27 are turned on
  • the pull-down node Q, the shift signal output terminal CR, the first drive signal output terminal OUT1 and the second drive signal output terminal OUT2 are pulled up.
  • the pull-up circuit 700 may include a ninth transistor M9, a twentieth transistor M20, and a twenty-third Transistor M23, twenty-sixth transistor (or, twelfth transistor M12, twenty-first transistor M21, twenty-fourth transistor M24, and twenty-seventh transistor M27).
  • the specific circuit structure is the same and will not be repeated here.
  • the second control circuit 800 may include a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17, and an eighteenth transistor M18.
  • the control electrode of the thirteenth transistor M13 is coupled to the first clock signal terminal to receive the first clock signal CLKA, and the first electrode of the thirteenth transistor M13 is coupled to the first pull-up node QB_A.
  • the control electrode of the fourteenth transistor M14 is coupled to the first control node H, the first electrode of the fourteenth transistor M14 is coupled to the second electrode of the thirteenth transistor M13, and the second electrode of the fourteenth transistor M14 is coupled to the first The two voltage terminals V2 are coupled.
  • the control pole of the fifteenth transistor M15 is coupled to the display input signal terminal to receive the display input signal STU2, the first pole of the fifteenth transistor M15 is coupled to the first pull-up node QB_A, and the second pole of the fifteenth transistor M15
  • the second voltage terminal is coupled to receive the second voltage V2.
  • the second voltage is supplied to the first pull-up node QB_A.
  • the display input signal STU2 is at a low level
  • the second voltage is supplied to the first pull-up node QB_A.
  • the control electrode of the sixteenth transistor M16 is coupled to the first clock signal terminal to receive the first clock signal CLKA, and the first electrode of the sixteenth transistor M16 is coupled to the second pull-up node QB_B.
  • the control electrode of the seventeenth transistor M17 is coupled to the first control node H, the first electrode of the seventeenth transistor M17 is coupled to the second electrode of the sixteenth transistor M16, and the second electrode of the seventeenth transistor M17 is coupled to the first The two voltage terminals are coupled to receive the second voltage V2.
  • the control pole of the eighteenth transistor M18 is coupled to the display input signal terminal to receive the display input signal STU2, the first pole of the eighteenth transistor M18 is coupled to the second pull-up node QB_B, and the second pole of the eighteenth transistor M18
  • the second voltage terminal is coupled to receive the second voltage V2.
  • the second voltage is supplied to the second pull-up node QB_B.
  • the display input signal STU2 is at a low level
  • the second voltage is supplied to the second pull-up node QB_B.
  • the pull-up circuit 700 may include the thirteenth transistor M13, the fourteenth transistor M14, the fifteenth The transistor M15 (or, the sixteenth transistor M16, the seventeenth transistor M17, and the eighteenth transistor M18).
  • the specific circuit structure is the same and will not be repeated here.
  • the reset circuit 900 may include a fifth transistor M5 and a sixth transistor M6.
  • the control electrode of the fifth transistor M5 is coupled to the blanking reset signal terminal to receive the blanking reset signal TRST, the first electrode of the fifth transistor M5 is coupled to the pull-down node Q, the second electrode of the fifth transistor M5 and the second voltage The terminal is coupled to receive the second voltage V2.
  • the fifth transistor M5 when the blanking reset signal TRST is at a low level, the fifth transistor M5 is turned on to provide the second voltage V2 to the pull-down node Q.
  • the control electrode of the sixth transistor M6 is coupled to the display reset signal terminal to receive the display reset signal STD, the first electrode of the sixth transistor M6 is coupled to the pull-down node Q, the second electrode of the sixth transistor M6 and the second voltage terminal V2 Coupling.
  • the sixth transistor M6 when the display reset signal STD is at a low level, the sixth transistor M6 is turned on to supply the second voltage V2 to the pull-down node Q.
  • the display input circuit 410 may include a fourth transistor M4 and a fourth leak-proof transistor M4_b.
  • the control electrode and the first electrode of the fourth transistor M4 and the control electrode of the fourth leak-proof transistor M4_b are coupled to the display input signal terminal to receive the display input signal STU2, the second electrode of the fourth transistor M4 and the fourth leak-proof transistor M4_b
  • the first pole of is coupled, and the second pole of the fourth leak-proof transistor M4_b is coupled to the pull-down node Q.
  • the display input circuit 420 may include a fourth transistor M4 and a fourth anti-leakage transistor M4_b.
  • the control electrode of the fourth transistor M4 is coupled to the display input signal terminal to receive the display input signal STU2, and the first electrode and the first voltage terminal are coupled to receive the first voltage V1.
  • the control electrode and the first electrode of the fourth leakage prevention transistor M4_b are coupled to the second electrode of the fourth transistor M4, and the second electrode is coupled to the pull-down node Q.
  • the display input circuit 430 may include a fourth transistor M4.
  • the control electrode and the first electrode of the fourth transistor are coupled to the display input signal terminal to receive the display input signal STU2, and the second electrode is coupled to the pull-down node Q.
  • the second control circuit 810 includes a thirteenth transistor M13, a fifteenth transistor M15, a sixteenth transistor M16, and an eighteenth transistor M18.
  • the control pole of the thirteenth transistor M13 is coupled to the first clock signal terminal CLKA, the first pole of the thirteenth transistor M13 is coupled to the first pull-up node QB_A, and the second pole and the second voltage of the thirteenth transistor M13 The terminal V2 is coupled.
  • the control pole of the fifteenth transistor M15 is coupled to the display input signal terminal STU2, the first pole of the fifteenth transistor M15 is coupled to the first pull-up node QB_A, and the second pole and the second voltage terminal of the fifteenth transistor M15 V2 is coupled.
  • the control electrode of the sixteenth transistor M16 is coupled to the first clock signal terminal CLKA, the first electrode of the sixteenth transistor M16 is coupled to the second pull-up node QB_B, and the second electrode and the second voltage of the sixteenth transistor M16 The terminal V2 is coupled.
  • the control electrode of the eighteenth transistor M18 is coupled to the display input signal terminal, the first electrode of the eighteenth transistor M18 is coupled to the second pull-up node QB_B, the second electrode of the eighteenth transistor M18 and the second voltage terminal V2 Coupling.
  • the second control circuit 810 does not include the fourteenth transistor M14 and the seventeenth transistor M17.
  • the second control circuit 820 includes a fifteenth transistor M15 and an eighteenth transistor M18.
  • the control pole of the fifteenth transistor M15 is coupled to the display input signal terminal STU2
  • the first pole of the fifteenth transistor M15 is coupled to the first pull-up node QB_A
  • the second pole and the second voltage terminal of the fifteenth transistor M15 V2 is coupled.
  • the control electrode of the eighteenth transistor M18 is coupled to the display input signal terminal
  • the first electrode of the eighteenth transistor M18 is coupled to the second pull-up node QB_B, the second electrode of the eighteenth transistor M18 and the second voltage terminal V2 Coupling.
  • the second control circuit 820 does not include the thirteenth transistor M13, the fourteenth transistor M14, the sixteenth transistor M16, and the seventeenth transistor M17.
  • FIG. 6 shows an exemplary circuit diagram of a shift register according to another embodiment of the present disclosure.
  • the difference between the shift register and the shift register in FIG. 3 is that the second control circuit 810 is replaced with the second control circuit 810, and a first leakage prevention transistor M1_b and a third leakage prevention transistor M3_b are added , A fifth leakage prevention transistor M5_b, a sixth leakage prevention transistor M6_b, a ninth leakage prevention transistor M9_b, a twelfth leakage prevention transistor M12_b, a twenty-eighth transistor M28, and a twenty-ninth transistor M29.
  • the first leakage prevention transistor M1_b is taken as an example to describe the working principle of the leakage prevention.
  • the control electrode of the first anti-leakage transistor M1_b is coupled to the second clock signal terminal CLKB, the first electrode of the first anti-leakage transistor M1_b is coupled to the second electrode of the twenty-eighth transistor M28, the first anti-leakage transistor M1_b
  • the second pole is coupled to the first control node H.
  • the control electrode of the twenty-eighth transistor M28 is coupled to the first control node H, and the first electrode of the twenty-eighth transistor M28 is coupled to the fifth voltage terminal V5 to receive a fifth voltage at a low level.
  • the twenty-eighth transistor M28 is turned on under the control of the level of the first control node H, so that the low-level signal input from the fifth voltage terminal V5 can be input to the first The first pole of the anti-leakage transistor M1_b, so that both the first and second poles of the first anti-leakage transistor M1_b are in a low level state, preventing the charge at the first control node H from leaking through the first anti-leakage transistor M1_b.
  • the combination of the first transistor M1 and the first leakage prevention transistor M1_b can achieve the same effect as the aforementioned first transistor M1, At the same time, it has the effect of preventing leakage.
  • the third anti-leakage transistor M3_b, the fifth anti-leakage transistor M5_b, the sixth anti-leakage transistor M6_b, the ninth anti-leakage transistor M9_b, and the twelfth anti-leakage transistor M12_b can be combined with the twenty-ninth transistor M29 to achieve anti-leakage
  • This structure can prevent the electric charge at the pull-down node Q from leaking.
  • the working principle of preventing leakage of the pull-down node Q is the same as the above-mentioned working principle of preventing leakage of the first control node H, and details are not described here.
  • the embodiment of the present disclosure also provides a gate driving circuit constituted by a shift register.
  • the gate driving circuit 30 may include multiple (eg, N) cascaded shift registers, wherein any one or more shift registers may adopt the shift registers provided by the embodiments of the present disclosure, For example, the structure of the shift register 10 or the shift register 20 or a modification thereof. It should be noted that only the first four stages of shift registers (A1, A2, A3, and A4) of the gate driving circuit 30 are schematically shown in FIG. 7.
  • the blanking input signal terminal STU1 and the display input signal terminal STU2 of the first-stage shift register A1 and the display input signal terminal STU2 of the second-stage shift register A2 both receive the input signal STU.
  • the blanking input signal terminal STU1 of the i+1th-stage shift register is coupled to the shift signal output terminal CR of the i-th stage shift register.
  • the display input signal terminal STU2 of the i+2th stage shift register is coupled to the shift signal output terminal CR of the ith stage shift register.
  • the display reset signal terminal STD of the i-th stage shift register is connected to the shift signal output terminal CR of the i+3th stage shift register.
  • the blanking reset signal terminal TRST and the blanking reset signal line TRST of the shift registers at all levels are coupled.
  • the gate driving circuit 30 may further include a first sub-clock signal line CLK_1 and a second sub-clock signal line CLK_2. As shown in FIG. 7, the first clock signal terminal CLKA of each stage of the shift register is coupled to the first sub-clock signal line CLK_1. The second clock signal terminal CLKB of each stage of the shift register is coupled to the second sub-clock signal line CLK_2.
  • the gate driving circuit 30 may further include a third sub-clock signal line CLKD_1, a fourth sub-clock signal line CLKD_2, a fifth sub-clock signal line CLKD_3, and a sixth sub-clock signal line CLKD_4.
  • the shift register includes the fourth clock signal terminal CLKD
  • the fourth clock signal terminal CLKD of the 4i-3 stage shift register is coupled to the third sub-clock signal line CLKD_1, and the 4i-2 stage shift register
  • the fourth clock signal terminal CLKD is coupled to the fourth sub-clock signal line CLKD_2
  • the fourth clock signal terminal CLKD of the shift register 4i-1 is coupled to the fifth sub-clock signal line CLKD_3
  • the shift register of the 4i stage The fourth clock signal terminal CLKD is coupled to the sixth sub-clock signal line CLKD_4.
  • the third sub-clock signal line CLKD_1 provides the fourth clock signal to the first-stage shift register
  • the fourth sub-clock signal line CLKD_2 provides the fourth clock signal to the second-stage shift register
  • the fifth sub-clock signal line CLKD_3 The third-stage shift register provides a fourth clock signal
  • the sixth sub-clock signal line CLKD_4 provides a fourth clock signal to the fourth-stage shift register.
  • the gate driving circuit 30 may further include a seventh sub-clock signal line CLKE_1, an eighth sub-clock signal line CLKE_2, a ninth sub-clock signal line CLKE_3, and a tenth sub-clock signal line CLKE_4.
  • the shift register includes the fifth clock signal terminal CLKE
  • the fifth clock signal terminal CLKE of the 4i-3 stage shift register and the seventh sub-clock signal line CLKE_1 are coupled, and the 4i-2 stage shift register
  • the fifth clock signal terminal CLKE is coupled to the eighth sub-clock signal line CLKE_2, and the fifth clock signal terminal CLKE of the 4i-1th stage shift register is coupled to the ninth sub-clock signal line CLKE_3.
  • the fifth clock signal terminal CLKE is coupled to the tenth sub-clock signal line CLKE_4.
  • the seventh sub-clock signal line CLKE_1 provides the fifth clock signal to the first-stage shift register
  • the eighth sub-clock signal line CLKE_2 provides the fifth clock signal to the second-stage shift register
  • the ninth sub-clock signal line CLKE_3 to The third-stage shift register provides a fifth clock signal
  • the tenth sub-clock signal line CLKE_4 provides the fifth clock signal to the fourth-stage shift register.
  • the shift register in the gate drive circuit 30 is, for example, the shift register shown in FIG. 3.
  • Fig. 8 shows a signal timing chart of the gate drive circuit 30 shown in Fig. 7 when used for sequential compensation on a row-by-row basis.
  • 1F and 2F represent the first frame and the second frame, respectively.
  • Display represents the display period in one frame
  • Blank represents the blanking period in one frame.
  • the signal STU represents the input signal STU.
  • TRST represents the signal supplied to the blanking reset signal line TRST.
  • the signals V3 and V4 represent signals provided to the third voltage terminal and the fourth voltage terminal of the shift register in the gate driving circuit 30, respectively.
  • the signals CLK_1 and CLK_2 represent signals of the signal CLK_2 provided to the first sub-clock signal line CLK_1 and the second sub-clock line, respectively.
  • the signals CLKD_1, CLKD_2, CLKD_3, and CLKD_4 respectively represent signals provided to the third subclock signal line CLKD_1, the fourth subclock signal line CLKD_2, the fifth subclock signal line CLKD_3, and the sixth subclock signal line CLKD_4.
  • the signals CLKE_1, CLKE_2, CLKE_3, and CLKE_4 represent signals provided to the seventh subclock signal line CLKE_1, the eighth subclock signal line CLKE_2, the ninth subclock signal line CLKE_3, and the tenth subclock signal line CLKE_4, respectively.
  • H ⁇ 1> and H ⁇ 2> represent the voltages of the first control node H in the first-stage shift register A1 and the second-stage shift register A2 in the gate drive circuit 30, respectively.
  • N ⁇ 1> and N ⁇ 2> represent the voltages of the second control node N in the first-stage shift register A1 and the second-stage shift register A2, respectively.
  • Q ⁇ 1> and Q ⁇ 2> represent the voltage of the pull-down node Q in the first-stage shift register A1 and the second-stage shift register A2 in the gate drive circuit 30, respectively.
  • OUT1 ⁇ 1>, OUT1 ⁇ 2>, OUT1 ⁇ 3> and OUT1 ⁇ 4> respectively represent the first-stage shift register A1, the second-stage shift register A2, and the third-stage shift register in the gate drive circuit 30 A3 and the corresponding first drive signal output terminal OUT1 in the fourth-stage shift register A4.
  • OUT2 ⁇ 1> and OUT2 ⁇ 2> respectively represent the corresponding second driving signal output terminal OUT2 in the first-stage shift register A1 and the second-stage shift register A2 in the gate driving circuit 30. It should be noted that, since the voltages of the shift signal output terminal CR and the drive signal output terminal OUT1 in the shift register of each stage are the same, the shift signal output terminal CR is not shown in FIG. 8.
  • the working principle of the gate driving circuit 30 shown in FIG. 7 when used for sequential compensation line by row is described below with reference to the signal timing chart in FIG. 8, for example, in the gate driving circuit 20 shown in FIG.
  • the shift register shown in Figure 3 can be used as the shift register.
  • the blanking reset signal line TRST and the second sub-clock signal line CLK_2 both provide a low level to provide the blanking reset signal terminal TRST and the second clock signal terminal CLKB of the shift registers at all levels
  • the low level causes the first transistor M1 and the fifth transistor M5 in the shift registers at all levels to be turned on.
  • the blanking input signal STU1 (high-level input signal STU) is provided to the first control node H, the voltage of the first control node H is high, and the second voltage V2 (high level) is provided to the pull-down node Q, the voltage of the pull-down node Q is high level.
  • the first control node H and the pull-down node Q at all levels are reset to achieve a global reset.
  • the blanking input signal terminal STU1 and the display input signal terminal STU2 of the first-stage shift register are connected to the input signal line STU, so the blanking input signal terminal STU1 and the display input signal terminal STU2 provide low power Ping signal.
  • the second clock signal terminal CLKB provides a low-level signal, so that the first transistor M1 is turned on, thereby providing the blanking input signal STU1 to the first control node H ⁇ 1>.
  • the voltage of the first control node H ⁇ 1> is low
  • the first clock signal CLKA (coupled to the first sub-clock signal line CLK_1)
  • the second transistor M2 is turned on, turning The first clock signal CLKA is supplied to the second control node N ⁇ 1> so that the voltage of the second control node N ⁇ 1> is high.
  • the third transistor M3 since the first clock signal CLKA is at a high level, the third transistor M3 is turned off to isolate the influence of the first control node H ⁇ 1> and the second control node N ⁇ 1> on the pull-down node Q ⁇ 1>.
  • the first capacitor C1 maintains the voltage difference between the first control node H ⁇ 1> and the second control node N ⁇ 1> until the blanking period.
  • the fourth voltage V4 is at a low level, and the tenth transistor M10 is turned on to control the voltage of the gate electrode of the twelfth transistor M12 to be at a low level. Therefore, the twelfth transistor M12 is turned on, and the second voltage V2 is supplied to the pull-down node Q ⁇ 1>, so that the voltage of the pull-down node Q ⁇ 1> is high. Since the input signal STU2 is shown as low level in the first period and the fourth transistor M4 is turned on, the first voltage V1 is supplied to the pull-down node Q ⁇ 1>, so that the voltage of the pull-down node Q ⁇ 1> becomes low level .
  • the eighth transistor M8 and the eleventh transistor M11 are turned on, pulling the first pull-up node QB_A and the second pull-up node QB_B high.
  • the pull-down node Q ⁇ 1> is at a low level, so that the nineteenth transistor M19, the twenty-second transistor M22, and the twenty-fifth transistor M25 are turned on, and the fourth clock signal CLKD (with the third sub-clock signal line CLKD_1 is coupled) and the fifth clock signal CLKE (coupled to the seventh sub-clock signal line CLKE_1) is provided to the shift signal output terminal CR ⁇ 1>, the first drive signal output terminal OUT1 ⁇ 1> and the second drive The signal output terminal OUT2 ⁇ 1>, respectively output high-level signals.
  • the fifteenth transistor M15 and the eighteenth transistor M18 are turned on, and the high-level second voltage V2 is provided to the first pull-up node QB_A and the second pull-up node, respectively QB_B, so that the first pull-up node QB_A and the second pull-up node QB_B can be assisted to pull up.
  • a low-level signal is provided to the fourth clock signal terminal CLKD through the third sub-clock signal line CLKD_1, and a low-level signal is provided to the fifth clock signal terminal CLKE through the seventh sub-clock signal line CLKE_1. Due to the existence of the second capacitor C2, the voltage of the pull-down node Q ⁇ 1> is further pulled down due to the bootstrap effect.
  • the nineteenth transistor M19, the twenty-second transistor M22, and the twenty-fifth transistor M25 remain on, so that the shift signal output terminal CR ⁇ 1>, the first drive signal output terminal OUT1 ⁇ 1>, and the second drive signal output Both OUT2 ⁇ 1> output low level signals.
  • the low-level signal output from the shift signal output terminal can be used for scanning shift of the upper and lower shift registers, and the low-level signal output from the two drive signal output terminals can be used to drive sub-pixels in the display panel Pixels for display.
  • the pull-down node Q ⁇ 1> remains low, and the nineteenth transistor M19, the twenty-second transistor M22, and the twenty-fifth transistor M25 remain on.
  • a high-level signal is provided to the fourth clock signal terminal CLKD through the third sub-clock signal line CLKD_1, and a high-level signal is provided to the fifth clock signal terminal CLKE through the seventh sub-clock signal line CLKE_1, so that the shift signal output terminal CR, Both the first drive signal output terminal OUT1 and the second drive signal output terminal OUT2 output high-level signals.
  • the pull-down node Q ⁇ 1> The voltage will increase by a certain amount.
  • the display reset signal terminal STD of the first-stage shift register A1 and the shift signal output terminal CR ⁇ 4> (ie, OUT1 ⁇ 4>) of the fourth-stage shift register A4 are connected, the fourth-stage shift The shift signal output terminal CR ⁇ 4> of the bit register A4 has not yet output a low-level signal, so the pull-down node Q ⁇ 1> will not be pulled up, so that the pull-up node Q ⁇ 1> can be kept at a low Level.
  • the twenty-first transistor M21, the twenty-fourth transistor M24, and the twenty-seventh transistor M27 are turned on to provide the second voltage V2 to the shift signal output terminal CR ⁇ 1> and the first drive signal output terminal OUT1 ⁇ 1> and the second drive signal output terminal OUT2 ⁇ 1>, respectively output high level signals.
  • the third transistor M3 may isolate the influence of the voltage at the first control node H ⁇ 1> and the second control node N ⁇ 1> on the pull-down node Q of the display period.
  • the first-stage shift register drives the sub-pixels in the first row of the display panel to complete the display, and so on, and the second-stage, third-stage shift registers, etc., drive the sub-pixels in the display panel row by row for one frame of display driving. At this point, the display period of the first frame ends.
  • the first control node H ⁇ 1> is written to a low level and held until the blanking period Blank.
  • the second transistor is turned on, and the first clock signal CLKA is at a high level, so the second control node N ⁇ 1> is written to a high level and held until the blanking period Blank.
  • the first sub-clock signal line CLK_1 provides a low-level signal to the first clock signal CLKA
  • the first control node H ⁇ 1> remains low
  • the second transistor M2 is turned on.
  • the first clock signal CLKA is supplied to the second control node N ⁇ 1>, so that the voltage of the second control node N ⁇ 1> becomes a low level.
  • the voltage of the first control node H ⁇ 1> also decreases accordingly, so that the lossless
  • the first clock signal CLKA is provided to the second control node N ⁇ 1>, so that the voltage of the second control node N ⁇ 1> can reach the lowest potential of the first clock signal CLKA and lossless output.
  • the third transistor M3 is turned on, thereby providing the voltage of the second control node N ⁇ 1> (the lossless first clock signal CLKA) to the pull-down node Q ⁇ 1>, so that the pull-down node Q ⁇ 1> becomes low. level.
  • the fourth clock signal CLKD and the fifth clock signal terminal CLKE are both high-level signals, so that the shift signal output terminal CR, the first drive signal output terminal OUT1, and the second drive signal output terminal OUT2 output high power Ping signal.
  • the third transistor M3 is turned off, the fourth clock signal CLKD and the fifth clock signal terminal CLKE are both low-level signals, the shift signal output terminal CR ⁇ 1>, the first drive signal output terminal OUT1 ⁇ 1> and the second drive The signal output terminals OUT2 ⁇ 1> all output low-level signals.
  • the voltage of the pull-down node Q ⁇ 1> is pulled down again.
  • the first transistor M1 in the second-stage shift register is turned on, and the blanking input signal STU1 ⁇ 2> is coupled to the shift in the first-stage shift register A1
  • the bit signal output terminal CR ⁇ 1> so the voltage of the first control node H ⁇ 2> in the second-stage shift register A2 is reduced to a low level.
  • the second sub-clock signal line CLK_2 provides a high-level signal to the second clock signal CLKB
  • the third sub-clock line CLKD_1 provides a low-level signal to the fourth clock signal terminal CLKD
  • the seventh sub-clock signal line CLKE_1 provides a high-level signal to the fifth clock signal terminal CLKE.
  • the shift signal output terminal CR ⁇ 1>, the first drive signal output terminal OUT1 ⁇ 1> output a low level signal
  • the second drive signal output terminal OUT2 ⁇ 1> output a high level signal.
  • the first transistor M1 in the second-stage shift register A2 is turned off, and the first control node H ⁇ 2> remains low until the blanking period BLANK of the next frame.
  • the first driving signal output terminal OUT1 ⁇ 1> outputs a low-level first driving signal to drive the sensing transistor (eg, P) in the first row of sub-pixels Type transistor).
  • the sensing transistor in the first row of sub-pixels can sense the driving current of the row of sub-pixels, so as to compensate based on the sensed driving current.
  • both the fourth clock signal CLKD and the fifth clock signal CLKE become high level.
  • the shift signal output terminal CR ⁇ 1>, the first drive signal output terminal OUT1 ⁇ 1> and the second drive signal output terminal OUT2 ⁇ 1> all output high level signals.
  • the voltage of the pull-down node Q rises.
  • the blanking reset signal line TRST provides a low-level signal to the blanking reset signal terminal TRST
  • the fifth transistor M5 is turned on, and the voltage of the pull-down node Q becomes a high level.
  • the fourth voltage is at a low level
  • the tenth transistor M10 is turned on, so that the voltage of the second pull-up node QB_B becomes a low level.
  • the twenty-first transistor M21, the twenty-fourth transistor M24 and the twenty-seventh transistor M27 are all turned on, the shift signal output terminal CR ⁇ 1>, the first drive signal output terminal OUT1 ⁇ 1> and the second The drive signal output terminals OUT2 ⁇ 1> output high-level signals respectively.
  • the driving of the gate driving circuit may refer to the above description, which will not be repeated here.
  • the blanking output signal output by the gate driving circuit can be used to drive the sensing transistor in the sub-pixel in the display panel.
  • the driving signal is sequentially provided line by line.
  • the gate driving circuit outputs a driving signal for the sub-pixels of the first row of the display panel.
  • the gate driving circuit outputs a driving signal for the sub-pixels of the second row of the display panel, and so on, in order to compensate sequentially by row.
  • the embodiments of the present disclosure also provide an array substrate and a display device including the gate driving circuit 30 described above.
  • the display device may be any product or component with a display function such as a liquid crystal panel, an LCD TV, a display, an OLED panel, an OLED TV, an electronic paper display device, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigator .
  • FIG. 9 shows a schematic flowchart of a method for driving a shift register according to an embodiment of the present disclosure.
  • the shift register may be any applicable shift register based on the embodiments of the present disclosure.
  • step 910 under the control of the second clock signal CLKB from the second clock signal terminal, the blanking input signal STU1 from the blanking input signal terminal is provided to the first control node H, and remains at The voltage difference between the first control node H and the second control node N. For example, see the description of the first period in FIG. 8.
  • the display output signal can be output according to the voltage of the pull-down node Q. For example, see the description of the third period in FIG. 8.
  • the pull-down node Q can be reset according to the display reset signal STD. For example, see the description of the fourth period in FIG. 8.
  • the first clock signal CLKA from the first clock signal terminal may be provided to the second control node N according to the voltage of the first control node H, and according to the voltage of the second control node N The voltage of the first control node H is controlled via the held voltage difference. Thereby, the first clock signal CLKA can be output to the second control node N without loss.
  • step 930 the voltage of the second control node N (ie, the lossless first clock signal CLKA) may be provided to the pull-down node Q according to the first clock signal CLKA.
  • steps 920 and 930 for example, refer to the description of the fifth period in FIG. 8 above.
  • the second control node N receives the first clock signal CLKA, so the voltage of the second control node N changes, and is controlled according to the voltage of the second control node N via the held voltage difference The voltage of the first control node H. For example, see the description of the sixth period in FIG. 8 above.
  • step 940 according to the voltage of the pull-down node Q, a shift signal and a driving signal (for example, a first driving signal and a second driving signal) are output.
  • a shift signal and a driving signal for example, a first driving signal and a second driving signal
  • the blanking input signal STU1 from the blanking input signal terminal is provided to the first control node H, so that the first clock signal is no longer provided to the second control node N.
  • the pull-down node Q can also be reset according to the blanking reset signal TRST. For example, see the description of the 11th period in FIG. 8.
  • the above steps are described in order, they do not constitute a limitation on the order of the methods, and the embodiments of the present disclosure can also be implemented in any other suitable order.
  • the above steps may occur in different periods of the same frame, or may occur in different periods of different frames.
  • the first step may occur during the blanking period of the first frame, and the other steps may occur during the display period and blanking period of the second frame. This disclosure does not limit this.

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Abstract

一种移位寄存器及其驱动方法、栅极驱动电路和显示装置。移位寄存器（10）包括消隐输入电路（100）、消隐控制电路（200）、消隐下拉电路（300）、和移位寄存电路（1000）。消隐输入电路（100）可根据第二时钟信号（CLKB）将消隐输入信号（STU1）提供到第一控制节点（H）。消隐控制电路（200）可根据第一控制节点（H）的电压将第一时钟信号（CLKA）提供到第二控制节点（N），以及保持在第一控制节点（H）和第二控制节点（N）之间的电压差。消隐下拉电路（300）可根据第一时钟信号（CLKA）将第二控制节点（N）的电压提供到下拉节点（Q）。移位寄存电路（1000）可根据下拉节点（Q）的电压，经由移位信号输出端（CR）提供移位信号，以及经由第一驱动信号输出端（OUT1）提供第一驱动信号。

Description

移位寄存器及其驱动方法、栅极驱动电路和显示装置 技术领域
本公开涉及显示技术领域，具体地，涉及移位寄存器及其驱动方法、栅极驱动电路和显示装置。
背景技术
随着显示技术的进步，相对于传统的液晶显示(Liquid Crystal Display，LCD)装置，新一代的有机发光二极管(Organic Light Emitting Diode，OLED)显示装置具有更低的制造成本，更快的反应速度，更高的对比度，更广的视角，更大的工作温度范围，不需要背光单元，色彩鲜艳及轻薄等优点，因此OLED显示技术成为当前发展最快的显示技术。
为了提高OLED面板的工艺集成度并降低成本，通常采用阵列基板行驱动(Gate Driver on Array，简称GOA)技术而将薄膜晶体管(TFT)的栅极驱动电路集成在显示面板的阵列基板上以形成对显示面板的扫描驱动。这种利用GOA技术而集成在阵列基板上的栅极驱动电路也称为GOA单元或移位寄存器。采用GOA电路的显示装置由于省去了绑定驱动电路的部分，可以从材料成本和制作工艺两方面降低成本。
发明内容
本公开的实施例提供了移位寄存器及其驱动方法、栅极驱动电路、以及显示装置。
根据本公开的第一方面，提供了一种移位寄存器。移位寄存器可包括消隐输入电路、消隐控制电路、消隐下拉电路、和移位寄存电路。消隐输入电路可根据来自第二时钟信号端的第二时钟信号将来自消隐输入信号端的消隐输入信号提供到第一控制节点。消隐控制电路可根据第一控制节点的电压将来自第一时钟信号端的第一时钟信号提供到第二控制节点，以及保持在第一控制节点和第二控制节点之间的电压差。消隐下拉电路可根据 第一时钟信号将第二控制节点的电压提供到下拉节点。移位寄存电路被配置为根据下拉节点的电压，经由移位信号输出端提供移位信号，以及经由第一驱动信号输出端提供第一驱动信号。
在本公开的实施例中，消隐控制电路可包括第二晶体管和第一电容。第二晶体管的控制极和第一控制节点耦接，第二晶体管的第一极和第一时钟信号端耦接，第二晶体管的第二极和第二控制节点耦接。第一电容被耦接在第一控制节点和第二控制节点之间。
在本公开的实施例中，消隐输入电路可包括第一晶体管。第一晶体管的控制极和第二时钟信号端耦接，第一晶体管的第一极和消隐输入信号端耦接，第一晶体管的第二极和第一控制节点耦接。
在本公开的实施例中，消隐下拉电路可包括第三晶体管。第三晶体管的控制极和第一时钟信号端耦接，第三晶体管的第一极和第二控制节点耦接，第三晶体管的第二极和下拉节点耦接。
在本公开的实施例中，移位寄存器还可包括显示输入电路和输出电路。显示输入电路可根据来自显示输入信号端的显示输入信号将来自第一电压端的第一电压提供到下拉节点。输出电路可根据下拉节点的电压，从移位信号输出端输出移位信号，以及从第一驱动信号输出端输出第一驱动信号。
在本公开的实施例中，显示输入电路可包括第四晶体管。第四晶体管的控制极和显示输入信号端耦接，第四晶体管的第一极和第一电压端耦接，第四晶体管的第二极和下拉节点耦接。
在本公开的实施例中，输出电路可包括第十九晶体管、第二十二晶体管和第二电容。第十九晶体管的控制极和下拉节点耦接，第十九晶体管的第一极和第四时钟信号端耦接以接收第四时钟信号，第十九晶体管的第二极和移位信号输出端耦接。第二十二晶体管的控制极和下拉节点耦接，第二十二晶体管的第一极和第四时钟信号端耦接以接收第四时钟信号，第二十二晶体管的第二极和第一驱动信号输出端耦接。第二电容被耦接在下拉节点和移位信号输出端之间。
在本公开的实施例中，移位寄存电路还可包括第一控制电路、上拉电 路和第二控制电路。第一控制电路可根据下拉节点的电压控制上拉节点的电压。上拉电路可根据上拉节点的电压，将来自第二电压端的第二电压提供到下拉节点、移位信号输出端和驱动信号输出端。第二控制电路可根据第一时钟信号和第一控制节点的电压控制上拉节点的电压，以及根据显示输入信号控制上拉节点的电压。
在本公开的实施例中，上拉节点可包括第一上拉节点。第一控制电路可包括第七晶体管和第八晶体管。第七晶体管的控制极和第一极和第三电压端耦接，第七晶体管的第二极和第一上拉节点耦接。第八晶体管的控制极和下拉节点耦接，第八晶体管的第一极和第一上拉节点耦接，第八晶体管的第二极和第二电压端耦接。上拉电路可包括第九晶体管、第二十晶体管和第二十三晶体管。第九晶体管的控制极和第一上拉节点耦接，第九晶体管的第一极和下拉节点耦接，第九晶体管的第二极和第二电压端耦接。第二十晶体管的控制极和第一上拉节点耦接，第二十晶体管的第一极和移位信号输出端耦接，第二十晶体管的第二极和第二电压端耦接。第二十三晶体管的控制极和第一上拉节点耦接，第二十三晶体管的第一极和第一驱动信号输出端耦接，第二十三晶体管的第二极和第二电压端耦接。第二控制电路可包括第十三晶体管、第十四晶体管和第十五晶体管。第十三晶体管的控制极和第一时钟信号端耦接，第十三晶体管的第一极和第一上拉节点耦接。第十四晶体管的控制极和第一控制节点耦接，第十四晶体管的第一极和第十三晶体管的第二极耦接，第十四晶体管的第二极和第二电压端耦接。第十五晶体管的控制极和显示输入信号端耦接，第十五晶体管的第一极和第一上拉节点耦接，第十五晶体管的第二极和第二电压端耦接。
在本公开的实施例中，上拉节点还可包括第二上拉节点。第一控制电路还包括第十晶体管和第十一晶体管。第十晶体管的控制极和第一极和第四电压端耦接，第十晶体管的第二极和第二上拉节点耦接。第十一晶体管的控制极和下拉节点耦接，第十一晶体管的第一极和第二上拉节点耦接，第十一晶体管的第二极和第二电压端耦接。上拉电路还可包括第十二晶体管、第二十一晶体管和第二十四晶体管。第十二晶体管的控制极和第二上 拉节点耦接，第十二晶体管的第一极和下拉节点耦接，第十二晶体管的第二极和第二电压端耦接。第二十一晶体管的控制极和第二上拉节点耦接，第二十一晶体管的第一极和移位信号输出端耦接，二十一晶体管的第二极和第二电压端耦接。第二十四晶体管的控制极和第二上拉节点耦接，第二十四晶体管的第一极和第一驱动信号输出端耦接，第二十四晶体管的第二极和第二电压端耦接。第二控制电路还可包括第十六晶体管、第十七晶体管和第十八晶体管。第十六晶体管的控制极和第一时钟信号端耦接，第十六晶体管的第一极和第二上拉节点耦接。第十七晶体管的控制极和第一控制节点耦接，第十七晶体管的第一极和第十六晶体管的第二极耦接，第十七晶体管的第二极和第二电压端耦接。第十八晶体管的控制极和显示输入信号端耦接，第十八晶体管的第一极和第二上拉节点耦接，第十八晶体管的第二极和第二电压端耦接。
在本公开的实施例中，移位寄存电路还可包括复位电路。复位电路可根据来自消隐复位信号端的消隐复位信号对下拉节点进行复位，以及根据来自显示复位信号端的显示复位信号对下拉节点进行复位。
在本公开的实施例中，复位电路可包括第五晶体管和第六晶体管。第五晶体管的控制极和消隐复位信号端耦接，第五晶体管的第一极和下拉节点耦接，第五晶体管的第二极和第二电压端耦接。第六晶体管的控制极和显示复位信号端耦接，第六晶体管的第一极和下拉节点耦接，第六晶体管的第二极和第二电压端耦接。
在本公开的实施例中，输出电路还可包括第二十五晶体管和第三电容。第二十五晶体管的控制极和下拉节点耦接，第二十五晶体管的第一极和第五时钟信号端耦接以接收第五时钟信号，第二十五晶体管的第二极和第二驱动信号输出端耦接。第三电容被耦接在下拉节点和第二驱动信号输出端之间。
在本公开的实施例中，上拉电路还可包括第二十六晶体管和第二十七晶体管。第二十六晶体管的控制极和第一上拉节点耦接，第二十六晶体管的第一极和第二驱动信号输出端耦接，第二十六晶体管的第二极和第二电 压端耦接。第二十七晶体管的控制极和第二上拉节点耦接，第二十七晶体管的第一极和第二驱动信号输出端耦接，第二十七晶体管的第二极和第二电压端耦接。
根据本公开的第二方面，提供了一种栅极驱动电路。栅极驱动电路可包括N个级联的如本公开的第一方面提供的移位寄存器、第一子时钟信号线和第二子时钟信号线。第i+1级移位寄存器的消隐输入信号端和第i级移位寄存器的移位信号输出端耦接。各级移位寄存器的第一时钟信号端和第一子时钟信号线耦接。各级移位寄存器的第二时钟信号端和第二子时钟信号线耦接。
在本公开的实施例中，栅极驱动电路还可包括消隐复位信号线、第一子时钟信号线和第二子时钟信号线。第i+2级移位寄存器的显示输入信号端和第i级移位寄存器的移位信号输出端耦接。各级移位寄存器的消隐复位信号端和消隐复位信号线耦接。第i级移位寄存器的显示复位信号端和第i+3级移位寄存器的移位信号输出端耦接。
在本公开的实施例中，栅极驱动电路还可包括第三子时钟信号线、第四子时钟信号线、第五子时钟信号线和第六子时钟信号线。第4i-3级移位寄存器的第四时钟信号端和第三子时钟信号线耦接。第4i-2级移位寄存器的第四时钟信号端和第四子时钟信号线耦接。第4i-1级移位寄存器的第四时钟信号端和第五子时钟信号线耦接。第4i级移位寄存器的第四时钟信号端和第六子时钟信号线耦接。
在本公开的实施例中，栅极驱动电路还可包括第七子时钟信号线、第八子时钟信号线、第九子时钟信号线和第十子时钟信号线。第4i-3级移位寄存器的第五时钟信号端和第七子时钟信号线耦接。第4i-2级移位寄存器的第五时钟信号端和第八子时钟信号线耦接。第4i-1级移位寄存器的第五时钟信号端和第九子时钟信号线耦接。第4i级移位寄存器的第五时钟信号端和第十子时钟信号线耦接。
根据本公开的第三方面，提供了一种显示装置。显示装置包括根据本公开的第二方面提供的栅极驱动电路。
根据本公开的第四方面，提供了一种用于驱动本公开的第一方面提供的移位寄存器的方法。在方法中，将消隐输入信号提供到第一控制节点，保持在第一控制节点和第二控制节点之间的电压差；根据第一控制节点的电压将第一时钟信号提供到第二控制节点，以及经由电压差控制第一控制节点的电压；根据第一时钟信号将第二控制节点的电压提供到下拉节点；以及根据下拉节点的电压，输出移位信号和第一驱动信号。
附图说明
为了更清楚地说明本公开的技术方案，下面将对实施例的附图进行简单说明。应当知道，以下描述的附图仅仅是本公开的一些实施例，而非对本公开的限制，其中相同的附图标记指示相同的元件或信号。在附图中：
图1示出了根据本公开的实施例的移位寄存器的示意性框图；
图2示出了根据本公开的实施例的移位寄存器的示意性框图；
图3示出了根据本公开的实施例的移位寄存器的示例性电路图；
图4(1)、(2)和(3)分别示出了根据本公开的实施例的显示输入电路的示例性电路图；
图5(1)和(2)分别示出了根据本公开的实施例的第二控制电路的示例性电路图；
图6示出了根据本公开的另一实施例的移位寄存器的示例性电路图；
图7示出了根据本公开的实施例的栅极驱动电路的示意图；
图8示出了根据本公开的实施例的栅极驱动电路的工作过程中各信号的时序图；以及
图9示出了根据本公开的实施例的用于驱动移位寄存器的方法的示意性流程图。
具体实施方式
为了使本公开的实施例的技术方案和优点更加清楚，下面将结合附图，对本公开的实施例的技术方案进行清楚、完整的描述。显然，所描述的实 施例仅仅是本公开的一部分实施例，而并非全部的实施例。基于所描述的实施例，本领域的普通技术人员在无需创造性劳动的前提下所获得的所有其它实施例，也都属于本公开的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“耦接”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，并且可以是直接连接也可以通过中间介质间接连接。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在显示领域，特别是有机发光二极管OLED显示技术中，栅极驱动电路通常都集成在集成电路IC中。集成电路IC设计中芯片的面积是影响芯片成本的主要因素。通常，栅极驱动电路包括检测电路、显示电路和输出两者复合脉冲的连接电路(或门电路)。此类电路结构非常复杂，难以满足高分辨率窄边框的要求。
在对OLED显示面板中的子像素进行补偿时，除了在子像素中设置像素补偿电路进行内部补偿外，还可以通过设置感测晶体管进行外部补偿。在进行外部补偿时，由移位寄存器构成的栅极驱动电路需要向显示面板中的子像素分别提供用于扫描晶体管和感测晶体管的驱动信号。例如，在一帧的显示时段(Display)提供用于扫描晶体管的扫描驱动信号，在一帧的消隐时段(Blank)提供用于感测晶体管的感测驱动信号。
在本公开的实施例中，“一帧”、“每帧”或“某一帧”包括依次进行的显示时段和消隐时段。例如，在显示时段中，栅极驱动电路输出显示输出信号，该显示输出信号可以用于驱动显示面板中的扫描晶体管，以进行从 第一行到最后一行的扫描，从而显示面板进行显示。在消隐时段中，栅极驱动电路输出消隐输出信号，该消隐输出信号可以用于驱动显示面板中的某一行子像素中的感测晶体管感测该行子像素的驱动电流，从而基于所感测的驱动电流进行补偿。。
本公开的实施例提供了移位寄存器及其驱动方法、栅极驱动电路、以及显示装置。下面结合附图对本公开的实施例及其示例进行详细说明。
图1示出了根据本公开的实施例的移位寄存器的示意性框图。如图1所示，移位寄存器10可包括消隐输入电路100、消隐控制电路200、消隐下拉电路300、和移位寄存电路1000。
在本公开的实施例中，消隐输入电路100可根据来自第二时钟信号端的第二时钟信号CLKB将来自消隐输入信号端的消隐输入信号STU1提供到第一控制节点H，以控制第一控制节点H的电压。例如，消隐输入电路100可与第二时钟信号端耦接以接收第二时钟信号CLKB，与消隐输入信号端耦接以接收消隐输入信号STU1。
消隐控制电路200可根据第一控制节点H的电压将来自第一时钟信号端的第一时钟信号CLKA提供到第二控制节点N，以控制第二控制节点N的电压。消隐控制电路200还可保持在第一控制节点H和第二控制节点N之间的电压差。例如，消隐控制电路200可与第一时钟信号端耦接以接收第一时钟信号CLKA。
消隐下拉电路300可根据第一时钟信号CLKA将第二控制节点N的电压提供到下拉节点Q，以控制下拉节点Q的电压。例如，消隐下拉电路300可与第一时钟信号端耦接以接收第一时钟信号CLKA。
在实施例中，由于消隐控制电路200可保持第一控制节点H和第二控制节点N之间的电压差，在第二控制节点N的电压改变时，第一控制节点H的电压也相应地改变，从而可以无损地将第一时钟信号CLKA提供到第二控制节点N。在此情况下，消隐下拉电路300可将第一时钟信号CLKA(即第二控制节点N的电压)无损地提供到下拉节点Q。由此，可以消除消隐时段在下拉节点Q写入低电位时晶体管的阈值电压损失。
此外，由于消隐控制电路200和消隐下拉电路300设置在第一控制节点H和下拉节点Q之间，所以可以防止第一控制节点H和第二控制节点N的电压对下拉节点Q的电压产生影响。
移位寄存电路1000可在下拉节点Q的控制下，经由移位信号输出端提供移位信号，以及经由第一驱动信号输出端提供第一驱动信号。在一帧的显示时段中，移位信号例如可以用于上下级移位寄存器单元的扫描移位。驱动信号可以用于驱动显示面板中的扫描晶体管，以进行驱动显示面板进行显示。在一帧的消隐时段中，移位信号例如也可以用于上下级移位寄存器单元的扫描移位。驱动信号可以用于驱动显示面板中的子像素中的感测晶体管，以进行该行子像素的外部补偿。
图2示出了根据本公开的另一实施例的移位寄存器的示意性框图。如图2所示，移位寄存器20可包括消隐输入电路100、消隐控制电路200、消隐下拉电路300、以及移位寄存电路1000。在实施例中，移位寄存电路1000可包括显示输入电路400和输出电路500。此外，在另外一些实施例中，移位寄存电路1000还可包括第一控制电路600、上拉电路700、第二控制电路800。进一步地，在又一些实施例中，移位寄存电路1000还可包括复位电路900。
图2示出了移位寄存电路1000包括显示输入电路400、输出电路500、第一控制电路600、上拉电路700、第二控制电路800和复位电路900的示例。其中，消隐输入电路100、消隐控制电路200和消隐下拉电路300已在上文中详细描述，在此不再赘述。以下主要描述移位寄存电路1000中的各部分电路。
如图2所示，显示输入电路400可根据来自显示输入信号端的显示输入信号STU2，将来自第一电压端的第一电压V1提供到下拉节点Q，以控制下拉节点Q的电压。例如，显示输入电路400可与显示输入信号端耦接以接收显示输入信号STU2，与第一电压端耦接以接收第一电压V1。在实施例中，第一电压端可提供直流低电平信号，即第一电压V1是低电平。
输出电路500可根据下拉节点Q的电压，从移位信号输出端CR输出 移位信号，以及从第一驱动信号输出端OUT1输出第一驱动信号。例如，输出电路500可与第四时钟信号端耦接以接收第四时钟信号CLKD。输出电路500可根据下拉节点Q的电压，将第四时钟信号CLKD提供至移位信号输出端CR以输出第四时钟信号CLKD作为移位信号，以及将第四时钟信号CLKD提供至第一驱动信号输出端OUT1以输出第四时钟信号CLKD作为第一驱动信号。
在实施例中，输出电路500也可根据下拉节点Q的电压，从第二驱动信号输出端OUT2输出第二驱动信号。例如，输出电路500可以和第五时钟信号端耦接以接收第五时钟信号CLKE。在实施例中，输出电路500还可根据下拉节点Q的电压，将第五时钟信号CLKE提供至第二驱动信号输出端OUT2以输出第五时钟信号CLKE作为第二输出信号。本领域技术人员可理解的是驱动信号输出端的数量不限于2个，也可以是2个以上，输出电路可根据相应的时钟信号输出相应的驱动信号。在实施例中，在显示时段，移位信号和相应的驱动信号也可被统称为显示输出信号，在消隐时段，移位信号和相应的驱动信号也可被统称为消隐输出信号。
第一控制电路600可根据下拉节点Q的电压控制上拉节点QB的电压。例如，第一控制电路600可与第二电压端耦接以接收第二电压V2，与第三电压端耦接以接收第三电压V3。在实施例中，第二电压端可提供直流高电平信号，即第二电压V2是高电平。第一控制电路600可在下拉节点Q的电压的控制下，根据第二电压V2和第三电压V3控制上拉节点QB的电压。
进一步地，第一控制电路600还可与第四电压端耦接以接收第四电压V4。第三电压端和第四电压端可交替提供直流低电平信号，例如第三电压V3和第四电压V4中的一者是低电平，另一者是高电平。在实施例中，第一控制电路600可在下拉节点Q的电压的控制下，根据第二电压V2和第三电压V3(或者第四电压)控制上拉节点QB的电压。
上拉电路700可根据上拉节点QB的电压，将来自第二电压端的第二电压V2提供到下拉节点Q、移位信号输出端CR、第一驱动信号输出端OUT1和第二驱动信号输出端OUT2。例如，上拉电路700可与第二电压端 耦接以接收第二电压V2。由此，上拉电路700通过对下拉节点Q、移位信号输出端CR和相应的驱动信号输出端进行上拉来降低各端的噪声。
第二控制电路800可根据第一时钟信号CLKA和第一控制节点H的电压，控制上拉节点QB的电压。例如，第二控制电路800可与第一时钟信号端耦接以接收第一时钟信号CLKA，与第二电压端耦接以接收第二电压。在实施例中，第二控制电路800可在第一时钟信号CLKA和第一控制节点H的电压的控制下，将第二电压提供到上拉节点QB。此外，第二控制电路800还可根据显示输入信号STU2，控制上拉节点QB的电压。例如，第二控制电路800可与显示输入信号端耦接以接收显示输入信号STU2。在实施例中，第二控制电路800可在显示输入信号STU的控制下，将第二电压提供到上拉节点QB。由此，第二控制电路800可对上拉节点QB进行上拉。
此外，复位电路900可根据来自消隐复位信号端的消隐复位信号TRST对下拉节点Q进行复位，以及根据来自显示复位信号端的显示复位信号STD对下拉节点Q进行复位。例如，复位电路900可与消隐复位信号端耦接以接收消隐复位信号TRST，与显示复位信号端耦接以接收显示复位信号STD，以及与第二电压端耦接以接收第二电压V2。在实施例中，复位电路900可根据消隐复位信号TRST将第二电压V2提供到下拉节点Q，以及根据显示复位信号STD将第二电压V2提供到下拉节点Q。
本领域技术人员可以理解，尽管图2中的移位寄存电路1000示出了显示输入电路400、输出电路500、第一控制电路600、上拉电路700、第二控制电路800和复位电路900，然而上述示例并不能限制本公开的保护范围。在实际应用中，技术人员可以根据情况选择使用或不使用上述各电路中的一个或多个，基于前述各电路的各种组合变型均不脱离本公开的原理，对此不再赘述。
以下通过示例性电路结构来对本公开提供的移位寄存器进行描述。
图3示出了根据本公开的实施例的移位寄存器的示例性电路图。移位寄存器例如是图2中所示的移位寄存器20。如图3所示，移位寄存器可包括第一晶体管M1至第二十七晶体管M27、以及第一电容C1至第三电容 C3。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其它特性相同的开关器件。本公开的实施例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。晶体管的栅极可被称为控制极。此外，按照晶体管的特性区分可以将晶体管分为N型和P型晶体管。当晶体管为P型晶体管时，导通电压为低电平电压(例如，0V、-5V、-10V或其它合适的电压)，关断电压为高电平电压(例如，5V、10V或其它合适的电压)。当晶体管为N型晶体管时，导通电压为高电平电压(例如，5V、10V或其它合适的电压)，关断电压为低电平电压(例如，0V、-5V、-10V或其它合适的电压)。
另外，需要说明的是，本公开的实施例中提供的移位寄存器中采用的晶体管均是以P型晶体管为例进行说明的。本公开的实施例包括但不限于此，例如移位寄存器中的至少部分晶体管也可以采用N型晶体管，并改变相应电压(第一电压、第二电压等)的电位。
在本公开的实施例中，上拉节点QB可包括第一上拉节点QB_A和第二上拉节点QB_B中的至少一个。图3示出了上拉节点QB包括第一上拉节点QB_A和第二上拉节点QB_B两者的情况。可以理解的是，上拉节点QB也可仅包括第一上拉节点QB_A和第二上拉节点QB_B中的一个，相关联的电路仅需进行相应地调整。
如图3所示，消隐输入电路100包括第一晶体管M1。第一晶体管M1的控制极和第二时钟信号端耦接以接收第二时钟信号CLKB，第一晶体管M1的第一极和消隐输入信号端耦接以接收消隐输入信号STU1，第一晶体管M1的第二极和第一控制节点H耦接。在实施例中，当第二时钟信号CLKB为低电平时，第一晶体管M1导通，从而可以将消隐输入信号提供到第一控制节点H，以控制第一控制节点H的电压。
消隐控制电路200包括第二晶体管M2和第一电容C1。第二晶体管 M2的控制极和第一控制节点H耦接，第二晶体管M2的第一极和第一时钟信号端耦接以接收第一时钟信号CLKA，第二晶体管M2的第二极和第二控制节点N耦接。第一电容的第一端和第一控制节点H耦接，第一电容的第二端和第二控制节点N耦接。在实施例中，当第一控制节点H的电压为低电平时，第二晶体管M2导通，将第一时钟信号CLKA提供到第二控制节点N，以控制第二控制节点N的电压。当第二控制节点N的电压改变时，由于第一电容C1保持第一控制节点H和第二控制节点N之间的电压差，因此第一控制节点H的电压也相应地改变。
消隐下拉电路300包括第三晶体管M3。第三晶体管M3的控制极和第一时钟信号端耦接以接收第一时钟信号CLKA，第三晶体管M3的第一极和第二控制节点N耦接，第三晶体管M3的第二极和下拉节点Q耦接。在实施例中，当第一时钟信号CLKA为低电平时，第三晶体管M3导通，将第二控制节点N的电压提供到下拉节点Q。
显示输入电路400包括第四晶体管M4。第四晶体管M4的控制极和显示输入信号端耦接以接收显示输入信号STU2，第四晶体管M4的第一极和第一电压端耦接以接收第一电压V1，第四晶体管M4的第二极和下拉节点Q耦接。在实施例中，当显示输入信号STU2为低电平时，第四晶体管M4导通，将第一电压V1提供到下拉节点Q，使得下拉节点Q的电压为低电平。
输出电路500包括第十九晶体管M19、第二十二晶体管M22、第二电容C2。第十九晶体管M19的控制极和下拉节点Q耦接，第十九晶体管M19的第一极和第四时钟信号端耦接以接收第四时钟信号CLKD，第十九晶体管M19的第二极和移位信号输出端CR耦接。第二十二晶体管M22的控制极和下拉节点Q耦接，第二十二晶体管M22的第一极和第四时钟信号端耦接以接收第四时钟信号CLKD，第二十二晶体管M22的第二极和第一驱动信号输出端耦接OUT1。第二电容C2的第一端和下拉节点Q耦接，第二电容C2的第二端和移位信号输出端CR耦接。
此外，输出电路500还可包括第二十五晶体管M25和第三电容C3。 第二十五晶体管M25的控制极和下拉节点Q耦接，第二十五晶体管M25的第一极和第五时钟信号端耦接以接收第五时钟信号CLKE，第二十五晶体管M25的第二极和第二驱动信号输出端OUT2耦接。第三电容C3的第一端和下拉节点Q耦接，第三电容C3的第二端和第二驱动信号输出端OUT2耦接。
在实施例中，当下拉节点Q为低电平时，第十九晶体管M19、第二十二晶体管M22、第二十五晶体管M25导通，将第四时钟信号CLKD提供到移位信号输出端CR和第一驱动信号输出端耦接OUT1，以及将第五时钟信号CLKE提供到第二驱动信号输出端OUT2。
第一控制电路600包括第七晶体管M7、第八晶体管M8、第十晶体管M10和第十一晶体管M11。第七晶体管M7的控制极和第一极和第三电压端耦接以接收第三电压V3，第七晶体管M7的第二极和第一上拉节点QB_A耦接。第八晶体管M8的控制极和下拉节点Q耦接，第八晶体管M8的第一极和第一上拉节点QB_A耦接，第八晶体管M8的第二极和第二电压端耦接以接收第二电压V2。第十晶体管M10的控制极和第一极与第四电压端V4耦接，第十晶体管M10的第二极和第二上拉节点QB_B耦接。第十一晶体管M11的控制极和下拉节点Q耦接，第十一晶体管M11的第一极和第二上拉节点QB_B耦接，第十一晶体管M11的第二极和第二电压端V2耦接以接收第二电压V2。
可理解地是，当上拉节点QB仅包括第一上拉节点QB_A(或者第二上拉节点QB_B)，第一控制电路600可包括第七晶体管M7和第八晶体管M8(或者第十晶体管M10和第十一晶体管M11)。具体电路结构类似，在此不再赘述。
在实施例中，第三电压端V3和第四电压端V4可以被配置为交替提供低电平。也就是说，第三电压端V3提供高电平时，第四电压端V4提供低电平，第十晶体管M10导通。第三电压端V3提供低电平时，第四电压端V4提供高电平，第七晶体管M7导通。因此，第七晶体管M7和第十晶体管M10中只有一个晶体管处于导通状态。这样可以避免晶体管长期导通引 起的性能漂移。
当第七晶体管M7导通时第三电压可以对第一上拉节点QB_A进行充电，当第十晶体管M10导通时第四电压可以对第二上拉节点QB_B进行充电，从而将第一上拉节点QB_A或第二上拉节点QB_B的电压控制为低电平。当下拉节点Q的电压为低电平时，第八晶体管M8和第十一晶体管M11导通。例如，在晶体管的设计上，可以将第七晶体管M7与第八晶体管M8配置为(例如对二者的尺寸比、阈值电压等配置)在M7和M8均导通时，第一上拉节点QB_A的电压可以被上拉至高电平，该高电平可以使得第二十晶体管M20、第二十三晶体管M23以及第二十六晶体管M26保持关断。另一方面，可以将第十晶体管M10与第十一晶体管M11配置为(例如对二者的尺寸比、阈值电压等配置)在M10和M11均导通时，第二上拉节点QB_B的电压可以被上拉至高电平，该高电平可以使得第二十一晶体管M21、第二十四晶体管M24以及第二十七晶体管M27保持关断。
如图3所示，上拉电路700包括第九晶体管M9、第二十晶体管M20、第二十三晶体管M23、第十二晶体管M12、第二十一晶体管M21、第二十四晶体管M24、第二十六晶体管M26和第二十七晶体管M27。
第九晶体管M9的控制极和第一上拉节点QB_A耦接，第九晶体管M9的第一极和下拉节点Q耦接，第九晶体管M9的第二极和第二电压端V2耦接。第二十晶体管M20的控制极和第一上拉节点QB_A耦接，第二十晶体管M20的第一极和移位信号输出端CR耦接，第二十晶体管M20的第二极和第二电压端V2耦接。第二十三晶体管M23的控制极和第一上拉节点QB_A耦接，第二十三晶体管M23的第一极和第一驱动信号输出端OUT1耦接，第二十三晶体管M23的第二极和第二电压端V2耦接。第二十六晶体管M26的控制极和第一上拉节点QB_A耦接，第二十六晶体管的第一极和第二驱动信号输出端OUT2耦接，第二十六晶体管的第二极和第二电压端V2耦接。在实施例中，当第一上拉节点QB_A的电压是低电平时，第九晶体管M9、第二十晶体管M20、第二十三晶体管M23、第二十 六晶体管导通，以对下拉节点Q、移位信号输出端CR、第一驱动信号输出端OUT1和第二驱动信号输出端OUT2进行上拉。
第十二晶体管M12的控制极和第二上拉节点QB_B耦接，第十二晶体管M12的第一极和下拉节点Q耦接，第十二晶体管M12的第二极和第二电压端V2耦接。第二十一晶体管M21的控制极和第二上拉节点QB_B耦接，第二十一晶体管M21的第一极和移位信号输出端CR耦接，第二十一晶体管M21的第二极和第二电压端V2耦接。第二十四晶体管M24的控制极和第二上拉节点QB_B耦接，第二十四晶体管M24的第一极和第一驱动信号输出端OUT1耦接，第二十四晶体管M24的第二极和第二电压端V2耦接。第二十七晶体管M27的控制极和第二上拉节点QB_B耦接，第二十七晶体管的第一极和第二驱动信号输出端OUT2耦接，第二十七晶体管的第二极和第二电压端V2耦接。在实施例中，当第二上拉节点QB_B的电压是低电平时，第十二晶体管M12、第二十一晶体管M21、第二十四晶体管M24和第二十七晶体管M27导通，以对下拉节点Q、移位信号输出端CR、第一驱动信号输出端OUT1和第二驱动信号输出端OUT2进行上拉。
可以理解的是，当上拉节点QB仅包括第一上拉节点QB_A(或者第二上拉节点QB_B)时，上拉电路700可包括第九晶体管M9、第二十晶体管M20、第二十三晶体管M23、第二十六晶体管(或者，第十二晶体管M12、第二十一晶体管M21、第二十四晶体管M24和第二十七晶体管M27)。具体电路结构相同，在此不再赘述。
如图3所示，第二控制电路800可包括第十三晶体管M13、第十四晶体管M14、第十五晶体管M15、第十六晶体管M16、第十七晶体管M17和第十八晶体管M18。
第十三晶体管M13的控制极和第一时钟信号端耦接以接收第一时钟信号CLKA，第十三晶体管M13的第一极和第一上拉节点QB_A耦接。第十四晶体管M14的控制极和第一控制节点H耦接，第十四晶体管M14的第一极和第十三晶体管M13的第二极耦接，第十四晶体管M14的第二极和第二电压端V2耦接。第十五晶体管M15的控制极和显示输入信号端耦 接以接收显示输入信号STU2，第十五晶体管M15的第一极和第一上拉节点QB_A耦接，第十五晶体管M15的第二极和第二电压端耦接以接收第二电压V2。在实施例中，当第一时钟信号CLKA和第一控制节点H的电压均为低电平时，将第二电压提供到第一上拉节点QB_A。此外，当显示输入信号STU2为低电平时，将第二电压提供到第一上拉节点QB_A。
第十六晶体管M16的控制极和第一时钟信号端耦接以接收第一时钟信号CLKA，第十六晶体管M16的第一极和第二上拉节点QB_B耦接。第十七晶体管M17的控制极和第一控制节点H耦接，第十七晶体管M17的第一极和第十六晶体管M16的第二极耦接，第十七晶体管M17的第二极和第二电压端耦接以接收第二电压V2。第十八晶体管M18的控制极和显示输入信号端耦接以接收显示输入信号STU2，第十八晶体管M18的第一极和第二上拉节点QB_B耦接，第十八晶体管M18的第二极和第二电压端耦接以接收第二电压V2。在实施例中，当第一时钟信号CLKA和第一控制节点H的电压均为低电平时，将第二电压提供到第二上拉节点QB_B。此外，当显示输入信号STU2为低电平时，将第二电压提供到第二上拉节点QB_B。
可以理解的是，当上拉节点QB仅包括第一上拉节点QB_A(或者第二上拉节点QB_B)时，上拉电路700可包括第十三晶体管M13、第十四晶体管M14、第十五晶体管M15(或者，第十六晶体管M16、第十七晶体管M17和第十八晶体管M18)。具体电路结构相同，在此不再赘述。
此外，如图3所示，复位电路900可包括第五晶体管M5和第六晶体管M6。第五晶体管M5的控制极和消隐复位信号端耦接以接收消隐复位信号TRST，第五晶体管M5的第一极和下拉节点Q耦接，第五晶体管M5的第二极和第二电压端耦接以接收第二电压V2。在实施例中，在消隐复位信号TRST为低电平时，第五晶体管M5导通，将第二电压V2提供到下拉节点Q。第六晶体管M6的控制极和显示复位信号端耦接以接收显示复位信号STD，第六晶体管M6的第一极和下拉节点Q耦接，第六晶体管M6的第二极和第二电压端V2耦接。在实施例中，在显示复位信号STD为低 电平时，第六晶体管M6导通，将第二电压V2提供到下拉节点Q。
可以理解的是，本公开的实施例中移位寄存器中的各电路并不限于以上电路结构，以下结合附图示意性地描述可选择的电路变形，该变形也非限制性的。
图4(1)、(2)和(3)分别示出了根据本公开的实施例的显示输入电路410、显示输入电路420和显示输入电路430的示例性电路图。
如图4(1)所示，显示输入电路410可包括第四晶体管M4和第四防漏晶体管M4_b。第四晶体管M4的控制极和第一极以及第四防漏晶体管M4_b的控制极与显示输入信号端耦接以接收显示输入信号STU2，第四晶体管M4的第二极和第四防漏晶体管M4_b的第一极耦接，第四防漏晶体管M4_b的第二极和下拉节点Q耦接。
如图4(2)所示，显示输入电路420可包括第四晶体管M4和第四防漏晶体管M4_b。第四晶体管M4的控制极和显示输入信号端耦接以接收显示输入信号STU2，第一极和第一电压端耦接以接收第一电压V1。第四防漏晶体管M4_b的控制极和第一极与第四晶体管M4的第二极耦接，第二极和下拉节点Q耦接。
如图4(3)所示，显示输入电路430可包括第四晶体管M4。第四晶体管的控制极和第一极与显示输入信号端耦接以接收显示输入信号STU2，第二极和下拉节点Q耦接。
图5(1)和(2)分别示出了根据本公开的实施例的第二控制电路800的示例性电路图。
如图5(1)所示，第二控制电路810包括第十三晶体管M13、第十五晶体管M15、第十六晶体管M16和第十八晶体管M18。第十三晶体管M13的控制极和第一时钟信号端CLKA耦接，第十三晶体管M13的第一极和第一上拉节点QB_A耦接，第十三晶体管M13的第二极和第二电压端V2耦接。第十五晶体管M15的控制极和显示输入信号端STU2耦接，第十五晶体管M15的第一极和第一上拉节点QB_A耦接，第十五晶体管M15的第二极和第二电压端V2耦接。第十六晶体管M16的控制极和第一时钟信号 端CLKA耦接，第十六晶体管M16的第一极和第二上拉节点QB_B耦接，第十六晶体管M16的第二极和第二电压端V2耦接。第十八晶体管M18的控制极和显示输入信号端耦接，第十八晶体管M18的第一极和第二上拉节点QB_B耦接，第十八晶体管M18的第二极和第二电压端V2耦接。相对于图3中移位寄存器20的第二控制电路800，第二控制电路810不包含第十四晶体管M14和第十七晶体管M17。
如图5(2)所示，第二控制电路820包括第十五晶体管M15和第十八晶体管M18。第十五晶体管M15的控制极和显示输入信号端STU2耦接，第十五晶体管M15的第一极和第一上拉节点QB_A耦接，第十五晶体管M15的第二极和第二电压端V2耦接。第十八晶体管M18的控制极和显示输入信号端耦接，第十八晶体管M18的第一极和第二上拉节点QB_B耦接，第十八晶体管M18的第二极和第二电压端V2耦接。相对于图3中移位寄存器20的第二控制电路800，第二控制电路820不包含第十三晶体管M13、第十四晶体管M14、第十六晶体管M16和第十七晶体管M17。
图6示出了根据本公开的另一实施例的移位寄存器的示例性电路图。如图6所示，移位寄存器与图3中的移位寄存器的区别在于，使用第二控制电路810替换第二控制电路800，并增加了第一防漏电晶体管M1_b、第三防漏电晶体管M3_b、第五防漏电晶体管M5_b、第六防漏电晶体管M6_b、第九防漏电晶体管M9_b、第十二防漏电晶体管M12_b、第二十八晶体管M28以及第二十九晶体管M29。下面以第一防漏电晶体管M1_b为例对防漏电的工作原理进行说明。
第一防漏电晶体管M1_b的控制极和第二时钟信号端CLKB耦接，第一防漏电晶体管M1_b的第一极和第二十八晶体管M28的第二极耦接，第一防漏电晶体管M1_b的第二极和第一控制节点H耦接。第二十八晶体管M28的控制极和第一控制节点H耦接，第二十八晶体管M28的第一极和第五电压端V5耦接以接收低电平的第五电压。当第一控制节点H处于低电平时，第二十八晶体管M28在第一控制节点H的电平的控制下导通，从而可以将第五电压端V5输入的低电平信号输入到第一防漏电晶体管M1_b 的第一极，从而使得第一防漏电晶体管M1_b的第一极和第二极都处于低电平状态，防止第一控制节点H处的电荷通过第一防漏电晶体管M1_b漏电。此时，由于第一防漏电晶体管M1_b的控制极和第一晶体管M1的控制极耦接，所以第一晶体管M1和第一防漏电晶体管M1_b的结合可以实现与前述第一晶体管M1相同的效果，同时具有防漏电的效果。
类似地，第三防漏电晶体管M3_b、第五防漏电晶体管M5_b、第六防漏电晶体管M6_b、第九防漏电晶体管M9_b、第十二防漏电晶体管M12_b可以分别结合第二十九晶体管M29实现防漏电结构，从而可以防止下拉节点Q处的电荷发生漏电。防止下拉节点Q发生漏电的工作原理和上述防止第一控制节点H发生漏电的工作原理相同，这里不再赘述。
本公开的实施例还提供了由移位寄存器构成的栅极驱动电路。如图7所示，栅极驱动电路30可包括多个(例如，N个)级联的移位寄存器，其中任意一个或多个移位寄存器可以采用本公开的实施例提供的移位寄存器，例如移位寄存器10或移位寄存器20的结构或其变型。需要说明的是，图7中仅示意性的示出了栅极驱动电路30的前四级移位寄存器(A1、A2、A3和A4)。
如图7所示，第一级移位寄存器A1的消隐输入信号端STU1和显示输入信号端STU2以及第二级移位寄存器A2的显示输入信号端STU2均接收输入信号STU。此外第i+1级移位寄存器的消隐输入信号端STU1和第i级移位寄存器的移位信号输出端CR耦接。第i+2级移位寄存器的显示输入信号端STU2和第i级移位寄存器的移位信号输出端CR耦接。除了最后三级移位寄存器外，第i级移位寄存器的显示复位信号端STD和第i+3级移位寄存器的移位信号输出端CR连接。此外，各级移位寄存器的消隐复位信号端TRST和消隐复位信号线TRST耦接。
在实施例中，栅极驱动电路30还可包括第一子时钟信号线CLK_1和第二子时钟信号线CLK_2。如图7所示，每一级移位寄存器的第一时钟信号端CLKA均和第一子时钟信号线CLK_1耦接。每一级移位寄存器的第二时钟信号端CLKB均和第二子时钟信号线CLK_2耦接。
如图7所示，栅极驱动电路30还可包括第三子时钟信号线CLKD_1、第四子时钟信号线CLKD_2、第五子时钟信号线CLKD_3和第六子时钟信号线CLKD_4。在移位寄存器包括第四时钟信号端CLKD的情形下，第4i-3级移位寄存器的第四时钟信号端CLKD和第三子时钟信号线CLKD_1耦接，第4i-2级移位寄存器的第四时钟信号端CLKD和第四子时钟信号线CLKD_2耦接，第4i-1级移位寄存器的第四时钟信号端CLKD和第五子时钟信号线CLKD_3耦接，第4i级移位寄存器的第四时钟信号端CLKD和第六子时钟信号线CLKD_4耦接。例如，第三子时钟信号线CLKD_1向第一级移位寄存器提供第四时钟信号，第四子时钟信号线CLKD_2向第二级移位寄存器提供第四时钟信号，第五子时钟信号线CLKD_3向第三级移位寄存器提供第四时钟信号，第六子时钟信号线CLKD_4向第四级移位寄存器提供第四时钟信号。
此外，栅极驱动电路30还可包括第七子时钟信号线CLKE_1、第八子时钟信号线CLKE_2、第九子时钟信号线CLKE_3和第十子时钟信号线CLKE_4。在移位寄存器包括第五时钟信号端CLKE的情形下，第4i-3级移位寄存器的第五时钟信号端CLKE和第七子时钟信号线CLKE_1耦接，第4i-2级移位寄存器的第五时钟信号端CLKE和第八子时钟信号线CLKE_2耦接，第4i-1级移位寄存器的第五时钟信号端CLKE和第九子时钟信号线CLKE_3耦接，第4i级移位寄存器的第五时钟信号端CLKE和第十子时钟信号线CLKE_4耦接。例如，第七子时钟信号线CLKE_1向第一级移位寄存器提供第五时钟信号，第八子时钟信号线CLKE_2向第二级移位寄存器提供第五时钟信号，第九子时钟信号线CLKE_3向第三级移位寄存器提供第五时钟信号，第十子时钟信号线CLKE_4向第四级移位寄存器提供第五时钟信号。
下面结合图8中的信号时序图，对图7中所示的栅极驱动电路30的工作过程进行说明。其中，栅极驱动电路30中的移位寄存器例如是图3所示的移位寄存器。
图8示出了图7所示的栅极驱动电路30在用于逐行顺序补偿时的信号 时序图。在图9中，1F和2F分别表示第一帧和第二帧。Display表示一帧中的显示时段，Blank表示一帧中的消隐时段。
信号STU表示输入信号STU。TRST表示提供给消隐复位信号线TRST的信号。信号V3和V4分别表示提供给栅极驱动电路30中移位寄存器的第三电压端和第四电压端的信号。信号CLK_1和CLK_2分别表示提供给第一子时钟信号线CLK_1和第二子时钟线的信号CLK_2的信号。信号CLKD_1、CLKD_2、CLKD_3和CLKD_4分别表示提供给第三子时钟信号线CLKD_1、第四子时钟信号线CLKD_2、第五子时钟信号线CLKD_3和第六子时钟信号线CLKD_4的信号。信号CLKE_1、CLKE_2、CLKE_3和CLKE_4分别表示提供给第七子时钟信号线CLKE_1、第八子时钟信号线CLKE_2、第九子时钟信号线CLKE_3和第十子时钟信号线CLKE_4的信号。
H<1>和H<2>分别表示栅极驱动电路30中第一级移位寄存器A1和第二级移位寄存器A2中的第一控制节点H的电压。N<1>、N<2>分别表示第一级移位寄存器A1和第二级移位寄存器A2中的第二控制节点N的电压。Q<1>和Q<2>分别表示栅极驱动电路30中第一级移位寄存器A1和第二级移位寄存器A2中的下拉节点Q的电压。OUT1<1>、OUT1<2>、OUT1<3>和OUT1<4>分别表示栅极驱动电路30中的第一级移位寄存器A1、第二级移位寄存器A2、第三级移位寄存器A3以及第四级移位寄存器A4中相应的第一驱动信号输出端OUT1。OUT2<1>、OUT2<2>分别表示栅极驱动电路30中的第一级移位寄存器A1、第二级移位寄存器A2中相应的第二驱动信号输出端OUT2。需要说明的是，由于每一级移位寄存器中的移位信号输出端CR和驱动信号输出端OUT1的电压相同，所以在图8中未示出移位信号输出端CR。
需要说明的是，图8所示的信号时序图中的信号电平只是示意性的，不代表真实电平值。
下面结合图8中的信号时序图，对图7中所示的栅极驱动电路30在用于逐行顺序补偿时的工作原理进行说明，例如，图7中所示的栅极驱动电 路20中的移位寄存器可以采用图3中所示的移位寄存器。
在第一帧1F开始前，消隐复位信号线TRST和第二子时钟信号线CLK_2均提供低电平，以向各级移位寄存器的消隐复位信号端TRST和第二时钟信号端CLKB提供低电平，使得各级移位寄存器中的第一晶体管M1和第五晶体管M5导通。将消隐输入信号STU1(高电平的输入信号STU)提供到第一控制节点H，第一控制节点H的电压为高电平，以及将第二电压V2(高电平)提供到下拉节点Q，下拉节点Q的电压为高电平。由此，对各级的第一控制节点H和下拉节点Q进行复位，以实现全局复位。
然后，第一帧1F开始，第三电压V3为高电平，第四电压V4为低电平。消隐复位信号线TRST提供的信号变为高电平，第五晶体管M5关断。
在第一帧1F的显示时段Display中，对第一级的移位寄存器A1的工作过程描述如下。
在第1时段中，第一级移位寄存器的消隐输入信号端STU1和显示输入信号端STU2均和输入信号线STU连接，因此消隐输入信号端STU1和显示输入信号端STU2均提供低电平信号。第二时钟信号端CLKB提供低电平信号，使得第一晶体管M1导通，从而将消隐输入信号STU1提供到第一控制节点H<1>。在此情况下，第一控制节点H<1>的电压为低电平，第一时钟信号CLKA(与第一子时钟信号线CLK_1耦接)为高电平，第二晶体管M2导通，将第一时钟信号CLKA提供到第二控制节点N<1>，使得第二控制节点N<1>的电压为高电平。此外，由于第一时钟信号CLKA为高电平，第三晶体管M3关断，以隔离第一控制节点H<1>和第二控制节点N<1>对下拉节点Q<1>的影响。第一电容C1保持第一控制节点H<1>与第二控制节点N<1>之间的电压差直到消隐时段。
另一方面，第四电压V4为低电平，第十晶体管M10导通，以控制第十二晶体管M12的控制极的电压为低电平。因此，第十二晶体管M12导通，将第二电压V2提供至下拉节点Q<1>，使得下拉节点Q<1>的电压为高电平。由于第1时段中显示输入信号STU2为低电平，第四晶体管M4导通，因此将第一电压V1提供到下拉节点Q<1>，使得下拉节点Q<1>的 电压变为低电平。由此，第八晶体管M8和第十一晶体管M11导通，将第一上拉节点QB_A和第二上拉节点QB_B拉高。此外，下拉节点Q<1>为低电平，使得第十九晶体管M19、第二十二晶体管M22和第二十五晶体管M25导通，将第四时钟信号CLKD(与第三子时钟信号线CLKD_1耦接)和第五时钟信号CLKE(与第七子时钟信号线CLKE_1耦接)相应地提供到移位信号输出端CR<1>、第一驱动信号输出端OUT1<1>和第二驱动信号输出端OUT2<1>，从而分别输出高电平信号。
此外，由于显示输入信号STU2为低电平，第十五晶体管M15和第十八晶体管M18导通，将高电平的第二电压V2分别提供到第一上拉节点QB_A和第二上拉节点QB_B，从而可以对第一上拉节点QB_A和第二上拉节点QB_B进行辅助上拉。
在第2时段中，通过第三子时钟信号线CLKD_1向第四时钟信号端CLKD提供低电平信号，通过第七子时钟信号线CLKE_1向第五时钟信号端CLKE提供低电平信号。由于第二电容C2的存在，使得下拉节点Q<1>的电压由于自举效应而进一步被拉低。第十九晶体管M19、第二十二晶体管M22和第二十五晶体管M25保持导通，从而移位信号输出端CR<1>、第一驱动信号输出端OUT1<1>和第二驱动信号输出端OUT2<1>均输出低电平信号。例如，从移位信号输出端输出的低电平信号可以用于上下级移位寄存器的扫描移位，而从两个驱动信号输出端输出的低电平信号可以用于驱动显示面板中的子像素进行显示。
在第3时段中，下拉节点Q<1>保持低电平，第十九晶体管M19、第二十二晶体管M22和第二十五晶体管M25保持导通。通过第三子时钟信号线CLKD_1向第四时钟信号端CLKD提供高电平信号，通过第七子时钟信号线CLKE_1向第五时钟信号端CLKE提供高电平信号，使得移位信号输出端CR、第一驱动信号输出端OUT1和第二驱动信号输出端OUT2均输出高电平信号。由于移位信号输出端CR<1>、第一驱动信号输出端OUT1<1>和第二驱动信号输出端OUT2<1>被复位至高电平，通过晶体管之间的耦合作用，下拉节点Q<1>的电压会上升一个幅度。此外，由于第一级 移位寄存器A1的显示复位信号端STD和第四级移位寄存器A4的移位信号输出端CR<4>(即，OUT1<4>)连接，此时第四级移位寄存器A4的移位信号输出端CR<4>还未输出低电平信号，所以不会对下拉节点Q<1>进行上拉，使得上拉节点Q<1>可以保持在一个较低的电平。
在第4时段中，第四级移位寄存器A4的移位信号输出端CR<4>输出低电平信号，向第一级移位寄存器A1的显示复位信号端STD提供低电平信号，第六晶体管M6导通，下拉节点Q<1>的电压变为高电平，实现对下拉节点Q<1>的复位。此外，由于下拉节点Q<1>的电压为高电平，第十一晶体管M11关断，第二上拉节点QB_B的电压通过第十晶体管M10而被拉低至低电平。由此，第十二晶体管M12导通，以对下拉节点Q<1>放噪。此外，第二十一晶体管M21、第二十四晶体管M24和第二十七晶体管M27导通，以将第二电压V2提供至移位信号输出端CR<1>、第一驱动信号输出端OUT1<1>和第二驱动信号输出端OUT2<1>，从而分别输出高电平信号。
在上述第一帧的显示时段中，由于第一时钟信号CLKA一直保持为低电平，所以第三晶体管M3保持关断。第三晶体管M3可以隔离第一控制节点H<1>和第二控制节点N<1>处的电压对显示时段的下拉节点Q的影响。
第一级移位寄存器驱动显示面板中第一行的子像素完成显示后，依次类推，第二级、第三级等移位寄存器逐行驱动显示面板中的子像素进行一帧的显示驱动。至此，第一帧的显示时段结束。
在显示时段Display开始时，第一控制节点H<1>被写入低电平并且保持到消隐时段Blank。第二晶体管导通，第一时钟信号CLKA为高电平，因此第二控制节点N<1>被写入高电平并且保持到消隐时段Blank。
在第一帧1F的消隐时段Blank中，对第一级移位寄存器A1的工作过程描述如下。
在第5时段中，第一子时钟信号线CLK_1向第一时钟信号CLKA提供低电平信号，第一控制节点H<1>保持低电平，第二晶体管M2导通。第一时钟信号CLKA被提供到第二控制节点N<1>，以使第二控制节点N<1> 的电压变为低电平。由于第一电容C1保持第一控制节点H<1>和第二控制节点N<1>之间的电压差，因此第一控制节点H<1>的电压也相应地降低，从而可以无损地将第一时钟信号CLKA提供到第二控制节点N<1>，以使得第二控制节点N<1>的电压可达到第一时钟信号CLKA的最低电位无损输出。此外，第三晶体管M3导通，进而将第二控制节点N<1>的电压(无损的第一时钟信号CLKA)提供到下拉节点Q<1>，使得下拉节点Q<1>变为低电平。在此时段，第四时钟信号CLKD和第五时钟信号端CLKE均为高电平信号，使得移位信号输出端CR、第一驱动信号输出端OUT1和第二驱动信号输出端OUT2均输出高电平信号。
在第6时段中，第一子时钟信号线CLK_1向第一时钟信号CLKA提供高电平信号，第二控制节点N<1>的电压变为高电平，经由第一电容C1所保持的电压差，使得第一控制节点H<1>的电压也相应地升高。
在第7时段中，第二子时钟信号线CLK_2向第二时钟信号CLKB提供低电平信号，第一晶体管M1导通，将高电平的消隐输入信号STU1提供到第一控制节点H<1>，已将其拉高至高电平。第二晶体管M2关断，第二控制节点N<1>的电压保持不变。
第三晶体管M3关断，第四时钟信号CLKD和第五时钟信号端CLKE均为低电平信号，移位信号输出端CR<1>、第一驱动信号输出端OUT1<1>和第二驱动信号输出端OUT2<1>均输出低电平信号。经由第二电容C2和第三电容C3的作用，将下拉节点Q<1>的电压再次拉低。
此外，因为第二时钟信号CLKB为低电平，使得第二级移位寄存器中的第一晶体管M1导通，且消隐输入信号STU1<2>耦接第一级移位寄存器A1中的移位信号输出端CR<1>，因此第二级移位寄存器A2中的第一控制节点H<2>的电压降低为低电平。
在第8时段中，第二子时钟信号线CLK_2向第二时钟信号CLKB提供高电平信号，第三子时钟线CLKD_1向第四时钟信号端CLKD提供低电平信号，第七子时钟信号线CLKE_1向第五时钟信号端CLKE提供高电平信号。此时，移位信号输出端CR<1>、第一驱动信号输出端OUT1<1>输 出低电平信号，第二驱动信号输出端OUT2<1>输出高电平信号。第二级移位寄存器A2中的第一晶体管M1关断，第一控制节点H<2>保持低电平直至下一帧的消隐时段BLANK。
在第9时段中，第二时钟信号CLKB保持高电平，第四时钟信号CLKD和第五时钟信号CLKE均为低电平。移位信号输出端CR<1>、第一驱动信号输出端OUT1<1>和第二驱动信号输出端OUT2<1>均输出低电平信号。
由上，在消隐时段的第7-9时段，第一驱动信号输出端OUT1<1>输出低电平的第一驱动信号，以驱动第一行子像素中的感测晶体管(例如，P型晶体管)。由此，第一行子像素中的感测晶体管能够感测该行子像素的驱动电流，从而基于所感测的驱动电流进行补偿。
在第10时段中，第四时钟信号CLKD和第五时钟信号CLKE均变为高电平。移位信号输出端CR<1>、第一驱动信号输出端OUT1<1>和第二驱动信号输出端OUT2<1>均输出高电平信号。在第二电容C2和第三电容C3的控制下，下拉节点Q的电压上升。
在第11时段中，消隐复位信号线TRST向消隐复位信号端TRST提供低电平信号，第五晶体管M5导通，下拉节点Q的电压变为高电平。第四电压为低电平，第十晶体管M10导通，使得第二上拉节点QB_B的电压变为低电平。相应地，第二十一晶体管M21、第二十四晶体管M24和第二十七晶体管M27均导通，移位信号输出端CR<1>、第一驱动信号输出端OUT1<1>和第二驱动信号输出端OUT2<1>分别输出高电平信号。
然后，在第二帧2F、第三帧3F等更多时间段中对栅极驱动电路的驱动可以参考上述描述，这里不再赘述。
如上所述，在每一帧的消隐时段，栅极驱动电路输出的消隐输出信号可用于驱动显示面板中子像素中的感测晶体管。如图所示，该驱动信号是逐行顺序提供的。例如，在第一帧的消隐时段，栅极驱动电路输出用于显示面板第一行子像素的驱动信号。在第二帧的消隐时段，栅极驱动电路输出用于显示面板第二行子像素的驱动信号，依次类推，进行逐行顺序补偿。
另一方面，本公开的实施例还提供包括以上所描述的栅极驱动电路30 的阵列基板和显示装置。在实施例中，显示装置可以为液晶面板、液晶电视、显示器、OLED面板、OLED电视、电子纸显示装置、手机、平板电脑、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
此外，本公开的实施例还提供了用于驱动移位寄存器的方法。图9示出了根据本公开的实施例的用于驱动移位寄存器的方法的示意性流程图。移位寄存器可以是基于本公开实施例的任何可适用的移位寄存器。
在一帧的显示阶段，在步骤910，在来自第二时钟信号端的第二时钟信号CLKB的控制下，将来自消隐输入信号端的消隐输入信号STU1提供到第一控制节点H，并保持在第一控制节点H和第二控制节点N之间的电压差。例如，参见对图8中的第1时段的描述。
在实施例中，可根据来自显示输入信号端的显示输入信号STU2将来自第一电压端的第一电压V1提供到下拉节点Q。例如，参见对图8中的第2时段的描述。
相应地，可根据下拉节点Q的电压，输出显示输出信号。例如，参见对图8中的第3时段的描述。
此外，可根据显示复位信号STD对下拉节点Q进行复位。例如，参见对图8中的第4时段的描述。
在一帧的消隐阶段，在步骤920，可根据第一控制节点H的电压将来自第一时钟信号端的第一时钟信号CLKA提供到第二控制节点N，以及根据第二控制节点N的电压经由所保持的电压差来控制第一控制节点H的电压。由此，可使得第一时钟信号CLKA可被无损输出到第二控制节点N。
在步骤930，可根据第一时钟信号CLKA将第二控制节点N的电压(即无损的第一时钟信号CLKA)提供到下拉节点Q。
步骤920和步骤930例如参见上文中对图8的第5时段的描述。
然后，在第一时钟信号CLKA改变后，第二控制节点N接收第一时钟信号CLKA，因此第二控制节点N的电压改变，进而根据第二控制节点N的电压经由所保持的电压差来控制第一控制节点H的电压。例如参见上文中对图8的第6时段的描述。
在步骤940，根据下拉节点Q的电压，输出移位信号和驱动信号(例如第一驱动信号和第二驱动信号)。此外，在第二时钟信号的控制下，将来自消隐输入信号端的消隐输入信号STU1提供到第一控制节点H，从而控制第一时钟信号不再提供给第二控制节点N。例如参见上文中对图8的第7-10时段的描述。
然后，还可根据消隐复位信号TRST对下拉节点Q进行复位。例如，参见对图8中的第11时段的描述。
本领域技术人员可以理解，以上各步骤虽然按顺序描述，但并不构成对方法顺序的限定，本公开实施例也可以以任何其它合适顺序实施。在实施例中，以上步骤可发生在同一帧的不同时段，也可发生在不同帧的不同时段。例如，第一步骤可发生在第一帧的消隐时段，其它步骤可发生在第二帧的显示时段和消隐时段。本公开对此不进行限制。
以上对本公开的若干实施方式进行了详细描述，但本公开的保护范围并不限于此。显然，对于本领域的普通技术人员来说，在不脱离本公开的精神和范围的情况下，可以对本公开的实施例进行各种修改、替换或变形。本公开的保护范围由所附权利要求限定。

Claims (20)

  1. 一种移位寄存器，包括消隐输入电路、消隐控制电路、消隐下拉电路、以及移位寄存电路；
    其中，所述消隐输入电路被配置为根据来自第二时钟信号端的第二时钟信号将来自消隐输入信号端的消隐输入信号提供到第一控制节点；
    所述消隐控制电路被配置为根据所述第一控制节点的电压将来自第一时钟信号端的第一时钟信号提供到第二控制节点，以及保持在所述第一控制节点和所述第二控制节点之间的电压差；
    所述消隐下拉电路被配置为根据所述第一时钟信号将所述第二控制节点的电压提供到下拉节点；
    所述移位寄存电路被配置为根据所述下拉节点的电压，经由移位信号输出端提供移位信号，以及经由第一驱动信号输出端提供第一驱动信号。
  2. 根据权利要求1所述的移位寄存器，其中，所述消隐控制电路包括第二晶体管和第一电容；
    其中，所述第二晶体管的控制极和所述第一控制节点耦接，所述第二晶体管的第一极和所述第一时钟信号端耦接，所述第二晶体管的第二极和所述第二控制节点耦接；
    所述第一电容被耦接在所述第一控制节点和所述第二控制节点之间。
  3. 根据权利要求1所述的移位寄存器，其中，所述消隐输入电路包括第一晶体管；
    其中，所述第一晶体管的控制极和所述第二时钟信号端耦接，所述第一晶体管的第一极和所述消隐输入信号端耦接，所述第一晶体管的第二极和所述第一控制节点耦接。
  4. 根据权利要求1所述的移位寄存器，其中，所述消隐下拉电路包括第三晶体管；
    其中，所述第三晶体管的控制极和所述第一时钟信号端耦接，所述第三晶体管的第一极和所述第二控制节点耦接，所述第三晶体管的第二极和 所述下拉节点耦接。
  5. 根据权利要求1所述的移位寄存器，其中，所述移位寄存电路包括显示输入电路和输出电路；
    其中，所述显示输入电路被配置为根据来自显示输入信号端的显示输入信号将来自第一电压端的第一电压提供到所述下拉节点；
    所述输出电路被配置为根据所述下拉节点的电压，从所述移位信号输出端输出移位信号，以及从所述第一驱动信号输出端输出第一驱动信号。
  6. 根据权利要求5所述的移位寄存器，其中，所述显示输入电路包括第四晶体管；
    其中，所述第四晶体管的控制极和所述显示输入信号端耦接，所述第四晶体管的第一极和所述第一电压端耦接，所述第四晶体管的第二极和所述下拉节点耦接。
  7. 根据权利要求5所述的移位寄存器，其中，所述输出电路包括：第十九晶体管、第二十二晶体管和第二电容；
    其中，所述第十九晶体管的控制极和所述下拉节点耦接，所述第十九晶体管的第一极和第四时钟信号端耦接以接收第四时钟信号，所述第十九晶体管的第二极和所述移位信号输出端耦接；
    所述第二十二晶体管的控制极和所述下拉节点耦接，所述第二十二晶体管的第一极和所述第四时钟信号端耦接以接收第四时钟信号，所述第二十二晶体管的第二极和所述第一驱动信号输出端耦接；
    所述第二电容被耦接在所述下拉节点和所述移位信号输出端之间。
  8. 根据权利要求5至7中任一项所述的移位寄存器，所述移位寄存电路还包括第一控制电路、上拉电路和第二控制电路；
    其中，所述第一控制电路被配置为根据所述下拉节点的电压控制上拉节点的电压；
    所述上拉电路被配置为根据所述上拉节点的电压，将来自第二电压端的第二电压提供到所述下拉节点、所述移位信号输出端和所述驱动信号输出端；
    所述第二控制电路被配置为根据所述第一时钟信号和所述第一控制节点的电压控制所述上拉节点的电压，以及根据所述显示输入信号控制所述上拉节点的电压。
  9. 根据权利要求8所述的移位寄存器，其中，所述上拉节点包括第一上拉节点；
    其中，所述第一控制电路包括：
    第七晶体管，所述第七晶体管的控制极和第一极和第三电压端耦接，所述第七晶体管的第二极和所述第一上拉节点耦接；以及
    第八晶体管，所述第八晶体管的控制极和所述下拉节点耦接，所述第八晶体管的第一极和所述第一上拉节点耦接，所述第八晶体管的第二极和所述第二电压端耦接；
    其中，所述上拉电路包括：
    第九晶体管，所述第九晶体管的控制极和所述第一上拉节点耦接，所述第九晶体管的第一极和所述下拉节点耦接，所述第九晶体管的第二极和所述第二电压端耦接；
    第二十晶体管，所述第二十晶体管的控制极和所述第一上拉节点耦接，所述第二十晶体管的第一极和所述移位信号输出端耦接，所述第二十晶体管的第二极和所述第二电压端耦接；以及
    第二十三晶体管，所述第二十三晶体管的控制极和所述第一上拉节点耦接，所述第二十三晶体管的第一极和所述第一驱动信号输出端耦接，所述第二十三晶体管的第二极和所述第二电压端耦接；
    其中，所述第二控制电路包括：
    第十三晶体管，所述第十三晶体管的控制极和所述第一时钟信号端耦接，所述第十三晶体管的第一极和所述第一上拉节点耦接；
    第十四晶体管，所述第十四晶体管的控制极和所述第一控制节点耦接，所述第十四晶体管的第一极和所述第十三晶体管的第二极耦接，所述第十四晶体管的第二极和所述第二电压端耦接；以及
    第十五晶体管，所述第十五晶体管的控制极和所述显示输入信号端耦 接，所述第十五晶体管的第一极和所述第一上拉节点耦接，所述第十五晶体管的第二极和所述第二电压端耦接。
  10. 根据权利要求9所述的移位寄存器，其中，所述上拉节点还包括第二上拉节点；
    其中，所述第一控制电路还包括：
    第十晶体管，所述第十晶体管的控制极和第一极和第四电压端耦接，所述第十晶体管的第二极和所述第二上拉节点耦接；以及
    第十一晶体管，所述第十一晶体管的控制极和所述下拉节点耦接，所述第十一晶体管的第一极和所述第二上拉节点耦接，所述第十一晶体管的第二极和所述第二电压端耦接；
    其中，所述上拉电路还包括：
    第十二晶体管，所述第十二晶体管的控制极和所述第二上拉节点耦接，所述第十二晶体管的第一极和所述下拉节点耦接，所述第十二晶体管的第二极和所述第二电压端耦接；
    第二十一晶体管，所述第二十一晶体管的控制极和所述第二上拉节点耦接，所述第二十一晶体管的第一极和所述移位信号输出端耦接，所述二十一晶体管的第二极和所述第二电压端耦接；以及
    第二十四晶体管，所述第二十四晶体管的控制极和所述第二上拉节点耦接，所述第二十四晶体管的第一极和所述第一驱动信号输出端耦接，所述第二十四晶体管的第二极和所述第二电压端耦接；
    其中，所述第二控制电路还包括：
    第十六晶体管，所述第十六晶体管的控制极和第一时钟信号端耦接，所述第十六晶体管的第一极和所述第二上拉节点耦接；
    第十七晶体管，所述第十七晶体管的控制极和所述第一控制节点耦接，所述第十七晶体管的第一极和所述第十六晶体管的第二极耦接，所述第十七晶体管的第二极和所述第二电压端耦接；以及
    第十八晶体管，所述第十八晶体管的控制极和所述显示输入信号端耦接，所述第十八晶体管的第一极和所述第二上拉节点耦接，所述第十八晶 体管的第二极和所述第二电压端耦接。
  11. 根据权利要求8所述的移位寄存器，所述移位寄存电路还包括复位电路；
    其中，所述复位电路被配置为根据来自消隐复位信号端的消隐复位信号对所述下拉节点进行复位，以及根据来自显示复位信号端的显示复位信号对所述下拉节点进行复位。
  12. 根据权利要求11所述的移位寄存器，其中，所述复位电路包括第五晶体管和第六晶体管；
    所述第五晶体管的控制极和所述消隐复位信号端耦接，所述第五晶体管的第一极和所述下拉节点耦接，所述第五晶体管的第二极和所述第二电压端耦接；
    所述第六晶体管的控制极和所述显示复位信号端耦接，所述第六晶体管的第一极和所述下拉节点耦接，所述第六晶体管的第二极和所述第二电压端耦接。
  13. 根据权利要求10所述的移位寄存器，其中，所述输出电路还包括第二十五晶体管和第三电容；
    所述第二十五晶体管的控制极和所述下拉节点耦接，所述第二十五晶体管的第一极和第五时钟信号端耦接以接收第五时钟信号，所述第二十五晶体管的第二极和第二驱动信号输出端耦接；
    所述第三电容被耦接在所述下拉节点和所述第二驱动信号输出端之间。
  14. 根据权利要求13所述的移位寄存器，其中，所述上拉电路还包括第二十六晶体管和第二十七晶体管；
    其中，所述第二十六晶体管的控制极和所述第一上拉节点耦接，所述第二十六晶体管的第一极和所述第二驱动信号输出端耦接，所述第二十六晶体管的第二极和所述第二电压端耦接；
    所述第二十七晶体管的控制极和所述第二上拉节点耦接，所述第二十七晶体管的第一极和所述第二驱动信号输出端耦接，所述第二十七晶体管的第二极和所述第二电压端耦接。
  15. 一种栅极驱动电路，包括N个级联的如权利要求1至14中任一项所述的移位寄存器、第一子时钟信号线和第二子时钟信号线；
    其中，第i+1级移位寄存器的消隐输入信号端和第i级移位寄存器的移位信号输出端耦接
    各级移位寄存器的第一时钟信号端和所述第一子时钟信号线耦接；
    各级移位寄存器的第二时钟信号端和所述第二子时钟信号线耦接；。
  16. 根据权利要求15所述的栅极驱动电路，还包括消隐复位信号线、第一子时钟信号线和第二子时钟信号线；
    其中，第i+2级移位寄存器的显示输入信号端和第i级移位寄存器的移位信号输出端耦接；
    各级移位寄存器的消隐复位信号端和所述消隐复位信号线耦接；
    第i级移位寄存器的显示复位信号端和第i+3级移位寄存器的移位信号输出端耦接。
  17. 根据权利要求15或16所述的栅极驱动电路，还包括第三子时钟信号线、第四子时钟信号线、第五子时钟信号线和第六子时钟信号线；
    其中，第4i-3级移位寄存器的第四时钟信号端和所述第三子时钟信号线耦接；
    第4i-2级移位寄存器的第四时钟信号端和所述第四子时钟信号线耦接；
    第4i-1级移位寄存器的第四时钟信号端和所述第五子时钟信号线耦接；
    第4i级移位寄存器的第四时钟信号端和所述第六子时钟信号线耦接。
  18. 根据权利要求15或16所述的栅极驱动电路，还包括第七子时钟信号线、第八子时钟信号线、第九子时钟信号线和第十子时钟信号线；
    其中，第4i-3级移位寄存器的第五时钟信号端和所述第七子时钟信号线耦接；
    第4i-2级移位寄存器的第五时钟信号端和所述第八子时钟信号线耦接；
    第4i-1级移位寄存器的第五时钟信号端和所述第九子时钟信号线耦接；
    第4i级移位寄存器的第五时钟信号端和所述第十子时钟信号线耦接。
  19. 一种显示装置，包括如权利要求15至18中任一项所述的栅极驱 动电路。
  20. 一种用于驱动如权利要求1至14中任一项所述的移位寄存器的方法，包括：
    将消隐输入信号提供到第一控制节点，保持在所述第一控制节点和第二控制节点之间的电压差；
    根据所述第一控制节点的电压将第一时钟信号提供到所述第二控制节点，以及经由所述电压差控制所述第一控制节点的电压；
    根据所述第一时钟信号将所述第二控制节点的电压提供到所述下拉节点；以及
    根据所述下拉节点的电压，输出移位信号和第一驱动信号。
PCT/CN2019/070966 2019-01-09 2019-01-09 移位寄存器及其驱动方法、栅极驱动电路和显示装置 WO2020142923A1 (zh)

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