WO2017156909A1 - 一种移位寄存器、栅极驱动电路及显示面板 - Google Patents

一种移位寄存器、栅极驱动电路及显示面板 Download PDF

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Publication number
WO2017156909A1
WO2017156909A1 PCT/CN2016/086830 CN2016086830W WO2017156909A1 WO 2017156909 A1 WO2017156909 A1 WO 2017156909A1 CN 2016086830 W CN2016086830 W CN 2016086830W WO 2017156909 A1 WO2017156909 A1 WO 2017156909A1
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Prior art keywords
node
switching transistor
output
shift register
signal end
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PCT/CN2016/086830
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English (en)
French (fr)
Inventor
马占洁
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京东方科技集团股份有限公司
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Priority to US15/531,377 priority Critical patent/US10127862B2/en
Publication of WO2017156909A1 publication Critical patent/WO2017156909A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present invention relates to the field of display technologies, and more particularly to a shift register, a gate drive circuit, and a display panel.
  • the GOA Gate Driver on Array
  • TFT Thin Film Transistor
  • the bonding area of the integrated circuit (IC) and the wiring space of the fan-out area can not only reduce the product cost in terms of material cost and manufacturing process, but also make the display panel Beautiful design with symmetrical and narrow borders on both sides.
  • this integrated process also eliminates the bonding process of the gate scan line direction, thereby increasing throughput and yield.
  • a general gate driving circuit is composed of a plurality of cascaded shift registers, and the scanning signals are sequentially input to the respective gate lines on the display panel through the shift registers of the stages.
  • the number of switching transistors in the current shift register is large, and the structure is relatively complicated, so that a large frame area is still occupied.
  • Embodiments of the present invention provide a shift register, a gate driving circuit, and a display panel for implementing a shift register having a simple structure.
  • a first node control module which is respectively connected to the input signal end, the first clock signal end, the first reference signal end, the first node, and the second node, where the first node control module is used Providing a signal of the input signal end to the first node under control of the first clock signal end, and providing a signal of the first reference signal end to the first node under control of the second node ;
  • a second node control module which is respectively connected to the second reference signal end, the third clock signal end, the first node, and the second node, where the second node control module is used at the third clock signal end Controlling, by the second node, the signal of the second reference signal end to the second node, and providing the signal of the third clock signal end to the second node under the control of the first node;
  • a first output module which is respectively connected to the first node, the second clock signal end, and an output end of the shift register, where the first output module is configured to be used under the control of the first node a signal of the two clock signal ends is provided to the output terminal, and a voltage difference between the first node and the output terminal is stabilized when the first node is in a floating state;
  • a second output module which is respectively connected to the second node, the first reference signal end, and the output end, where the second output module is configured to use the first reference under the control of the second node A signal at the signal end is supplied to the output.
  • the first node control module includes: a first switching transistor and a second switching transistor,
  • a gate of the first switching transistor is connected to the first clock signal terminal, a source is connected to the input signal terminal, and a drain is connected to the first node;
  • a gate of the second switching transistor is connected to the second node, a source is connected to the first reference signal end, and a drain is connected to the first node.
  • the second node control module includes: a third switching transistor and a fourth switching transistor,
  • a gate of the third switching transistor is connected to the third clock signal end, a source is connected to the second reference signal end, and a drain is connected to the second node;
  • the gate of the fourth switching transistor is connected to the first node, the source is connected to the third clock signal end, and the drain is connected to the second node.
  • the first output module includes: a fifth switching transistor and a first capacitor,
  • a gate of the fifth switching transistor is connected to the first node, a source is connected to the second clock signal end, and a drain is connected to the output end;
  • the first capacitor is connected between a gate and a drain of the fifth switching transistor.
  • the second output module includes: a sixth switching transistor
  • the gate of the sixth switching transistor is connected to the second node, the source is connected to the first reference signal end, and the drain is connected to the output end.
  • the second output module further includes a second capacitor connected between the gate and the source of the sixth switching transistor.
  • all of the switching transistors are P-type transistors, or all of the switching transistors are N-type transistors.
  • the embodiment of the present invention further provides a gate driving circuit, comprising a plurality of cascaded shift registers provided by the embodiments of the present invention, wherein
  • the input signal terminal of the first stage shift register is connected to the start signal end;
  • the input signal terminals of the remaining stages of shift registers are connected to the output of the shift register of the previous stage.
  • the embodiment of the invention further provides a display panel comprising the above-mentioned gate driving circuit provided by the embodiment of the invention.
  • the method further includes: an organic electrode illuminating pixel row corresponding to each stage of the shift register in the gate driving circuit; wherein
  • Each of the organic electroluminescent pixel rows emits light under the control of the corresponding light emitting control end, and the light emitting control end corresponding to each of the organic electroluminescent pixel rows is connected to the third clock signal end of the corresponding stage shift register.
  • a shift register, a gate driving circuit and a display panel are provided in the embodiment of the invention, wherein the shift register comprises: a first node control module, a second node control module, a first output module and a second output module.
  • the first node control module is configured to provide the signal of the input signal end to the first node under the control of the first clock signal end, and provide the signal of the first reference signal end to the first node under the control of the second node; Module is used in The signal of the second reference signal end is provided to the second node under the control of the third clock signal end, and the signal of the third clock signal end is provided to the second node under the control of the first node;
  • the first output module is used at the first node Controlling the signal of the second clock signal end to the output end, and stabilizing the voltage difference between the first node and the output end when the first node is in the floating state;
  • the second output module is used under the control of the second node
  • the signal of the first reference signal terminal is supplied to the
  • FIG. 1 is a block diagram showing the structure of a shift register according to an embodiment of the present invention.
  • 2a is a schematic diagram showing a specific structure of a shift register according to an embodiment of the present invention.
  • 2b is a schematic diagram showing a specific structure of a shift register according to another embodiment of the present invention.
  • FIG. 3a is a schematic diagram showing a specific structure of a shift register according to still another embodiment of the present invention.
  • FIG. 3b is a schematic diagram showing the structure of a shift register according to still another embodiment of the present invention.
  • Figure 4a is a circuit timing diagram corresponding to the shift register shown in Figure 3a;
  • Figure 4b is a circuit timing diagram corresponding to the shift register shown in Figure 3b;
  • FIG. 5 is a block diagram showing the structure of a gate driving circuit according to an embodiment of the present invention.
  • a shift register provided by an embodiment of the present invention includes: a first node control module 11 , a second node control module 12 , a first output module 13 , and a second output module 14 .
  • the first node control module 11 is configured to provide the signal of the input signal terminal Input to the first node A under the control of the first clock signal terminal CK1, and provide the signal of the first reference signal terminal Vref1 under the control of the second node B. Give the first node A.
  • the second node control module 12 is connected to the second reference signal terminal Vref2, the third clock signal terminal CK3, the first node A and the second node B, respectively.
  • the second node control module 12 is configured to provide the signal of the second reference signal terminal Vref2 to the second node B under the control of the third clock signal terminal CK3, and the third clock signal terminal CK3 under the control of the first node A The signal is provided to the second node B.
  • the first output module 13 is connected to the first node A, the second clock signal terminal CK2 and the output terminal Output of the shift register, respectively.
  • the first output module 13 is configured to provide the signal of the second clock signal terminal CK2 to the output terminal Output under the control of the first node A, and stabilize the first node A and the output terminal Output when the first node A is in the floating state. The voltage difference between them.
  • the second output module 14 is connected to the second node B, the first reference signal terminal Vref1 and the output terminal, respectively.
  • the second output module 14 is configured to provide a signal of the first reference signal terminal Vref1 to the output terminal Output under the control of the second node B.
  • the above shift register includes a first node control module, a second node control module, a first output module and a second output module.
  • the first node control module is configured to provide the signal of the input signal end to the first node under the control of the first clock signal end, and provide the signal of the first reference signal end to the first node under the control of the second node.
  • the second node control module is configured to provide the signal of the second reference signal end to the second node under the control of the third clock signal end, and provide the signal of the third clock signal end to the second node under the control of the first node.
  • the first output module is configured to provide a signal of the second clock signal end to the output end under the control of the first node, and stabilize the voltage difference between the first node and the output end when the first node is in the floating state.
  • the second output module is configured to provide a signal of the first reference signal end to the output terminal under the control of the second node.
  • the shift register can realize the function of shift output by a simple structure by the cooperation of the above four modules, thereby reducing the production cost.
  • the first node control module 11 includes: a first switching transistor M1 and a second switching transistor M2.
  • the gate of the first switching transistor M1 is connected to the first clock signal terminal CK1, the source is connected to the input signal terminal InpuM, and the drain is connected to the first node A.
  • the gate of the second switching transistor M2 is connected to the second node B, the source is connected to the first reference signal terminal Vref1, and the drain is connected to the first node A.
  • the first switching transistor M1 when the first switching transistor M1 is in an on state under the control of the first clock signal terminal CK1, the first switch crystal M1 that is turned on is input. The signal of the signal terminal Input is supplied to the first node A.
  • the second switching transistor M2 When the second switching transistor M2 is in an on state under the control of the second node B, the turned-on second switching transistor M2 supplies the signal of the first reference signal terminal Vref1 to the first node A.
  • the first switching transistor M1 and the second switching transistor M2 are N-type transistors, or 2b and FIG. 3b, the first switching transistor M1 and the second switching transistor M2 are both P-type transistors, which are not limited herein.
  • the N-type transistor is in an on state when its gate potential is at a high potential, and is in an off state when its gate potential is at a low potential.
  • the P-type transistor is turned on when its gate potential is low, and is turned off when its gate potential is high.
  • the above is only a specific structure of the first node control module in the shift register.
  • the specific structure of the first node control module is not limited to the above structure provided by the embodiment of the present invention, and may be known to those skilled in the art. Other structures are not limited here.
  • the second node control module 12 includes a third switching transistor M3 and a fourth switching transistor M4.
  • the gate of the third switching transistor M3 is connected to the third clock signal terminal CK3, the source is connected to the second reference signal terminal Vref2, and the drain is connected to the second node B.
  • the gate of the fourth switching transistor M4 is connected to the first node A, the source is connected to the third clock signal terminal CK3, and the drain is connected to the second node B.
  • the third switching transistor M3 when the third switching transistor M3 is in an on state under the control of the third clock signal terminal CK3, the turned-on third switching transistor M3 is second.
  • the signal of the reference signal terminal Vref2 is supplied to the second node B; when the fourth switching transistor M4 is in the on state under the control of the first node A, the fourth switching transistor M4 that is turned on will signal the third clock signal terminal CK3.
  • the second node B Provided to the second node B.
  • the above shift register provided by the embodiment of the present invention, as shown in FIG. 2a and FIG. 3a, the third switching transistor M3 and the fourth switching transistor M4 are N-type transistors, or, as shown in FIG. 2b As shown in FIG. 3b, the third switching transistor M3 and the fourth switching transistor M4 are both P-type transistors, which are not limited herein.
  • the above is only a specific structure of the second node control module in the shift register.
  • the specific structure of the second node control module is not limited to the above structure provided by the embodiment of the present invention, and may be known to those skilled in the art. Other structures are not limited here.
  • the first output module 13 includes: a fifth switching transistor M5 and a first capacitor C1.
  • the gate of the fifth switching transistor M5 is connected to the first node A, the source is connected to the second clock signal terminal CK2, and the drain is connected to the output terminal Output.
  • the first capacitor C1 is connected between the gate and the drain of the fifth switching transistor M5.
  • the fifth switching transistor M5 when the fifth switching transistor M5 is in an on state under the control of the first node A, the fifth switching transistor M5 that is turned on will be the second clock signal.
  • the signal of the terminal CK2 is supplied to the output terminal Output.
  • the fifth switching transistor M5 is an N-type transistor, or, for example, As shown in FIG. 2b and FIG. 3b, the fifth switching transistor M5 is a P-type transistor, which is not limited herein.
  • the above is only a specific structure of the first output module in the shift register.
  • the specific structure of the first output module is not limited to the above structure provided by the embodiment of the present invention, and may be other known to those skilled in the art. Structure, not limited here.
  • the second output module 14 includes: a sixth switching transistor M6.
  • the gate of the sixth switching transistor M6 is connected to the second node B, the source is connected to the first reference signal terminal Vref1, and the drain is connected to the output terminal Output.
  • the sixth switching transistor M6 when the sixth switching transistor M6 is in an on state under the control of the second node B, the sixth switching transistor M6 that is turned on sets the first reference signal.
  • the signal of the terminal Vref1 is supplied to the output terminal Output.
  • the sixth switching transistor M6 is an N-type transistor, or, as shown in FIG. 2b, the sixth switching transistor M6 is P.
  • the transistor is not limited herein.
  • the second output module 14 further includes a sixth switch.
  • the above is only a specific structure of the second output module in the shift register.
  • the specific structure of the second output module is not limited to the above structure provided by the embodiment of the present invention, and may be other known to those skilled in the art. Structure, not limited here.
  • the switching transistor mentioned in the above embodiment of the present invention may be a thin film transistor (TFT) or a metal oxide semiconductor field effect transistor (MOS), which is not limited herein. .
  • TFT thin film transistor
  • MOS metal oxide semiconductor field effect transistor
  • the source and the drain of these switching transistors are interchangeable according to the type of the transistor and the input signal, and no specific distinction is made here.
  • the polarities of all the switching transistors are designed to be the same.
  • all switching transistors (M1, M2, M3, M4, M5 and M6) are N
  • the switching transistors when all the switching transistors (M1, M2, M3, M4, M5, and M6) are N-type transistors, the first The potential of a reference signal terminal Vref1 is a low potential, and the potential of the second reference signal terminal Vref2 is a high potential.
  • the switching transistors when all the switching transistors (M1, M2, M3, M4, M5, and M6) are P-type transistors, the potential of the first reference signal terminal Vref1 is high, and the second reference signal terminal The potential of Vref2 is low.
  • the operation of the shift register shown in FIG. 3a is described as an example.
  • all of the switching transistors are N-type switching transistors.
  • the potential of the first reference signal terminal Vref1 is a low potential
  • the potential of the second reference signal terminal Vref2 is a high potential.
  • Corresponding input and output timing diagram is shown in FIG. 4a. Specifically, the first stage T1, the second stage T2, the third stage T3, the fourth stage T4 and the fifth in the input/output timing diagram shown in FIG. 4a are selected. Five stages of phase T5.
  • the second node B controls the sixth switching transistor M6 and the second switching transistor M2 to be turned on, and the turned-on second switching transistor M2 supplies the low potential signal of the first reference signal terminal Verf1 to the first node A, so the first node A The potential is low and is held by the first capacitor C1.
  • the tube M6 supplies the low potential signal of the first reference signal terminal Verf1 to the output terminal Output, so that the potential of the output terminal Output is low.
  • the first node A controls the fourth switching transistor M4 and the fifth switching transistor M5 to be turned on, and the turned-on fourth switching transistor M4 supplies the low potential signal of the third clock signal terminal CK3 to the second node B, thus the second node B The potential is low and is held by the second capacitor C2.
  • the fifth switching transistor M5 turned on under the control of the first node A supplies the low potential signal of the second clock signal terminal CK2 to the output terminal Output, so that the potential of the output terminal Output is low.
  • the fourth switching transistor M4 is turned on, and the turned-on fourth switching transistor M4 supplies the low potential signal of the third clock signal terminal CK3 to the second node B. Therefore, the potential of the second node B is low and is held by the second capacitor C2, and the sixth switching transistor M6 is turned off.
  • the turned-on third switching transistor M3 supplies the high potential signal of the second reference signal terminal Vref2 to the second node B, so that the potential of the second node B is high and is held by the second capacitor C2.
  • the second node B controls the second switching transistor M2 and the sixth switching transistor M6 to be turned on.
  • the turned-on second switching transistor M2 supplies the low potential signal of the first reference signal terminal Vref1 to the first node A, further ensuring that the fourth switching transistor M4 and the fifth switching transistor M5 are turned off.
  • the turned-on sixth switching transistor M6 supplies the low potential signal of the first reference signal terminal Vref1 to the output terminal Output, so that the potential of the output terminal Output is low.
  • the second node B controls the sixth switching transistor M6 and the second switching transistor M2 to be turned on, and the turned-on second switching transistor M2 supplies the low potential signal of the first reference signal terminal Verf1 to the first node A, so the first node A The potential is low and is held by the first capacitor C1.
  • the sixth switching transistor M6 turned on under the control of the second node B supplies the low potential signal of the first reference signal terminal Verf1 to the output terminal Output, so that the potential of the output terminal Output is low.
  • the fourth phase and the fifth phase are repeatedly executed to ensure that the potential of the output terminal is kept low.
  • the operation of the shift register shown in FIG. 3b is taken as an example.
  • all the switching transistors are P-type switching transistors.
  • the potential of the first reference signal terminal Vref1 is at a high potential, and the potential of the second reference signal terminal Vref2 is at a low potential.
  • Corresponding input and output timing diagram is shown in FIG. 4b. Specifically, the first stage T1, the second stage T2, the third stage T3, the fourth stage T4 and the fifth in the input/output timing diagram shown in FIG. 4b are selected. Five stages of phase T5.
  • the second node B controls the sixth switching transistor M6 and the second switching transistor M2 to be turned on, and the turned-on second switching transistor M2 supplies the high potential signal of the first reference signal terminal Verf1 to the first node A, so the first node A
  • the potential is high and is held by the first capacitor C1.
  • the sixth switching transistor M6 turned on under the control of the second node B supplies the high potential signal of the first reference signal terminal Verf1 to the output terminal Output, so that the potential of the output terminal Output is high.
  • the first node A controls the fourth switching transistor M4 and the fifth switching transistor M5 to be turned on, and the turned-on fourth switching transistor M4 supplies the high potential signal of the third clock signal terminal CK3 to the second node B, thus the second node B The potential is high and is held by the second capacitor C2.
  • the fifth switching transistor M5 turned on under the control of the first node A supplies the high potential signal of the second clock signal terminal CK2 to the output terminal Output, so that the potential of the output terminal Output is high.
  • the pass is more sufficient to completely input the low potential signal of the second clock signal terminal CK2 to the output terminal Output.
  • the fourth switching transistor M4 since the potential of the first node A is low, the fourth switching transistor M4 is turned on, and the turned-on fourth switching transistor M4 supplies the high potential signal of the third clock signal terminal CK3 to the second node B, Therefore, the potential of the second node B is high and is held by the second capacitor C2, and the sixth switching transistor M6 is turned off.
  • the second node B controls the second switching transistor M2 and the sixth switching transistor M6 to be turned on.
  • the turned-on second switching transistor M2 supplies the high potential signal of the first reference signal terminal Vref1 to the first node A, further ensuring that the fourth switching transistor M4 and the fifth switching transistor M5 are turned off.
  • the turned-on sixth switching transistor M6 supplies the high potential signal of the first reference signal terminal Vref1 to the output terminal Output, so that the potential of the output terminal Output is high.
  • the second node B controls the sixth switching transistor M6 and the second switching transistor M2 to be turned on, and the turned-on second switching transistor M2 supplies the high potential signal of the first reference signal terminal Verf1 to the first node A, so the first node A The potential is high and is held by the first capacitor C1.
  • the sixth switching transistor M6 turned on under the control of the second node B supplies the high potential signal of the first reference signal terminal Verf1 to the output terminal Output, so that the potential of the output terminal Output is high.
  • an embodiment of the present invention further provides a gate driving circuit, as shown in FIG. 5, including a plurality of cascaded shift registers: SR(1), SR(2), ...SR(n )...SR(N-1), SR(N) (N total shift registers, 1 ⁇ n ⁇ N), input signal terminal Input and start signal terminal of the first stage shift register SR(1)
  • the STV is connected, except for the first stage shift register SR(1), the input signal terminals Input of the remaining stages of the shift register SR(n) and the output terminal Output_n of the upper stage shift register SR(n-1), respectively. -1 is connected.
  • each shift register in the above-mentioned gate driving circuit is the same as the above-mentioned shift register of the present invention, and the details are not described again.
  • an embodiment of the present invention further provides a display panel including the above-described gate driving circuit provided by the embodiment of the present invention.
  • the display panel can be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • Other indispensable components of the display panel are understood by those of ordinary skill in the art, and the description thereof is not to be construed as limiting the invention.
  • the display panel provided by the embodiment of the present invention may be a liquid crystal display panel or an organic electroluminescent display panel, which is not limited herein.
  • organic electroluminescent pixels arranged in a matrix are generally disposed, and each row of organic electroluminescent pixels is generally displayed in a light-emitting display.
  • data writing is first performed under the control of the scanning signal, and then displayed under the control of the light-emitting control terminal according to the written data. Therefore, in one frame time, the signal of the light-emitting control terminal controls the organic electroluminescent pixel to be turned off only for a short period of time, and the other time is to control the illumination of the organic electroluminescent pixel, thereby ensuring the organic electroluminescent pixel.
  • the light is displayed during the display period.
  • the gate scan signal for controlling the writing of the organic electroluminescence pixel data starts to be output to write the data voltage signal into the organic electroluminescence pixel.
  • the signal control of the light-emitting control terminal starts to control the illumination of the organic electroluminescent pixel, and the organic electroluminescence The pixel emits the brightness controlled by the written data voltage signal.
  • the organic electrode illuminating pixel row corresponding to each stage shift register in the gate driving circuit is further included.
  • Each of the organic electroluminescent pixel rows emits light under the control of the corresponding light emitting control end, and the light emitting control end corresponding to each of the organic electroluminescent pixel rows is connected to the third clock signal end of the corresponding stage shift register. That is, the light-emitting control end corresponding to each organic electroluminescent pixel row is used as the third clock signal end of the shift register of the corresponding stage in the gate driving circuit, thereby reducing the setting of the signal line and making the gate driving circuit in the display panel
  • the structure is relatively simple.
  • Embodiments of the present invention provide a shift register, a gate driving circuit, and a display panel.
  • the shift register includes: a first node control module, a second node control module, a first output module, and a second output module.
  • the first node control module is configured to provide the signal of the input signal end to the first node under the control of the first clock signal end, and provide the signal of the first reference signal end to the first node under the control of the second node.
  • the second node control module is configured to provide the signal of the second reference signal end to the second node under the control of the third clock signal end, and provide the signal of the third clock signal end to the second node under the control of the first node.
  • the first output module is configured to provide a signal of the second clock signal end to the output end under the control of the first node, and stabilize the voltage difference between the first node and the output end when the first node is in the floating state.
  • the second output module is configured to provide a signal of the first reference signal end to the output terminal under the control of the second node.
  • the shift register can realize the function of shift output by a simple structure by the cooperation of the above four modules, thereby reducing the production cost.

Abstract

一种移位寄存器、栅极驱动电路及显示面板，在移位寄存器中，第一节点控制模块11在第一时钟信号端CK1的控制下将输入信号端Input的信号提供给第一节点A，在第二节点B的控制下将第一参考信号端Vref1的信号提供给第一节点A；第二节点控制模块12在第三时钟信号端CK3的控制下将第二参考信号端Vref2的信号提供给第二节点B，在第一节点A的控制下将第三时钟信号端CK3的信号提供给第二节点B；第一输出模块13在第一节点A的控制下将第二时钟信号端CK2的信号提供给输出端Output，在第一节点A处于浮接状态时稳定第一节点A与输出端Output之间的电压差；第二输出模块14在第二节点B的控制下将第一参考信号端Vref1的信号提供给输出端Output。通过四个模块的相互配合，能够通过简单的结构实现移位输出的功能。

Description

一种移位寄存器、栅极驱动电路及显示面板 技术领域
本发明涉及显示技术领域，更具体地涉及一种移位寄存器、栅极驱动电路及显示面板。
背景技术
随着显示技术的飞速发展，显示器越来越向着高集成度和低成本的方向发展。其中，GOA(Gate Driver on Array，阵列基板行驱动)技术将TFT(Thin Film Transistor，薄膜晶体管)栅极开关电路集成在显示面板的阵列基板上以形成对显示面板的扫描驱动，从而可以省去栅极集成电路(IC，Integrated Circuit)的绑定(Bonding)区域以及扇出(Fan-out)区域的布线空间，不仅可以在材料成本和制作工艺两方面降低产品成本，而且可以使显示面板做到两边对称和窄边框的美观设计。并且，这种集成工艺还可以省去栅极扫描线方向的绑定工艺，从而提高了产能和良率。
一般的栅极驱动电路均是由多个级联的移位寄存器组成，通过各级移位寄存器实现依次向显示面板上的各行栅线输入扫描信号。但是目前的移位寄存器中开关晶体管的个数较多，结构比较复杂，因此仍会占用较大的边框面积。
发明内容
本发明实施例提供了一种移位寄存器、栅极驱动电路及显示面板，用以实现一种结构简单的移位寄存器。
本发明实施例提供的一种移位寄存器，包括：
第一节点控制模块，分别与输入信号端、第一时钟信号端、第一参考信号端、第一节点和第二节点相连，所述第一节点控制模块用于 在所述第一时钟信号端的控制下将所述输入信号端的信号提供给所述第一节点，在所述第二节点的控制下将所述第一参考信号端的信号提供给所述第一节点；
第二节点控制模块，分别与第二参考信号端、第三时钟信号端、所述第一节点和所述第二节点相连，所述第二节点控制模块用于在所述第三时钟信号端的控制下将所述第二参考信号端的信号提供给所述第二节点，在所述第一节点的控制下将所述第三时钟信号端的信号提供给所述第二节点；
第一输出模块，分别与所述第一节点、第二时钟信号端和所述移位寄存器的输出端相连，所述第一输出模块用于在所述第一节点的控制下将所述第二时钟信号端的信号提供给所述输出端，在所述第一节点处于浮接状态时稳定所述第一节点与所述输出端之间的电压差；以及
第二输出模块，分别与所述第二节点、所述第一参考信号端和所述输出端相连，所述第二输出模块用于在所述第二节点的控制下将所述第一参考信号端的信号提供给所述输出端。
较佳地，在本发明实施例提供的上述移位寄存器中，所述第一节点控制模块包括：第一开关晶体管和第二开关晶体管，
所述第一开关晶体管的栅极与所述第一时钟信号端相连，源极与所述输入信号端相连，漏极与所述第一节点相连；并且
第二开关晶体管的栅极与所述第二节点相连，源极与所述第一参考信号端相连，漏极与所述第一节点相连。
较佳地，在本发明实施例提供的上述移位寄存器中，所述第二节点控制模块包括：第三开关晶体管和第四开关晶体管，
所述第三开关晶体管的栅极与所述第三时钟信号端相连，源极与所述第二参考信号端相连，漏极与所述第二节点相连；并且
所述第四开关晶体管的栅极与所述第一节点相连，源极与所述第三时钟信号端相连，漏极与所述第二节点相连。
较佳地，在本发明实施例提供的上述移位寄存器中，所述第一输出模块包括：第五开关晶体管和第一电容器，
所述第五开关晶体管的栅极与所述第一节点相连，源极与所述第二时钟信号端相连，漏极与所述输出端相连；并且
所述第一电容器连接于所述第五开关晶体管的栅极与漏极之间。
较佳地，在本发明实施例提供的上述移位寄存器中，所述第二输出模块包括：第六开关晶体管，
所述第六开关晶体管的栅极与所述第二节点相连，源极与所述第一参考信号端相连，漏极与所述输出端相连。
较佳地，在本发明实施例提供的上述移位寄存器中，所述第二输出模块还包括连接于所述第六开关晶体管的栅极与源极之间的第二电容器。
较佳地，在本发明实施例提供的上述移位寄存器中，所有开关晶体管均为P型晶体管，或所有开关晶体管均为N型晶体管。
相应地，本发明实施例还提供了一种栅极驱动电路，包括多个级联的本发明实施例提供的上述任一种移位寄存器，其中，
第一级移位寄存器的输入信号端与起始信号端相连；并且
除第一级移位寄存器之外，其余各级移位寄存器的输入信号端均与上一级移位寄存器的输出端相连。
相应地，本发明实施例还提供了一种显示面板，包括本发明实施例提供的上述栅极驱动电路。
较佳地，在本发明实施例提供的上述显示面板中，还包括：与所述栅极驱动电路中的各级移位寄存器一一对应的有机电极发光像素行；其中
各有机电致发光像素行在对应的发光控制端的控制下发光，且与各有机电致发光像素行对应的发光控制端与对应级移位寄存器的第三时钟信号端相连。
本发明实施例提供的一种移位寄存器、栅极驱动电路及显示面板，其中移位寄存器包括：第一节点控制模块，第二节点控制模块，第一输出模块和第二输出模块。第一节点控制模块用于在第一时钟信号端的控制下将输入信号端的信号提供给第一节点，在第二节点的控制下将第一参考信号端的信号提供给第一节点；第二节点控制模块用于在 第三时钟信号端的控制下将第二参考信号端的信号提供给第二节点，在第一节点的控制下将第三时钟信号端的信号提供给第二节点；第一输出模块用于在第一节点的控制下将第二时钟信号端的信号提供给输出端，在第一节点处于浮接状态时稳定第一节点与输出端之间的电压差；第二输出模块用于在第二节点的控制下将第一参考信号端的信号提供给输出端。移位寄存器通过上述四个模块的相互配合，能够通过简单的结构实现移位输出的功能，从而可以降低生产成本。
附图说明
图1示出了根据本发明实施例的移位寄存器的结构示意图；
图2a示出了根据本发明实施例的移位寄存器的具体结构示意图；
图2b示出了根据本发明另一实施例的移位寄存器的具体结构示意图；
图3a示出了根据本发明又一实施例的移位寄存器的具体结构示意图；
图3b示出了根据本发明再一实施例的移位寄存器的具体结构示意图
图4a是与图3a中示出的移位寄存器的对应的电路时序图；
图4b是与图3b中示出的移位寄存器的对应的电路时序图；
图5示出了根据本发明实施例的栅极驱动电路的结构示意图。
具体实施方式
下面结合附图，对本发明实施例提供的移位寄存器、栅极驱动电路及显示面板的具体实施方式进行详细的说明。
如图1所示，本发明实施例提供的一种移位寄存器包括：第一节点控制模块11，第二节点控制模块12，第一输出模块13和第二输出模块14。
第一节点控制模块11分别与输入信号端Input、第一时钟信号端 CK1、第一参考信号端Vref1、第一节点A和第二节点B相连。第一节点控制模块11用于在第一时钟信号端CK1的控制下将输入信号端Input的信号提供给第一节点A，在第二节点B的控制下将第一参考信号端Vref1的信号提供给第一节点A。
第二节点控制模块12分别与第二参考信号端Vref2、第三时钟信号端CK3、第一节点A和第二节点B相连。第二节点控制模块12用于在第三时钟信号端CK3的控制下将第二参考信号端Vref2的信号提供给第二节点B，在第一节点A的控制下将第三时钟信号端CK3的信号提供给第二节点B。
第一输出模块13分别与第一节点A、第二时钟信号端CK2和移位寄存器的输出端Output相连。第一输出模块13用于在第一节点A的控制下将第二时钟信号端CK2的信号提供给输出端Output，在第一节点A处于浮接状态时稳定第一节点A与输出端Output之间的电压差。
第二输出模块14分别与第二节点B、第一参考信号端Vref1和输出端相连Output。第二输出模块14用于在第二节点B的控制下将第一参考信号端Vref1的信号提供给输出端Output。
本发明实施例提供的上述移位寄存器包括第一节点控制模块，第二节点控制模块，第一输出模块和第二输出模块。第一节点控制模块用于在第一时钟信号端的控制下将输入信号端的信号提供给第一节点，在第二节点的控制下将第一参考信号端的信号提供给第一节点。第二节点控制模块用于在第三时钟信号端的控制下将第二参考信号端的信号提供给第二节点，在第一节点的控制下将第三时钟信号端的信号提供给第二节点。第一输出模块用于在第一节点的控制下将第二时钟信号端的信号提供给输出端，在第一节点处于浮接状态时稳定第一节点与输出端之间的电压差。第二输出模块用于在第二节点的控制下将第一参考信号端的信号提供给输出端。移位寄存器通过上述四个模块的相互配合，能够通过简单的结构实现移位输出的功能，从而可以降低生产成本。
下面结合具体实施例，对本发明进行详细说明。需要说明的是， 本实施例中是为了更好的解释本发明，但不限制本发明。
较佳地，在本发明实施例提供的上述移位寄存器中，如图2a至图3b所示，第一节点控制模块11包括：第一开关晶体管M1和第二开关晶体管M2。
第一开关晶体管M1的栅极与第一时钟信号端CK1相连，源极与输入信号端InpuM相连，漏极与第一节点A相连。
第二开关晶体管M2的栅极与第二节点B相连，源极与第一参考信号端Vref1相连，漏极与第一节点A相连。
在具体实施时，本发明实施例提供的上述移位寄存器中，当第一开关晶体管M1在第一时钟信号端CK1的控制下处于导通状态时，导通的第一开关晶体M1管将输入信号端Input的信号提供给第一节点A。当第二开关晶体管M2在第二节点B的控制下处于导通状态时，导通的第二开关晶体管M2将第一参考信号端Vref1的信号提供给第一节点A。
进一步地，在具体实施时，本发明实施例提供的上述移位寄存器中，如图2a和图3a所示，第一开关晶体管M1和第二开关晶体管M2均为N型晶体管，或者，如图2b和图3b所示，第一开关晶体管M1和第二开关晶体管M2均为P型晶体管，在此不作限定。
具体地，N型晶体管在其栅极电位为高电位时处于导通状态，在其栅极电位为低电位时处于截止状态。P型晶体管在其栅极电位为低电位时处于导通状态，在其栅极电位为高电位时处于截止状态。
以上仅是举例说明移位寄存器中第一节点控制模块的具体结构，在具体实施时，第一节点控制模块的具体结构不限于本发明实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不做限定。
较佳地，在本发明实施例提供的上述移位寄存器中，如图2a至图3b所示，第二节点控制模块12包括第三开关晶体管M3和第四开关晶体管M4。
第三开关晶体管M3的栅极与第三时钟信号端CK3相连，源极与第二参考信号端Vref2相连，漏极与第二节点B相连。
第四开关晶体管M4的栅极与第一节点A相连，源极与第三时钟信号端CK3相连，漏极与第二节点B相连。
在具体实施时，本发明实施例提供的上述移位寄存器中，当第三开关晶体管M3在第三时钟信号端CK3的控制下处于导通状态时，导通的第三开关晶体管M3将第二参考信号端Vref2的信号提供给第二节点B；当第四开关晶体管M4在第一节点A的控制下处于导通状态时，导通的第四开关晶体管M4将第三时钟信号端CK3的信号提供给第二节点B。
进一步地，在具体实施时，本发明实施例提供的上述移位寄存器，如图2a和图3a所示，第三开关晶体管M3和第四开关晶体管M4均为N型晶体管，或者，如图2b和图3b所示，第三开关晶体管M3和第四开关晶体管M4均为P型晶体管，在此不作限定。
以上仅是举例说明移位寄存器中第二节点控制模块的具体结构，在具体实施时，第二节点控制模块的具体结构不限于本发明实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不做限定。
较佳地，在本发明实施例提供的上述移位寄存器中，如图2a至图3b所示，第一输出模块13包括：第五开关晶体管M5和第一电容器C1.
第五开关晶体管M5的栅极与第一节点A相连，源极与第二时钟信号端CK2相连，漏极与输出端Output相连。
第一电容器C1连接于第五开关晶体管M5的栅极与漏极之间。
在具体实施时，本发明实施例提供的上述移位寄存器中，当第五开关晶体管M5在第一节点A的控制下处于导通状态时，导通的第五开关晶体管M5将第二时钟信号端CK2的信号提供给输出端Output。当第一节点A处于浮接状态时，由于第一电容器C1的自举作用，第一节点A的电位随着输出端Output的电位的改变而改变，从而使第一节点A与输出端Output之间的电压差保持稳定。
进一步地，在具体实施时，本发明实施例提供的上述移位寄存器，如图2a和图3a所示，第五开关晶体管M5为N型晶体管，或者，如 图2b和图3b所示，第五开关晶体管M5为P型晶体管，在此不作限定。
以上仅是举例说明移位寄存器中第一输出模块的具体结构，在具体实施时，第一输出模块的具体结构不限于本发明实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不做限定。
较佳地，在本发明实施例提供的上述移位寄存器中，如图2a和图2b所示，第二输出模块14包括：第六开关晶体管M6。
第六开关晶体管M6的栅极与第二节点B相连，源极与第一参考信号端Vref1相连，漏极与输出端Output相连。
在具体实施时，本发明实施例提供的上述移位寄存器中，当第六开关晶体管M6在第二节点B的控制下处于导通状态时，导通的第六开关晶体管M6将第一参考信号端Vref1的信号提供给输出端Output。
进一步地，在具体实施时，本发明实施例提供的上述移位寄存器，如图2a所示，第六开关晶体管M6为N型晶体管，或者，如图2b所示，第六开关晶体管M6为P型晶体管，在此不作限定。
较佳地，为了稳定第六开关晶体管M6的栅极电压，在本发明实施例提供的上述移位寄存器中，如图3a和图3b所示，第二输出模块14还包括连接于第六开关晶体管M6的栅极与源极之间的第二电容器C2。
以上仅是举例说明移位寄存器中第二输出模块的具体结构，在具体实施时，第二输出模块的具体结构不限于本发明实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不做限定。
需要说明的是本发明上述实施例中提到的开关晶体管可以是薄膜晶体管(TFT，Thin Film Transistor)，也可以是金属氧化物半导体场效应管(MOS，Metal Oxide Scmiconductor)，在此不做限定。在具体实施中，这些开关晶体管的源极和漏极根据晶体管类型以及输入信号的不同，其功能可以互换，在此不做具体区分。
较佳地，为了简化在本发明实施例提供的上述移位寄存器中，为了简化制作工艺，将所有开关晶体管的极性设计为相同。如图2a和图3a所示，所有开关晶体管(M1、M2、M3、M4、M5和M6)均为N 型晶体管，或如图2b和图3b所示，所有开关晶体管(M1、M2、M3、M4、M5和M6)均为P型晶体管。
进一步地，在本发明实施例提供的上述移位寄存器中，如图2a和图3a所示，当所有开关晶体管(M1、M2、M3、M4、M5和M6)均为N型晶体管时，第一参考信号端Vref1的电位为低电位，第二参考信号端Vref2的电位为高电位。如图2b和图3b所示，当所有开关晶体管(M1、M2、M3、M4、M5和M6)均为P型晶体管时，第一参考信号端Vref1的电位为高电位，第二参考信号端Vref2的电位为低电位。
下面结合电路时序图对本发明实施例提供的上述移位寄存器的工作过程作以描述。下述描述中以1表示高电位信号，0表示低电位信号，其中，1和0代表其逻辑电位，仅是为了更好的解释本发明实施例提供的上述移位寄存器的工作过程，而不是在具体实施时施加在各开关晶体管的栅极上的电位。
实施例一
以图3a所示的移位寄存器的结构为例对其工作过程作以描述，其中，在图3a所示的移位寄存器中，所有开关晶体管均为N型开关晶体管。第一参考信号端Vref1的电位为低电位，第二参考信号端Vref2的电位为高电位。对应的输入输出时序图如图4a所示，具体地，选取如图4a所示的输入输出时序图中的第一阶段T1、第二阶段T2、第三阶段T3、第四阶段T4和第五阶段T5五个阶段。
在第一阶段T1，Input＝0，CK1＝0，CK2＝1，CK3＝1。
由于CK3＝1，第三开关晶体管M3导通，导通的第三开关晶体管M3将第二参考信号端Verf2的高电位信号提供给第二节点B，因此第二节点B的电位为高电位，并通过第二电容器C2进行保持。第二节点B控制第六开关晶体管M6和第二开关晶体管M2导通，导通的第二开关晶体管M2将第一参考信号端Verf1的低电位信号提供给第一节点A，因此第一节点A的电位为低电位，并通过第一电容器C1进行保持。第一节点A控制第五开关晶体管截止。由于CK1＝0，因此第一开关晶体管M1截止。在第二节点B的控制下导通的第六开关晶体 管M6将第一参考信号端Verf1的低电位信号提供给输出端Output，因此输出端Output的电位为低电位。
在第二阶段T2，Input＝1，CK1＝1，CK2＝0，CK3＝0。
由于CK1＝1，第一开关晶体管M1导通，导通的第一开关晶体管M1将输入信号端Input的高电位信号提供给第一节点A，因此第一节点A的电位为高电位，并通过第一电容器C1进行保持。第一节点A控制第四开关晶体管M4和第五开关晶体管M5导通，导通的第四开关晶体管M4将第三时钟信号端CK3的低电位信号提供第二节点B，因此第二节点B的电位为低电位，并通过第二电容器C2进行保持。第二节点B控制第二开关晶体管M2和第六开关晶体管M6截止。由于CK3＝0，因此第三开关晶体管M3截止。在第一节点A的控制下导通的第五开关晶体管M5将第二时钟信号端CK2的低电位信号提供给输出端Output，因此输出端Output的电位为低电位。
在第三阶段T3，Input＝0，CK1＝0，CK2＝1，CK3＝0。
由于CK1＝0，因此第一开关晶体管M1截止。由于CK3＝0，因此第三开关晶体管M3截止。由于第一节点A处于浮接状态(Floating)，因此第一节点A的电位仍为高电位，第二开关晶体管M2导通，导通的第二开关晶体管M2将第二时钟信号端CK2的高电位信号提供给输出端Output，因此输出端Output的电位为高电位。由于第一电容器C1的自举作用，输出端Output的电位由T2阶段的低电位变为高电位，因此第一节点A的电位进一步被拉高，以保证第二开关晶体管M2的导通更加充分，以使第二时钟信号端CK2的高电位信号完整输入到输出端Output。在此阶段，由于第一节点A的电位为高电位，因此第四开关晶体管M4导通，导通的第四开关晶体管M4将第三时钟信号端CK3的低电位信号提供给第二节点B，因此第二节点B的电位为低电位，并通过第二电容器C2进行保持，第六开关晶体管M6截止。
在第四阶段T4，Input＝0，CK1＝1，CK2＝0，CK3＝1。
由于CK1＝1，第一开关晶体管M1导通，导通的第一开关晶体管M1将输入信号端Input的低电位信号提供给第一节点A，因此第一节点A的电位为低电位，并通过第一电容器C1进行保持。第一节点A 控制第四开关晶体管M4和第五开关晶体管截止。由于CK3＝1，因此第三开关晶体管M3导通。导通的第三开关晶体管M3将第二参考信号端Vref2的高电位信号提供给第二节点B，因此第二节点B的电位为高电位，并通过第二电容器C2进行保持。第二节点B控制第二开关晶体管M2和第六开关晶体管M6导通。导通的第二开关晶体管M2将第一参考信号端Vref1的低电位信号提供给第一节点A，进一步保证第四开关晶体管M4和第五开关晶体管M5截止。导通的第六开关晶体管M6将第一参考信号端Vref1的低电位信号提供给输出端Output，因此输出端Output的电位为低电位。
在第五阶段T5，Input＝0，CK1＝0，CK2＝1，CK3＝1。
由于CK3＝1，第三开关晶体管M3导通，导通的第三开关晶体管M3将第二参考信号端Verf2的高电位信号提供给第二节点B，因此第二节点B的电位为高电位，并通过第二电容器C2进行保持。第二节点B控制第六开关晶体管M6和第二开关晶体管M2导通，导通的第二开关晶体管M2将第一参考信号端Verf1的低电位信号提供给第一节点A，因此第一节点A的电位为低电位，并通过第一电容器C1进行保持。第一节点A控制第五开关晶体管截止。由于CK1＝0，因此第一开关晶体管截止。在第二节点B的控制下导通的第六开关晶体管M6将第一参考信号端Verf1的低电位信号提供给输出端Output，因此输出端Output的电位为低电位。
在本发明实施例提供的上述移位寄存器中，在第五阶段之后，一直重复执行第四阶段和第五阶段的工作过程，以保证输出端的电位保持为低电位。
实施例二
以图3b所示的移位寄存器的结构为例对其工作过程作以描述，其中，在图3b所示的移位寄存器中，所有开关晶体管均为P型开关晶体管。第一参考信号端Vref1的电位为高电位，第二参考信号端Vref2的电位为低电位。对应的输入输出时序图如图4b所示，具体地，选取如图4b所示的输入输出时序图中的第一阶段T1、第二阶段T2、第三阶段T3、第四阶段T4和第五阶段T5五个阶段。
在第一阶段T1，Input＝1，CK1＝1，CK2＝0，CK3＝0。
由于CK3＝0，第三开关晶体管M3导通，导通的第三开关晶体管M3将第二参考信号端Verf2的低电位信号提供给第二节点B，因此第二节点B的电位为低电位，并通过第二电容器C2进行保持。第二节点B控制第六开关晶体管M6和第二开关晶体管M2导通，导通的第二开关晶体管M2将第一参考信号端Verf1的高电位信号提供给第一节点A，因此第一节点A的电位为高电位，并通过第一电容器C1进行保持。第一节点A控制第五开关晶体管截止。由于CK1＝1，因此第一开关晶体管M1截止。在第二节点B的控制下导通的第六开关晶体管M6将第一参考信号端Verf1的高电位信号提供给输出端Output，因此输出端Output的电位为高电位。
在第二阶段T2，Input＝0，CK1＝0，CK2＝1，CK3＝1。
由于CK1＝0，因此第一开关晶体管M1导通，导通的第一开关晶体管M1将输入信号端Input的低电位信号提供给第一节点A，因此第一节点A的电位为低电位，并通过第一电容器C1进行保持。第一节点A控制第四开关晶体管M4和第五开关晶体管M5导通，导通的第四开关晶体管M4将第三时钟信号端CK3的高电位信号提供第二节点B，因此第二节点B的电位为高电位，并通过第二电容器C2进行保持。第二节点B控制第二开关晶体管M2和第六开关晶体管M6截止。由于CK3＝1，因此第三开关晶体管M3截止。在第一节点A的控制下导通的第五开关晶体管M5将第二时钟信号端CK2的高电位信号提供给输出端Output，因此输出端Output的电位为高电位。
在第三阶段T3，Input＝1，CK1＝1，CK2＝0，CK3＝1。
由于CK1＝1，因此第一开关晶体管M1截止。由于CK3＝1，因此第三开关晶体管M3截止。由于第一节点A处于浮接状态(Floating)，第一节点A的电位仍为低电位，第二开关晶体管M2导通，导通的第二开关晶体管M2将第二时钟信号端CK2的低电位信号提供给输出端Output，因此输出端Output的电位为低电位。由于第一电容器C1的自举作用，输出端Output的电位由T2阶段的高电位变为低电位，因此第一节点A的电位进一步被拉低，以保证第二开关晶体管M2的导 通更加充分，以使第二时钟信号端CK2的低电位信号完整输入到输出端Output。在此阶段，由于第一节点A的电位为低电位，因此第四开关晶体管M4导通，导通的第四开关晶体管M4将第三时钟信号端CK3的高电位信号提供给第二节点B，因此第二节点B的电位为高电位，并通过第二电容器C2进行保持，第六开关晶体管M6截止。
在第四阶段T4，Input＝1，CK1＝0，CK2＝1，CK3＝0。
由于CK1＝0，第一开关晶体管M1导通，导通的第一开关晶体管M1将输入信号端Input的高电位信号提供给第一节点A，因此第一节点A的电位为高电位，并通过第一电容器C1进行保持。第一节点A控制第四开关晶体管M4和第五开关晶体管截止。由于CK3＝0，第三开关晶体管M3导通，导通的第三开关晶体管M3将第二参考信号端Vref2的低电位信号提供给第二节点B，因此第二节点B的电位为低电位，并通过第二电容器C2进行保持。第二节点B控制第二开关晶体管M2和第六开关晶体管M6导通。导通的第二开关晶体管M2将第一参考信号端Vref1的高电位信号提供给第一节点A，进一步保证第四开关晶体管M4和第五开关晶体管M5截止。导通的第六开关晶体管M6将第一参考信号端Vref1的高电位信号提供给输出端Output，因此输出端Output的电位为高电位。
在第五阶段T5，Input＝1，CK1＝1，CK2＝0，CK3＝0。
由于CK3＝0，因此第三开关晶体管M3导通，导通的第三开关晶体管M3将第二参考信号端Verf2的低电位信号提供给第二节点B，因此第二节点B的电位为低电位，并通过第二电容器C2进行保持。第二节点B控制第六开关晶体管M6和第二开关晶体管M2导通，导通的第二开关晶体管M2将第一参考信号端Verf1的高电位信号提供给第一节点A，因此第一节点A的电位为高电位，并通过第一电容器C1进行保持。第一节点A控制第五开关晶体管截止。由于CK1＝1，因此第一开关晶体管截止。在第二节点B的控制下导通的第六开关晶体管M6将第一参考信号端Verf1的高电位信号提供给输出端Output，因此输出端Output的电位为高电位。
在本发明实施例提供的上述移位寄存器中，在第五阶段之后，一 直重复执行第四阶段和第五阶段的工作过程，以保证输出端的电位保持为高电位。
基于同一发明构思，本发明实施例还提供了一种栅极驱动电路，如图5所示，包括级联的多个移位寄存器：SR(1)、SR(2)...SR(n)...SR(N-1)、SR(N)(共N个移位寄存器，1≤n≤N)，第一级移位寄存器SR(1)的输入信号端Input与起始信号端STV相连，除第一级移位寄存器SR(1)之外，其余各级移位寄存器SR(n)的输入信号端Input分别与上一级移位寄存器SR(n-1)的输出端Output_n-1相连。
具体地，上述栅极驱动电路中的每个移位寄存器的具体结构与本发明上述移位寄存器在功能和结构上均相同，重复之处不再赘述。
基于同一发明构思，本发明实施例还提供了一种显示面板，包括本发明实施例提供的上述栅极驱动电路。该显示面板可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示面板的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，电不应作为对本发明的限制。
在具体实施时，本发明实施例提供的上述显示面板可以是液晶显示面板，也可以是有机电致发光显示面板，在此不作限定。
进一步地，当本发明实施例提供的上述显示面板为有机电致发光显示面板时，一般设置有呈矩阵排列的有机电致发光像素，每一行有机电致发光像素在发光显示时，一般是在一帧的时间内，先在扫描信号的控制下实现数据写入，之后在发光控制端的控制下依据写入的数据进行显示。因此，在一帧时间内，发光控制端的信号只有在一小段时间内是控制有机电致发光像素关闭的，其余时间都是控制有机电致发光像素发光的，以此来保证有机电致发光像素在显示周期中发光显示。并且一般在发光控制端的信号控制有机电致发光像素关闭时，控制有机电致发光像素数据写入的栅极扫描信号开始输出，以便将数据电压信号写入到有机电致发光像素中。数据电压信号写入完毕后，发光控制端的信号控制开始控制有机电致发光像素发光，有机电致发光 像素便发出写入的数据电压信号所控制的亮度。
因此，在具体实施时，当本发明实施例提供的上述显示面板为有机电致发光显示面板时，还包括与栅极驱动电路中的各级移位寄存器一一对应的有机电极发光像素行。
各有机电致发光像素行在对应的发光控制端的控制下发光，且与各有机电致发光像素行对应的发光控制端与对应级移位寄存器的第三时钟信号端相连。即利用与各有机电致发光像素行对应的发光控制端作为栅极驱动电路中对应级的移位寄存器的第三时钟信号端，从而可以减少信号线的设置，使显示面板中栅极驱动电路的结构相对简单。
本发明实施例提供了一种移位寄存器、栅极驱动电路及显示面板。移位寄存器包括：第一节点控制模块，第二节点控制模块，第一输出模块和第二输出模块。第一节点控制模块用于在第一时钟信号端的控制下将输入信号端的信号提供给第一节点，在第二节点的控制下将第一参考信号端的信号提供给第一节点。第二节点控制模块用于在第三时钟信号端的控制下将第二参考信号端的信号提供给第二节点，在第一节点的控制下将第三时钟信号端的信号提供给第二节点。第一输出模块用于在第一节点的控制下将第二时钟信号端的信号提供给输出端，在第一节点处于浮接状态时稳定第一节点与输出端之间的电压差。第二输出模块用于在第二节点的控制下将第一参考信号端的信号提供给输出端。移位寄存器通过上述四个模块的相互配合，能够通过简单的结构实现移位输出的功能，从而可以降低生产成本。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (10)

  1. 一种移位寄存器，包括：
    第一节点控制模块，分别与输入信号端、第一时钟信号端、第一参考信号端、第一节点和第二节点相连，所述第一节点控制模块用于在所述第一时钟信号端的控制下将所述输入信号端的信号提供给所述第一节点，在所述第二节点的控制下将所述第一参考信号端的信号提供给所述第一节点；
    第二节点控制模块，分别与第二参考信号端、第三时钟信号端、所述第一节点和所述第二节点相连，所述第二节点控制模块用于在所述第三时钟信号端的控制下将所述第二参考信号端的信号提供给所述第二节点，在所述第一节点的控制下将所述第三时钟信号端的信号提供给所述第二节点；
    第一输出模块分别与所述第一节点、第二时钟信号端和所述移位寄存器的输出端相连，所述第一输出模块用于在所述第一节点的控制下将所述第二时钟信号端的信号提供给所述输出端，在所述第一节点处于浮接状态时稳定所述第一节点与所述输出端之间的电压差；以及
    第二输出模块分别与所述第二节点、所述第一参考信号端和所述输出端相连，所述第二输出模块用于在所述第二节点的控制下将所述第一参考信号端的信号提供给所述输出端。
  2. 如权利要求1所述的移位寄存器，其中，所述第一节点控制模块包括：第一开关晶体管和第二开关晶体管，
    所述第一开关晶体管的栅极与所述第一时钟信号端相连，源极与所述输入信号端相连，漏极与所述第一节点相连；并且
    所述第二开关晶体管的栅极与所述第二节点相连，源极与所述第一参考信号端相连，漏极与所述第一节点相连。
  3. 如权利要求1所述的移位寄存器，其中，所述第二节点控制模块包括：第三开关晶体管和第四开关晶体管，
    所述第三开关晶体管的栅极与所述第三时钟信号端相连，源极与所述第二参考信号端相连，漏极与所述第二节点相连；并且
    所述第四开关晶体管的栅极与所述第一节点相连，源极与所述第三 时钟信号端相连，漏极与所述第二节点相连。
  4. 如权利要求1所述的移位寄存器，其中，所述第一输出模块包括：第五开关晶体管和第一电容器，
    所述第五开关晶体管的栅极与所述第一节点相连，源极与所述第二时钟信号端相连，漏极与所述输出端相连；并且
    所述第一电容器连接于所述第五开关晶体管的栅极与漏极之间。
  5. 如权利要求1所述的移位寄存器，其中，所述第二输出模块包括：第六开关晶体管，
    所述第六开关晶体管的栅极与所述第二节点相连，源极与所述第一参考信号端相连，漏极与所述输出端相连。
  6. 如权利要求5所述的移位寄存器，其中，所述第二输出模块还包括连接于所述第六开关晶体管的栅极与源极之间的第二电容器。
  7. 如权利要求2-6任一项所述的移位寄存器，其中，所有开关晶体管均为P型晶体管，或所有开关晶体管均为N型晶体管。
  8. 一种栅极驱动电路，包括多个级联的如权利要求1-7任一项所述的移位寄存器，其中，
    第一级移位寄存器的输入信号端与起始信号端相连；并且
    除第一级移位寄存器之外，其余各级移位寄存器的输入信号端均与上一级移位寄存器的输出端相连。
  9. 一种显示面板，包括如权利要求8所述的栅极驱动电路。
  10. 如权利要求9所述显示面板，还包括：与所述栅极驱动电路中的各级移位寄存器一一对应的有机电极发光像素行；其中，
    各有机电致发光像素行在对应的发光控制端的控制下发光，且与各有机电致发光像素行对应的发光控制端与对应级移位寄存器的第三时钟信号端相连。
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