WO2021164424A1 - 移位寄存器、其驱动方法、驱动电路及显示装置 - Google Patents

移位寄存器、其驱动方法、驱动电路及显示装置 Download PDF

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Publication number
WO2021164424A1
WO2021164424A1 PCT/CN2020/140309 CN2020140309W WO2021164424A1 WO 2021164424 A1 WO2021164424 A1 WO 2021164424A1 CN 2020140309 W CN2020140309 W CN 2020140309W WO 2021164424 A1 WO2021164424 A1 WO 2021164424A1
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Prior art keywords
terminal
signal
electrically connected
node
switch transistor
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PCT/CN2020/140309
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English (en)
French (fr)
Inventor
程鸿飞
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京东方科技集团股份有限公司
北京京东方技术开发有限公司
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Priority to US17/416,459 priority Critical patent/US11783743B2/en
Publication of WO2021164424A1 publication Critical patent/WO2021164424A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2230/00—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a shift register, a driving method thereof, a driving circuit, and a display device.
  • the array substrate row drive (Gate Driver on Array, GOA) technology integrates the thin film transistor (TFT) gate switch circuit on the array substrate of the display panel to form a scan drive for the display panel, which can save
  • TFT thin film transistor
  • the bonding area of the gate integrated circuit (Integrated Circuit, IC) and the wiring space of the fan-out area can not only reduce the product cost in terms of material cost and manufacturing process, but also make the display panel do To the aesthetic design of symmetrical and narrow border on both sides; and, this integrated process can also eliminate the bonding process in the direction of the gate scan line, thereby improving productivity and yield.
  • the control circuit is configured to adjust the signals of the first node and the second node according to the signal of the first clock signal terminal, the signal of the second clock signal terminal, and the signal of the input signal terminal;
  • the first output circuit is configured to provide the signal of the first reference signal terminal to the output signal terminal in response to the signal of the first node;
  • a first switching transistor wherein a first terminal of the first switching transistor is electrically connected to the second node, a control terminal of the first switching transistor is electrically connected to a second reference signal terminal, and the first switching transistor The second end of is electrically connected to the second output circuit;
  • the second output circuit is used to provide the signal of the second reference signal terminal to the output signal terminal under the signal control of the second terminal of the first switch transistor.
  • control circuit includes: an input circuit, a first node control circuit, and a second node control circuit; wherein:
  • the input circuit is configured to provide the signal of the first reference signal terminal to the third node in response to the signal of the second clock signal terminal and the signal of the input signal terminal;
  • the first node control circuit is configured to adjust the signal of the third node according to the signal of the first clock signal terminal, and provide the signal of the first clock signal terminal to the signal of the third node in response to the signal of the third node.
  • the first node and in response to the signal of the second node, providing the signal of the first reference signal terminal to the first node;
  • the second node control circuit is configured to provide the signal of the input signal terminal to the second node in response to the signal of the first clock signal terminal.
  • the input circuit includes: a second switch transistor and a third switch transistor; wherein:
  • the first terminal of the second switch transistor is electrically connected to the first reference signal terminal, the control terminal of the second switch transistor is electrically connected to the input signal terminal, and the second terminal of the second switch transistor is electrically connected to The third node is electrically connected;
  • the first terminal of the third switch transistor is electrically connected with the first reference signal terminal
  • the control terminal of the third switch transistor is electrically connected with the second clock signal terminal
  • the second terminal of the third switch transistor is electrically connected.
  • the terminal is electrically connected to the third node.
  • the first node control circuit includes: a fourth switch transistor, a fifth switch transistor, and a first capacitor; wherein:
  • the first terminal of the fourth switch transistor is electrically connected to the first clock signal terminal, the control terminal of the fourth switch transistor is electrically connected to the third node, and the second terminal of the fourth switch transistor is electrically connected to the The first node is electrically connected;
  • the first terminal of the fifth switch transistor is electrically connected to the first reference signal terminal, the control terminal of the fifth switch transistor is electrically connected to the second node, and the second terminal of the fifth switch transistor is electrically connected to The first node is electrically connected;
  • the first end of the first capacitor is electrically connected to the first clock signal end, and the second end of the first capacitor is electrically connected to the third node.
  • the second node control circuit includes: a sixth switch transistor; a first terminal of the sixth switch transistor is electrically connected to the input signal terminal, and a control terminal of the sixth switch transistor is electrically connected to the A clock signal terminal is electrically connected, and the second terminal of the sixth switch transistor is electrically connected to the second node.
  • the first output circuit includes: a seventh switch transistor and a second capacitor; wherein:
  • the first terminal of the seventh switch transistor is electrically connected to the first reference signal terminal, the control terminal of the seventh switch transistor is electrically connected to the first node, and the second terminal of the seventh switch transistor is electrically connected to The output signal terminal is electrically connected;
  • the first terminal of the second capacitor is electrically connected with the first node, and the second terminal of the second capacitor is electrically connected with the first reference signal terminal.
  • the second output circuit includes: an eighth switch transistor and a third capacitor; wherein:
  • the first terminal of the eighth switch transistor is electrically connected to the second reference signal terminal, the control terminal of the eighth switch transistor is electrically connected to the second terminal of the first switch transistor, and the eighth switch transistor The second end of is electrically connected to the output signal end;
  • the first terminal of the third capacitor is electrically connected with the second terminal of the first switch transistor, and the second terminal of the third capacitor is electrically connected with the output signal terminal.
  • the embodiments of the present disclosure also provide some driving circuits, including any of the above-mentioned shift registers; among them:
  • the input signal terminal of the first stage shift register is electrically connected to the trigger signal terminal;
  • the input signal terminal of the next stage shift register is electrically connected to the output signal terminal of the previous stage shift register.
  • the embodiments of the present disclosure also provide some display devices, including the above-mentioned driving circuit.
  • the embodiments of the present disclosure also provide some driving methods for any of the above-mentioned shift registers, including:
  • a signal of the second level is applied to the input signal terminal, a signal of the first level is applied to the first clock signal terminal, and a signal of the second level is applied to the second clock signal terminal;
  • a signal of the second level is applied to the input signal terminal, a signal of the second level is applied to the first clock signal terminal, and a signal of the first level is applied to the second clock signal terminal;
  • the input signal terminal is loaded with a first level signal
  • the first clock signal terminal is loaded with a first level signal
  • the second clock signal terminal is loaded with a second level signal
  • the input signal terminal is loaded with a first level signal
  • the first clock signal terminal is loaded with a second level signal
  • the second clock signal terminal is loaded with a first level signal
  • FIG. 1 is a schematic diagram of the structure of some shift registers provided by the embodiments of the disclosure.
  • FIG. 2 is a schematic diagram of the structure of some shift registers provided by the embodiments of the disclosure.
  • FIG. 3 is a schematic diagram of specific structures of some shift registers provided by embodiments of the disclosure.
  • FIG. 4 is a signal timing diagram provided by an embodiment of the disclosure.
  • FIG. 5 is a flowchart of a driving method provided by an embodiment of the disclosure.
  • FIG. 6 is a schematic structural diagram of a driving circuit provided by an embodiment of the disclosure.
  • Some shift registers provided by the embodiments of the present disclosure, as shown in FIG. 1, may include:
  • the control circuit 10 is configured to adjust the signals of the first node N1 and the second node N2 according to the signal of the first clock signal terminal CK1, the signal of the second clock signal terminal CK2, and the signal of the input signal terminal GPIN;
  • the first output circuit 20 is configured to provide the signal of the first reference signal terminal VGL to the output signal terminal GPOUT in response to the signal of the first node N1;
  • the first switch transistor T1 wherein the first terminal of the first switch transistor T1 is electrically connected to the second node N2, the control terminal of the first switch transistor T1 is electrically connected to the second reference signal terminal VGH, and the first terminal of the first switch transistor T1 is electrically connected to the second reference signal terminal VGH.
  • the two ends are electrically connected to the second output circuit 30;
  • the second output circuit 30 is configured to provide the signal of the second reference signal terminal VGH to the output signal terminal GPOUT under the signal control of the second terminal of the first switching transistor T1.
  • the above-mentioned shift register provided by the embodiment of the present disclosure can realize the shift output of signals through the cooperation of the above-mentioned circuits. Moreover, by providing the first switching transistor, the second output circuit can be isolated from the second node, thereby reducing the leakage current signal to the second terminal of the first switching transistor, and making the signal of the second terminal of the first switching transistor more stable. Furthermore, the second output circuit can stably provide the signal of the second reference signal terminal to the output signal terminal, so that the signal output by the output signal terminal is more stable.
  • the signal output by the above-mentioned shift register provided by the embodiment of the present disclosure can be used as the light emission control signal of the light emission control transistor, or can be used as the gate scan signal of the scan control transistor.
  • control circuit 10 may include: an input circuit 11, a first node control circuit 12, and a second node control circuit 13; among them:
  • the input circuit 11 is configured to provide the signal of the first reference signal terminal VGL to the third node N3 in response to the signal of the second clock signal terminal CK2 and the signal of the input signal terminal GPIN;
  • the first node control circuit 12 is configured to adjust the signal of the third node N3 according to the signal of the first clock signal terminal CK1, and provide the signal of the first clock signal terminal CK1 to the first node N1 in response to the signal of the third node N3 , And in response to the signal of the second node N2, providing the signal of the first reference signal terminal VGL to the first node N1;
  • the second node control circuit 13 is configured to provide the signal of the input signal terminal GPIN to the second node N2 in response to the signal of the first clock signal terminal CK1.
  • control circuit 10 can be adjusted according to the signal of the first clock signal terminal CK1, the signal of the second clock signal terminal CK2 and the signal of the input signal terminal GPIN through the cooperation of the input circuit 11 and the first node control circuit 12 The signal of the third node N3, thereby adjusting the signal of the first node N1.
  • the signal of the input signal terminal GPIN can be provided to the second node N2 in response to the signal of the first clock signal terminal CK1.
  • the input circuit 11 may include: a second switching transistor T2 and a third switching transistor T3; wherein:
  • the first terminal of the second switch transistor T2 is electrically connected to the first reference signal terminal VGL, the control terminal of the second switch transistor T2 is electrically connected to the input signal terminal GPIN, and the second terminal of the second switch transistor T2 is electrically connected to the third node N3. connect;
  • the first terminal of the third switch transistor T3 is electrically connected to the first reference signal terminal VGL, the control terminal of the third switch transistor T3 is electrically connected to the second clock signal terminal CK2, and the second terminal of the third switch transistor T3 is electrically connected to the third node N3 is electrically connected.
  • the second switch transistor T2 when the second switch transistor T2 is in the on state in response to the signal of the input signal terminal GPIN, it can provide the signal of the first reference signal terminal VGL to the third node N3.
  • the third switch transistor T3 can provide the signal of the first reference signal terminal VGL to the third node N3 when it is in the on state in response to the signal of the second clock signal terminal CK2.
  • the first node control circuit 12 may include: a fourth switch transistor T4, a fifth switch transistor T5, and a first capacitor C1; wherein:
  • the first terminal of the fourth switch transistor T4 is electrically connected to the first clock signal terminal CK1, the control terminal of the fourth switch transistor T4 is electrically connected to the third node N3, and the second terminal of the fourth switch transistor T4 is electrically connected to the first node N1. connect;
  • the first terminal of the fifth switch transistor T5 is electrically connected to the first reference signal terminal VGL, the control terminal of the fifth switch transistor T5 is electrically connected to the second node N2, and the second terminal of the fifth switch transistor T5 is electrically connected to the first node N1. connect;
  • the first terminal of the first capacitor C1 is electrically connected to the first clock signal terminal CK1, and the second terminal of the first capacitor C1 is electrically connected to the third node N3.
  • the fourth switch transistor T4 when the fourth switch transistor T4 is turned on in response to the signal of the third node N3, it can provide the signal of the first clock signal terminal CK1 to the first node N1.
  • the fifth switch transistor T5 when the fifth switch transistor T5 is in the on state in response to the signal of the second node N2, it can provide the signal of the first reference signal terminal VGL to the first node N1.
  • the first capacitor C1 maintains a stable voltage difference between its two terminals.
  • the first capacitor C1 can adjust the voltage of the signal at the third node N3.
  • the second node control circuit 13 may include: a sixth switch transistor T6; the first terminal of the sixth switch transistor T6 is electrically connected to the input signal terminal GPIN, The control terminal of the sixth switch transistor T6 is electrically connected to the first clock signal terminal CK1, and the second terminal of the sixth switch transistor T6 is electrically connected to the second node N2.
  • the sixth switch transistor T6 when the sixth switch transistor T6 is in the on state in response to the signal of the first clock signal terminal CK1, it can provide the signal of the input signal terminal GPIN to the second node N2.
  • the first output circuit 20 may include: a seventh switching transistor T7 and a second capacitor C2; wherein:
  • the first terminal of the seventh switch transistor T7 is electrically connected to the first reference signal terminal VGL, the control terminal of the seventh switch transistor T7 is electrically connected to the first node N1, and the second terminal of the seventh switch transistor T7 is electrically connected to the output signal terminal GPOUT. connect;
  • the first terminal of the second capacitor C2 is electrically connected to the first node N1, and the second terminal of the second capacitor C2 is electrically connected to the first reference signal terminal VGL.
  • the seventh switch transistor T7 when the seventh switch transistor T7 is in the on state in response to the signal of the first node N1, the first reference signal terminal VGL may be provided to the output signal terminal GPOUT.
  • the second capacitor C2 can store the signal of the first node N1.
  • the voltage difference between the first node N1 and the control terminal of the seventh switching transistor T7 can be kept unchanged. .
  • the second output circuit 30 may include: an eighth switching transistor T8 and a third capacitor C3; wherein:
  • the first terminal of the eighth switch transistor T8 is electrically connected to the second reference signal terminal VGH, the control terminal of the eighth switch transistor T8 is electrically connected to the second terminal of the first switch transistor T1, and the second terminal of the eighth switch transistor T8 is electrically connected to The output signal terminal GPOUT is electrically connected;
  • the first end of the third capacitor C3 is electrically connected to the second end of the first switching transistor T1, and the second end of the third capacitor C3 is electrically connected to the output signal terminal GPOUT.
  • the eighth switch transistor T8 can provide the signal of the second reference signal terminal VGH to the output signal terminal GPOUT when the eighth switch transistor T8 is in the ON state in response to the signal of the second terminal of the first switch transistor T1.
  • the third capacitor C3 keeps the voltage difference between its two ends unchanged.
  • the third capacitor C3 can adjust the voltage of the signal at the second terminal of the first switching transistor T1.
  • all switch transistors are N-type transistors.
  • all switch transistors may also be P-type transistors. Not limited.
  • the P-type transistor is turned on under the action of a low-level signal, and it is turned off under the action of a high-level signal; the N-type transistor is turned on under the action of a high-level signal, Cut off under the action of low-level signal.
  • each of the above-mentioned switching transistors may be a thin film transistor (TFT, Thin Film Transistor) or a metal oxide semiconductor field effect transistor (MOS, Metal Oxide Scmiconductor). This is not limited.
  • TFT Thin Film Transistor
  • MOS Metal Oxide Scmiconductor
  • the control terminal of each switching transistor is used as the gate, and the first terminal of the above-mentioned switching transistor can be used as the source and the second terminal as the drain. Or the first end of the switching transistor is used as the drain and the second end is used as the source, and no specific distinction is made here.
  • all switch transistors in the shift register provided by the embodiment of the present disclosure may be N-type transistors, and the signal of the first reference signal terminal VGL may be a low-level signal, and the second reference signal terminal VGL may be a low-level signal.
  • the signal of the reference signal terminal VGH may be a high-level signal.
  • all switch transistors may also be P-type transistors, and the signal at the first reference signal terminal VGL may be a high-level signal, and the signal at the second reference signal terminal VGH may be a low-level signal.
  • Flat signal may be N-type transistors, and the signal of the first reference signal terminal VGL may be a low-level signal, and the second reference signal terminal VGL may be a low-level signal.
  • the high-level voltage of the first clock signal terminal CK1 may be the same as the voltage of the second reference signal terminal VGH.
  • the voltage of the low level of the first clock signal terminal CK1 may be the same as the voltage of the first reference signal terminal VGL.
  • the specific voltage values of the first clock signal terminal CK1, the second clock signal terminal CK2, the first reference signal terminal VGL, and the second reference signal terminal VGH can be determined according to actual application conditions, and are not limited here.
  • 1 means high level and 0 means low level. It should be noted that 1 and 0 are logic levels, which are only used to better explain the specific working process of the embodiments of the present disclosure, rather than specific voltage values.
  • the working process of the shift register provided by the embodiment of the present disclosure will be described in conjunction with the signal timing diagram shown in FIG. 4, where the signal of the first reference signal terminal VGL It is a low-level signal, and the signal of the second reference signal terminal VGH is a high-level signal.
  • the first stage t1, the second stage t2, the third stage t3, and the third stage t3 in the signal timing diagram shown in FIG. 4 are selected.
  • the fourth stage t4 is selected.
  • the second switching transistor T2 and the third switching transistor T3 are turned on, and the low-level signal of the first reference signal terminal VGL is provided to the third node N3, so that the third node N3 is a low-level signal, and the fourth switching transistor T4 is turned off .
  • the second node N2 maintains the signal of the previous stage.
  • the second node N2 is a low-level signal, and the fifth switch transistor T5 is turned off.
  • the high level signal of the second reference signal terminal VGH turns on the first switch transistor T1, provides the low level signal of the second node N2 to the control terminal of the eighth switch transistor T8, and the eighth switch transistor T8 is turned off.
  • the first node N1 maintains a high-level signal
  • the seventh switch transistor T7 is turned on, and the low-level signal of the first reference signal terminal VGL is provided to the output signal terminal GPOUT, so that the output signal terminal GPOUT outputs a low-level signal.
  • the second switch transistor T2 is turned on and provides the low-level signal of the first reference signal terminal VGL to the third node N3, so that the signal of the third node N3 is a low-level signal, and the fourth switch transistor T4 is turned off.
  • the sixth switch transistor T6 is turned on to provide the high level signal of the input signal terminal GPIN to the second node N2, so that the second node N2 is at a high level.
  • the fifth switch transistor T5 is turned on, and the low-level signal of the first reference signal terminal VGL is provided to the first node N1, so that the signal of the first node N1 is low, and the seventh switch transistor T7 is turned off.
  • the high-level signal of the second reference signal terminal VGH turns on the first switch transistor T1, and provides the high-level signal of the second node N2 to the control terminal of the eighth switch transistor T8.
  • the eighth switch transistor T8 is turned on to turn on
  • the high level signal of the second reference signal terminal VGH is provided to the output signal terminal GPOUT, and the second terminal of the third capacitor C3 is changed from low level to high level. Due to the bootstrap effect of the third capacitor C3, the voltage of the signal at the control terminal of the eighth switch transistor T8 is pulled up.
  • the signal voltage at the second terminal of the first switching transistor T1 is higher than the voltage of the high-level signal at the second reference signal terminal VGH, and the voltages of the signals at the first terminal and the control terminal of the first switching transistor T1 are equal to the second reference signal terminal
  • the voltage of the high-level signal of VGH turns off the first switching transistor T1.
  • the voltage of the signal at the control terminal of the eighth switch transistor T8 is higher than the voltage of the high-level signal at the second reference signal terminal VGH, so that the conduction degree of the eighth switch transistor T8 is improved.
  • the control terminal of the eighth switching transistor T8 can be isolated from the second node N2, and the influence of the leakage current on the signal of the control terminal of the eighth switching transistor T8 is reduced, so that the eighth switching transistor T8 The signal at the control terminal of the signal is more stable, so that the eighth switch transistor T8 can stably provide the high-level signal of the second reference signal terminal VGH to the output signal terminal GPOUT, so that the signal output by the output signal terminal GPOUT is more stable.
  • the third switch transistor T3 is turned on to provide the low-level signal of the first reference signal terminal VGL to the third node N3, so that the signal of the third node N3 is a low-level signal, and the fourth switch transistor T4 is turned off.
  • the fourth switch transistor T4 and the sixth switch transistor T6 are both turned off, and the first node N1 and the second node N2 maintain the signal of the previous stage.
  • the second node N2 maintains a high-level signal
  • the fifth switch transistor T5 is turned on to provide a low-level signal of the first reference signal terminal VGL to the first node N1.
  • the first node N1 maintains a low level signal
  • the seventh switch transistor T7 is turned off.
  • the voltage of the signal at the control terminal of the eighth switching transistor T8 remains unchanged, the first switching transistor T1 is still turned off, and the eighth switching transistor T8 is turned on, and the high-level signal of the second reference signal terminal VGH is provided to the output signal terminal GPOUT , The output signal terminal GPOUT outputs a high level signal.
  • the signal of the first clock signal terminal CK1 changes from a low level to a high level at the beginning of the fourth phase t4. Due to the bootstrap effect of the first capacitor C1, the voltage of the signal at the third node N3 is pulled up, so that the third The signal at the node N3 is a high-level signal, and the fourth switch transistor T4 is turned on.
  • the sixth switch transistor T6 is turned on to provide a low-level signal of the input signal terminal GPIN to the second node N2, so that the second node N2 is at a low level.
  • the fifth switching transistor T5 is turned off.
  • the second node N2 is at a low level, and the control terminal of the first switch transistor T1 is at a high level, so that the first switch transistor T1 is turned on, and a low level signal is provided to the control terminal of the eighth switch transistor T8, so that the eighth The switching transistor T8 is turned off.
  • the fourth switch transistor T4 is turned on, and the high level signal of the first clock signal terminal CK1 is provided to the first node N1, so that the first node N1 is at a high level, and the seventh switch transistor T7 is turned on, and the first reference signal
  • the low-level signal of the terminal VGL is provided to the output signal terminal GPOUT, and the output signal terminal GPOUT outputs a low-level signal.
  • the embodiments of the present disclosure also provide some driving methods of any of the above-mentioned shift registers provided by the embodiments of the present disclosure, as shown in FIG. 5, including:
  • a signal of the second level is applied to the input signal terminal, a signal of the first level is applied to the first clock signal terminal, and a signal of the second level is applied to the second clock signal terminal;
  • a signal of the second level is applied to the input signal terminal, a signal of the second level is applied to the first clock signal terminal, and a signal of the first level is applied to the second clock signal terminal;
  • a signal of the first level is applied to the input signal terminal, a signal of the first level is applied to the first clock signal terminal, and a signal of the second level is applied to the second clock signal terminal;
  • a signal of the first level is applied to the input signal terminal, a signal of the second level is applied to the first clock signal terminal, and a signal of the first level is applied to the second clock signal terminal.
  • the first level may be a low level, and correspondingly, the second level may be a high level; or vice versa, the first level may be a high level.
  • the second level is a low level, which depends on whether the transistor in the shift register is an N-type transistor or a P-type transistor.
  • FIG. 4 shows some signal timing diagrams when the transistors in the shift register are N-type transistors, and the first level is low level, and the second level is high level.
  • the embodiments of the present disclosure also provide some driving circuits, as shown in FIG. 6, including any of the shift registers provided by multiple cascaded embodiments of the present disclosure: SR(1), SR(2)... SR(n-1), SR(n)..., SR(N-1), SR(N) (a total of N shift registers, 1 ⁇ n ⁇ N); among them,
  • the input signal terminal GPIN of the first stage shift register SR(1) is electrically connected to the frame trigger signal terminal STV;
  • the input signal terminals GPIN of the other stages of shift register SR(n) are respectively the output signal terminals of the previous stage shift register SR(n-1) adjacent to it GPOUT is electrically connected.
  • each shift register in the above-mentioned driving circuit is the same in function and structure as any of the above-mentioned shift registers provided in the embodiments of the present disclosure, and the repetition will not be repeated.
  • the first reference signal terminal VGL of the shift registers of each stage is connected to the same reference signal line Vgl
  • the second reference signal terminal VGH of the shift register of each stage is connected to the same reference signal line Vgl.
  • the same reference signal line Vgh is connected.
  • the first clock signal terminal CK1 of the odd-numbered stage shift register is electrically connected to the first clock line clk1, and the second clock signal terminal CK2 is electrically connected to the second clock line clk2;
  • the first clock signal terminal CK1 is electrically connected to the second clock line clk2, and the second clock signal terminal CK2 is electrically connected to the first clock line clk1.
  • the driving circuit provided by the embodiment of the present disclosure can be used as a gate driving circuit and applied to provide a gate scanning signal of a scanning control transistor.
  • the driving circuit provided by the embodiment of the present disclosure can be used as a light-emitting driving circuit, which is applied to provide a light-emitting control signal of a light-emitting control transistor.
  • the embodiments of the present disclosure also provide some display devices, including the above-mentioned driving circuit provided by the present disclosure.
  • the above-mentioned driving circuit provided by the present disclosure.
  • the above-mentioned display device provided by the embodiment of the present disclosure may be an organic light-emitting display device, or may also be a liquid crystal display device, which is not limited herein.
  • an organic light emitting display device a plurality of organic light emitting diodes and a pixel circuit connected to each organic light emitting diode are generally provided.
  • a pixel circuit is provided with a light emission control transistor for controlling the light emission of an organic light emitting diode and a scan control transistor for controlling data signal input.
  • the organic light-emitting display device may include the above-mentioned drive circuit provided by the embodiment of the present disclosure, and the drive circuit may be used as a light-emitting drive circuit.
  • the driving circuit can also be used as a gate drive circuit to provide the gate scan signal of the scan control transistor.
  • the organic light-emitting display device may also include two of the above-mentioned drive control circuits provided by the embodiments of the present disclosure.
  • the gate driving circuit is used to provide the gate scanning signal of the scanning control transistor, and it is not limited herein.
  • a plurality of pixel electrodes and a switching transistor connected to each pixel electrode are generally provided.
  • the above-mentioned display device provided by the embodiment of the present disclosure is a liquid crystal display device
  • the above-mentioned drive circuit provided by the embodiment of the present disclosure may be used as a gate drive circuit and applied to provide a gate scan signal of a switching transistor.
  • the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and so on.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and so on.
  • Other indispensable components of the display device are understood by those of ordinary skill in the art, and will not be repeated here, nor should they be used as a limitation to the present disclosure.
  • Some shift registers provided by the embodiments of the present disclosure include: a control circuit, a first output circuit, and a second output circuit. Through the cooperation of the above-mentioned circuits, the shifted output of the signal can be realized, and the output signal can be used as the light-emitting control signal of the light-emitting control transistor or the gate scanning signal of the scan control transistor.
  • Some driving circuits provided by the embodiments of the present disclosure include any of the above-mentioned shift registers. By integrating the above-mentioned driving circuit on the display panel to provide scanning driving signals or light-emitting driving signals to the display panel, the display panel can be symmetrical and narrow on both sides. The beautiful design of the frame can also omit the bonding process in the direction of the gate scan line, thereby improving productivity and yield.

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Abstract

一种移位寄存器、其驱动方法、驱动电路及显示装置，移位寄存器包括：控制电路（10）、第一输出电路（20）、第二输出电路（30）以及第一开关晶体管（T1）。通过各电路的相互配合，可以实现信号的移位输出。并且，通过设置第一开关晶体管（T1），可以将第二输出电路（30）与第二节点（N2）隔离，从而降低漏电流对第一开关晶体管（T1）的第二端的信号的影响，使第一开关晶体管（T1）的第二端的信号更加稳定，进而使第二输出电路（30）可以稳定地将第二参考信号端（VGH）的信号提供给输出信号端（OUT），以使输出信号端（OUT）输出的信号更稳定。

Description

移位寄存器、其驱动方法、驱动电路及显示装置
相关申请的交叉引用
本申请要求在2020年2月19日提交中国专利局、申请号为202010105859.4、申请名称为“一种移位寄存器、其驱动方法、驱动电路及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，特别涉及移位寄存器、其驱动方法、驱动电路及显示装置。
背景技术
随着显示技术的飞速发展，显示面板越来越向着高集成度和低成本的方向发展。其中，阵列基板行驱动(Gate Driver on Array，GOA)技术将薄膜晶体管(Thin Film Transistor，TFT)栅极开关电路集成在显示面板的阵列基板上以形成对显示面板的扫描驱动，从而可以省去栅极集成电路(Integrated Circuit，IC)的绑定(Bonding)区域以及扇出(Fan-out)区域的布线空间，不仅可以在材料成本和制备工艺两方面降低产品成本，而且可以使显示面板做到两边对称和窄边框的美观设计；并且，这种集成工艺还可以省去栅极扫描线方向的Bonding工艺，从而提高了产能和良率。
发明内容
本公开实施例提供的移位寄存器，包括：
控制电路，被配置为根据第一时钟信号端的信号、第二时钟信号端的信号和输入信号端的信号，调整第一节点和第二节点的信号；
第一输出电路，被配置为响应于所述第一节点的信号，将第一参考信号端的信号提供给输出信号端；
第一开关晶体管，其中，所述第一开关晶体管的第一端与所述第二节点 电连接，所述第一开关晶体管的控制端与第二参考信号端电连接，所述第一开关晶体管的第二端与所述第二输出电路电连接；
所述第二输出电路用于在所述第一开关晶体管的第二端的信号控制下，将所述第二参考信号端的信号提供给所述输出信号端。
可选地，所述控制电路包括：输入电路、第一节点控制电路、第二节点控制电路；其中：
所述输入电路被配置为响应于所述第二时钟信号端的信号和所述输入信号端的信号，将所述第一参考信号端的信号提供给第三节点；
所述第一节点控制电路被配置为根据所述第一时钟信号端的信号调整所述第三节点的信号，响应于所述第三节点的信号，将所述第一时钟信号端的信号提供给所述第一节点，以及响应于所述第二节点的信号，将所述第一参考信号端的信号提供给所述第一节点；
所述第二节点控制电路被配置为响应于所述第一时钟信号端的信号，将所述输入信号端的信号提供给所述第二节点。
可选地，所述输入电路包括：第二开关晶体管和第三开关晶体管；其中：
所述第二开关晶体管的第一端与所述第一参考信号端电连接，所述第二开关晶体管的控制端与所述输入信号端电连接，所述第二开关晶体管的第二端与所述第三节点电连接；
所述第三开关晶体管的第一端与所述第一参考信号端电连接，所述第三开关晶体管的控制端与所述第二时钟信号端电连接，所述第三开关晶体管的第二端与所述第三节点电连接。
可选地，所述第一节点控制电路包括：第四开关晶体管、第五开关晶体管以及第一电容；其中：
所述第四开关晶体管的第一端与所述第一时钟信号端电连接，所述第四开关晶体管的控制端与所述第三节点电连接，所述第四开关晶体管的第二端与所述第一节点电连接；
所述第五开关晶体管的第一端与所述第一参考信号端电连接，所述第五 开关晶体管的控制端与所述第二节点电连接，所述第五开关晶体管的第二端与所述第一节点电连接；
所述第一电容的第一端与所述第一时钟信号端电连接，所述第一电容的第二端与所述第三节点电连接。
可选地，所述第二节点控制电路包括：第六开关晶体管；所述第六开关晶体管的第一端与所述输入信号端电连接，所述第六开关晶体管的控制端与所述第一时钟信号端电连接，所述第六开关晶体管的第二端与所述第二节点电连接。
可选地，所述第一输出电路包括：第七开关晶体管和第二电容；其中：
所述第七开关晶体管的第一端与所述第一参考信号端电连接，所述第七开关晶体管的控制端与所述第一节点电连接，所述第七开关晶体管的第二端与所述输出信号端电连接；
所述第二电容的第一端与所述第一节点电连接，所述第二电容的第二端与所述第一参考信号端电连接。
可选地，所述第二输出电路包括：第八开关晶体管和第三电容；其中：
所述第八开关晶体管的第一端与所述第二参考信号端电连接，所述第八开关晶体管的控制端与所述第一开关晶体管的第二端电连接，所述第八开关晶体管的第二端与所述输出信号端电连接；
所述第三电容的第一端与所述第一开关晶体管的第二端电连接，所述第三电容的第二端与所述输出信号端电连接。
相应地，本公开实施例还提供了一些驱动电路，包括上述任一些移位寄存器；其中：
第一级移位寄存器的输入信号端与触发信号端电连接；
每相邻两级移位寄存器中，下一级移位寄存器的输入信号端与上一级移位寄存器的输出信号端电连接。
相应地，本公开实施例还提供了一些显示装置，包括上述驱动电路。
相应地，本公开实施例还提供了一些上述任一些移位寄存器的驱动方法， 包括：
第一阶段，对输入信号端加载第二电平的信号，对第一时钟信号端加载第一电平的信号，对第二时钟信号端加载第二电平的信号；
第二阶段，对输入信号端加载第二电平的信号，对第一时钟信号端加载第二电平的信号，对第二时钟信号端加载第一电平的信号；
第三阶段，对输入信号端加载第一电平的信号，对第一时钟信号端加载第一电平的信号，对第二时钟信号端加载第二电平的信号；
第四阶段，对输入信号端加载第一电平的信号，对第一时钟信号端加载第二电平的信号，对第二时钟信号端加载第一电平的信号。
附图说明
图1为本公开实施例提供的一些移位寄存器的结构示意图；
图2为本公开实施例提供的一些移位寄存器的结构示意图；
图3为本公开实施例提供的一些移位寄存器的具体结构示意图；
图4为本公开实施例提供的信号时序图；
图5为本公开实施例提供的驱动方法的流程图；
图6为本公开实施例提供的驱动电路的结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第 二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
本公开实施例提供的一些移位寄存器，如图1所示，可以包括：
控制电路10，被配置为根据第一时钟信号端CK1的信号、第二时钟信号端CK2的信号和输入信号端GPIN的信号，调整第一节点N1和第二节点N2的信号；
第一输出电路20，被配置为响应于第一节点N1的信号，将第一参考信号端VGL的信号提供给输出信号端GPOUT；
第一开关晶体管T1，其中，第一开关晶体管T1的第一端与第二节点N2电连接，第一开关晶体管T1的控制端与第二参考信号端VGH电连接，第一开关晶体管T1的第二端与第二输出电路30电连接；
第二输出电路30用于在第一开关晶体管T1的第二端的信号控制下，将第二参考信号端VGH的信号提供给输出信号端GPOUT。
本公开实施例提供的上述移位寄存器，通过上述电路的相互配合，可以实现信号的移位输出。并且，通过设置了第一开关晶体管，可以将第二输出电路与第二节点隔离，从而降低漏电流对第一开关晶体管的第二端的信号，使第一开关晶体管的第二端的信号更加稳定，进而可以使第二输出电路可以稳定的将第二参考信号端的信号提供给输出信号端，以使输出信号端输出的信号更稳定。
并且，本公开实施例提供的上述移位寄存器输出的信号，可以作为发光控制晶体管的发光控制信号，也可以作为扫描控制晶体管的栅极扫描信号。
在具体实施时，在本公开实施例中，如图2所示，控制电路10可以包括：输入电路11、第一节点控制电路12、第二节点控制电路13；其中：
输入电路11被配置为响应于第二时钟信号端CK2的信号和输入信号端GPIN的信号，将第一参考信号端VGL的信号提供给第三节点N3；
第一节点控制电路12被配置为根据第一时钟信号端CK1的信号调整第三节点N3的信号，响应于第三节点N3的信号，将第一时钟信号端CK1的信号提供给第一节点N1，以及响应于第二节点N2的信号，将第一参考信号端VGL的信号提供给第一节点N1；
第二节点控制电路13被配置为响应于第一时钟信号端CK1的信号，将输入信号端GPIN的信号提供给第二节点N2。
在具体实施时，控制电路10通过输入电路11和第一节点控制电路12的相互配合，可以根据第一时钟信号端CK1的信号、第二时钟信号端CK2的信号和输入信号端GPIN的信号调整第三节点N3的信号，从而调整第一节点N1的信号。通过设置了第二节点控制电路13，可以响应于第一时钟信号端CK1的信号，将输入信号端GPIN的信号提供给第二节点N2。
在具体实施时，在本公开实施例中，如图3所示，输入电路11可以包括：第二开关晶体管T2和第三开关晶体管T3；其中：
第二开关晶体管T2的第一端与第一参考信号端VGL电连接，第二开关晶体管T2的控制端与输入信号端GPIN电连接，第二开关晶体管T2的第二端与第三节点N3电连接；
第三开关晶体管T3的第一端与第一参考信号端VGL电连接，第三开关晶体管T3的控制端与第二时钟信号端CK2电连接，第三开关晶体管T3的第二端与第三节点N3电连接。
在具体实施时，第二开关晶体管T2响应于输入信号端GPIN的信号处于导通状态时，可以将第一参考信号端VGL的信号提供给第三节点N3。
在具体实施时，第三开关晶体管T3响应于第二时钟信号端CK2的信号处于导通状态时，可以将第一参考信号端VGL的信号提供给第三节点N3。
在具体实施时，在本公开实施例中，如图3所示，第一节点控制电路12可以包括：第四开关晶体管T4、第五开关晶体管T5以及第一电容C1；其中：
第四开关晶体管T4的第一端与第一时钟信号端CK1电连接，第四开关晶体管T4的控制端与第三节点N3电连接，第四开关晶体管T4的第二端与第一节点N1电连接；
第五开关晶体管T5的第一端与第一参考信号端VGL电连接，第五开关晶体管T5的控制端与第二节点N2电连接，第五开关晶体管T5的第二端与第一节点N1电连接；
第一电容C1的第一端与第一时钟信号端CK1电连接，第一电容C1的第二端与第三节点N3电连接。
在具体实施时，第四开关晶体管T4响应于第三节点N3的信号处于导通状态时，可以将第一时钟信号端CK1的信号提供给第一节点N1。
在具体实施时，第五开关晶体管T5响应于第二节点N2的信号处于导通状态时，可以将第一参考信号端VGL的信号提供给第一节点N1。
在具体实施时，第一电容C1保持其两端电压差稳定，当第一时钟信号端CK1的信号的电压发生变化时，第一电容C1可以调整第三节点N3的信号的电压。
在具体实施时，在本公开实施例中，如图3所示，第二节点控制电路13可以包括：第六开关晶体管T6；第六开关晶体管T6的第一端与输入信号端GPIN电连接，第六开关晶体管T6的控制端与第一时钟信号端CK1电连接，第六开关晶体管T6的第二端与第二节点N2电连接。
在具体实施时，第六开关晶体管T6响应于第一时钟信号端CK1的信号处于导通状态时，可以将输入信号端GPIN的信号提供给第二节点N2。
在具体实施时，在本公开实施例中，如图3所示，第一输出电路20可以包括：第七开关晶体管T7和第二电容C2；其中：
第七开关晶体管T7的第一端与第一参考信号端VGL电连接，第七开关晶体管T7的控制端与第一节点N1电连接，第七开关晶体管T7的第二端与 输出信号端GPOUT电连接；
第二电容C2的第一端与第一节点N1电连接，第二电容C2的第二端与第一参考信号端VGL电连接。
在具体实施时，第七开关晶体管T7响应于第一节点N1的信号处于导通状态时，可以将第一参考信号端VGL提供给输出信号端GPOUT。
在具体实施时，第二电容C2可以存储第一节点N1的信号，当第一节点N1处于浮接状态时，可以保持第一节点N1与第七开关晶体管T7的控制端之间电压差不变。
在具体实施时，在本公开实施例中，如图3所示，第二输出电路30可以包括：第八开关晶体管T8和第三电容C3；其中：
第八开关晶体管T8的第一端与第二参考信号端VGH电连接，第八开关晶体管T8的控制端与第一开关晶体管T1的第二端电连接，第八开关晶体管T8的第二端与输出信号端GPOUT电连接；
第三电容C3的第一端与第一开关晶体管T1的第二端电连接，第三电容C3的第二端与输出信号端GPOUT电连接。
在具体实施时，第八开关晶体管T8响应于第一开关晶体管T1的第二端的信号处于导通状态时，可以将第二参考信号端VGH的信号提供给输出信号端GPOUT。
在具体实施时，第三电容C3保持其两端电压差不变，当输入信号端GPIN的信号的电压发生变化时，第三电容C3可以调整第一开关晶体管T1的第二端的信号的电压。
以上仅是举例说明本公开实施例提供的移位寄存器中各电路的具体结构，在具体实施时，上述各电路的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不作限定。
具体地，为了制作工艺统一，在本公开实施例提供的移位寄存器中，如图3所示，所有开关晶体管均为N型晶体管，当然，所有开关晶体管也可以均为P型晶体管，在此不作限定。
具体地，在本公开实施例提供的移位寄存器中，P型晶体管在低电平信号作用下导通，在高电平信号作用下截止；N型晶体管在高电平信号作用下导通，在低电平信号作用下截止。
具体地，在本公开实施例提供的移位寄存器中，上述各开关晶体管可以是薄膜晶体管(TFT，Thin Film Transistor)，也可以是金属氧化物半导体场效应管(MOS，Metal Oxide Scmiconductor)，在此不作限定。并且根据上述各开关晶体管的类型不同以及各开关晶体管的控制端的信号的不同，将各开关晶体管的控制端作为栅极，并可以将上述开关晶体管的第一端作为源极，第二端作为漏极，或者将开关晶体管的第一端作为漏极，第二端作为源极，在此不作具体区分。
在具体实施时，如图3所示，在本公开实施例提供的移位寄存器中所有开关晶体管可以均为N型晶体管，则第一参考信号端VGL的信号可以为低电平信号，第二参考信号端VGH的信号可以为高电平信号。在本公开实施例提供的移位寄存器中所有开关晶体管也可以均为P型晶体管，则第一参考信号端VGL的信号可以为高电平信号，第二参考信号端VGH的信号可以为低电平信号。
在具体实施时，第一时钟信号端CK1的高电平的电压可以与第二参考信号端VGH的电压相同。第一时钟信号端CK1的低电平的电压可以与第一参考信号端VGL的电压相同。当然，第一时钟信号端CK1、第二时钟信号端CK2、第一参考信号端VGL和第二参考信号端VGH的具体电压值可以根据实际应用情况确定，在此不作限定。
下面结合具体实施例，对本公开进行详细说明。需要说明的是，本实施例中是为了更好的解释本公开，但不限制本公开。
下面结合电路时序图对本公开实施例提供的移位寄存器的工作过程作以描述。下述描述中以1表示高电平，0表示低电平。需要说明的是，1和0是逻辑电平，其仅是为了更好的解释本公开实施例的具体工作过程，而不是具体的电压值。
下面以图3所示的移位寄存器的结构为例，结合图4所示的信号时序图对本公开实施例提供的上述移位寄存器的工作过程进行描述，其中，第一参考信号端VGL的信号为低电平信号，第二参考信号端VGH的信号为高电平信号，具体地，选取如图4所示的信号时序图中的第一阶段t1、第二阶段t2、第三阶段t3、第四阶段t4。
在第一阶段t1，CK1＝0，CK2＝1，GPIN＝1。
由于CK1＝0，第六开关晶体管T6截止；由于CK2＝1，第三开关晶体管T3导通；由于GPIN＝1，第二开关晶体管T2导通。
第二开关晶体管T2和第三开关晶体管T3导通，将第一参考信号端VGL的低电平信号提供给第三节点N3，使第三节点N3为低电平信号，第四开关晶体管T4截止。
第六开关晶体管T6截止，则第二节点N2保持上一阶段的信号。第二节点N2为低电平信号，第五开关晶体管T5截止。第二参考信号端VGH的高电平信号使第一开关晶体管T1导通，将第二节点N2的低电平信号提供给第八开关晶体管T8的控制端，第八开关晶体管T8截止。
第一节点N1保持为高电平信号，第七开关晶体管T7导通，将第一参考信号端VGL的低电平信号提供给输出信号端GPOUT，使输出信号端GPOUT输出低电平信号。
在第二阶段t2，CK1＝1，CK2＝0，GPIN＝1。
由于CK1＝1，第六开关晶体管T6导通；由于CK2＝0，第三开关晶体管T3截止；由于GPIN＝1，第二开关晶体管T2导通。
第二开关晶体管T2导通，将第一参考信号端VGL的低电平信号提供给第三节点N3，使得第三节点N3的信号为低电平信号，第四开关晶体管T4截止。
第六开关晶体管T6导通，将输入信号端GPIN的高电平信号提供给第二节点N2，使第二节点N2为高电平。第五开关晶体管T5导通，将第一参考信号端VGL的低电平信号提供给第一节点N1，使第一节点N1的信号为低电平， 第七开关晶体管T7截止。
第二参考信号端VGH的高电平信号使第一开关晶体管T1导通，将第二节点N2的高电平信号提供给第八开关晶体管T8的控制端，第八开关晶体管T8导通，将第二参考信号端VGH的高电平信号提供给输出信号端GPOUT，并且使第三电容C3的第二端由低电平变为高电平。由于第三电容C3的自举作用，第八开关晶体管T8的控制端的信号的电压被拉高。此时第一开关晶体管T1的第二端的信号电压高于第二参考信号端VGH的高电平信号的电压，第一开关晶体管T1的第一端和控制端的信号的电压等于第二参考信号端VGH的高电平信号的电压，使第一开关晶体管T1截止。第八开关晶体管T8的控制端的信号的电压高于第二参考信号端VGH的高电平信号的电压，从而使第八开关晶体管T8的导通程度提高。
并且，由于第一开关晶体管T1截止，可以将第八开关晶体管T8的控制端与第二节点N2隔离，降低漏电流对第八开关晶体管T8的控制端的信号的影响，从而使第八开关晶体管T8的控制端的信号更稳定，进而使第八开关晶体管T8可以稳定的将第二参考信号端VGH的高电平信号提供给输出信号端GPOUT，使输出信号端GPOUT输出的信号更加稳定。
在第三阶段t3，CK1＝0，CK2＝1，GPIN＝0。
由于CK1＝0，第六开关晶体管T6截止；由于CK2＝1，第三开关晶体管T3导通；由于GPIN＝0，第二开关晶体管T2截止。
第三开关晶体管T3导通，将第一参考信号端VGL的低电平信号提供给第三节点N3，使得第三节点N3的信号为低电平信号，第四开关晶体管T4截止。
第四开关晶体管T4和第六开关晶体管T6均截止，则第一节点N1和第二节点N2保持上一阶段的信号。第二节点N2保持为高电平信号，第五开关晶体管T5导通，将第一参考信号端VGL的低电平信号提供给第一节点N1。第一节点N1保持为低电平信号，第七开关晶体管T7截止。第八开关晶体管T8的控制端的信号的电压保持不变，则第一开关晶体管T1仍截止，第八开 关晶体管T8导通，将第二参考信号端VGH的高电平信号提供给输出信号端GPOUT，输出信号端GPOUT输出高电平信号。
在第四阶段t4，CK1＝1，CK2＝0，GPIN＝0。
由于CK1＝1，第六开关晶体管T6导通；由于CK2＝0，第三开关晶体管T3截止；由于GPIN＝0，第二开关晶体管T2截止。
第一时钟信号端CK1的信号在第四阶段t4开始时由低电平变为高电平，由于第一电容C1的自举作用，将第三节点N3的信号的电压拉高，使得第三节点N3的信号为高电平信号，第四开关晶体管T4导通。
第六开关晶体管T6导通，将输入信号端GPIN的低电平信号提供给第二节点N2，使第二节点N2为低电平。第五开关晶体管T5截止。第二节点N2为低电平，第一开关晶体管T1的控制端为高电平，使第一开关晶体管T1导通，将低电平信号提供给第八开关晶体管T8的控制端，使第八开关晶体管T8截止。
第四开关晶体管T4导通，将第一时钟信号端CK1的高电平信号提供给第一节点N1，使第一节点N1为高电平，第七开关晶体管T7导通，将第一参考信号端VGL的低电平信号提供给输出信号端GPOUT，输出信号端GPOUT输出低电平信号。
基于同一发明构思，本公开实施例还提供了一些本公开实施例提供的上述任一些移位寄存器的驱动方法，如图5所示，包括：
S501、第一阶段，对输入信号端加载第二电平的信号，对第一时钟信号端加载第一电平的信号，对第二时钟信号端加载第二电平的信号；
S502、第二阶段，对输入信号端加载第二电平的信号，对第一时钟信号端加载第二电平的信号，对第二时钟信号端加载第一电平的信号；
S503、第三阶段，对输入信号端加载第一电平的信号，对第一时钟信号端加载第一电平的信号，对第二时钟信号端加载第二电平的信号；
S504、第四阶段，对输入信号端加载第一电平的信号，对第一时钟信号端加载第二电平的信号，对第二时钟信号端加载第一电平的信号。
本公开实施例提供的上述驱动方法，可以使移位寄存器稳定的输出信号。在具体实施时，在本公开实施例提供的上述驱动方法中，第一电平可以为低电平，对应地，第二电平为高电平；或者反之，第一电平可以为高电平，对应地，第二电平为低电平，具体需要根据移位寄存器中的晶体管是N型晶体管还是P型晶体管而定。具体地，图4示出了移位寄存器中的晶体管是N型晶体管的一些信号时序图，且第一电平为低电平，第二电平为高电平。
基于同一发明构思，本公开实施例还提供了一些驱动电路，如图6所示，包括级联的多个本公开实施例提供的任一些移位寄存器：SR(1)、SR(2)…SR(n-1)、SR(n)…，SR(N-1)、SR(N)(共N个移位寄存器，1≤n≤N)；其中，
第一级移位寄存器SR(1)的输入信号端GPIN与帧触发信号端STV电连接；
除第一级移位寄存器SR(1)之外，其余各级移位寄存器SR(n)的输入信号端GPIN分别与其相邻的上一级移位寄存器SR(n-1)的输出信号端GPOUT电连接。
具体地，上述驱动电路中的每个移位寄存器的具体结构与本公开实施例提供的上述任一些移位寄存器在功能和结构上均相同，重复之处不再赘述。
在具体实施时，在本公开提供的上述驱动电路中，各级移位寄存器的第一参考信号端VGL均与同一参考信号线Vgl相连，各级移位寄存器的第二参考信号端VGH均与同一参考信号线Vgh相连。
在具体实施时，在具体实施时，奇数级移位寄存器的第一时钟信号端CK1电连接第一时钟线clk1，第二时钟信号端CK2电连接第二时钟线clk2；偶数级移位寄存器的第一时钟信号端CK1电连接第二时钟线clk2，第二时钟信号端CK2电连接第一时钟线clk1。
在具体实施时，本公开实施例提供的驱动电路可以作为栅极驱动电路，应用于提供扫描控制晶体管的栅极扫描信号。
在具体实施时，本公开实施例提供的驱动电路可以作为发光驱动电路，应用于提供发光控制晶体管的发光控制信号。
基于同一公开构思，本公开实施例还提供了一些显示装置，包括本公开提供的上述驱动电路。其具体实施可参见上述移位寄存器的实施过程，相同之处不再赘述。
在具体实施时，本公开实施例提供的上述显示装置可以为有机发光显示装置，或者也可以为液晶显示装置，在此不作限定。
在有机发光显示装置中，一般设置有多个有机发光二极管以及与各有机发光二极管连接的像素电路。一般像素电路中设置有用于控制有机发光二极管发光的发光控制晶体管和用于控制数据信号输入的扫描控制晶体管。在具体实施时，在本公开实施例提供的上述显示装置为有机发光显示装置时，该有机发光显示装置可以包括一个本公开实施例提供的上述驱动电路，该驱动电路可以作为发光驱动电路，应用于提供发光控制晶体管的发光控制信号；或者，该驱动电路也可以作为栅极驱动电路，应用于提供扫描控制晶体管的栅极扫描信号。当然，该有机发光显示装置也可以包括两个本公开实施例提供的上述驱动控制电路，其中一个驱动电路可以作为发光驱动电路，应用于提供发光控制晶体管的发光控制信号；则另一个驱动电路作为栅极驱动电路，应用于提供扫描控制晶体管的栅极扫描信号，在此不作限定。
在液晶显示装置中，一般设置有多个像素电极，以及与各像素电极连接的开关晶体管。在具体实施时，在本公开实施例提供的上述显示装置为液晶显示装置时，本公开实施例提供的上述驱动电路可以作为栅极驱动电路，应用于提供开关晶体管的栅极扫描信号。
该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
本公开实施例提供的一些移位寄存器，包括：控制电路、第一输出电路、第二输出电路。通过上述电路的相互配合，可以实现信号的移位输出，输出的信号可以作为发光控制晶体管的发光控制信号，也可以作为扫描控制晶体 管的栅极扫描信号。本公开实施例提供的一些驱动电路，包括上述任一些移位寄存器，通过在显示面板上集成上述驱动电路以对显示面板提供扫描驱动信号或发光驱动信号，可以使显示面板做到两边对称和窄边框的美观设计，还可以省去栅极扫描线方向的Bonding工艺，从而提高了产能和良率。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (10)

  1. 一种移位寄存器，其中，包括：
    控制电路，被配置为根据第一时钟信号端的信号、第二时钟信号端的信号和输入信号端的信号，调整第一节点和第二节点的信号；
    第一输出电路，被配置为响应于所述第一节点的信号，将第一参考信号端的信号提供给输出信号端；
    第一开关晶体管，其中，所述第一开关晶体管的第一端与所述第二节点电连接，所述第一开关晶体管的控制端与第二参考信号端电连接，所述第一开关晶体管的第二端与所述第二输出电路电连接；
    所述第二输出电路用于在所述第一开关晶体管的第二端的信号控制下，将所述第二参考信号端的信号提供给所述输出信号端。
  2. 如权利要求1所述的移位寄存器，其中，所述控制电路包括：输入电路、第一节点控制电路、第二节点控制电路；其中：
    所述输入电路被配置为响应于所述第二时钟信号端的信号和所述输入信号端的信号，将所述第一参考信号端的信号提供给第三节点；
    所述第一节点控制电路被配置为根据所述第一时钟信号端的信号调整所述第三节点的信号，响应于所述第三节点的信号，将所述第一时钟信号端的信号提供给所述第一节点，以及响应于所述第二节点的信号，将所述第一参考信号端的信号提供给所述第一节点；
    所述第二节点控制电路被配置为响应于所述第一时钟信号端的信号，将所述输入信号端的信号提供给所述第二节点。
  3. 如权利要求2所述的移位寄存器，其中，所述输入电路包括：第二开关晶体管和第三开关晶体管；其中：
    所述第二开关晶体管的第一端与所述第一参考信号端电连接，所述第二开关晶体管的控制端与所述输入信号端电连接，所述第二开关晶体管的第二端与所述第三节点电连接；
    所述第三开关晶体管的第一端与所述第一参考信号端电连接，所述第三开关晶体管的控制端与所述第二时钟信号端电连接，所述第三开关晶体管的第二端与所述第三节点电连接。
  4. 如权利要求2所述的移位寄存器，其中，所述第一节点控制电路包括：第四开关晶体管、第五开关晶体管以及第一电容；其中：
    所述第四开关晶体管的第一端与所述第一时钟信号端电连接，所述第四开关晶体管的控制端与所述第三节点电连接，所述第四开关晶体管的第二端与所述第一节点电连接；
    所述第五开关晶体管的第一端与所述第一参考信号端电连接，所述第五开关晶体管的控制端与所述第二节点电连接，所述第五开关晶体管的第二端与所述第一节点电连接；
    所述第一电容的第一端与所述第一时钟信号端电连接，所述第一电容的第二端与所述第三节点电连接。
  5. 如权利要求2所述的移位寄存器，其中，所述第二节点控制电路包括：第六开关晶体管；所述第六开关晶体管的第一端与所述输入信号端电连接，所述第六开关晶体管的控制端与所述第一时钟信号端电连接，所述第六开关晶体管的第二端与所述第二节点电连接。
  6. 如权利要求1所述的移位寄存器，其中，所述第一输出电路包括：第七开关晶体管和第二电容；其中：
    所述第七开关晶体管的第一端与所述第一参考信号端电连接，所述第七开关晶体管的控制端与所述第一节点电连接，所述第七开关晶体管的第二端与所述输出信号端电连接；
    所述第二电容的第一端与所述第一节点电连接，所述第二电容的第二端与所述第一参考信号端电连接。
  7. 如权利要求1所述的移位寄存器，其中，所述第二输出电路包括：第八开关晶体管和第三电容；其中：
    所述第八开关晶体管的第一端与所述第二参考信号端电连接，所述第八 开关晶体管的控制端与所述第一开关晶体管的第二端电连接，所述第八开关晶体管的第二端与所述输出信号端电连接；
    所述第三电容的第一端与所述第一开关晶体管的第二端电连接，所述第三电容的第二端与所述输出信号端电连接。
  8. 一种驱动电路，其中，包括级联的多个如权利要求1-7任一项所述的移位寄存器；其中：
    第一级移位寄存器的输入信号端与触发信号端电连接；
    每相邻两级移位寄存器中，下一级移位寄存器的输入信号端与上一级移位寄存器的输出信号端电连接。
  9. 一种显示装置，其中，包括如权利要求8所述的驱动电路。
  10. 一种如权利要求1-7任一项所述的移位寄存器的驱动方法，其中，包括：
    第一阶段，对输入信号端加载第二电平的信号，对第一时钟信号端加载第一电平的信号，对第二时钟信号端加载第二电平的信号；
    第二阶段，对输入信号端加载第二电平的信号，对第一时钟信号端加载第二电平的信号，对第二时钟信号端加载第一电平的信号；
    第三阶段，对输入信号端加载第一电平的信号，对第一时钟信号端加载第一电平的信号，对第二时钟信号端加载第二电平的信号；
    第四阶段，对输入信号端加载第一电平的信号，对第一时钟信号端加载第二电平的信号，对第二时钟信号端加载第一电平的信号。
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