WO2014015580A1 - 栅极驱动电路、方法及液晶显示器 - Google Patents

栅极驱动电路、方法及液晶显示器 Download PDF

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Publication number
WO2014015580A1
WO2014015580A1 PCT/CN2012/084688 CN2012084688W WO2014015580A1 WO 2014015580 A1 WO2014015580 A1 WO 2014015580A1 CN 2012084688 W CN2012084688 W CN 2012084688W WO 2014015580 A1 WO2014015580 A1 WO 2014015580A1
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Prior art keywords
clock signal
output
module
gate
high level
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PCT/CN2012/084688
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English (en)
French (fr)
Inventor
陈小川
薛海林
薛艳娜
李月
王学路
Original Assignee
北京京东方光电科技有限公司
京东方科技集团股份有限公司
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Application filed by 北京京东方光电科技有限公司, 京东方科技集团股份有限公司 filed Critical 北京京东方光电科技有限公司
Priority to US14/127,313 priority Critical patent/US9886921B2/en
Priority to EP12881530.5A priority patent/EP2879126B1/en
Publication of WO2014015580A1 publication Critical patent/WO2014015580A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention relates to gate drive technology, and more particularly to a gate drive circuit, method and liquid crystal display. Background technique
  • the GOA Gate On Array
  • COF Chip On Flex/Film
  • COG Chip On Glass
  • the GOA circuit commonly used in the gate driving circuit adopts the 10T1C mode, and one GOA unit in the gate driving circuit can only drive one row of gates, and requires 10 TFTs for driving each row of gates, and a small-sized display device
  • PPI Pixel Per Inch
  • the dot pitch is very small, sometimes less than 30*90 ⁇ ⁇ , to deploy 10 TFTs in a space of 90 ⁇ m It is necessary to arrange the 10 TFTs in a row, so that a large one is required for the sealing area.
  • the present invention provides a gate driving circuit, the gate driving circuit includes a multi-level GOA unit, and each GOA unit includes a pull-up module and an output module.
  • the pull-up module is configured to output a second clock signal to the office when the input signal is high Output module
  • the output module is configured to be turned on when the second clock signal is at a high level, and output a third clock signal as a first gate driving signal when turned on, and use a fourth clock signal as a second gate Drive signal output;
  • the third clock signal is in the same phase as the fourth clock signal, and the period of the second clock signal is twice the period of the third clock signal.
  • the GOA unit further includes a pull-down module for pulling down the pull-up module.
  • the third clock signal changes from a low level to a high level
  • the fourth clock signal changes from a high level to a low level. Level.
  • the pull-up module includes: a switching device, a boosting device, and a switching device 3. wherein the source of the switching device is used as an input signal terminal, the gate is connected to the source, and the drain is connected to the boost device.
  • the other end of the boost device is connected to the drain of the switching device 3;
  • the gate of the switching device 3 is connected at a connection point of the drain of the switching device 1 and the boosting device, the source serves as a second clock signal input terminal, and the drain is connected to the other end of the boosting device;
  • a connection point of the boosting device and the three drains of the switching device is used as an output end of the pull-up module, and is connected to the output module.
  • the output module includes: a switching device 7 and a switching device 10; wherein a gate of the switching device 7 is connected to an output end of the pull-up module, a source is used as a third clock signal input end, and a drain is used as a drain a first gate driving signal output terminal; a gate of the switching device 10 is connected to an output end of the pull-up module, a source serves as a fourth clock signal input terminal, and a drain serves as a second gate driving signal output terminal.
  • the output module is further configured to: when the third clock signal changes from a low level to a high level, and when the fourth clock signal changes from a high level to a low level, A gate drive signal is pulled low.
  • the output module further includes a switching device XI, a gate connected to the fourth clock signal input end, a source connected to the first gate driving signal output end, and a drain connected to the low level end.
  • the present invention also provides a liquid crystal display comprising the above gate drive Circuit.
  • the invention also provides a gate driving method, the gate driving method comprising:
  • the pull-up module When the input signal is high, the pull-up module outputs the second clock signal to the output module; when the second clock signal is high, the output module is turned on, and the third clock signal is used as the first gate driving signal. Outputting, outputting the fourth clock signal as a second gate driving signal;
  • the third clock signal is in the same phase as the fourth clock signal, and the period of the second clock signal is twice the period of the third clock signal.
  • the third clock signal changes from a low level to a high level
  • the fourth clock signal changes from a high level to a low level. Level.
  • the method further includes: The third clock signal changes from a low level to a high level, and when the fourth clock signal changes from a high level to a low level, the output module pulls the first gate drive signal low.
  • one GOA unit can output two gate driving signals, so that two rows of pixels are driven by one GOA unit, which requires less TFT than the existing GOA circuit.
  • Driving two rows of pixels saves space for TFT deployment, thereby reducing the package area of the liquid crystal display and realizing the narrow border of the liquid crystal display.
  • FIG. 1 is a schematic diagram showing the functional structure of each GOA unit in the gate driving circuit of the present invention
  • FIG. 2 is a schematic diagram showing the specific structure of a GOA unit in a gate driving circuit according to an embodiment of the present invention
  • FIG. 3 is a timing diagram of input and output signals of a GOA unit of a gate driving circuit according to an embodiment of the present invention
  • FIG. 4 is a flowchart of implementing a gate driving method according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram showing a specific structure of a GOA unit in a three-gate driving circuit according to an embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of a specific structure of a GOA unit in a four-gate driving circuit according to an embodiment of the present invention.
  • the array substrate includes p (p is an integer not less than 1) data driving lines and q (q is an integer not less than 1) gate driving lines, and the data driving lines and gates Pixels are arranged on the interlaced area of the driving line, that is, the pixel array of the liquid crystal display is provided with p rows and q columns of pixels, and the gate driving circuit of the liquid crystal display outputs a gate driving signal to the pixels through the gate driving line, thereby driving
  • the pixels are turned on, so that each pixel can receive the data signal output by the data driving circuit through the data driving line, and then perform image display based on the data signal.
  • the gate driving circuit of the liquid crystal display comprises a multi-level GOA unit, and each level of the GOA unit can drive two adjacent rows of pixels. Specifically, each level of the GOA unit drives adjacent two rows of pixels through two gate driving lines, in the GOA. When the unit outputs a high level signal, the corresponding adjacent two rows of pixels are driven to be turned on by the corresponding gate driving lines, so that the adjacent two rows of pixels can receive the data signal; when the GOA unit outputs a low level signal, the corresponding The adjacent two rows of pixels are turned off, and the reception of the data signal is stopped.
  • the multi-level GOA unit in the gate drive circuit sequentially outputs a high-level signal, and drives one by one in units of two adjacent pixels.
  • Each GOA unit has an input signal terminal (INPUT terminal), a reset signal input terminal (RESET input terminal), a low level (VSS) terminal, a first clock signal (CLK1) input terminal, and a second clock signal (CLK2) input terminal. a third clock signal (CLK3) input terminal, a fourth clock signal (CLK4) input terminal, a first gate drive signal (OUTPUT-n) output terminal, and a second gate drive signal (OUTPUT_n+1) output terminal
  • OUTPUT—n is the gate drive signal of the nth row of pixels
  • OUTPUT ⁇ n+1 is the gate drive signal of the n+1th row of pixels.
  • n is an integer not less than 1, and n is not less than the total number of rows of pixels p.
  • OUTPUT-n+1 can be left empty).
  • the signal OUTPUT_n-1 output by the above first stage GOA unit is INPUT, and the output signal OUTPUT_n+2 of the following first stage GOA unit is RESET; in particular, for the first stage In the GOA unit, the STV signal (frame open signal) is INPUT.
  • a dummy GOA unit (dummy GOA unit) that is redundantly connected is generally designed to be reset.
  • each level of the GOA unit includes a pull-up module 11 and an output module 12.
  • the pull-up module 11 outputs CLK2 to the output module 12 when the INPUT is high level, and the output module 12 is turned on when the CLK2 is high level, and uses CLK3 as the first gate driving signal when turned on ( OUTPUT — n ) Output, CLK4 is output as the second gate drive signal ( OUTPUT — n+1 ), where CLK3 and CLK4 have opposite phases and the same period.
  • the pull-up module 11 is further configured to stop outputting CLK 2 to when RESET is high.
  • the output module 12 enables the output module 12 to quickly stop outputting the gate drive signal and complete the reset operation. It can be seen that the output module 12 can realize the normal output in one cycle under the action of the pull-up module 11, complete a shift, and also reset the GOA unit according to the RESET signal to complete the reset of the GOA unit working process. operating.
  • Each level of the GOA unit further includes a pull-down module 13 for pulling down the voltage of the pull-up module 11, that is, suppressing the noise of the pull-up module 11.
  • the specific circuit structure of each level of the GOA unit is as shown in FIG. 2 , wherein the pull-up module 11 includes a switching device M1, a switching device 2, a boost device C1, and a switching device three M3, the source of the M1.
  • the gate is connected to the source, the drain is connected to the source of M2, the connection point between the M1 drain and the M2 source is the pull-up (PU) point, and the drain of the M2 is connected to the low-level (VSS) terminal.
  • the gate is connected to the RESET terminal.
  • One end of the boosting device C1 is connected to the gate of M3 and connected to the PU point, and the other end of C1 is connected to the drain of M3 and serves as the output terminal of the pull-up module 11, and the source of the M3 is used.
  • the second clock signal input terminal is connected to the gate of M3 and connected to the PU point, and the other end of C1 is connected to the drain of M3 and serves as the output terminal of the pull-up module 11, and the source of the M3 is used.
  • Output module 12 includes switching device seven M7, switching device eleven Mi l and switching device ten
  • the gate of M7 is connected to the output end of the pull-up module 11, that is, connected to the connection point of the drains of C1 and M3, the source is used as the input end of CLK3, the drain is used as the output terminal of OUTPUT-n; the gate of M10
  • the output terminal of the pull-up module 11 is connected, that is, connected to the connection point of the drains of C1 and M3, the source serves as the input end of the fourth clock signal, and the drain serves as the OUTPUT-n+1 output terminal;
  • the source connection of the Mi l The drain of M7 is connected to the OUTPUT-n output terminal, and the gate is connected to the source of M10, that is, connected to the input terminal of CLK4, and the drain is connected to the VSS terminal.
  • the pull-down module 13 includes a switching device four M4 having a gate connected to the RESET terminal, a drain connected to the drain of M3, that is, an output terminal of the pull-up module 11, and a source connected to the VSS terminal. The output voltage of the pull-up module 11 is pulled down according to the RESET signal.
  • the pull-down module 13 can also include a switching device five M5, a switching device six M6, and a switching device eight.
  • M8 switching device nine M9 and switching device twelve M12, wherein the source of M9 is used as the input end of CLK1, the gate of M9 is connected to the source, the drain is connected to the source of M8, and the gate of M5, the connection point is Pull down the (PD) point; the gate of M8 is connected to the gate of M6 and connected to the PU point, the drain of M8 is connected to the drain of M6 to the VSS terminal, the source of M6 is connected to the drain of M5, the source of M5 The pole is connected to the source of the M9;
  • the source of M12 is connected to the PU point, the gate is connected to the PD point of the pull-down module, and the drain of M2 is connected to M12.
  • the drain is connected to the low level (VSS) terminal.
  • the working process of the above GOA unit is as follows: When the gate drive signal OUTPUT_n-1 outputted by the GOA unit of the previous stage, that is, the INPUT of the GOA unit of the current stage is at a high level, M1 is turned on, charging the PU point, and C1 further Pulling up the PU point voltage, that is, charging the gate of M3, M3 is turned on; after that, CLK2 changes from low level to high level, and because M3 is turned on, the high level signal of CLK2 is transmitted to the gate of M7.
  • the drain of M7 that is, the output terminal of OUTPUT-n outputs CLK3 of high level, that is, the output OUTPUT-n, driving the pixel of the nth row to be turned on.
  • next stage GOA unit When the next stage GOA unit outputs OUTPUT_n+2, that is, when the RESET of the GOA unit of this stage is high level, M2 is turned on, discharging for the PU point, pulling the voltage of the PU point low, so that the voltage of the M3 gate is pulled. Low, M3 is disconnected, CLK2 cannot be sent to the gates of M7 and M10, so that M7 and M10 remain off, and the OUTPUT-n output and OUTPUT-n+1 output of the GOA unit of this stage stop output.
  • CLK1 and CLK2 are two clock signals having opposite phases and the same period
  • CLK3 and CLK4 are two clock signals having opposite phases and the same period
  • the period of CLK2 is The period of CLK3 is twice
  • the period of CLK3 and CLK4 is the time when one line of pixels is turned on, that is, one of the p points of one frame of image, where p is like The total number of lines.
  • CLK2 changes from low level to high level
  • CLK3 changes from low level to high level
  • CLK4 changes from high level to low level.
  • CLK2 of the GOA unit of this stage is the same as CLK1 of the adjacent stage GOA unit
  • CLK2 of the adjacent stage GOA unit is the same as CLK1 of the GOA unit of the current stage. That is to say, the phases of CLK1 of adjacent GOA units are opposite and the periods are the same, and the phases between CLK2 are opposite and the periods are the same.
  • the function of CI and C1 in the pull-up module 11 is to further increase the PU point voltage when CLK2 is at a high level, thereby reducing the coupling noise of CLK2 to the PU point through the parasitic capacitance of M3. That is, the noise of the output module 11 is also reduced accordingly.
  • M2 has a similar function to M12. It can pull the PU voltage low when RESET is high.
  • the pull down module 13 is also optional. M6, M8, M5, M9 are used to control the voltage of PD, PD voltage control M12 is turned on, PU voltage is pulled low, and then M3 is turned off, and CLK2 high level signal is not output to output module 12. It can be understood that the voltage of the PD point can be controlled in other ways, or the M12 can be controlled by a separate signal line, and only the effect of the voltage drop of the PU point in the embodiment of the M12 can be realized.
  • the voltage of the PD also controls the opening of M4, and the voltage input to the output module 12 of the pull-up module 11 can be pulled down, and the voltage of the pull-up module 11 can be pulled down, that is, the noise of the output module 12 can also be suppressed.
  • M4 can also be turned on by the RESET signal in this embodiment.
  • the pull-down module 13 can be divided into three branches, namely, the first pull-down branches M6, M8, M5, M9 and M12, and the second pull-down branches M6, M8, M5, M9 and M4. , the third pull-down branch M4 (its gate is connected to RESET), these three branches can exist alone or in combination.
  • Mil is also optional in output module 12. Its role is that under the action of CLK4, Mil further pulls the OUTPUT-n output low, so that the OUTPUT-n output stops OUTPUT-n and suppresses the noise generated by the OUTPUT-n output during this process.
  • the M1 M12 may be a metal-oxide-semiconductor (MOS) tube.
  • C1 is a capacitor device. Since the source and drain of the transistor are fabricated in the same process, the names are interchangeable and can be changed in name depending on the direction of the voltage.
  • This embodiment provides a gate driving method. As shown in FIG. 4, the method may mainly include the following steps:
  • Step 401 When the input signal is high, the pull-up module outputs the second clock signal to the input.
  • Step 402 When the second clock signal is at a high level, the output module is turned on, the third clock signal is output as the first gate driving signal, and the fourth clock signal is output as the second gate driving signal.
  • the third clock signal is in the same phase as the fourth clock signal, and the period of the second clock signal is twice the period of the third clock signal. Specifically, when the second clock signal changes from a low level to a high level, the third clock signal changes from a low level to a high level, and the fourth clock signal changes from a high level to a low level. .
  • the method may further include: The clock signal changes from a low level to a high level, and when the fourth clock signal changes from a high level to a low level, the output module pulls the first gate drive signal low.
  • each level of the GOA unit is as shown in FIG. 5, and its composition structure is basically the same as that of the second embodiment. The difference is that the switching device thirteen M13 is added, and the gate is connected to the PD point, the source.
  • the pole is connected to the output end of the pull-up module 11, that is, connected to the connection point of the drains of C1 and M3, and the drain is connected to the VSS terminal;
  • the gate of M4 is connected to the RESET input terminal, and the source is connected to the output end of the pull-up module 11, That is, it is connected at the connection point of the drains of C1 and M3, and the drain is connected to the VSS terminal; at this time, M4 is controlled by the RESET signal alone, and M13 is controlled by the PD point voltage signal alone.
  • the M13 pulls down the pull-up module under the control of the PD point
  • the M4 pulls down the pull-up module under the RESET control, so that M4 and Ml 3 jointly complete the role of M4 in the first embodiment, that is, the M4 in the first embodiment is not It needs to be in working condition all the time, which is beneficial to prolong the service life.
  • the specific circuit structure of each level of the GOA unit is as shown in FIG. 6, and its composition structure is basically the same as that of the GOA unit in the third embodiment.
  • the difference is that the switching device is added to the fourteen M14 in the pull-down module.
  • the gate of M14 is connected to the input end of CLK1, and the source is connected to the output end of the pull-up module 11, that is, connected to the connection point of the drains of C1 and M3, and the drain is connected to the VSS terminal.
  • CLK1 is high level
  • the M14 can further pull down the pull-up module to further improve the noise cancellation capability of the GOA unit.
  • one GOA unit can only drive one row of pixels, and the space required for deploying the TFT is larger; and in the gate driving circuit of the present invention, one GOA unit can drive two rows of pixels, compared with In the prior art, less TFT is needed, which can save TFT deployment space, reduce package area, and realize narrow frame of liquid crystal display.

Abstract

一种栅极驱动电路，包括多级GOA单元。每个GOA单元包括上拉模块（11）、输出模块（12）。该上拉模块（11）在输入信号（INPUT）为高电平时，将第二时钟信号（CLK2）输出给该输出模块（12）；该输出模块在（12）该第二时钟信号（CLK2）为高电平时导通，并在导通时将第三时钟信号（CLK3）作为第一栅极驱动信号（OUTPUT_n）输出，将第四时钟信号（CLK4）作为第二栅极驱动信号（OUTPUT_n+1）输出；该第三时钟信号（CLK3）与第四时钟信号（CLK4）相位相反且周期相同，该第二时钟信号（CLK2）的周期为该第三时钟信号（CLK3）周期的两倍。还公开了一种液晶显示器以及栅极驱动方法，通过一个GOA单元驱动两行像素，从而节省了TFT部署空间，减小了液晶显示器的封装区域。

Description

栅极驱动电路、 方法及液晶显示器 技术领域
本发明涉及栅极驱动技术， 尤其涉及一种栅极驱动电路、 方法及液晶显 示器。 背景技术
液晶显示器是目前常用的平板显示器， 其中薄膜晶体管液晶显示器 ( Thin Film Transistor Liquid Crystal Display, TFT-LCD )是目前液晶显示器 中的主流产品。 随着 TFT-LCD产品的竟争日益激烈， 各厂家纷纷通过釆用 新技术来降低产品的成本， 提高产品的市场竟争力。 其中， GOA ( Gate on Array )技术是指将 TFT-LCD的栅极驱动器（Gate Driver ) 集成在阵列基板 上， 形成对面板的扫描驱动。 相比传统覆晶薄膜（Chip On Flex/Film, COF ) 和直接绑定在玻璃上（Chip On Glass, COG )的工艺， 其不仅可以节省成本， 而且面板可以做到两边对称美观设计， 省去了栅集成电路（Gate IC )的绑定 ( Bonding ) 区域以及扇出 （ Fan-out ) 布线空间， 实现了窄边框的设计； 同 时由于可以省去栅极方向绑定的工艺， 对产能和良品率提升也比较有利。
目前， 现在栅极驱动电路中常用的 GOA电路釆用 10T1C模式， 栅极驱 动电路中的一个 GOA单元仅能够驱动一行栅极，且驱动每行栅极需要 10个 TFT, 而小尺寸的显示装置在高每英寸像素数（PPI, Pixel Per Inch ) 的分辨 率下， 点距（Dot pitch )会非常小， 有时候不足 30*90 μ πι, 要在 90 μ πι的 空间上部署 10个 TFT就需要将这 10个 TFT排布成一排， 这样， 就需要很 大的一个去†装区或 ( sealing area )。 发明内容
有鉴于此， 本发明的主要目的在于提供一种栅极驱动电路、 方法及显示 器， 能够减小 GOA电路占用的空间， 进而减小显示装置的封装区域。
为达到上述目的， 本发明的技术方案是这样实现的：
本发明提供了一种栅极驱动电路， 所述栅极驱动电路包括多级 GOA单 元， 每个 GOA单元包括上拉模块、 输出模块，
所述上拉模块， 用于在输入信号为高电平时， 将第二时钟信号输出给所 述输出模块；
所述输出模块， 用于在所述第二时钟信号为高电平时导通， 并在导通时 将第三时钟信号作为第一栅极驱动信号输出，将第四时钟信号作为第二栅极 驱动信号输出；
所述第三时钟信号与第四时钟信号相位相反周期相同， 所述第二时钟信 号的周期为所述第三时钟信号周期的二倍。
在上述方案中， 所述 GOA单元还包括下拉模块， 用于对上拉模块进行 下拉。
在上述方案中， 所述第二时钟信号由低电平变为高电平时， 所述第三时 钟信号由低电平变为高电平， 所述第四时钟信号由高电平变为低电平。
在上述方案中， 所述上拉模块包括： 开关器件一、 升压器件、 开关器件 三； 其中， 开关器件一的源极作为输入信号端， 栅极连接源极， 漏极连接升 压器件的一端；
升压器件的另一端连接开关器件三的漏极；
开关器件三的栅极连接在开关器件一的漏极与升压器件的连接点上， 源 极作为第二时钟信号输入端 , 漏极与所述升压器件的另一端连接；
所述升压器件与开关器件三漏极的连接点作为所述上拉模块的输出端， 连接所述输出模块。
在上述方案中， 所述输出模块包括： 开关器件七和开关器件十； 其中， 开关器件七的栅极连接所述上拉模块的输出端， 源极作为第三时钟信号输入 端， 漏极作为第一栅极驱动信号输出端； 开关器件十的栅极连接所述上拉模 块的输出端， 源极作为第四时钟信号输入端， 漏极作为第二栅极驱动信号输 出端。
在上述方案中， 所述输出模块， 还用于在所述第三时钟信号由低电平变 为高电平， 所述第四时钟信号由高电平变为低电平时， 将所述第一栅极驱动 信号拉低。
在上述方案中， 所述输出模块还包括开关器件十一， 栅极连接所述第四 时钟信号输入端， 源极连接所述第一栅极驱动信号输出端， 漏极连接低电平 端。
在上述方案中，相邻 GOA单元的第二时钟信号之间相位相反周期相同。 本发明还提供了一种液晶显示器， 所述液晶显示器包括上述的栅极驱动 电路。
本发明还提供了一种栅极驱动方法， 所述栅极驱动方法包括：
在输入信号为高电平时， 上拉模块将第二时钟信号输出给输出模块； 在所述第二时钟信号为高电平时， 输出模块导通， 将第三时钟信号作为 第一栅极驱动信号输出， 将第四时钟信号作为第二栅极驱动信号输出；
所述第三时钟信号与第四时钟信号相位相反周期相同， 所述第二时钟信 号的周期为所述第三时钟信号周期的二倍。
在上述方案中， 所述第二时钟信号由低电平变为高电平时， 所述第三时 钟信号由低电平变为高电平， 所述第四时钟信号由高电平变为低电平。
在上述方案中， 所述将第三时钟信号作为第一栅极驱动信号输出之后， 所述将第四栅极驱动信号作为第二栅极驱动信号输出之前， 所述方法还包 括： 在所述第三时钟信号由低电平变为高电平， 所述第四时钟信号由高电平 变为低电平时， 所述输出模块将所述第一栅极驱动信号拉低。
本发明的栅极驱动电路中一个 GOA单元能够输出两个栅极驱动信号， 这样， 通过一个 GOA单元来驱动两行像素， 相较于现有的 GOA电路来说， 需要较少的 TFT便可驱动两行像素， 节省了 TFT部署空间， 从而减小了液 晶显示器的封装区域， 实现了液晶显示器的窄边框。 附图说明
图 1为本发明栅极驱动电路中每个 GOA单元的功能结构示意图； 图 2为本发明实施例一栅极驱动电路中 GOA单元的具体组成结构示意 图；
图 3为本发明实施例一栅极驱动电路的 GOA单元的输入输出信号的时 序图；
图 4为本发明实施例二栅极驱动方法的实现流程图；
图 5为本发明实施例三栅极驱动电路中 GOA单元的具体组成结构示意 图； 和
图 6为本发明实施例四栅极驱动电路中 GOA单元的具体组成结构示意 图。 具体实施方式 本发明中的液晶显示器， 其阵列基板上包含 p ( p为不小于 1的整数） 条数据驱动线和 q ( q为不小于 1的整数）条栅极驱动线， 在数据驱动线和 栅极驱动线交错的区域上设置有像素， 也就是说， 液晶显示器的阵列基板上 设置有 p行 q列像素， 液晶显示器的栅极驱动电路通过栅极驱动线向像素输 出栅极驱动信号， 从而驱动像素打开， 使得各像素能够接收数据驱动电路通 过数据驱动线输出的数据信号， 进而基于数据信号进行图像显示。
液晶显示器的栅极驱动电路包括多级 GOA单元， 每级 GOA单元可以 驱动相邻的两行像素， 具体地， 每级 GOA单元通过两条栅极驱动线驱动相 邻的两行像素， 在 GOA单元输出高电平信号时， 通过相应的栅极驱动线驱 动相应的相邻两行像素打开， 使得所述相邻两行像素能够接收数据信号； 在 GOA单元输出低电平信号时， 相应的相邻两行像素关闭， 停止接收数据信 号。 如此， 在一帧画面里， 栅极驱动电路中的多级 GOA单元， 依次输出高 电平信号， 以相邻两行像素为单位逐一进行驱动。
每个 GOA单元具有输入信号端（ INPUT端）、复位信号输入端（ RESET 输入端）、 低电平 （VSS )端、 第一时钟信号 （CLK1 )输入端、 第二时钟信 号（ CLK2 )输入端、 第三时钟信号（ CLK3 )输入端、 第四时钟信号（ CLK4 ) 输入端、 第一栅极驱动信号 （OUTPUT— n ) 输出端和第二栅极驱动信号 ( OUTPUT— n+1 )输出端，其中， OUTPUT— n为第 n行像素的栅极驱动信号， OUTPUT— n+1为第 n+1行像素的栅极驱动信号。 （n为不小于 1 的整数， n 不小于像素的总行数 p,如果 n为最后一行像素，则 OUTPUT— n+1端可以空 接）。 非第一级的任意一级 GOA单元， 以上一级 GOA单元输出的信号 OUTPUT— n-1为 INPUT, 以下一级 GOA单元的输出信号 OUTPUT— n+2为 RESET;特别的，对于第一级 GOA单元，以 STV信号（帧开启信号）为 INPUT, 对于最后一级 GOA单元，一般会设计一个多余接空的伪 GOA单元（ dummy GOA单元）来对其进行复位。
具体的， 如图 1所示， 每级 GOA单元包含上拉模块 11、 输出模块 12。 其中， 上拉模块 11在 INPUT为高电平时， 将 CLK2输出给输出模块 12, 输 出模块 12在所述 CLK2为高电平时导通， 并在导通时将 CLK3作为第一栅 极驱动信号 （ OUTPUT— n ) 输出， 将 CLK4 作为第二栅极驱动信号 ( OUTPUT— n+1 )输出， 其中， CLK3和 CLK4相位相反且周期相同。
此外，上拉模块 11还用于在 RESET为高电平时，停止将 CLK 2输出给 所述输出模块 12 , 使得输出模块 12能够迅速停止输出栅极驱动信号及完成 复位操作。 由此可知， 输出模块 12在上拉模块 11的作用下可以实现在一个 周期内正常输出， 完成一次移位， 并且还根据 RESET信号使得所述 GOA单 元复位， 完成所述 GOA单元工作过程的复位操作。
每级 GOA单元还包含下拉模块 13 , 用于对上拉模块 11的电压进行下 拉， 即抑制上拉模块 11的噪声。
实施例一
本实施例中， 每级 GOA单元的具体电路结构如图 2所示， 其中， 上拉 模块 11 包括开关器件一 Ml、 开关器件二 M2、 升压器件 C1和开关器件三 M3 , Ml的源极作为 INPUT端 , 栅极连接源极 , 漏极与 M2的源极连接 , Ml漏极与 M2源极的连接点为拉升（PU )点， M2的漏极连接低电平（VSS ) 端， 栅极连接 RESET端， 升压器件 C1 的一端与 M3的栅极连接并连接在 PU点上， C1的另一端与 M3的漏极连接并作为上拉模块 11的输出端， M3 的源极作为第二时钟信号输入端。
输出模块 12 包括开关器件七 M7、 开关器件十一 Mi l 和开关器件十
M10 , 其中， M7的栅极连接上拉模块 11的输出端， 即连接在 C1与 M3漏 极的连接点上， 源极作为 CLK3输入端， 漏极作为 OUTPUT— n输出端； M10 的栅极连接上拉模块 11的输出端， 即连接在 C1与 M3漏极的连接点上， 源 极作为第四时钟信号的输入端， 漏极作为 OUTPUT— n+1输出端； Mi l的源 极连接 M7的漏极， 即连接 OUTPUT— n输出端， 栅极连接 M10的源极， 即 连接 CLK4输入端， 漏极连接 VSS端。
下拉模块 13 包括开关器件四 M4 , 其栅极连接 RESET端， 漏极连接 M3的漏极， 即上拉模块 11的输出端， 源极连接 VSS端。 根据 RESET信号 对上拉模块 11的输出端电压进行下拉。
下拉模块 13还可以包括开关器件五 M5、 开关器件六 M6、 开关器件八
M8、 开关器件九 M9和开关器件十二 M12 , 其中 M9的源极作为 CLK1输 入端， M9的栅极连接源极， 漏极与 M8的源极、 以及 M5的栅极连接， 该 连接点为拉低 ( PD )点； M8的栅极与 M6的栅极连接并连接在 PU点上， M8的漏极与 M6的漏极连接 VSS端， M6的源极连接 M5的漏极， M5的源 极连接 M9的源极；
M12的源极连接 PU点，栅极连接下拉模块的 PD点， M2的漏极与 M12 的漏极连接低电平 （VSS )端。
上述 GOA单元的工作过程如下： 在上一级 GOA单元输出的栅极驱动 信号 OUTPUT— n-1时 , 即本级 GOA单元的 INPUT为高电平时， Ml导通 , 为 PU点充电， C1进一步拉高 PU点电压， 也就是为 M3的栅极充电， M3 导通； 之后， CLK2由低电平变为高电平， 由于 M3导通， 将 CLK2的高电 平信号传输到 M7的栅极和 M10的栅极， 使得 M7和 M10导通， CLK3也 为高电平， 则 M7的漏极即 OUTPUT— n输出端输出高电平的 CLK3 , 即输出 OUTPUT— n, 驱动第 n行像素打开； 然后， CLK3 由高电平变为低电平， OUTPUT— n输出端停止 OUTPUT— n , CLK4由低电平变为高电平， 由于 M10 仍处于导通状态， M10的漏极即 OUTPUT— η+1输出端输出高电平的 CLK4 , 即输出 OUTPUT— η+1 ,驱动第 η+1行的像素打开 , Ml 1也导通 ,将 OUTPUT— n 输出端进一步拉低， 使得 OUTPUT— n输出端停止 OUTPUT— n并抑制此过程 中 OUTPUT— n输出端产生的噪声。 在 CLK3由低电平再变为高电平， CLK4 由高电平变为低电平时， CLK2由高电平变为低电平， M7和 M10被断开， OUTPUT— n输出端和 OUTPUT— n+1输出端被迅速拉低， 停止输出。
在下一级 GOA单元输出 OUTPUT— n+2时，即本级 GOA单元的 RESET 为高电平时， M2导通， 为 PU点放电， 将 PU点的电压拉低， 使得 M3栅极 的电压被拉低， M3断开， CLK2不能被送到 M7和 M10的栅极， 使得 M7 和 M10保持断开状态 ,本级 GOA单元的 OUTPUT— n输出端和 OUTPUT— n+1 输出端停止输出。
在上述过程中， CLK2 由高电平变为低电平时， CLK1 由低电平变为高 电平， M9导通， 为 PD点充电， 拉高 PD点电压， M5导通， M5为 PD点充 电， 进一步拉高 PD点电压， 使得 M12和 M4导通， M12在导通时为 PU点 放电， 抑制上拉模块 11产生的噪声， M4在导通时为 C1的另一端、 M3的 漏极、 M7的栅极以及 M10的栅极放电， 抑制输出模块 12产生的噪声。 在 CLK2为高电平时， 也就是本级 GOA单元正常输出时， M6和 M8也导通 , 用于抑制上拉模块 11产生的噪声。
上述 GOA单元的输入输出信号时序如图 3所示， 其中， CLK1与 CLK2 是相位相反且周期相同的两个时钟信号， CLK3和 CLK4是相位相反且周期 相同的两个时钟信号， CLK2的周期为 CLK3周期的两倍， CLK3和 CLK4 的周期为一行像素打开的时间， 也就是一帧图像的 p分之一， 其中， p为像 素的总行数。 其中， CLK2 由低电平变为高电平时， CLK3 由低电平变为高 电平， CLK4由高电平变为低电平。 特别的， 本级 GOA单元的 CLK2与相 邻级 GOA单元的 CLK1相同，相邻级 GOA单元的 CLK2与本级 GOA单元 的 CLK1相同。 也就是说， 相邻 GOA单元的 CLK1之间相位相反且周期相 同， CLK2之间相位相反且周期相同。
通过上述工作过程的描述可知，所述上拉模块 11中的 CI , C1的作用为 在 CLK2为高电平时， 进一步拉高 PU点电压， 进而减少 CLK2通过 M3的 寄生电容向 PU点耦合噪声， 即输出模块 11的噪声也会相应减少。 M2有类 似于 M12的作用， 可以在 RESET为高电平对 PU点电压进行拉低。
下拉模块 13也是可选的。 其中 M6、 M8 、 M5、 M9用于控制 PD的电 压， PD 的电压控制 M12 的开启， 对 PU点电压进行拉低， 进而加快关闭 M3 , 不将 CLK2高电平信号输出给输出模块 12。 可以理解的， 可以用其他 方式控制 PD点的电压， 也可以通过单独的信号线控制 M12, 只需实现 M12 在本实施例中的对 PU点电压拉低作用即可。 与此同时， PD的电压还控制 M4的开启， 可以对上拉模块 11输入到输出模块 12的电压进行下拉， 对上 拉模块 11 电压进行下拉， 即也可以认为抑制输出模块 12噪声。 当然， M4 在本实施例中还可以由 RESET信号控制开启。 通过以上分析可以得知， 可 以将下拉模块 13分为 3条支路， 即第一下拉支路 M6、 M8 、 M5、 M9和 M12, 第二下拉支路 M6、 M8 、 M5、 M9和 M4, 第三下拉支路 M4 (其栅 极连接 RESET ), 这三个支路可以单独或组合存在。
输出模块 12中 Mil也是可选的。其作用是 Mil在 CLK4的作用下，将 OUTPUT— n输出端进一步拉低，使得 OUTPUT— n输出端停止 OUTPUT— n并 抑制此过程中 OUTPUT— n输出端产生的噪声。
其中， 上述 M1 M12 具体可以为金属-氧化物 -半导体场效应晶体 ( Metal-Oxide-Semiconductor, MOS )管。 C1为电容器件。 由于晶体管的源 极和漏极的制作工艺相同， 名称上是可以互换的， 其可根据电压的方向在名 称上改变。
实施例二
本实施例提供了一种栅极驱动方法， 如图 4所示， 所述方法主要可以包 括如下步骤：
步骤 401 : 在输入信号为高电平时， 上拉模块将第二时钟信号输出给输 出模块；
步骤 402: 在所述第二时钟信号为高电平时， 输出模块导通， 将第三时 钟信号作为第一栅极驱动信号输出，将第四时钟信号作为第二栅极驱动信号 输出。
这里， 所述第三时钟信号与第四时钟信号相位相反周期相同， 所述第二 时钟信号的周期为所述第三时钟信号周期的二倍。 特别的， 所述第二时钟信 号由低电平变为高电平时， 所述第三时钟信号由低电平变为高电平， 所述第 四时钟信号由高电平变为低电平。
其中， 所述将第三时钟信号作为第一栅极驱动信号输出之后， 所述将第 四栅极驱动信号作为第二栅极驱动信号输出之前， 所述方法还可以包括： 在 所述第三时钟信号由低电平变为高电平， 所述第四时钟信号由高电平变为低 电平时， 所述输出模块将所述第一栅极驱动信号拉低。
实施例三
本实施例中， 每级 GOA单元的具体电路结构如图 5所示， 其组成结构 与实施例二基本相同， 所不同的是， 增加了开关器件十三 M13 , 其栅极连接 PD点， 源极连接在上拉模块 11的输出端， 即连接在 C1与 M3漏极的连接 点上， 漏极连接 VSS端； M4栅极连接 RESET输入端， 源极连接在上拉模 块 11的输出端， 即连接在 C1与 M3漏极的连接点上， 漏极连接 VSS端； 而此时的 M4单独受 RESET信号控制， M13单独受 PD点电压信号控制。 如此， M13在 PD点的控制下对上拉模块进行下拉， M4在 RESET控制下对 上拉模块进行下拉，使得 M4和 Ml 3共同完成实施例一中 M4的作用， 即实 施例一中 M4不需要一直处于工作状态， 有利于延长使用寿命。
实施例四
本实施例中， 每级 GOA单元的具体电路结构如图 6所示， 其组成结构 与实施例三中的 GOA单元基本相同， 所不同的是， 在下拉模块中又增加了 开关器件十四 M14, M14的栅极连接 CLK1输入端， 源极连接在上拉模块 11的输出端，即连接在 C1与 M3漏极的连接点上，漏极连接 VSS端，如此， 在 CLK1为高电平时， M14能将上拉模块进一步拉低， 进一步提高 GOA单 元的去噪声能力。
现有技术中一个 GOA单元只能驱动一行像素， 部署 TFT需要的空间较 大； 而本发明的栅极驱动电路中， 一个 GOA单元可以驱动两行像素， 相较 于现有技术来说需要较少的 TFT便可实现， 从而可以节省 TFT部署空间， 减小封装区域， 实现了液晶显示器的窄边框化。
以上所述， 仅为本发明的较佳实施例而已， 并非用于限定本发明的保护 范围。
附图标记说明： M1-TFT 开关器件一； M2-TFT 开关器件二； M3-TFT 开关器件三； M4-TFT开关器件四； M5-TFT开关器件五； M6-TFT开关器件 六； M7-TFT 开关器件七； M8-TFT 开关器件八； M9-TFT 开关器件九； M10-TFT开关器件十； M11-TFT开关器件十一； M12-TFT开关器件十二； M13-TFT开关器件十三； M14-TFT开关器件十四； C1-升压器件； 11-上拉模 块； 12-输出模块； 13-下拉模块。

Claims

权利要求书
1、 一种栅极驱动电路， 所述栅极驱动电路包括多级 GOA单元， 每个 GOA单元包括：
上拉模块， 用于在输入信号为高电平时， 将第二时钟信号输出给所述输 出模块； 和
输出模块， 用于在所述第二时钟信号为高电平时导通， 并在导通时将第 三时钟信号作为第一栅极驱动信号输出，将第四时钟信号作为第二栅极驱动 信号输出，
所述第三时钟信号与第四时钟信号相位相反周期相同， 所述第二时钟信 号的周期为所述第三时钟信号周期的二倍。
2、 根据权利要求 1所述的栅极驱动电路， 其中， 所述 GOA单元还包括 下拉模块， 用于对上拉模块电压进行下拉。
3、 根据权利要求 1 所述的栅极驱动电路， 其中， 所述第二时钟信号由 低电平变为高电平时， 所述第三时钟信号由低电平变为高电平， 所述第四时 钟信号由高电平变为低电平。
4、 根据权利要求 1 所述的栅极驱动电路， 所述上拉模块包括： 开关器 件一、 升压器件、 开关器件三； 其中，
开关器件一的源极作为输入信号端， 栅极连接源极， 漏极连接升压器件 的一端；
升压器件的另一端连接开关器件三的漏极；
开关器件三的栅极连接在开关器件一的漏极与升压器件的连接点上， 源 极作为第二时钟信号输入端 , 漏极与所述升压器件的另一端连接；
所述升压器件与开关器件三漏极的连接点作为所述上拉模块的输出端， 连接所述输出模块。
5、 根据权利要求 1 所述的栅极驱动电路， 所述输出模块包括： 开关器 件七和开关器件十； 其中， 开关器件七的栅极连接所述上拉模块的输出端， 源极作为第三时钟信号输入端， 漏极作为第一栅极驱动信号输出端； 开关器 件十的栅极连接所述上拉模块的输出端， 源极作为第四时钟信号输入端， 漏 极作为第二栅极驱动信号输出端。
6、 根据权利要求 1 所述的栅极驱动方法， 所述输出模块还用于在所述 第三时钟信号由低电平变为高电平， 所述第四时钟信号由高电平变为低电平 时， 将所述第一栅极驱动信号拉低。
7、 根据权利要求 5所述的栅极驱动电路， 所述输出模块还包括开关器 件十一， 栅极连接所述第四时钟信号输入端， 源极连接所述第一栅极驱动信 号输出端， 漏极连接低电平端。
8、根据权利要求 1至 6任一项所述的栅极驱动电路，相邻 GOA单元的 第二时钟信号之间相位相反周期相同。
9、 一种液晶显示器， 所述液晶显示器包括如权利要求 1至 6任一项所 述的栅极驱动电路。
10、 一种栅极驱动方法， 所述栅极驱动方法包括：
在输入信号为高电平时， 上拉模块将第二时钟信号输出给输出模块； 在所述第二时钟信号为高电平时， 输出模块导通， 将第三时钟信号作为 第一栅极驱动信号输出， 将第四时钟信号作为第二栅极驱动信号输出； 所述第三时钟信号与第四时钟信号相位相反周期相同， 所述第二时钟信 号的周期为所述第三时钟信号周期的二倍。
11、 根据权利要求 10所述的栅极驱动方法， 其中， 所述第二时钟信号 由低电平变为高电平时， 所述第三时钟信号由低电平变为高电平， 所述第四 时钟信号由高电平变为低电平。
12、 根据权利要求 10所述的栅极驱动方法， 其中， 所述将第三时钟信 号作为第一栅极驱动信号输出之后， 所述将第四栅极驱动信号作为第二栅极 驱动信号输出之前， 所述方法还包括： 在所述第三时钟信号由低电平变为高 电平， 所述第四时钟信号由高电平变为低电平时， 所述输出模块将所述第一 栅极驱动信号拉低。
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US9886921B2 (en) 2018-02-06
US20140159997A1 (en) 2014-06-12
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EP2879126A4 (en) 2016-01-20
EP2879126A1 (en) 2015-06-03
EP2879126B1 (en) 2019-07-31

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