WO2013143307A1 - 栅极驱动电路、栅极驱动方法及液晶显示器 - Google Patents

栅极驱动电路、栅极驱动方法及液晶显示器 Download PDF

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Publication number
WO2013143307A1
WO2013143307A1 PCT/CN2012/085194 CN2012085194W WO2013143307A1 WO 2013143307 A1 WO2013143307 A1 WO 2013143307A1 CN 2012085194 W CN2012085194 W CN 2012085194W WO 2013143307 A1 WO2013143307 A1 WO 2013143307A1
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WIPO (PCT)
Prior art keywords
switching device
unit
tft switching
pull
shift register
Prior art date
Application number
PCT/CN2012/085194
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English (en)
French (fr)
Inventor
陈希
崔文海
Original Assignee
北京京东方光电科技有限公司
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Application filed by 北京京东方光电科技有限公司 filed Critical 北京京东方光电科技有限公司
Priority to US13/884,713 priority Critical patent/US9378692B2/en
Priority to EP12842680.6A priority patent/EP2667376B1/en
Priority to JP2015502060A priority patent/JP6193969B2/ja
Priority to KR1020137012244A priority patent/KR101521732B1/ko
Publication of WO2013143307A1 publication Critical patent/WO2013143307A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/041—Temperature compensation

Definitions

  • the present invention relates to a gate driving technique, and more particularly to a gate driving circuit, a gate driving method, and a liquid crystal display. Background technique
  • the GOA Gate on Array
  • COF Chip On Flex/Film
  • COG Chip On Glass
  • the existing gate drive circuit includes a multi-stage shift register.
  • Figure 1 shows the structure of each stage shift register in the existing gate drive circuit.
  • the shift register of each stage specifically includes a TFT switching device - M1, a TFT switching device M2, a TFT switching device three M3, a TFT switching device four M4, a pull-down unit PD, and a boosting device C1;
  • the drain and the gate of M1 are connected to the input terminal (INPUT), and receive the output signal of the upper shift register;
  • the drain of M2 is connected to the source of M1, the gate of M2 is connected to the reset terminal (RESET), and Receiving the output signal of the lower shift register, the source of M2 is connected to the low voltage signal terminal (VSS), and receives the low voltage signal;
  • the drain of M3 is connected to the clock signal end, the gate of M3 is connected to the source of M1, the source of M3
  • the pole is used as the signal
  • One end of C1 and Ml And the gate of M3 is connected to the other end connected to the source of M3; pull-down unit PD only to C1 in parallel, while one end connected to the low pressure end signal (the VSS), and the other end connected to the drain of M3.
  • the working principle of the above gate driving circuit is as follows: When the input signal of INPUT is high level, M1 is turned on to charge the PU node; when the clock signal is high, M3 is turned on, and the output of the OUTPUT is pulsed by the clock signal, The Bootstrapping function of C1 further pulls up the PU node; after that, the reset signal of RESET turns on M2 and M4, and discharges the PU and OUTPUT.
  • the circuit device of the pull-down unit PD is controlled by the clock signal to the PU node and The OUTPUT is further discharged, which ensures that the line corresponding to the shift register of the stage will not generate noise during non-working time.
  • the timing of each signal is shown in Figure 2.
  • the shift shown in Figure 1 is applied.
  • the OUTPUT transitions from a high level to a low level, and the pixel jump voltage is large, which affects the picture quality of the liquid crystal display.
  • MLG multi-level gate
  • the principle of MLG is to generate a feedback at the output.
  • the signal is sent to the DC/DC IC, which in turn generates a voltage and outputs it.
  • the existing gate driving circuit generally employs an ⁇ -Si process, and since the mobility of the high-temperature TFT is about half lower than that of the high-temperature TFT under low temperature conditions, in order to avoid the gate driving A failure occurs when the circuit is in a lower temperature condition. It is usually used in a solution that adds a temperature compensation circuit outside the gate drive circuit.
  • the thermal device can be connected in parallel to the feedback circuit that generates the gate high level Vgh. , Vgh rises with temperature; the voltage may rise above 30V, DC/DC IC can not withstand such a high voltage, at this time, the function of MLG will be invalid. When the MLG function fails, there will be a large jump voltage at the moment of the TFT cutoff, which affects the picture quality of the TFT panel. Summary of the invention
  • Embodiments of the present invention provide a gate driving circuit including a multi-stage shift register, wherein each stage shift register includes a pull-up driving unit, a pull-up unit, a reset unit, and a pull-down unit, and the shift register further includes : supplementary unit; among them,
  • the pull-up unit is configured to use a clock signal of the first clock end as an output signal of the shift register of the current stage when turned on;
  • the supplemental unit is connected to the pull-up unit for turning the second clock end when conducting
  • the clock signal is used as the output signal of the shift register of this stage.
  • the pull-up drive unit is coupled to an input node of the pull-up unit for controlling the turn-on and turn-off of the pull-up unit.
  • the pull-up driving unit includes a TFT switching device 1 and a TFT switching device 2;
  • a drain and a gate of the TFT switching device are connected to an output of the upper shift register; a drain of the TFT switching device 2 is connected to a source of the TFT switching device,
  • the gate of the TFT switching device 2 is connected to the output terminal of the lower shift register, and the source of the TFT switching device 2 is connected at a low level.
  • the pull-up unit includes a TFT switching device 3 and a boosting device; wherein a drain of the TFT switching device 3 is connected to a first clock terminal, and a gate of the TFT switching device 3 and a TFT switch The source of the device 1 is connected, and the source of the TFT switching device 3 is the output terminal of the shift register of the current stage;
  • the boosting device has a first end connected to a source of the TFT switching device and a gate of the TFT switching device 3, and a second end connected to a source of the TFT switching device 3.
  • the reset unit includes a TFT switching device 4; a drain of the TFT switching device 4 is connected to a source of the TFT switching device 3, and a gate of the TFT switching device 4 and an output of a lower shift register Connected to the terminals, the source of the TFT switching device 4 is connected to a low level.
  • the supplemental unit includes a TFT switching device 5 and a TFT switching device 6; wherein
  • the drain and the gate of the TFT switching device 5 are connected to the second clock terminal, the drain of the TFT switching device 6 is connected to the source of the TFT switching device 5, the gate of the TFT switching device 6 and the TFT of the pull-up driving unit
  • the source of the switching device 1 is connected, and the source of the TFT switching device 6 is connected to the output terminal of the pull-up unit, and is also the output terminal of the shift register of the stage.
  • the TFT switching device 5 and the TFT switching device 6 are metal-oxide-semiconductor field effect transistors.
  • the clock signal of the second clock terminal transitions to a high level at a moment when the first clock terminal clock signal goes low.
  • Embodiments of the present invention provide a liquid crystal display including the gate driving circuit as described above.
  • the embodiment of the invention further provides a gate driving method, the method comprising: When the signal outputted from the output terminal of the upper shift register is at a high level, the pull-up driving unit is turned on, and the shift register of the current stage starts charging;
  • the pull-up unit When the clock signal of the first clock terminal is high level and the clock signal of the second clock terminal is low level, the pull-up unit is turned on, and the clock signal of the first clock end is used as an output signal of the shift register of the current stage;
  • the clock signal of the first clock end jumps to a low level
  • the clock signal of the second clock end jumps to a high level
  • the supplemental unit is turned on
  • the clock signal of the second clock end is used as a shift register of the current stage. Output signal.
  • the high level of the clock signal of the second clock terminal is lower than the high level of the clock signal of the first clock terminal.
  • the invention adopts a supplemental unit of each stage shift register in the gate driving circuit, and at the instant when the TFT is turned off, the supplementary unit is turned on, and controls the output of the shift register, thereby reducing the jump voltage of the pixel and realizing the MLG function. Improve the picture quality of the LCD display.
  • 1 is a schematic structural diagram of each stage of a mobile register in a conventional gate driving circuit
  • FIG. 2 is a timing chart of input and output signals of a shift register of the conventional gate driving circuit shown in FIG. 1;
  • FIG. 3 is a schematic structural diagram of a shift register in a gate driving circuit according to an embodiment of the present invention
  • FIG. 4 is a structural diagram of a specific implementation of a shift register of a gate driving circuit according to an embodiment of the present invention
  • Timing diagram of the input and output signals of the shift register of the gate drive circuit
  • FIG. 6 is a schematic diagram of a principle of an MLG function implemented by a gate driving circuit according to an embodiment of the present invention
  • FIG. 7 is a schematic flowchart of an implementation of a gate driving method according to an embodiment of the present invention.
  • M1-TFT switching device one M2-TFT switching device two; M3-TFT switching device three; M4-TFT switching device four; M5-TFT switching device five; M6-TFT switching device six; PD-down Unit; C1-boost device; 31-GOA circuit unit; 32-supplement unit.
  • the gate driving circuit includes a multi-stage shift register, wherein each stage shift register includes a pull-up driving unit, a pull-up unit, a reset unit, a pull-down unit, and further includes:
  • the pull-up unit is configured to use a clock signal of the first clock end as an output of the shift register of the current stage when turned on;
  • the supplemental unit is connected to the pull-up unit, and is used for guiding
  • the clock signal of the second clock terminal is used as the output of the shift register of this stage.
  • the shift register includes a GOA circuit unit 31 and a supplement unit 32; wherein the GOA circuit unit 31 Connected to an input terminal (INPUT), a reset terminal (RESET), a first clock terminal (CLK1), and a low voltage signal terminal (VSS), the input terminal (INPUT) receiving an output signal of the upper shift register, the reset terminal ( RESET) receiving an output signal of the lower stage shift register, the low voltage signal terminal (VSS) receiving the low voltage signal, and generally, the voltage level of the VSS is the same as the low level of the clock signal of CLK1; the replenishing unit 32 respectively
  • the second clock terminal (CLK2) is connected to the output terminal (OUTPUT) of the GOA circuit unit 31 to control the output of the GOA circuit unit 31.
  • the working process of the above shift register is specifically as follows: When the clock signal of CLK1 is high level, the clock signal of CLK2 is low level, and the output signal of OUTPUT is the pulse signal of CLK1, and the voltage value at this time is recorded as Vghl, when When the clock signal of CLK1 goes low, the clock signal of CLK2 of the replenishing unit 32 becomes a high level.
  • the replenishing unit 32 is turned on, and the output signal of the OUTPUT is the pulse signal of CLK2, and the voltage value is recorded as Vgh2, as a whole, the voltage value of the OUTPUT output jumps from Vghl to Vgh2, and the shift register of the existing gate drive circuit jumps directly from Vghl to 0, thereby realizing a greatly reduced pixel jump voltage.
  • the role of MLG has improved the picture quality.
  • the GOA circuit unit 31 includes a pull-up driving unit, a pull-up unit, a reset unit, and a pull-down unit.
  • a supplemental unit wherein the pull-up unit is configured to use a clock signal of the first clock end as an output signal of the shift register of the current stage when turned on; the supplemental unit is connected to the pull-up unit, and is used for The clock signal of the second clock terminal is used as the shift register of the current stage when turned on. Output signal of the device.
  • the pull-up driving unit is connected to an input node of the pull-up unit for controlling the turning-on and turning-off of the pull-up unit.
  • the pull-up driving unit includes a TFT switching device M1 and a TFT switching device M2;
  • the pull-up unit includes a TFT switching device three M3 and a boosting device C1;
  • the drain and the gate of the M1 are connected to the INPUT; the drain of the M2 is connected to the source of the M1, the gate of the M2 is connected to the RESET, and the source of the M2 is connected to the VSS;
  • the drain of the M3 is connected to the source of the M1, the source of the M3 is the output of the GOA circuit unit 31, and is also the output of the shift register of the stage; C1, the first end is connected to the source of the M1 and the gate of the M3, and the second end is connected to the source of the M3.
  • the reset unit specifically includes a TFT switching device M4; the drain of the M4 is connected to the source of the M3, the gate of the M4 is connected to the RESET, and the source of the M4 is connected. VSS.
  • the GOA circuit unit 31 further includes a pull-down unit PD connected in parallel with the C1, and the first end is connected to VSS, and the second end is connected to the drain of the M3.
  • the replenishing unit 32 specifically includes a TFT switching device five M5 and a TFT switching device six M6; wherein, the drain and the gate of the M5 are connected to the CLK2, and the drain of the M6 is connected to the source of the M5, M6
  • the gate is connected to the first end of C1 of the pull-up driving unit of the GOA circuit unit 31, and the source of M6 is connected to the output terminal of the pull-up unit, that is, the source of M3, and is the shift register of the same stage. Output.
  • Ml, M2, M3, M4, M5, M6 may specifically be a metal-oxide-semiconductor field-effect transistor (MOS) tube.
  • MOS metal-oxide-semiconductor field-effect transistor
  • the specific working process of the above gate driving circuit is as follows: When the input signal of INPUT is high level, M1 is turned on to charge the PU node; when the clock signal of CLK1 is high level and the clock signal of CLK2 is low level, M3 On, at this time, the OUTPUT output signal is the pulse signal of CLK1. At this time, the voltage value is recorded as Vghl, and the first bootstrapping action of C1 pulls the PU node for the first time. Next, when CLK1 When the clock signal goes low, the clock signal of CLK2 of the replenishing unit 32 becomes a high level for a short period of time. At this time, M5 and M6 are turned on, and the signal of the OUTPUT output is the pulse signal of CLK2.
  • the voltage value is recorded as Vgh2.
  • the second Bootstrapping function of CI pulls the PU node up again.
  • the voltage value of the OUTPUT output jumps from Vghl to Vgh2, which is directly changed from Vghl to the shift register in the existing gate drive circuit.
  • the pixel jump voltage is greatly reduced, thereby realizing the role of the MLG and improving the picture quality.
  • the PU node and the OUTPUT are discharged by the CLK1 control pull-down unit PD, ensuring that the shift register of the gate driving circuit does not generate noise during non-working hours.
  • the timing chart of each input and output signal is shown in FIG. 5.
  • the voltage value Vgh2 of CLK2 is smaller than the voltage value Vghl of CLK1.
  • the input signal of the INPUT in FIG. 5 is an example of the output signal of the upper shift register of the existing gate driving circuit.
  • the INPUT is The timing diagram of the input signal is the output signal of the upper shift register of the gate drive circuit of the embodiment of the present invention.
  • FIG. 6 shows the principle of the MLG function implemented by the gate driving circuit of the embodiment of the present invention.
  • the OUTPUT will also be a low level.
  • the output voltage value of OUTPUT is Vgh2
  • recharging occurs, which reduces the pixel jump voltage A Vp, thereby improving the picture quality
  • Vp is the voltage waveform of the pixel (Pixel)
  • Vcom is the voltage of the common electrode
  • Vd is the voltage waveform of the data line (Data)
  • Vgl is the gate low level.
  • Embodiments of the present invention also provide a liquid crystal display, wherein the liquid crystal display includes a gate driving circuit as described above.
  • the present invention also provides a gate driving method implemented by using the above gate driving circuit, and the implementation process of the method is shown in FIG. 7, including:
  • Step 701 When the signal outputted from the output end of the upper shift register is at a high level, the pull-up driving unit is turned on, and the shift register of the current stage starts to be charged;
  • Step 702 When the clock signal of the first clock end is a high level and the clock signal of the second clock end is a low level, the pull-up unit is turned on, and the clock signal of the first clock end is used as an output signal of the shift register of the current stage. ;
  • Step 703 the clock signal of the first clock end jumps to a low level, the clock signal of the second clock end jumps to a high level, the supplemental unit is turned on, and the clock signal of the second clock end is used as the current level.
  • the output signal of the shift register is used as the current level.
  • the high level of the clock signal of the second clock end is smaller than the clock of the first clock end.
  • the high level of the clock signal of the second clock end and the above description of the first clock end are only preferred embodiments of the present invention, and are not intended to limit the scope of the present invention.
  • Various modifications and improvements can be made by those skilled in the art without departing from the spirit and scope of the invention. These modifications and improvements are also considered to be within the scope of the invention.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Shift Register Type Memory (AREA)
  • Liquid Crystal (AREA)

Abstract

一种栅极驱动电路、栅极驱动方法及液晶显示器，所述栅极驱动电路包括多级移位寄存器，每一级移位寄存器包括上拉驱动单元、上拉单元、复位单元、下拉单元，和补充单元（32）。所述上拉单元，用于在导通时将第一时钟端（CLK1）的时钟信号作为本级移位寄存器的输出信号；所述补充单元（32），与所述上拉单元相连接，用于在导通时将第二时钟端（CLK2）的时钟信号作为本级移位寄存器的输出信号。通过栅极驱动电路中每级移位寄存器的补充单元（32）在TFT截止瞬间导通工作，对移位寄存器的输出进行控制，能够降低跳变电压，实现MLG功能，提升液晶显示器的画面品质。

Description

栅极驱动电路、 栅极驱动方法及液晶显示器 技术领域
本发明涉及栅极驱动技术， 尤其涉及一种栅极驱动电路、 栅极驱动方法 及液晶显示器。 背景技术
液晶显示器是目前常用的平板显示器， 其中薄膜场效应晶体管液晶显示 器 ( Thin Film Transistor Liquid Crystal Display, TFT-LCD )是目前液晶显示 器中的主流产品。 随着 TFT-LCD产品的竟争日益激烈， 各厂家纷纷通过釆用 新技术来降低产品的成本， 提高产品的市场竟争力。 其中， GOA ( Gate on Array )技术是指将 TFT-LCD的栅极驱动器（ Gate Driver )集成在阵列基板上， 形成对面板的扫描驱动。 相比传统覆晶薄膜（Chip On Flex/Film, COF )和直 接绑定在玻璃上 （Chip On Glass, COG ) 的工艺， 其不仅可以节省成本， 而 且面板可以做到两边对称美观设计， 省去了栅线集成电路（Gate IC ) 的绑定 ( Bonding ) 区域以及扇出 （ Fan-out )布线空间， 实现了窄边框的设计； 同时 由于可以省去栅线（Gate )方向绑定（Bonding ) 的工艺， 对产能和良品率提 升也比较有利。
但是， 相比于 COF和 COG技术， GOA技术也存在一定的问题， 现有的 栅极驱动电路包括多级移位寄存器， 图 1为现有的栅极驱动电路中每级移位 寄存器的结构图， 如图 1所示， 所述每级移位寄存器具体包括 TFT开关器件 — Ml , TFT开关器件二 M2、 TFT开关器件三 M3、 TFT开关器件四 M4, 下 拉单元 PD以及升压器件 C1 ; 其中， Ml 的漏极和栅极与输入端 （INPUT ) 连接， 并接收上级移位寄存器的输出信号； M2的漏极连接 Ml的源极， M2 的栅极与复位端 （RESET ) 连接， 并接收下级移位寄存器的输出信号， M2 的源极连接低压信号端 （VSS ), 并接收低压信号； M3 的漏极与时钟信号端 相连， M3的栅极与 Ml的源极相连， M3的源极作为本级移位寄存器的信号 输出端 （OUTPUT ); M4 的漏极与 M3 的源极相连， M4 的栅极与复位端 ( RESET )相连， M4的漏极与低压信号端 （VSS )相连； C1 的一端分别与 Ml的源极和 M3的栅极相连， 另一端连接 M3的源极； 下拉单元 PD不仅与 C1并联， 同时一端与低压信号端 （VSS )相连， 另一端与 M3的漏极相连。 上述栅极驱动电路的工作原理为： 当 INPUT 的输入信号为高电平时， Ml导通 , 对 PU节点进行充电； 当时钟信号为高时， M3导通， OUTPUT的 输出时钟信号的脉冲， 同时 C1的自举 ( Bootstrapping )作用将 PU节点进一 步拉高；之后 RESET的复位信号使 M2和 M4导通 ,对 PU和 OUTPUT放电； 接下来， 通过时钟信号控制下拉单元 PD的电路器件对 PU节点和 OUTPUT 进一步放电， 保证了该级移位寄存器所对应的行在非工作时间内不会有噪声 发生， 具体各信号的时序如图 2所示， 通常情况下， 应用如图 1所示的移位 寄存器时， 在 TFT截止瞬间， OUTPUT由高电平跳变为低电平， 像素跳变电 压较大， 影响液晶显示器的画面品质。
通常情况下， 会考虑将多级栅极（Multi-Level Gate, MLG )的功能附加 在栅极驱动电路上， 以减少跳变电压， 提高画面品质， MLG的产生原理为在 输出端引出一个反馈信号到 DC/DC IC, 随之产生一个电压并输出。
但是， 现有的栅极驱动电路通常釆用 α-Si的工艺， 由于考虑到低温条件 下 a-Si相比高温 TFT的迁移率大约会有一半左右的下降， 因此， 为了避免当 栅极驱动电路处于一个较低的温度状况时出现失效的情况， 通常釆用在栅极 驱动电路外部增加温度补偿电路的解决方案， 具体可以为在产生栅极高电平 Vgh的反馈电路上并联热敏器件， 使 Vgh随温度下降而上升； 的电压可能会上升到 30V以上， DC/DC IC无法承受如此高的电压， 此时， MLG的功能则会失效。 而 MLG功能一旦失效， 则在 TFT截止瞬间， 会存在 一个较大的跳变电压， 影响 TFT面板的画面品质。 发明内容
有鉴于此， 本发明的主要目的在于提供一种栅极驱动电路、 栅极驱动方 法及显示器， 能够实现具有 MLG功能的栅极驱动电路。
本发明实施例提供了一种栅极驱动电路， 包括多级移位寄存器， 其中每 一级移位寄存器包括上拉驱动单元、 上拉单元、 复位单元、 下拉单元， 所述 移位寄存器还包括： 补充单元； 其中，
所述上拉单元， 用于在导通时将第一时钟端的时钟信号作为本级移位寄 存器的输出信号；
所述补充单元， 与所述上拉单元相连接， 用于在导通时将第二时钟端的 时钟信号作为本级移位寄存器的输出信号。
在一个示例中， 所述上拉驱动单元连接上拉单元的输入节点， 用于控制 上拉单元的接通和断开。
在一个示例中， 所述上拉驱动单元包括 TFT开关器件一、 TFT开关器件 二； 其中，
TFT开关器件一的漏极和栅极与上级移位寄存器的输出端相连； 所述 TFT开关器件二的漏极与所述 TFT开关器件一的源极相连， 所述
TFT开关器件二的栅极与下级移位寄存器的输出端相连， 所述 TFT开关器件 二的源极低电平连接。
在一个示例中， 所述上拉单元包括 TFT开关器件三和升压器件； 其中， 所述 TFT开关器件三的漏极与第一时钟端相连，所述 TFT开关器件三的 栅极与 TFT开关器件一的源极相连，所述 TFT开关器件三的源极为本级移位 寄存器的输出端；
所述升压器件， 第一端分别与所述 TFT 开关器件一的源极和所述 TFT 开关器件三的栅极相连， 第二端与所述 TFT开关器件三的源极相连。
在一个示例中，所述复位单元包括 TFT开关器件四； 所述 TFT开关器件 四的漏极与 TFT开关器件三的源极相连，所述 TFT开关器件四的栅极与下级 移位寄存器的输出端相连， 所述 TFT开关器件四的源极与低电平连接。
在一个示例中，所述补充单元，包括 TFT开关器件五和 TFT开关器件六； 其中，
TFT开关器件五的漏极和栅极与第二时钟端连接， TFT开关器件六的漏 极与 TFT开关器件五的源极连接， TFT开关器件六的栅极与所述上拉驱动单 元的 TFT开关器件一的源极相连， TFT开关器件六的源极与所述上拉单元的 输出端相连接， 同时为本级移位寄存器的输出端。
在一个示例中， 所述 TFT开关器件五和 TFT开关器件六为金属 -氧化物- 半导体场效应晶体管。
在一个示例中， 所述第二时钟端的时钟信号在第一时钟端时钟信号变为 低电平的瞬间跳变为高电平。
本发明实施例提供了一种液晶显示器， 所述液晶显示器包括如上所述的 栅极驱动电路。
本发明实施例还提供了一种栅极驱动方法， 所述方法包括： 在上级移位寄存器的输出端输出的信号为高电平时，上拉驱动单元导通， 本级移位寄存器开始充电；
当第一时钟端的时钟信号为高电平且第二时钟端的时钟信号为低电平 时， 上拉单元导通， 将所述第一时钟端的时钟信号作为本级移位寄存器的输 出信号；
所述第一时钟端的时钟信号跳变为低电平， 所述第二时钟端的时钟信号 跳变为高电平， 补充单元导通， 将所述第二时钟端的时钟信号作为本级移位 寄存器的输出信号。
在一个示例中， 所述第二时钟端的时钟信号的高电平小于所述第一时钟 端的时钟信号的高电平。
本发明通过栅极驱动电路中每级移位寄存器的补充单元，在 TFT截止的 瞬间， 补充单元导通工作， 对移位寄存器的输出进行控制， 能够降低像素的 跳变电压， 实现 MLG功能， 提升液晶显示器的画面品质。 附图说明
图 1为现有栅极驱动电路中每级移动寄存器的结构示意图；
图 2为图 1所示现有栅极驱动电路的移位寄存器的输入输出信号的时序 图；
图 3为本发明实施例的栅极驱动电路中移位寄存器的功能结构示意图； 图 4为本发明实施例的栅极驱动电路的移位寄存器的具体实现结构图； 图 5为本发明实施例的栅极驱动电路的移位寄存器的输入输出信号的时 序图；
图 6为本发明实施例的栅极驱动电路实现的 MLG功能的原理示意图； 图 7为本发明实施例的栅极驱动方法的实现流程示意图。
附图标记说明： M1-TFT开关器件一； M2-TFT开关器件二； M3-TFT开 关器件三； M4-TFT开关器件四； M5-TFT开关器件五； M6-TFT开关器件六； PD-下拉单元； C1-升压器件； 31-GOA电路单元； 32-补充单元。 具体实施方式
为使本领域的技术人员更好地理解本发明的技术方案， 下面结合附图对 本发明提供的栅极驱动电路、 栅极驱动方法和液晶显示器进行详细描述。 显 然， 所描述的实施例仅仅是本发明一部分实施例， 而不是全部的实施例。 基 于本发明中的实施例， 本领域普通技术人员在没有作出创造性劳动前提下所 获得的所有其他实施例， 都属于本发明保护的范围。
本发明实施例的基本思想为： 所述栅极驱动电路包括多级移位寄存器， 其中每一级移位寄存器包括上拉驱动单元、 上拉单元、 复位单元、 下拉单元， 并且还包括： 补充单元； 其中， 所述上拉单元， 用于在导通时将第一时钟端 的时钟信号作为本级移位寄存器的输出； 所述补充单元， 与所述上拉单元相 连接， 用于在导通时将第二时钟端的时钟信号作为本级移位寄存器的输出。
为使本发明的目的、 技术方案和优点更加清楚明白， 以下列举实施例并 参照附图， 对本发明进一步详细说明。
图 3示出了本发明栅极驱动电路中每级移位寄存器的功能结构， 如图 3 所示， 所述移位寄存器包括 GOA电路单元 31 和补充单元 32; 其中， 所述 GOA电路单元 31与输入端（ INPUT )、复位端（ RESET )、第一时钟端（ CLK1 ) 和低压信号端 （VSS ) 连接， 所述输入端 （INPUT )接收上级移位寄存器的 输出信号， 所述复位端 （RESET )接收下级移位寄存器的输出信号， 所述低 压信号端（VSS )接收低压信号， 通常情况下， 所述 VSS的电压电平与 CLK1 的时钟信号的低电平相同； 补充单元 32分别与第二时钟端（CLK2 )和 GOA 电路单元 31的输出端（ OUTPUT )相连，控制所述 GOA电路单元 31的输出。
上述移位寄存器的工作过程具体为： 当 CLK1的时钟信号为高电平时， CLK2的时钟信号为低电平， OUTPUT的输出信号即为 CLK1的脉冲信号， 此时的电压值记为 Vghl , 当 CLK1 的时钟信号变为低电平时， 补充单元 32 的 CLK2的时钟信号变为高电平， 此时， 补充单元 32导通， OUTPUT的输出 信号即为 CLK2 的脉冲信号， 此时电压值记为 Vgh2, 整体来看， OUTPUT 输出的电压值从 Vghl跳变到 Vgh2, 相对于现有栅极驱动电路的移位寄存器 直接从 Vghl跳变到 0, 实现像素跳变电压的大大减小， 进而实现了 MLG的 作用， 提升了画面品质。
图 4 示出了本发明实施例的栅极驱动电路的移位寄存器的具体实现结 构， 如图 4所示， 上述 GOA电路单元 31包括上拉驱动单元和上拉单元、 复 位单元、 下拉单元、 补充单元， 其中， 所述上拉单元， 用于在导通时将第一 时钟端的时钟信号作为本级移位寄存器的输出信号； 所述补充单元， 与所述 上拉单元相连接， 用于在导通时将第二时钟端的时钟信号作为本级移位寄存 器的输出信号。
其中， 所述上拉驱动单元， 连接上拉单元的输入节点， 用于控制上拉单 元的接通和断开。
在一个示例中， 进一步地， 所述上拉驱动单元包括 TFT开关器件一 Ml、 TFT开关器件二 M2;
所述上拉单元包括 TFT开关器件三 M3和升压器件 C1 ;
所述 Ml的漏极和栅极与 INPUT相连； 所述 M2的漏极与所述 Ml的源 极相连， 所述 M2的栅极与 RESET相连， 所述 M2的源极连接 VSS; 所述 M3的漏极与 CLK1相连， 所述 M3的栅极与 Ml的源极相连， 所述 M3的源 极为所述 GOA电路单元 31的输出端， 同时也为本级移位寄存器的输出端； 所述 C1 , 第一端分别与所述 Ml的源极和 M3的栅极相连， 第二端与 M3的 源极相连。
在一个示例中， 进一步地， 所述复位单元具体包括 TFT开关器件四 M4; 所述 M4的漏极与 M3的源极相连， 所述 M4的栅极与 RESET相连， 所述 M4的源极连接 VSS。
在一个示例中，进一步地，所述 GOA电路单元 31还包括：下拉单元 PD, 与所述 C1并联， 且第一端连接 VSS, 第二端与所述 M3的漏极相连。
在一个示例中， 上述补充单元 32具体包括 TFT开关器件五 M5和 TFT 开关器件六 M6; 其中， 所述 M5的漏极和栅极与 CLK2相连， M6的漏极与 M5的源极相连， M6的栅极与 GOA电路单元 31的上拉驱动单元的 C1的第 一端相连， M6的源极与所述上拉单元的输出端， 即 M3的源极相连， 同时为 本级移位寄存器的输出端。
其中， 上述 Ml、 M2、 M3、 M4、 M5、 M6具体可以为金属-氧化物 -半导 体场效应晶体 ( Metal-Oxide-Semiconductor, MOS )管。
上述栅极驱动电路的具体工作过程为： 当 INPUT 的输入信号为高电平 时， Ml导通， 对 PU节点充电； 当 CLK1的时钟信号为高电平且 CLK2的时 钟信号为低电平时， M3导通， 此时 OUTPUT输出的信号即为 CLK1的脉冲 信号， 此时电压值记为 Vghl , 同时 C1 的第一次自举 ( Bootstrapping )作用 将 PU节点第一次拉高； 接下来当 CLK1 的时钟信号变为低电平时， 补充单 元 32的 CLK2的时钟信号变为高电平、 且持续一个较短的时间， 此时， M5、 M6导通， OUTPUT输出的信号即为 CLK2的脉冲信号，此时电压值记为 Vgh2 , 同时 CI 的第二次 Bootstrapping作用将 PU节点再一次拉高， 整体来看， OUTPUT输出的电压值从 Vghl跳变到 Vgh2,相对于现有栅极驱动电路中移 位寄存器直接从 Vghl跳变到 0, 实现了像素跳变电压的大大减小， 进而实现 了 MLG的作用， 提升了画面品质。 然后， 通过 CLK1控制下拉单元 PD对 PU节点和 OUTPUT进行放电， 保证该栅极驱动电路的移位寄存器在非工作 时间不会产生噪声。
具体地， 上述过程中， 各输入输出信号的时序图参考图 5 , 由图 5可知， CLK2的电压值 Vgh2要小于 CLK1的电压值 Vghl。应当理解，图 5中的 INPUT 的输入信号是以现有栅极驱动电路的上级移位寄存器的输出信号进行的举 例， 当具体利用本发明实施例提供的栅极驱动电路时， 此时 INPUT的输入信 号的时序图则为本发明实施例的栅极驱动电路的上级移位寄存器的输出信 号。
图 6示出了本发明实施例的栅极驱动电路实现的 MLG功能的原理， 如 图 6所示， 在 CLK1变为低电平的瞬间， 即 TFT截止的瞬间， OUTPUT也将 为低电平， 然而由于 CLK2的输入， 此时 OUTPUT的输出电压值为 Vgh2, 此时会发生再次充电（Recharging ), 达到减小像素跳变电压 A Vp的效果， 进 而可以提升画面质量； 其中， 图 6中 Vp为像素 （Pixel ) 的电压波形， Vcom 为公共电极的电压， Vd为数据线（Data ) 的电压波形， Vgl为栅极低电平。
本发明实施例还提供了一种液晶显示器， 其中， 所述液晶显示器包括有 如上所述的栅极驱动电路。
本发明还提供了一种利用上述栅极驱动电路实现的栅极驱动方法， 所述 方法的实现流程参见图 7, 包括：
步骤 701 , 在上级移位寄存器的输出端输出的信号为高电平时， 上拉驱 动单元导通， 本级移位寄存器开始充电；
步骤 702, 当第一时钟端的时钟信号为高电平且第二时钟端的时钟信号 为低电平时， 上拉单元导通， 将所述第一时钟端的时钟信号作为本级移位寄 存器的输出信号；
步骤 703 , 所述第一时钟端的时钟信号跳变为低电平， 所述第二时钟端 的时钟信号跳变为高电平， 补充单元导通， 将所述第二时钟端的时钟信号作 为本级移位寄存器的输出信号。
其中， 所述第二时钟端的时钟信号的高电平小于所述第一时钟端的时钟 信号的高电平。 其中， 所述第二时钟端的时钟信号的高电平和第一时钟端的 以上所述， 仅为本发明的较佳实施例而已， 并非用于限定本发明的保护 范围。 对于本领域内的普通技术人员而言， 在不脱离本发明的精神和实质的 情况下， 可以做出各种变型和改进， 这些变型和改进也视为本发明的保护范 围。

Claims

权 利 要 求 书
1、 一种栅极驱动电路， 包括多级移位寄存器， 其中每一级移位寄存器包 括上拉驱动单元、 上拉单元、 复位单元、 下拉单元， 所述移位寄存器还包括： 补充单元； 其中，
所述上拉单元， 用于在导通时将第一时钟端的时钟信号作为本级移位寄 存器的输出信号；
所述补充单元， 与所述上拉单元相连接， 用于在导通时将第二时钟端的 时钟信号作为本级移位寄存器的输出信号。
2、根据权利要求 1所述的栅极驱动电路， 其中， 所述上拉驱动单元连接 上拉单元的输入节点， 用于控制上拉单元的接通和断开。
3、根据权利要求 2所述的栅极驱动电路， 其中， 所述上拉驱动单元包括 TFT开关器件一、 TFT开关器件二； 其中，
TFT开关器件一的漏极和栅极与上级移位寄存器的输出端相连； 所述 TFT开关器件二的漏极与所述 TFT开关器件一的源极相连， 所述
TFT开关器件二的栅极与下级移位寄存器的输出端相连， 所述 TFT开关器件 二的源极与低电平连接。
4、根据权利要求 3所述的栅极驱动电路， 其中， 所述上拉单元包括 TFT 开关器件三和升压器件； 其中，
所述 TFT开关器件三的漏极与第一时钟端相连，所述 TFT开关器件三的 栅极与 TFT开关器件一的源极相连，所述 TFT开关器件三的源极为本级移位 寄存器的输出端；
所述升压器件， 第一端分别与所述 TFT 开关器件一的源极和所述 TFT 开关器件三的栅极相连， 第二端与所述 TFT开关器件三的源极相连。
5、根据权利要求 4所述的栅极驱动电路， 其中， 所述复位单元包括 TFT 开关器件四； 所述 TFT开关器件四的漏极与 TFT开关器件三的源极相连， 所 述 TFT开关器件四的栅极与下级移位寄存器的输出端相连，所述 TFT开关器 件四的源极与低电平连接。
6、 根据权利要求 5 所述的栅极驱动电路， 其中， 所述补充单元， 包括 TFT开关器件五和 TFT开关器件六； 其中，
TFT开关器件五的漏极和栅极与第二时钟端连接， TFT开关器件六的漏 极与 TFT开关器件五的源极连接， TFT开关器件六的栅极与所述上拉驱动单 元的 TFT开关器件一的源极相连， TFT开关器件六的源极与所述上拉单元的 输出端相连接， 同时为本级移位寄存器的输出端。
7、 根据权利要求 6所述的栅极驱动电路， 其中， 所述 TFT开关器件五 和 TFT开关器件六为金属 -氧化物-半导体场效应晶体管。
8、根据权利要求 6所述的栅极驱动电路， 其中， 所述第二时钟端的时钟 信号在第一时钟端时钟信号变为低电平的瞬间跳变为高电平。
9、一种液晶显示器，包括如权利要求 1至 8任一项所述的栅极驱动电路。
10、 一种栅极驱动方法， 包括：
在上级移位寄存器的输出端输出的信号为高电平时，上拉驱动单元导通， 本级移位寄存器开始充电；
当第一时钟端的时钟信号为高电平且第二时钟端的时钟信号为低电平 时， 上拉单元导通， 将所述第一时钟端的时钟信号作为本级移位寄存器的输 出信号；
所述第一时钟端的时钟信号跳变为低电平， 所述第二时钟端的时钟信号 跳变为高电平， 补充单元导通， 将所述第二时钟端的时钟信号作为本级移位 寄存器的输出信号。
11、根据权利要求 10所述的栅极驱动方法， 其中， 所述第二时钟端的时 钟信号的高电平小于所述第一时钟端的时钟信号的高电平。
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Cited By (1)

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Publication number Priority date Publication date Assignee Title
CN111210768A (zh) * 2018-11-22 2020-05-29 联咏科技股份有限公司 有机发光二极管驱动装置的感测电路及其驱动装置

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102779494B (zh) 2012-03-29 2015-08-05 北京京东方光电科技有限公司 一种栅极驱动电路、方法及液晶显示器
CN102915714B (zh) * 2012-10-11 2015-05-27 京东方科技集团股份有限公司 一种移位寄存器、液晶显示栅极驱动装置和液晶显示装置
KR102015396B1 (ko) * 2012-11-27 2019-08-28 엘지디스플레이 주식회사 쉬프트 레지스터와 이의 구동방법
CN103198783B (zh) * 2013-04-01 2015-04-29 京东方科技集团股份有限公司 移位寄存器单元、移位寄存器和显示装置
KR101580758B1 (ko) * 2013-04-02 2016-01-04 보에 테크놀로지 그룹 컴퍼니 리미티드 잔상 제거 장치, 디스플레이 디바이스, 잔상 제거 방법
CN103247275B (zh) * 2013-04-22 2015-03-11 合肥京东方光电科技有限公司 一种移位寄存器单元、栅极驱动电路及阵列基板
CN103258514B (zh) * 2013-05-06 2015-05-20 深圳市华星光电技术有限公司 Goa驱动电路及驱动方法
CN103680388B (zh) * 2013-12-26 2015-11-11 深圳市华星光电技术有限公司 用于平板显示的可修复的goa电路及显示装置
TWI539435B (zh) 2014-08-29 2016-06-21 友達光電股份有限公司 驅動電路
CN104240766A (zh) * 2014-09-26 2014-12-24 合肥京东方光电科技有限公司 移位寄存器单元及栅极驱动装置
CN104575435B (zh) * 2015-02-05 2017-12-15 京东方科技集团股份有限公司 显示基板栅极线驱动方法及驱动单元、显示装置
KR20160137866A (ko) 2015-05-22 2016-12-01 삼성디스플레이 주식회사 게이트 구동 장치, 그것을 포함하는 표시 장치 및 그 구동 방법
KR102339648B1 (ko) * 2015-06-24 2021-12-16 엘지디스플레이 주식회사 게이트 구동회로와 이를 이용한 표시장치
CN204946515U (zh) * 2015-09-08 2016-01-06 京东方科技集团股份有限公司 阵列基板行驱动goa单元的保护电路和阵列基板
CN105609137B (zh) * 2016-01-05 2019-06-07 京东方科技集团股份有限公司 移位寄存器、栅线集成驱动电路、阵列基板及显示装置
CN105549289B (zh) * 2016-03-09 2018-12-21 武汉华星光电技术有限公司 一种阵列基板、显示器和测试系统
US11813669B2 (en) 2016-12-13 2023-11-14 General Electric Company Method for making an integrated core-shell structure
US20180161866A1 (en) 2016-12-13 2018-06-14 General Electric Company Multi-piece integrated core-shell structure for making cast component
KR102643465B1 (ko) 2017-01-17 2024-03-05 삼성디스플레이 주식회사 표시 장치 및 그 구동 방법
CN106782336B (zh) * 2017-02-07 2019-01-22 京东方科技集团股份有限公司 栅极驱动单元及其驱动方法、栅极驱动电路和显示装置
CN106991984B (zh) * 2017-05-12 2018-05-18 惠科股份有限公司 移位元暂存电路及其应用的显示面板
CN109389926B (zh) * 2017-08-11 2022-02-25 京东方科技集团股份有限公司 移位寄存器、栅极驱动电路、阵列基板
KR102508522B1 (ko) 2017-11-09 2023-03-10 삼성전자주식회사 3차원 반도체 메모리 소자 및 이의 전기적 불량 판별 방법
CN108364622B (zh) * 2018-04-24 2020-11-06 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、驱动装置和显示装置
CN109935188B (zh) * 2019-03-08 2020-11-24 合肥京东方卓印科技有限公司 栅极驱动单元、方法、栅极驱动模组、电路及显示装置
CN110223655A (zh) * 2019-06-28 2019-09-10 昆山龙腾光电有限公司 栅极驱动电路及显示装置
CN113450732B (zh) * 2020-03-25 2023-06-02 Oppo广东移动通信有限公司 像素电路及其驱动方法、显示装置、电子设备
US11315473B2 (en) * 2020-06-16 2022-04-26 Tcl China Star Optoelectronics Technology Co., Ltd. Gate-on-array driving circuit
CN114974163B (zh) * 2022-06-28 2023-05-26 惠科股份有限公司 扫描驱动电路、阵列基板和显示面板
US20240218828A1 (en) 2022-11-01 2024-07-04 General Electric Company Gas Turbine Engine

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101174070A (zh) * 2006-10-31 2008-05-07 三星电子株式会社 栅极驱动电路、显示装置及改善显示装置的方法
US20100158188A1 (en) * 2008-12-23 2010-06-24 Hong-Woo Lee Method of Driving a Gate Line and Gate Drive Circuit for Performing the Method
CN102012591A (zh) * 2009-09-04 2011-04-13 北京京东方光电科技有限公司 移位寄存器单元及液晶显示器栅极驱动装置
CN102013244A (zh) * 2010-11-10 2011-04-13 友达光电股份有限公司 液晶显示器驱动电路及相关驱动方法
CN202102694U (zh) * 2011-05-25 2012-01-04 京东方科技集团股份有限公司 一种薄膜晶体管移位寄存器、液晶面板及显示设备
CN102779494A (zh) * 2012-03-29 2012-11-14 北京京东方光电科技有限公司 一种栅极驱动电路、方法及液晶显示器

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3292520B2 (ja) * 1991-10-11 2002-06-17 株式会社東芝 液晶表示装置
KR100495798B1 (ko) * 1997-09-09 2005-09-20 삼성전자주식회사 액정표시장치및킥백전압보상회로
KR100617611B1 (ko) * 1999-12-30 2006-09-01 비오이 하이디스 테크놀로지 주식회사 다중 레벨을 갖는 게이트 구동 신호 발생 회로
KR100619162B1 (ko) * 2000-12-30 2006-09-05 비오이 하이디스 테크놀로지 주식회사 액정표시모듈의 저소비전력 구동장치
KR20020091451A (ko) 2001-05-30 2002-12-06 주식회사 현대 디스플레이 테크놀로지 박막트랜지스터 액정표시장치의 멀티 레벨 게이트구동전압발생회로
GB2397710A (en) * 2003-01-25 2004-07-28 Sharp Kk A shift register for an LCD driver, comprising reset-dominant RS flip-flops
KR100551729B1 (ko) * 2003-03-19 2006-02-13 비오이 하이디스 테크놀로지 주식회사 액정표시장치의 게이트 라인 구동방법 및 그 구동회로
US7319452B2 (en) 2003-03-25 2008-01-15 Samsung Electronics Co., Ltd. Shift register and display device having the same
KR100697387B1 (ko) * 2004-09-03 2007-03-20 비오이 하이디스 테크놀로지 주식회사 액정표시장치용 쉬프트 레지스터
KR101300038B1 (ko) * 2006-08-08 2013-08-29 삼성디스플레이 주식회사 게이트 구동회로 및 이를 포함하는 표시 장치
JP4990034B2 (ja) * 2006-10-03 2012-08-01 三菱電機株式会社 シフトレジスタ回路およびそれを備える画像表示装置
CN101779227B (zh) 2007-10-24 2012-03-28 夏普株式会社 显示面板和显示装置
WO2010067643A1 (ja) * 2008-12-12 2010-06-17 シャープ株式会社 シフトレジスタ回路および表示装置ならびにシフトレジスタ回路の駆動方法
TWI406218B (zh) 2009-01-09 2013-08-21 Chunghwa Picture Tubes Ltd 高可靠度閘極驅動電路
CN101763900A (zh) * 2010-01-18 2010-06-30 友达光电股份有限公司 移位寄存器电路
JP5435481B2 (ja) * 2010-02-26 2014-03-05 株式会社ジャパンディスプレイ シフトレジスタ、走査線駆動回路、電気光学装置および電子機器

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101174070A (zh) * 2006-10-31 2008-05-07 三星电子株式会社 栅极驱动电路、显示装置及改善显示装置的方法
US20100158188A1 (en) * 2008-12-23 2010-06-24 Hong-Woo Lee Method of Driving a Gate Line and Gate Drive Circuit for Performing the Method
CN102012591A (zh) * 2009-09-04 2011-04-13 北京京东方光电科技有限公司 移位寄存器单元及液晶显示器栅极驱动装置
CN102013244A (zh) * 2010-11-10 2011-04-13 友达光电股份有限公司 液晶显示器驱动电路及相关驱动方法
CN202102694U (zh) * 2011-05-25 2012-01-04 京东方科技集团股份有限公司 一种薄膜晶体管移位寄存器、液晶面板及显示设备
CN102779494A (zh) * 2012-03-29 2012-11-14 北京京东方光电科技有限公司 一种栅极驱动电路、方法及液晶显示器

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
MA, ZHANJIE: "The Investigation to Improve Kickback Voltage of Pixel Electrode of a-Si TFT LCD", ADVANCED DISPLAY, no. 4, April 2009 (2009-04-01), pages 19 - 27, XP008169422 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111210768A (zh) * 2018-11-22 2020-05-29 联咏科技股份有限公司 有机发光二极管驱动装置的感测电路及其驱动装置
US11205382B2 (en) 2018-11-22 2021-12-21 Novatek Microelectronics Corp. Sensing circuit for OLED driver and OLED driver using the same

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