WO2016107096A1 - 移位寄存器单元及驱动方法、栅极驱动电路及显示器件 - Google Patents

移位寄存器单元及驱动方法、栅极驱动电路及显示器件 Download PDF

Info

Publication number
WO2016107096A1
WO2016107096A1 PCT/CN2015/081624 CN2015081624W WO2016107096A1 WO 2016107096 A1 WO2016107096 A1 WO 2016107096A1 CN 2015081624 W CN2015081624 W CN 2015081624W WO 2016107096 A1 WO2016107096 A1 WO 2016107096A1
Authority
WO
WIPO (PCT)
Prior art keywords
pull
node
voltage
signal
shift register
Prior art date
Application number
PCT/CN2015/081624
Other languages
English (en)
French (fr)
Inventor
李付强
李成
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 鄂尔多斯市源盛光电有限责任公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/896,793 priority Critical patent/US20160372063A1/en
Priority to EP15801310.2A priority patent/EP3242289A4/en
Publication of WO2016107096A1 publication Critical patent/WO2016107096A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3622—Control of matrices with row and column drivers using a passive matrix
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G09G2320/0214—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display with crosstalk due to leakage current of pixel switch in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a shift register unit and a driving method, a gate driving circuit, and a display device.
  • Liquid crystal display has the advantages of low radiation, small size and low energy consumption, and is widely used in electronic products such as notebook computers, flat-panel televisions or mobile phones.
  • the liquid crystal display comprises a matrix formed by pixels in two directions of horizontal and vertical.
  • the data driving circuit can sequentially latch the input display data and the clock signal into an analog signal and input it to the liquid crystal panel.
  • the data line, the gate drive circuit can convert the input clock signal into a voltage for controlling the on/off of the pixel through the shift register, and apply it to the gate line of the liquid crystal panel row by row.
  • the existing gate drive circuit often uses a GOA (Gate Driver on Array) design to integrate a TFT (Thin Film Transistor) gate switch circuit on the array substrate of the display panel to form a display.
  • GOA Gate Driver on Array
  • TFT Thin Film Transistor
  • the scan drive of the panel allows the gate drive integrated circuit portion to be omitted.
  • Such a gate switching circuit integrated on an array substrate using GOA technology is also referred to as a GOA circuit or a shift register circuit.
  • the existing GOA circuit is provided with a pull-up node PU and a pull-down node PD.
  • the pull-up node PU is configured to control the shift register unit to output a scan signal to the corresponding gate line
  • the pull-down node PD is configured to control the shift register unit to output a scan signal to the corresponding gate line in the non-output stage.
  • a GOA circuit includes a plurality of TFTs, which may cause a leakage current (I off ) or a threshold voltage shift (Vth shift) due to defects in the fabrication process of the array substrate.
  • Embodiments of the present disclosure provide a shift register unit and a driving method, a gate driving circuit, and a display device, which can prevent a shift register unit from erroneously outputting a scan signal to a corresponding gate line in a non-output stage.
  • a shift register unit including a pull-up module, a first input module, a second input module, a pull-down control module, and a pull-down module;
  • the pull-up module is connected to the pull-up node, the first clock signal end, and the signal output end of the current stage; and is configured to transmit, by the pull-up node, a signal input by the first clock signal end to the The signal output of this stage;
  • the first input module is connected to the first signal input end, the first voltage end, and the pull-up node; and is configured to pull the voltage of the pull-up node under the control of the input signal of the first signal input end a voltage to the first voltage terminal;
  • the second input module is connected to the second signal input end, the second voltage end, and the pull-up node; and is configured to pull the voltage of the pull-up node under the control of the input signal of the second signal input end a voltage to the second voltage terminal;
  • the pull-down control module is connected to the second clock signal end, the pull-up node, the pull-down node, and the third voltage end; and is configured to pull the voltage of the pull-down node to the first layer under the control of the pull-up node a voltage of the three voltage terminals, or inputting the second clock signal end input signal to the pull-down node under the control of the second clock signal end input signal;
  • the pull-down module is connected to the pull-down node, the pull-up node, the local signal output end, and the third voltage end; for controlling the pull-up node under the control of the pull-down node
  • the potential and the output voltage of the signal output of the current stage are pulled to the voltage of the third voltage terminal.
  • a gate driving circuit including at least two stages of any one of the shift register units as described above;
  • the second signal input of each of the shift register units of each stage is connected to the signal output of the present stage of the adjacent shift register unit of the next stage.
  • a display device comprising any one of the gate drive circuits as described above.
  • a driving method for driving any one of the shift register units as described above comprising:
  • the first input module pulls the potential of the pull-up node to the voltage of the first voltage terminal through the signal input by the first signal input terminal; under the control of the pull-up node, the pull-down control module pulls the potential of the pull-down node a voltage to the third voltage terminal;
  • the pull-up node turns on the pull-up module, so that a signal input by the first clock signal end is transmitted to the signal output end of the current stage; and under the control of the pull-up node, the pull-down control The module maintains a potential of the pull-down node at a voltage of the third voltage terminal;
  • the second input module pulls the voltage of the pull-up node to the voltage of the second voltage terminal through a signal input by the second signal input terminal, and the pull-up module is turned off under the control of the pull-up node;
  • the second clock signal end turns on the pull-down control module, and transmits a signal input by the second clock signal end to the pull-down node; under the control of the pull-down node potential, the pull-down module will The potential and the signal at the output of the signal of the stage are pulled to the voltage of the third voltage terminal.
  • Embodiments of the present disclosure provide a shift register unit and a driving method, a gate driving circuit, and a display device.
  • the shift register unit includes a pull-up module, a first input module, a second input module, a pull-down control module, and a pull-down module.
  • the potential of the pull-up node can be controlled by the first input module and the second input module.
  • the pull-up module can be turned on, so that the first clock signal end is input.
  • the signal is output as a scan signal from the signal output terminal of the stage to scan the gate line corresponding to the shift register unit.
  • the pull-down control module can be pulled up by the pull-down control module to turn on the pull-down module under the control of the pull-down node, thereby pulling down the potential of the pull-up node and/or the output signal of the signal output of the current stage, thereby ensuring that the shift is performed.
  • the non-output phase of the bit register unit there is no scan signal output.
  • the potential of the pull-down node when the potential of the pull-up node is pulled low in the non-output stage of the shift register unit, the potential of the pull-down node can be kept pulled up by the pull-down control module, thereby avoiding leakage current and threshold voltage drift of the TFT The pull-down node potential is pulled down, causing the shift register unit to erroneously output a scan signal to the corresponding gate line in the non-output stage, thereby improving the stability and reliability of the GOA circuit.
  • 1a is a schematic structural diagram of a shift register unit according to an embodiment of the present disclosure
  • FIG. 1b is a schematic structural diagram of another shift register unit according to an embodiment of the present disclosure.
  • FIG. 2 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of another shift register unit according to an embodiment of the present disclosure.
  • FIG. 4 is a timing diagram of signals during operation of a shift register unit according to an embodiment of the present disclosure
  • FIG. 5 is a schematic structural diagram of another shift register unit according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of still another shift register unit according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of still another shift register unit according to an embodiment of the present disclosure.
  • the embodiment of the present disclosure provides a shift register unit, as shown in FIG. 1a, which may include a pull-up module 50, a first input module 20, a second input module 30, a pull-down control module 10, and a pull-down module 40.
  • the pull-up module 50 is respectively connected to the pull-up node PU, the first clock signal terminal CK, and the current signal output terminal Output.
  • the signal input by the first clock signal terminal CK is transmitted to the signal output terminal Output of the current stage under the control of the pull-up node PU.
  • the first input module 20 is connected to the first signal input terminal Input, the first voltage terminal VDD and the pull-up node PU, respectively, for pulling up the voltage of the pull-up node PU under the control of the input signal of the first signal input terminal Input The voltage to the first voltage terminal VDD.
  • the second input module 30 is connected to the second signal input terminal Reset, the second voltage terminal VSS, and the pull-up node PU, respectively, for pulling down the voltage of the pull-up node PU under the control of the second signal input terminal Reset input signal.
  • the voltage of the second voltage terminal VSS is connected to the second signal input terminal Reset, the second voltage terminal VSS, and the pull-up node PU, respectively, for pulling down the voltage of the pull-up node PU under the control of the second signal input terminal Reset input signal.
  • the pull-down control module 10 is respectively connected to the second clock signal terminal CKB, the pull-up node PU, the pull-down node PD, and the third voltage terminal VGL; for pulling down the voltage of the pull-down node PD to the third voltage under the control of the pull-up node PU
  • the voltage of the terminal VGL or the second clock signal terminal CKB input signal is input to the pull-down node PD under the control of the second clock signal terminal CKB input signal.
  • the pull-down module 40 is respectively connected to the pull-down node PD, the pull-up node PU, the local signal output terminal Output and the third voltage terminal VGL; for controlling the potential of the pull-up node PU and/or the level under the control of the pull-down node PD The output voltage of the signal output terminal is pulled down to the voltage of the third voltage terminal VGL.
  • At least two stages of the shift register unit (SR0, as described above) SR1...SRn) can constitute a gate drive circuit.
  • the first signal input terminal Input of each of the shift register units of each stage is connected to the signal output terminal Output of the adjacent stage shift register unit of the adjacent stage. Further, the first signal input terminal Input of the first stage shift register unit SR0 receives the start signal STV.
  • the second signal input terminal Reset of each of the shift register units of each stage is connected to the signal output terminal Output of the adjacent stage shift register unit. Furthermore, the second signal input Reset of the last stage shift register unit SRn can input the reset signal RST.
  • the number of shift register units is equal to the number of gate lines of the display area. That is, the signal output terminal Output of each stage of each stage shift register unit is connected with a row of gate lines of the display area, thereby shifting the input scan signal through the multi-stage shift register to realize the progressive line of each row of gate lines. scanning.
  • the gate driving circuit provided by the present disclosure can also realize scanning in different directions according to different input positions of the start signal STV.
  • the first stage shift register unit When the second signal input terminal Reset of the last stage shift register unit SRn of the shift register units (SR0, SR1 ... SRn) of the gate drive circuit receives the start signal STV, the first stage shift register unit When the first signal input terminal Input of SR0 inputs the reset signal RST, the signal output terminals of the respective stages of the respective stages sequentially output the scan signals to the corresponding gate lines (Gn, Gn-1) in the reverse direction (from bottom to top). ...G0).
  • the module originally connected to the second voltage terminal VSS and the third voltage terminal VGL may be connected to the first voltage terminal VDD; for example, the original connection is second.
  • the second input module 20 of the voltage terminal VSS is connected to the first voltage terminal VDD, and connects the pull-down control module 10 and the pull-down module 40 originally connected to the third voltage terminal VGL to the first voltage terminal VDD.
  • the first voltage terminal VDD module such as the first input module 20, to the second voltage terminal VSS or the third voltage terminal VGL.
  • the first voltage terminal VDD is input to the high level
  • the second voltage terminal VSS is input to the low level as an example.
  • Embodiments of the present disclosure provide a shift register unit including a pull-up module, a first input module, a second input module, a pull-down control module, and a pull-down module.
  • the potential of the pull-up node can be controlled by the first input module and the second input module.
  • the pull-up module can be turned on, so that the first clock signal end is input.
  • the signal is output as a scan signal from the signal output terminal of the stage to scan the gate line corresponding to the shift register unit.
  • the pull-down node When the potential of the pull-up node is pulled low, the pull-down node can be pulled up by the pull-down control module to turn on the pull-down module under the control of the pull-down node, thereby outputting the potential of the pull-up node and/or the signal of the current stage.
  • the output signal of the terminal is pulled down to ensure that no scan signal is output during the non-output phase of the shift register unit.
  • the potential of the pull-down node when the potential of the pull-up node is pulled low in the non-output stage of the shift register unit, the potential of the pull-down node can be kept pulled up by the pull-down control module, thereby avoiding leakage current and threshold voltage drift of the TFT The pull-down node potential is pulled down, causing the shift register unit to erroneously output a scan signal to the corresponding gate line in the non-output stage, thereby improving the stability and reliability of the GOA circuit.
  • the pull-down control module 10 may include a first transistor M1 and a second transistor M2.
  • the gate of the first transistor M1 is connected to the pull-up node PU, the first pole is connected to the third voltage terminal VGL, and the second pole is connected to the pull-down node PD.
  • the potential of the pull-up node PU needs to be kept in a high state, so that it can be first under the control of the pull-up node PU.
  • the transistor M1 is turned on to pull down the potential of the pull-down node PD to the voltage of the third voltage terminal VGL through the first transistor M1, thereby preventing the potential of the pull-down node PD from rising, causing the potential of the pull-up node PU to be pulled low by the pull-down module 40.
  • the gate of the second transistor M2 and the first pole are connected to the second clock signal terminal CKB, and the second pole is connected to the pull-down node PD.
  • the second clock signal terminal CKB input signal can turn on the second transistor M2, and the second clock signal is passed through the second transistor M2.
  • the terminal CKB input signal is transmitted to the pull-down node PD, and the potential of the pull-down node PD is kept in a pulled-up state.
  • the pull-down node PD can turn on the pull-down module 40, so that the potential of the pull-up node PU and the output signal of the signal output terminal of the current stage are pulled low.
  • the potential of the pull-down node PD can be kept pulled up by the pull-down control module 10, thereby avoiding leakage current due to the TFT.
  • the threshold voltage drift pulls down the potential of the pull-down node, which causes the shift register unit to erroneously output the scan signal to the corresponding gate line in the non-output stage, thereby improving the stability and reliability of the GOA circuit.
  • the first input module 20 can include:
  • the third transistor M3 has a gate connected to the first signal input terminal Input, a first pole connected to the first voltage terminal VDD, and a second pole connected to the pull-up node PU.
  • the potential of the pull-up node PU can be pulled up to the voltage of the first voltage terminal VDD through the third transistor M3.
  • the second input module 30 can include:
  • the fourth transistor M4 has a gate connected to the second signal input terminal Reset, and the first pole is connected
  • the pull-up node PU has a second pole connected to the second voltage terminal VSS.
  • the potential of the pull-up node PU can be pulled down to the voltage of the second voltage terminal VSS through the fourth transistor M4.
  • the pull-down module 40 may include a fifth transistor M5 and a sixth transistor M6.
  • the fifth transistor M5 has a gate connected to the pull-down node PD, a first pole connected to the third voltage terminal VGL, and a second pole connected to the pull-up node PU.
  • the fifth transistor M5 can be turned on to pull down the potential of the pull-up node PU to the voltage of the third voltage terminal VGL through the fifth transistor M5.
  • the sixth transistor M6 has a gate connected to the pull-down node PD, a first pole connected to the signal output terminal of the current stage, and a second pole connected to the third voltage terminal VGL.
  • the sixth transistor M6 can be turned on to pull down the signal outputted by the signal output terminal of the first stage to the voltage of the third voltage terminal VGL through the sixth transistor M6.
  • the pull-up module 50 can include:
  • the seventh transistor M7 has a gate connected to the pull-up node PU, a first pole connected to the first clock signal terminal CK, and a second pole connected to the signal output terminal Output of the current stage.
  • the seventh transistor M7 can be turned on, so that the signal input by the first clock signal terminal CK is output to the signal output terminal Output of the present stage through the seventh transistor M7.
  • the gate line corresponding to the shift register unit is scanned as a scan signal.
  • the first pole of the transistor may be a drain and the second pole may be a source. Since the source and drain of the transistor used here are symmetrical, the source and drain are interchangeable. In the embodiment of the present invention, in order to distinguish the two poles of the transistor except the gate, one of the poles is referred to as a source and the other pole is referred to as a drain. If the source is selected as the signal input, the drain acts as the signal output and vice versa.
  • the first signal input terminal Input inputs a high level, turns on the third transistor M3, and pulls the potential of the pull-up node PU to a high level input by the first voltage terminal VDD through the third transistor M3. At the same time, the high level of the first voltage terminal VDD input charges the parasitic capacitance of the seventh transistor M7.
  • the first transistor M1 can be turned on, so that the potential of the pull-down node PD can be pulled down to the low level input by the third voltage terminal VGL through the first transistor M1. Since the potential of the pull-down node PD is at a low level, the fifth transistor M5 and the sixth transistor M6 are in an off state.
  • the first transistor M1 since the PU is at a high level, the first transistor M1 is turned on, although the CKB is input at a high level and the second transistor M2 is turned on, but the first transistor M1 and the second transistor are turned on.
  • the size of the transistor M2 is designed such that the potential of the pull-down node PD is still low even when both are turned on.
  • the first signal input terminal Input and the second signal input terminal Reset input a low level, and the third transistor and the fourth transistor are in an off state.
  • the parasitic capacitance of the seventh transistor M7 itself is further pulled up by the bootstrap action of the pull-up node PU.
  • the seventh transistor M7 is turned on, and the high level input from the first clock signal terminal CK is transmitted to the signal output terminal Output of the current stage to scan the gate line corresponding to the shift register unit as a scan signal.
  • the potential of the pull-up node PU since the potential of the pull-up node PU is at a high level, the potential of the pull-down node PD can be held at the low level input by the third voltage terminal VGL through the first transistor M1. In this case, the fifth transistor M5 and the sixth transistor M6 are in an off state.
  • the first signal input terminal Input inputs a low level, and the third transistor M3 is in an off state.
  • the second signal input terminal Reset inputs a high level, and the fourth transistor M4 is in an on state, so that the potential of the pull-up node PU can be pulled down to the low level input by the second voltage terminal VSS through the fourth transistor M4.
  • the seventh transistor M7 is in an off state.
  • the second clock signal input terminal CKB inputs a high level, turns on the second transistor M2, and transmits the second clock signal input terminal CKB to the high level through the second transistor M2 to the pull-down node PD.
  • the fifth transistor M5 and the sixth transistor M6 can be turned on under the potential control of the pull-down node PD.
  • the potential of the pull-up node PU can be pulled down to the low level input by the third voltage terminal VGL through the fifth transistor M5, so that the potential of the pull-up node PU can be prevented from being erroneously pulled high, so that the seventh transistor M7 is erroneously turned on.
  • the sixth transistor M6 can pull down the signal outputted by the output terminal of the current stage to the low level input by the third voltage terminal VGL, thereby avoiding the output stage of the signal output terminal of the shift register unit in the non-output stage of the shift register unit.
  • the gate line incorrectly outputs a scan signal.
  • the T1 to T3 stages may be referred to as the operating time of the shift register unit.
  • the signal output terminal of this stage only outputs a high level in the second stage T2 stage, so the second stage T2 can be the data output stage of the shift register unit, and the first stage T1 and the second stage T2 are the shift register unit. In the non-output phase, the output of the signal output terminal of this stage is low level.
  • the above transistors may be all P-type transistors.
  • the transistors in the shift register unit and the transistors connected to the gate lines in the pixel unit are P-type transistors. The timing of the drive signal and the input signal of the circuit need to be adjusted accordingly.
  • the module or transistor connecting the second voltage terminal VSS and the third voltage terminal VGL in FIG. 3 may be connected to the first voltage terminal VDD; the first voltage terminal VDD module or the transistor and the second voltage terminal VSS or The third voltage terminal VGL is connected.
  • the direction of the drive signal needs to be reversed in FIG. The specific working process is the same as above, and will not be described here.
  • the pull-down control module 10 may further include a capacitor C as shown in FIG.
  • the one end of the capacitor C is connected to the pull-down node PD, and the other end is connected to the third voltage terminal VGL.
  • the state of the pull-down node PD can be maintained at a high level by the energy storage function of the capacitor C, thereby avoiding Due to leakage current of the transistor or the like, noise is generated such that the potential of the pull-down node PD is lowered, thereby lowering the potential of the pull-down node PD.
  • the pull-down control module 10 may further include an eighth transistor M8 as shown in FIG. 6.
  • the gate of the eighth transistor M8 is connected to the signal output terminal of the current stage, the first pole is connected to the pull-down node PD, and the second pole is connected to the third voltage terminal VGL.
  • the seventh transistor M7 is turned on, and the high level input to the first clock signal terminal can be output to the output terminal of the current stage signal, and can also be transmitted to the gate of the eighth transistor M8. Therefore, the eighth transistor M8 is turned on, so that since the first electrode of the eighth transistor M8 and the second electrode of the first transistor M1 are both connected to the pull-down node PD, the eighth transistor M8 and the first transistor M1 can The potential of the pull-down node PD is pulled down to the low level input by the third voltage terminal VGL, thereby ensuring that the potential of the pull-down node PD remains low in the second phase T2 (ie, the data output phase of the shift register unit).
  • the pull-down control module 10 can include the capacitor C and the eighth transistor M8 at the same time, and the beneficial effects are the same as those in the second embodiment and the third embodiment, and details are not described herein again.
  • Embodiments of the present disclosure provide a display device including any of the gate driving circuits as described above, which has the same advantageous effects as the gate driving circuit provided by the foregoing embodiments of the present disclosure, since the gate driving circuit is implemented in the foregoing The details have been explained in this example. I won't go into details here.
  • the display device may specifically be any liquid crystal display product or component having a display function, such as a liquid crystal display, a liquid crystal television, a digital photo frame, a mobile phone, a tablet computer, or the like.
  • An embodiment of the present disclosure provides a driving method for driving any one of the above shift register units, and the method may include:
  • the first input module 20 pulls up the potential of the pull-up node PU to the voltage of the first voltage terminal VDD through the signal input by the first signal input terminal Input; under the control of the pull-up node PU, the pull-down control module 10 pulls down the node PD The potential is pulled down to the voltage of the third voltage terminal VGL, thereby preventing the pull-down node PD from turning on the pull-down module 40.
  • the pull-up node PU turns on the pull-up module 50, so that the signal input by the first clock signal terminal CK is transmitted to the signal output terminal Output of the current stage, and is output as a scan signal to the corresponding gate line of the shift register unit.
  • the gate line is scanned; under the control of the pull-up node PU, the pull-down control module 10 can maintain the potential of the pull-down node PD at the voltage of the third voltage terminal VGL, thereby preventing the pull-down node PD from turning on the pull-down module 40.
  • the second input module 30 pulls down the potential of the pull-up node PU to the voltage of the second voltage terminal VSS through a signal input by the second signal input terminal Reset. Since the second voltage terminal VSS is input to the low level, the potential of the pull-up node PU is low. Under the control of the pull-up node PU, the pull-up module 50 is turned off, so that the signal output terminal of the current stage has no scan signal output in the non-output stage.
  • the second clock signal terminal CKB turns on the pull-down control module 10, and transmits a signal input by the second clock signal terminal CKB to the pull-down node PD. Since the second clock signal terminal CKB is input to a high level, the potential of the pull-down node PD is at a high level. Under the control of the PD potential of the pull-down node, the pull-down module 40 pulls down the potential of the pull-up node PU and the signal of the output of the signal of the current stage to the voltage of the third voltage terminal VGL, respectively, to ensure that the output of the signal of the stage is not output. There is no scan signal output at the stage.
  • the foregoing may be performed by a program instruction related hardware, where the foregoing program may be stored in a computer readable storage medium, and when executed, the program includes the steps of the foregoing method embodiment; and the foregoing storage medium includes: a ROM, A variety of media that can store program code, such as RAM, disk, or optical disk.

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Shift Register Type Memory (AREA)

Abstract

一种移位寄存器单元及驱动方法、栅极驱动电路及显示器件。所述移位寄存器单元包括上拉模块(50)、第一输入模块(20)、第二输入模块(30)、下拉控制模块(10)以及下拉模块(40)，这种移位寄存器单元能够避免在非输出阶段向对应的栅线误输出扫描信号，提高了电路的稳定性和可靠性。

Description

移位寄存器单元及驱动方法、栅极驱动电路及显示器件 技术领域
本公开涉及显示技术领域，尤其涉及一种移位寄存器单元及驱动方法、栅极驱动电路及显示器件。
背景技术
液晶显示器(Liquid Crystal Display，简称LCD)具有低辐射、体积小及低耗能等优点，被广泛地应用在笔记本电脑、平面电视或移动电话等电子产品中。液晶显示器包括位于水平和垂直两个方向的像素形成的矩阵，当液晶显示器进行显示时，数据驱动电路可以将输入的显示数据及时钟信号定时顺序锁存，转换成模拟信号后输入到液晶面板的数据线，栅级驱动电路则可以将输入的时钟信号经过移位寄存器转换成控制像素开启/关断的电压，并逐行施加到液晶面板的栅级线上。
为了进一步降低液晶显示器产品的生产成本，现有的栅极驱动电路常采用GOA(Gate Driver on Array)设计将TFT(Thin Film Transistor)栅极开关电路集成在显示面板的阵列基板上以形成对显示面板的扫描驱动，从而可以省掉栅极驱动集成电路部分。这种利用GOA技术集成在阵列基板上的栅极开关电路也称为GOA电路或移位寄存器电路。
现有的GOA电路中设置有上拉节点PU以及下拉节点PD。其中，上拉节点PU用于控制移位寄存器单元向对应的栅线输出扫描信号，而下拉节点PD用于控制移位寄存器单元在非输出阶段，不会向对应的栅线输出扫描信号。然而这种GOA电路中包括多个TFT，由于阵列基板制作工艺中的缺陷会导致阵列基板上的薄膜晶体管出现漏电流(Ioff)或者阈值电压漂移(Vth shift)的不良现象产生。这样一来，在电位拉升的过程中，会因为TFT的漏电流及阈值电压漂移而对下拉节点PD的电位进行下拉，导致移位寄存器单元在非输出阶段向对应的栅线误输出扫描信号，从而降低了GOA电路的稳定性和可靠性。
发明内容
本公开的实施例提供一种移位寄存器单元及驱动方法、栅极驱动电路及显示器件，能够避免移位寄存器单元在非输出阶段向对应的栅线误输出扫描信号。
相应地，本公开的实施例采用如下技术方案：
根据本公开实施例的一方面，提供一种移位寄存器单元，包括上拉模块、第一输入模块、第二输入模块、下拉控制模块以及下拉模块；
所述上拉模块，连接上拉节点、第一时钟信号端以及本级信号输出端；用于在所述上拉节点的控制下，将所述第一时钟信号端输入的信号传输至所述本级信号输出端；
所述第一输入模块，连接第一信号输入端、第一电压端以及所述上拉节点；用于在所述第一信号输入端输入信号的控制下，将所述上拉节点的电压拉至所述第一电压端的电压；
所述第二输入模块，连接第二信号输入端、第二电压端以及所述上拉节点；用于在所述第二信号输入端输入信号的控制下，将所述上拉节点的电压拉至所述第二电压端的电压；
所述下拉控制模块，连接第二时钟信号端、所述上拉节点、下拉节点、第三电压端；用于在所述上拉节点的控制下将所述下拉节点的电压拉至所述第三电压端的电压，或在所述第二时钟信号端输入信号的控制下将所述第二时钟信号端输入信号输入至所述下拉节点；
所述下拉模块，连接所述下拉节点、所述上拉节点、所述本级信号输出端以及所述第三电压端；用于在所述下拉节点的控制下，将所述上拉节点的电位和所述本级信号输出端的输出电压拉至所述第三电压端的电压。
根据本公开实施例的另一方面，提供一种栅极驱动电路，包括至少两级如上所述的任意一种移位寄存器单元；
除第一级移位寄存器单元外，其余每级移位寄存器单元的第一信号输入端与其相邻的上一级移位寄存器单元的本级信号输出端相连 接；
除最后一级移位寄存器单元外，其余每级移位寄存器单元的第二信号输入端与其相邻的下一级移位寄存器单元的本级信号输出端相连接。
根据本公开实施例的另一方面，提供一种显示器件，包括如上所述的任意一种栅极驱动电路。
根据本公开实施例的又一方面，提供一种用于驱动如上所述的任意一种移位寄存器单元的驱动方法，包括：
第一阶段，第一输入模块通过第一信号输入端输入的信号将上拉节点的电位拉至第一电压端的电压；在所述上拉节点的控制下，下拉控制模块将下拉节点的电位拉至所述第三电压端的电压；
第二阶段，所述上拉节点将所述上拉模块开启，使得第一时钟信号端输入的信号传输至所述本级信号输出端；在所述上拉节点的控制下，所述下拉控制模块将所述下拉节点的电位保持在所述第三电压端的电压；
第三阶段，第二输入模块通过第二信号输入端输入的信号将所述上拉节点的拉至第二电压端的电压，在所述上拉节点的控制下，所述上拉模块关闭；
第二时钟信号端开启所述下拉控制模块，并将所述第二时钟信号端输入的信号传输至所述下拉节点；在所述下拉节点电位的控制下，下拉模块将所述上拉节点的电位和所述本级信号输出端的信号拉至所述第三电压端的电压。
本公开实施例提供一种移位寄存器单元及驱动方法、栅极驱动电路及显示器件。其中，所述移位寄存器单元包括上拉模块、第一输入模块、第二输入模块、下拉控制模块以及下拉模块。这样一来，可以通过第一输入模块和第二输入模块对上拉节点的电位进行控制，当上拉节点的电位被拉高时，可以将上拉模块打开，从而使得第一时钟信号端输入的信号作为扫描信号从本级信号输出端输出，以对于所述移位寄存器单元相对应的栅线进行扫描。当上拉节点的电位被拉低时， 可以通过下拉控制模块将下拉节点的电位拉高，以在下拉节点的控制下将下拉模块开启，从而对上拉节点的电位和/或本级信号输出端的输出信号进行下拉，从而可以确保在移位寄存器单元的非输出阶段，无扫描信号输出。其中，在移位寄存器单元的非输出阶段中上拉节点的电位被拉低时，下拉节点的电位可以通过下拉控制模块保持拉高状态，因此，能够避免由于TFT的漏电流及阈值电压漂移对下拉节点电位进行下拉，而导致移位寄存器单元在非输出阶段向对应的栅线误输出扫描信号，从而提高了GOA电路的稳定性和可靠性。
附图说明
为了更清楚地说明本公开实施例或已知的技术方案，下面将对实施例或已知的技术方案描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1a为本公开实施例提供的一种移位寄存器单元的结构示意图；
图1b为本公开实施例提供的另一种移位寄存器单元的结构示意图；
图2为本公开实施例提供的一种栅极驱动电路的结构示意图；
图3为本公开实施例提供的另一种移位寄存器单元的结构示意图；
图4为本公开实施例提供的一种移位寄存器单元工作过程中的信号时序图；
图5为本公开实施例提供的另一种移位寄存器单元的结构示意图；
图6为本公开实施例提供的又一种移位寄存器单元的结构示意图；
图7为本公开实施例提供的又一种移位寄存器单元的结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开实施例提供一种移位寄存器单元，如图1a所示，可以包括上拉模块50、第一输入模块20、第二输入模块30、下拉控制模块10以及下拉模块40。
其中，上拉模块50，分别连接上拉节点PU、第一时钟信号端CK以及本级信号输出端Output。用于在上拉节点PU的控制下，将第一时钟信号端CK输入的信号传输至本级信号输出端Output。
第一输入模块20，分别连接第一信号输入端Input、第一电压端VDD以及上拉节点PU，用于在第一信号输入端Input输入信号的控制下，将上拉节点PU的电压上拉至第一电压端VDD的电压。
第二输入模块30，分别连接第二信号输入端Reset、第二电压端VSS以及上拉节点PU，用于在第二信号输入端Reset输入信号的控制下，将上拉节点PU的电压下拉至第二电压端VSS的电压。
下拉控制模块10，分别连接第二时钟信号端CKB、上拉节点PU、下拉节点PD、第三电压端VGL；用于在上拉节点PU的控制下将下拉节点PD的电压下拉至第三电压端VGL的电压，或在第二时钟信号端CKB输入信号的控制下将第二时钟信号端CKB输入信号输入至下拉节点PD。
下拉模块40，分别连接下拉节点PD、上拉节点PU、本级信号输出端Output以及第三电压端VGL；用于在下拉节点PD的控制下，将上拉节点PU的电位和/或本级信号输出端Output的输出电压下拉至第三电压端VGL的电压。
需要说明的是，第一，至少两级如上所述的移位寄存器单元(SR0、 SR1…SRn)能够构成一种栅极驱动电路。
其中，除第一级移位寄存器单元SR0外，其余每级移位寄存器单元的第一信号输入端Input与其相邻的上一级移位寄存器单元的本级信号输出端Output相连接。此外，第一级移位寄存器单元SR0的第一信号输入端Input接收起始信号STV。
除最后一级移位寄存器单元SRn外，其余每级移位寄存器单元的第二信号输入端Reset与其相邻的下一级移位寄存器单元的本级信号输出端Output相连接。此外，最后一级移位寄存器单元SRn的第二信号输入端Reset可以输入复位信号RST。
第二，移位寄存器单元的数量与显示区域的栅线的数量相等。即每一级移位寄存器单元的本级信号输出端Output与显示区域的一行栅线相连接，从而通过多级移位寄存器对输入的扫描信号进行移位，来实现对各行栅线的逐行扫描。本公开提供的栅极驱动电路，还可以根据起始信号STV输入位置的不同实现不同方向的扫描。
具体的，如图2所示，当上述栅极驱动电路的各级移位寄存器单元(SR0、SR1…SRn)中的第一极移位寄存器单元SR0的第一信号输入端Input接收起始信号STV，最后一级移位寄存器单元SRn的第二信号输入端Reset输入复位信号RST时，各级移位寄存器(SR0、SR1…SRn)的本级信号输出端Output按正向(从上至下)顺序地将扫描信号输出到与其相对应的栅线(G0、G1、G2…Gn)上。
当上述栅极驱动电路的各级移位寄存器单元(SR0、SR1…SRn)中的最后一级移位寄存器单元SRn的第二信号输入端Reset接收起始信号STV，第一级移位寄存器单元SR0的第一信号输入端Input输入复位信号RST时，各级的本级信号输出端Output按反向(从下至上)顺序地将扫描信号输出到与其相对应的栅线(Gn、Gn-1…G0)上。
其中，为了实现上述反向扫描，还需要将图1a中第一电压端VDD与第二电压端VSS(或第三电压端VGL)的连接位置进行互换。
具体的，如图1b所示，可以将原本连接第二电压端VSS和第三电压端VGL的模块与第一电压端VDD相连接；例如将原本连接第二 电压端VSS的第二输入模块20与第一电压端VDD相连接，将原本连接第三电压端VGL的下拉控制模块10和下拉模块40与第一电压端VDD相连接。此外，还需要将原本连接第一电压端VDD模块，例如第一输入模块20，与第二电压端VSS或第三电压端VGL相连接。
上述栅极驱动电路具有前述实施例中的移位寄存器单元相同的有益效果，由于已经对移位寄存器单元的结构和有益效果进行了描述，在此不再赘述。
第三、本公开实施例中是以第一电压端VDD输入高电平，第二电压端VSS以及第三电压端VGL输入低电平为例进行的说明。
本公开实施例提供一种移位寄存器单元，包括上拉模块、第一输入模块、第二输入模块、下拉控制模块以及下拉模块。这样一来，可以通过第一输入模块和第二输入模块对上拉节点的电位进行控制，当上拉节点的电位被拉高时，可以将上拉模块开启，从而使得第一时钟信号端输入的信号作为扫描信号从本级信号输出端输出，以对于所述移位寄存器单元相对应的栅线进行扫描。当上拉节点的电位被拉低时，可以通过下拉控制模块将下拉节点的电位拉高，以在下拉节点的控制下将下拉模块开启，从而对上拉节点的电位和/或本级信号输出端的输出信号进行下拉，从而可以确保在移位寄存器单元的非输出阶段，无扫描信号输出。其中，在移位寄存器单元的非输出阶段中上拉节点的电位被拉低时，下拉节点的电位可以通过下拉控制模块保持拉高状态，因此，能够避免由于TFT的漏电流及阈值电压漂移对下拉节点电位进行下拉，而导致移位寄存器单元在非输出阶段向对应的栅线误输出扫描信号，从而提高了GOA电路的稳定性和可靠性。
以下通过多个实施例，对其它附图所示的移位寄存器单元的具体结构进行详细的举例说明。其它连接方式的移位寄存器单元同理可得，在此不再一一赘述。
实施例一
如图3所示，
下拉控制模块10可以包括：第一晶体管M1和第二晶体管M2。
其中，第一晶体管M1的栅极连接上拉节点PU，第一极连接第三电压端VGL，第二极与下拉节点PD相连接。
具体的，在移位寄存器单元的输出阶段，为了保证本级信号输出端能够输出扫描信号，上拉节点PU的电位需要保持拉高状态，因此可以在上拉节点PU的控制下，将第一晶体管M1导通，以通过第一晶体管M1将下拉节点PD的电位下拉至第三电压端VGL的电压，从而避免下拉节点PD的电位上升，造成上拉节点PU的电位被下拉模块40拉低。
第二晶体管M2的栅极和第一极连接第二时钟信号端CKB，第二极与下拉节点PD相连接。
具体的，在移位寄存器单元的非输出阶段中上拉节点的电位被拉低时，第二时钟信号端CKB输入信号可以将第二晶体管M2导通，通过第二晶体管M2将第二时钟信号端CKB输入信号传输至下拉节点PD，保持下拉节点PD的电位处于拉高状态。这样一来，下拉节点PD可以将下拉模块40开启，从而使得上拉节点PU的电位以及本级信号输出端Output的输出信号被拉低。
综上所述，在移位寄存器单元的非输出阶段中上拉节点的电位被拉低时，下拉节点PD的电位可以通过下拉控制模块10保持拉高状态，因此，能够避免由于TFT的漏电流及阈值电压漂移对下拉节点电位进行下拉，而导致移位寄存器单元在非输出阶段向对应的栅线误输出扫描信号，从而提高了GOA电路的稳定性和可靠性。
第一输入模块20可以包括：
第三晶体管M3，其栅极连接第一信号输入端Input，第一极连接第一电压端VDD，第二极与上拉节点PU相连接。
具体的，当第一信号输入端Input输入的信号将第三晶体管M3导通后，可以通过第三晶体管M3将上拉节点PU的电位上拉至第一电压端VDD的电压。
第二输入模块30可以包括：
第四晶体管M4，其栅极连接第二信号输入端Reset，第一极连接 上拉节点PU，第二极与第二电压端VSS相连接。
具体的，当第二信号输入端Reset输入的信号将第四晶体管M4导通后，可以通过第四晶体管M4将上拉节点PU的电位下拉至所述第二电压端VSS的电压。
下拉模块40可以包括：第五晶体管M5和第六晶体管M6。
其中，第五晶体管M5，其栅极连接下拉节点PD，第一极连接所述第三电压端VGL，第二极与上拉节点PU相连接。
具体的，在下拉节点PD的控制下，可以将第五晶体管M5导通，以通过所述第五晶体管M5将上拉节点PU的电位下拉至所述第三电压端VGL的电压。
第六晶体管M6，其栅极连接下拉节点PD，第一极连接本级信号输出端Output，第二极与第三电压端VGL相连接。
具体的，在下拉节点PD的控制下，可以将第六晶体管M6导通，以通过所述第六晶体管M6将本级信号输出端Output输出的信号下拉至第三电压端VGL的电压。
上拉模块50可以包括：
第七晶体管M7，其栅极连接上拉节点PU，第一极连接第一时钟信号端CK，第二极与本级信号输出端Output相连接。
具体的，在上拉节点PU的控制下，可以将第七晶体管M7导通，以通过所述第七晶体管M7将第一时钟信号端CK输入的信号输出至所述本级信号输出端Output，以作为扫描信号对于所述移位寄存器单元相对应的栅线进行扫描。
需要说明的是，本公开实施例中的所有晶体管均以N型晶体管为例进行的说明。其中所述晶体管的第一极可以为漏极、第二极可以为源极。由于这里采用的晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本发明实施例中，为区分晶体管除栅极之外的两极，将其中一极称为源极，另一极称为漏极。若选取源极作为信号输入端、则漏极作为信号输出端，反之亦然。
以下结合移位寄存器单元的时序图，如图4所示，对如图3所示 的移位寄存器单元的工作过程进行详细的描述。
第一阶段T1，CK＝0；CKB＝1；PU＝1；PD＝0；Input＝1；Output＝0；Reset＝0。需要说明的是，以下实施例中，“0”表示低电平；“1”表示高电平。
第一信号输入端Input输入高电平，将第三晶体管M3导通，通过第三晶体管M3将上拉节点PU的电位拉升至第一电压端VDD输入的高电平。同时第一电压端VDD输入的高电平为第七晶体管M7的寄生电容充电。
由于上拉节点PU的电位为高电平，因此可以将第一晶体管M1导通，从而可以通过第一晶体管M1将下拉节点PD的电位下拉至第三电压端VGL输入的低电平。由于下拉节点PD的电位为低电平，因此第五晶体管M5和第六晶体管M6处于截止状态。
需要注意，在该第一阶段T1中，由于PU为高电平，第一晶体管M1导通，尽管此时CKB输入高电平，第二晶体管M2导通，但由于第一晶体管M1和第二晶体管M2的尺寸被设计为使得即便二者均导通时，下拉节点PD的电位仍然为低电平。
第二阶段T2，CK＝1；CKB＝0；PU＝1；PD＝0；Input＝0；Output＝1；Reset＝0。
第一信号输入端Input和第二信号输入端Reset输入低电平，第三晶体管和第四晶体管处于截止状态。第七晶体管M7自身的寄生电容在自举作用下，将上拉节点PU的电位进一步拉高。第七晶体管M7导通，将第一时钟信号端CK输入的高电平传输至本级信号输出端Output，以作为扫描信号对该移位寄存器单元对应的栅线进行扫描。
此外，同第一阶段T1，由于上拉节点PU的电位为高电平，因此可以通过第一晶体管M1将下拉节点PD的电位保持在第三电压端VGL输入的低电平。在此情况下，第五晶体管M5和第六晶体管M6处于截止状态。
第三阶段T3，CK＝0；CKB＝1；PU＝0；PD＝1；Input＝0；Output＝0；Reset＝1。
第一信号输入端Input输入低电平，第三晶体管M3处于截止状态。第二信号输入端Reset输入高电平，第四晶体管M4处于导通状，从而可以通过第四晶体管M4将上拉节点PU的电位下拉至第二电压端VSS输入的低电平。在此情况下，第七晶体管M7处于截止状态。
第二时钟信号输入端CKB输入高电平，将第二晶体管M2导通，并通过第二晶体管M2将第二时钟信号输入端CKB输入高电平传输至下拉节点PD。在下拉节点PD的电位控制下，可以将第五晶体管M5和第六晶体管M6导通。通过第五晶体管M5可以将上拉节点PU的电位下拉至第三电压端VGL输入的低电平，从而可以防止上拉节点PU的电位误拉高，以导致第七晶体管M7误导通。同时，第六晶体管M6可以将本级信号输出端Output输出的信号下拉至第三电压端VGL输入的低电平，从而可以避免在移位寄存器单元的非输出阶段，本级信号输出端Output向栅线误输出扫描信号。
需要说明的是，T1～T3阶段可以称为移位寄存器单元的工作时间。本级信号输出端Output只有在第二阶段T2阶段才输出高电平，因此第二阶段T2可以为移位寄存器单元的数据输出阶段，第一阶段T1和第二阶段T2为移位寄存器单元的非输出阶段，在此阶段内本级信号输出端Output输出低电平。
此外，上述晶体管(T1～T7)也可以均为P型晶体管。当移位寄存器单元中的晶体管，以及像素单元中与栅线相连的晶体管均为P型晶体管时。需要对驱动信号的时序，以及电路的输入信号进行相应的调整。
具体的，可以将图3中连接第二电压端VSS和第三电压端VGL的模块或晶体管与第一电压端VDD相连接；将连接第一电压端VDD模块或晶体管与第二电压端VSS或第三电压端VGL相连接。此外，图4中需要对驱动信号的方向进行翻转。具体的工作过程同上所述，在此不再赘述。
实施例二
在实施例一的基础上，下拉控制模块10如图5所示，还可以包括电容C。
其中，所述电容C的一端连接下拉节点PD，另一端与第三电压端VGL相连接。
这样一来，在本级信号输出端Output向栅线输出扫描信号以后，即进入上述第三阶段T3后，可以通过电容C的储能作用维持下拉节点PD处于高电平的状态，从而可以避免由于晶体管的漏电流等原因导致产生使得下拉节点PD的电位有所下降、从而降低下拉节点PD的电位的噪声。
实施例三
在实施例一的基础上，下拉控制模块10如图6所示，还可以包括第八晶体管M8。
其中，第八晶体管M8的栅极连接本级信号输出端Output，第一极连接下拉节点PD，第二极与第三电压端VGL相连接。
在上述第二阶段T2，第七晶体管M7导通，可以将第一时钟信号端输入的高电平在输出至本级信号输出端Output的同时，还可以传输至第八晶体管M8的栅极，从而将第八晶体管M8导通，这样一来，由于第八晶体管M8的第一极及第一晶体管M1的第二极均与下拉节点PD相连接，因此第八晶体管M8和第一晶体管M1能够共同将下拉节点PD的电位下拉至第三电压端VGL输入的低电平，从而可以确保在上述第二阶段T2(即移位寄存器单元的数据输出阶段)，下拉节点PD的电位保持低电平，以避免误将第五晶体管M5和第六晶体管M6导通，从而避免误将上拉节点PU的电位和本级信号输出端Output的输出信号下拉至低电平，进而可以提高GOA电路的稳定性和可靠性。
实施例四
在实施例一的基础上，下拉控制模块10如图7所示，可以同时包括上述电容C和第八晶体管M8，其有益效果同实施例二和实施例三，在此不再赘述。
本公开实施例提供一种显示器件，包括如上所述的任意一种栅极驱动电路，其具有与本公开前述实施例提供的栅极驱动电路相同的有益效果，由于栅极驱动电路在前述实施例中已经进行了详细说明，此 处不再赘述。
该显示器件具体可以为液晶显示器、液晶电视、数码相框、手机、平板电脑等任何具有显示功能的液晶显示产品或者部件。
本公开实施例提供一种用于驱动上述任意一种移位寄存器单元的驱动方法，所述方法可以包括：
第一阶段T1，CK＝0；CKB＝1；Input＝1；Reset＝0。
第一输入模块20通过第一信号输入端Input输入的信号将上拉节点PU的电位上拉至第一电压端VDD的电压；在上拉节点PU的控制下，下拉控制模块10将下拉节点PD的电位下拉至第三电压端VGL的电压，从而避免下拉节点PD将下拉模块40开启。
第二阶段，CK＝1；CKB＝0；Input＝0；Reset＝0。
上拉节点PU将上拉模块50开启，使得第一时钟信号端CK输入的信号传输至本级信号输出端Output，以作为扫描信号输出至于所述移位寄存器单元对应的栅线，并对所述栅线进行扫描；在上拉节点PU的控制下，下拉控制模块10可以将下拉节点PD的电位保持在第三电压端VGL的电压，从而避免下拉节点PD将下拉模块40开启。
第三阶段，CK＝0；CKB＝1；Input＝0；Reset＝1。
第二输入模块30通过第二信号输入端Reset输入的信号将上拉节点PU的电位下拉至第二电压端VSS的电压。由于第二电压端VSS输入低电平，因此上拉节点PU的电位为低电平。在上拉节点PU的控制下，所述上拉模块50关闭，使得本级信号输出端Output在非输出阶段无扫描信号输出。
第二时钟信号端CKB开启下拉控制模块10，并将第二时钟信号端CKB输入的信号传输至所述下拉节点PD。由于第二时钟信号端CKB输入高电平，因此下拉节点PD的电位为高电平。在下拉节点PD电位的控制下，下拉模块40分别将上拉节点PU的电位和本级信号输出端Output的信号下拉至第三电压端VGL的电压，以确保本级信号输出端Output在非输出阶段无扫描信号输出。
本领域普通技术人员可以理解：实现上述方法实施例的全部或部分步 骤可以通过程序指令相关的硬件来完成，前述的程序可以存储于一计算机可读取存储介质中，该程序在执行时，执行包括上述方法实施例的步骤；而前述的存储介质包括：ROM、RAM、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。
本申请要求于2015年1月4日递交的中国专利申请第201510002311.6号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (11)

  1. 一种移位寄存器单元，包括上拉模块、第一输入模块、第二输入模块、下拉控制模块以及下拉模块；
    所述上拉模块，连接上拉节点、第一时钟信号端以及本级信号输出端；用于在所述上拉节点的控制下，将所述第一时钟信号端输入的信号传输至所述本级信号输出端；
    所述第一输入模块，连接第一信号输入端、第一电压端以及所述上拉节点；用于在所述第一信号输入端输入信号的控制下，将所述上拉节点的电压拉至所述第一电压端的电压；
    所述第二输入模块，连接第二信号输入端、第二电压端以及所述上拉节点；用于在所述第二信号输入端输入信号的控制下，将所述上拉节点的电压拉至所述第二电压端的电压；
    所述下拉控制模块，连接第二时钟信号端、所述上拉节点、下拉节点、第三电压端；用于在所述上拉节点的控制下将所述下拉节点的电压拉至所述第三电压端的电压，或在所述第二时钟信号端输入信号的控制下将所述第二时钟信号端输入信号输入至所述下拉节点；
    所述下拉模块，连接所述下拉节点、所述上拉节点、所述本级信号输出端以及所述第三电压端；用于在所述下拉节点的控制下，将所述上拉节点的电位和所述本级信号输出端的输出电压拉至所述第三电压端的电压。
  2. 根据权利要求1所述的移位寄存器单元，其中，所述下拉控制模块包括：第一晶体管和第二晶体管；
    所述第一晶体管的栅极连接所述上拉节点，第一极连接所述第三电压端，第二极与所述下拉节点相连接；
    所述第二晶体管的栅极和第一极连接所述第二时钟信号端，第二极与所述下拉节点相连接。
  3. 根据权利要求2所述的移位寄存器单元，其中，所述下拉控制模块还包括：
    第八晶体管，其栅极连接所述本级信号输出端，第一极连接所述下拉节点，第二极与所述第三电压端相连接。
  4. 根据权利要求2或3所述的移位寄存器单元，其中，所述下拉控制模块还包括：
    电容，其一端连接所述下拉节点，另一端与所述第三电压端相连接。
  5. 根据权利要求1或2所述的移位寄存器单元，其中，所述第一输入模块包括：
    第三晶体管，其栅极连接所述第一信号输入端，第一极连接第一电压端，第二极与所述上拉节点相连接。
  6. 根据权利要求1或2所述的移位寄存器单元，其中，所述第二输入模块包括：
    第四晶体管，其栅极连接所述第二信号输入端，第一极连接所述上拉节点，第二极与所述第二电压端相连接。
  7. 根据权利要求1或2所述的移位寄存器单元，其中，所述下拉模块包括：第五晶体管和第六晶体管；
    所述第五晶体管，其栅极连接所述下拉节点，第一极连接所述第三电压端，第二极与所述上拉节点相连接；
    所述第六晶体管，其栅极连接所述下拉节点，第一极连接所述本级信号输出端，第二极与所述第三电压端相连接。
  8. 根据权利要求1或2所述的移位寄存器单元，其中，所述上拉模块包括：
    第七晶体管，其栅极连接所述上拉节点，第一极连接所述第一时钟信号端，第二极与所述本级信号输出端相连接。
  9. 一种栅极驱动电路，其中，包括至少两级如权利要求1-8任一项所述的移位寄存器单元；
    除第一级移位寄存器单元外，其余每级移位寄存器单元的第一信号输入端与其相邻的上一级移位寄存器单元的本级信号输出端相连接；
    除最后一级移位寄存器单元外，其余每级移位寄存器单元的第二信号输入端与其相邻的下一级移位寄存器单元的本级信号输出端相连接。
  10. 一种显示器件，其中，包括如权利要求9所述的栅极驱动电路。
  11. 一种用于驱动如权利要求1-8任一项所述的移位寄存器单元的驱动方法，其中，
    在第一阶段，第一输入模块通过第一信号输入端输入的信号将上拉节点的电位拉至第一电压端的电压；在所述上拉节点的控制下，下拉控制模块将下拉节点的电位拉至所述第三电压端的电压；
    在第二阶段，所述上拉节点将所述上拉模块开启，使得第一时钟信号端输入的信号传输至所述本级信号输出端；在所述上拉节点的控制下，所述下拉控制模块将所述下拉节点的电位保持在所述第三电压端的电压；
    在第三阶段，第二输入模块通过第二信号输入端输入的信号将所述上拉节点的电位拉至第二电压端的电压，在所述上拉节点的控制下，所述上拉模块关闭；
    第二时钟信号端开启所述下拉控制模块，并将所述第二时钟信号端输入的信号传输至所述下拉节点；在所述下拉节点电位的控制下，下拉模块分别将所述上拉节点的电位和所述本级信号输出端的信号拉至所述第三电压端的电压。
PCT/CN2015/081624 2015-01-04 2015-06-17 移位寄存器单元及驱动方法、栅极驱动电路及显示器件 WO2016107096A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US14/896,793 US20160372063A1 (en) 2015-01-04 2015-06-17 Shift register unit and driving method thereof, gate driving circuit and display apparatus
EP15801310.2A EP3242289A4 (en) 2015-01-04 2015-06-17 Shift register unit and drive method, grid drive circuit and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201510002311.6A CN104485086A (zh) 2015-01-04 2015-01-04 移位寄存器单元及驱动方法、栅极驱动电路及显示器件
CN201510002311.6 2015-01-04

Publications (1)

Publication Number Publication Date
WO2016107096A1 true WO2016107096A1 (zh) 2016-07-07

Family

ID=52759626

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/081624 WO2016107096A1 (zh) 2015-01-04 2015-06-17 移位寄存器单元及驱动方法、栅极驱动电路及显示器件

Country Status (4)

Country Link
US (1) US20160372063A1 (zh)
EP (1) EP3242289A4 (zh)
CN (1) CN104485086A (zh)
WO (1) WO2016107096A1 (zh)

Families Citing this family (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104485086A (zh) * 2015-01-04 2015-04-01 京东方科技集团股份有限公司 移位寄存器单元及驱动方法、栅极驱动电路及显示器件
CN104575430B (zh) * 2015-02-02 2017-05-31 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
CN104732945B (zh) 2015-04-09 2017-06-30 京东方科技集团股份有限公司 移位寄存器及驱动方法、阵列基板栅极驱动装置、显示面板
CN104793382A (zh) * 2015-05-12 2015-07-22 合肥鑫晟光电科技有限公司 一种阵列基板、其驱动方法、显示面板及显示装置
CN105096865B (zh) * 2015-08-06 2018-09-07 京东方科技集团股份有限公司 移位寄存器的输出控制单元、移位寄存器及其驱动方法以及栅极驱动装置
CN105427799B (zh) * 2016-01-05 2018-03-06 京东方科技集团股份有限公司 移位寄存单元、移位寄存器、栅极驱动电路及显示装置
CN105609072B (zh) * 2016-01-07 2018-03-27 武汉华星光电技术有限公司 栅极驱动电路和使用栅极驱动电路的液晶显示器
CN105448266B (zh) * 2016-01-07 2018-01-12 武汉华星光电技术有限公司 栅极驱动电路和使用栅极驱动电路的液晶显示器
CN106023914A (zh) * 2016-05-16 2016-10-12 京东方科技集团股份有限公司 移位寄存器及其操作方法
CN105761660B (zh) 2016-05-16 2018-01-09 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
CN105895045B (zh) * 2016-06-12 2018-02-09 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路及其驱动方法
CN106228927A (zh) * 2016-07-13 2016-12-14 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
CN106128347B (zh) * 2016-07-13 2018-09-11 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
CN106023946B (zh) * 2016-08-04 2019-01-04 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动装置以及显示装置
CN106098003B (zh) * 2016-08-08 2019-01-22 武汉华星光电技术有限公司 Goa电路
CN106205461B (zh) * 2016-09-30 2019-04-02 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
CN106251804B (zh) * 2016-09-30 2018-12-21 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
TWI607450B (zh) * 2016-12-30 2017-12-01 友達光電股份有限公司 移位暫存器與採用其之閘極驅動電路
CN106531121B (zh) * 2017-01-23 2017-10-27 京东方科技集团股份有限公司 栅极驱动单元及其驱动方法、栅极驱动电路和显示装置
CN108428425B (zh) * 2017-02-15 2022-03-08 上海和辉光电股份有限公司 一种扫描驱动电路、移位寄存器及其驱动方法
CN106601178B (zh) 2017-02-23 2019-07-16 合肥京东方光电科技有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
CN106782338B (zh) 2017-02-24 2018-11-23 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
CN106710561B (zh) * 2017-03-08 2019-09-17 京东方科技集团股份有限公司 一种移位寄存器、栅线集成驱动电路及显示装置
CN106960652B (zh) * 2017-04-21 2018-10-30 京东方科技集团股份有限公司 栅极驱动单元、驱动方法、栅极驱动电路和显示装置
CN107134245B (zh) 2017-05-09 2019-01-22 京东方科技集团股份有限公司 驱动电路及其驱动方法、显示面板和显示装置
CN107146568B (zh) * 2017-07-11 2018-12-21 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
CN107248401B (zh) * 2017-08-08 2020-04-03 京东方科技集团股份有限公司 Goa电路及其驱动方法、显示装置
CN109903729B (zh) * 2017-12-08 2024-04-16 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路及驱动方法、显示装置
CN107958649B (zh) * 2018-01-02 2021-01-26 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
CN110322848B (zh) * 2018-03-30 2021-01-08 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路、显示装置及驱动方法
CN108597454B (zh) * 2018-05-09 2020-09-15 上海天马有机发光显示技术有限公司 一种移位寄存器及其驱动方法、扫描驱动电路和显示装置
CN111223459B (zh) 2018-11-27 2022-03-08 元太科技工业股份有限公司 移位寄存器以及栅极驱动电路
CN110189694B (zh) * 2019-06-19 2022-04-15 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法以及栅极驱动电路
CN110264948B (zh) * 2019-06-25 2022-04-01 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
CN110880301B (zh) * 2019-12-12 2022-07-01 京东方科技集团股份有限公司 一种移位寄存器及其驱动方法、栅极驱动电路
CN111768741A (zh) * 2020-06-24 2020-10-13 京东方科技集团股份有限公司 一种移位寄存器、栅极驱动电路及显示面板
US11967278B2 (en) * 2021-03-09 2024-04-23 Chengdu Boe Optoelectronics Technology Co., Ltd. Shift register, driving circuit and display substrate

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120207266A1 (en) * 2009-12-11 2012-08-16 Mitsubishi Electric Corporation Shift register circuit
CN102956213A (zh) * 2012-10-16 2013-03-06 北京京东方光电科技有限公司 一种移位寄存器单元及阵列基板栅极驱动装置
CN103226981A (zh) * 2013-04-10 2013-07-31 京东方科技集团股份有限公司 一种移位寄存器单元及栅极驱动电路
CN104036738A (zh) * 2014-03-27 2014-09-10 京东方科技集团股份有限公司 一种移位寄存器单元、栅极驱动电路及显示装置
CN104252853A (zh) * 2014-09-04 2014-12-31 京东方科技集团股份有限公司 移位寄存器单元及驱动方法、栅极驱动电路及显示器件
CN104485086A (zh) * 2015-01-04 2015-04-01 京东方科技集团股份有限公司 移位寄存器单元及驱动方法、栅极驱动电路及显示器件

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103366704B (zh) * 2013-07-10 2015-08-19 京东方科技集团股份有限公司 一种移位寄存器单元及栅极驱动电路、显示装置
CN103927965B (zh) * 2014-03-21 2017-02-22 京东方科技集团股份有限公司 驱动电路及驱动方法、goa单元、goa电路及显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120207266A1 (en) * 2009-12-11 2012-08-16 Mitsubishi Electric Corporation Shift register circuit
CN102956213A (zh) * 2012-10-16 2013-03-06 北京京东方光电科技有限公司 一种移位寄存器单元及阵列基板栅极驱动装置
CN103226981A (zh) * 2013-04-10 2013-07-31 京东方科技集团股份有限公司 一种移位寄存器单元及栅极驱动电路
CN104036738A (zh) * 2014-03-27 2014-09-10 京东方科技集团股份有限公司 一种移位寄存器单元、栅极驱动电路及显示装置
CN104252853A (zh) * 2014-09-04 2014-12-31 京东方科技集团股份有限公司 移位寄存器单元及驱动方法、栅极驱动电路及显示器件
CN104485086A (zh) * 2015-01-04 2015-04-01 京东方科技集团股份有限公司 移位寄存器单元及驱动方法、栅极驱动电路及显示器件

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3242289A4 *

Also Published As

Publication number Publication date
CN104485086A (zh) 2015-04-01
EP3242289A4 (en) 2018-08-08
US20160372063A1 (en) 2016-12-22
EP3242289A1 (en) 2017-11-08

Similar Documents

Publication Publication Date Title
WO2016107096A1 (zh) 移位寄存器单元及驱动方法、栅极驱动电路及显示器件
US11263942B2 (en) Shift register unit and driving method thereof, gate driving circuit, and display device
US10424242B2 (en) Gate drive circuit having shift register circuit and inverting circuit for outputting an output signal
US10943554B2 (en) Anti-leakage circuit for shift register unit, method of driving shift register unit, gate driver on array circuit and touch display device
US11328672B2 (en) Shift register unit and driving method thereof, gate driving circuit, and display device
US10546549B2 (en) Shift register unit and its driving method, gate drive circuit and display device
US10127875B2 (en) Shift register unit, related gate driver and display apparatus, and method for driving the same
US9875709B2 (en) GOA circuit for LTPS-TFT
US10497454B2 (en) Shift register, operation method thereof, gate driving circuit and display device
US11227524B2 (en) Shift register unit and driving method thereof, gate driving circuit and driving method thereof, and display device
US20180122289A1 (en) Shift register, driving method, gate driving circuit and display device
US9916805B2 (en) GOA circuit for LTPS-TFT
US9293223B2 (en) Shift register unit, gate driving circuit and display device
WO2016188367A1 (zh) 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
WO2017181647A1 (zh) 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
WO2016095468A1 (zh) 移位寄存器单元及驱动方法、栅极驱动电路及显示装置
WO2016201909A1 (zh) 移位寄存器单元、栅极驱动电路和显示装置
WO2020010852A1 (zh) 移位寄存器单元、驱动方法、栅极驱动电路和显示装置
WO2018209937A1 (zh) 移位寄存器及其驱动方法、栅极驱动电路、显示装置
WO2017166867A1 (en) Gate driver on array unit, related gate driver on array circuit, display device containing the same, and method for driving the same
US10796780B2 (en) Shift register unit and driving method thereof, gate driving circuit and display apparatus
US11170696B2 (en) Gate drive circuit and display panel
US11322068B2 (en) Display device having gate driver
US10403210B2 (en) Shift register and driving method, driving circuit, array substrate and display device
US20190122625A1 (en) Shift register unit and driving method thereof, gate driving circuit and display panel

Legal Events

Date Code Title Description
REEP Request for entry into the european phase

Ref document number: 2015801310

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 14896793

Country of ref document: US

Ref document number: 2015801310

Country of ref document: EP

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15801310

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE