US9916805B2 - GOA circuit for LTPS-TFT - Google Patents
GOA circuit for LTPS-TFT Download PDFInfo
- Publication number
- US9916805B2 US9916805B2 US14/913,991 US201614913991A US9916805B2 US 9916805 B2 US9916805 B2 US 9916805B2 US 201614913991 A US201614913991 A US 201614913991A US 9916805 B2 US9916805 B2 US 9916805B2
- Authority
- US
- United States
- Prior art keywords
- tft
- node
- drain
- source
- goa
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active, expires
Links
Images
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3696—Generation of voltages supplied to electrode drivers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
- G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
- G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0404—Matrix technologies
- G09G2300/0408—Integration of the drivers onto the display substrate
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0283—Arrangement of drivers for different directions of scanning
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/08—Details of timing specific for flat panels, other than clock recovery
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
- G09G2320/0214—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display with crosstalk due to leakage current of pixel switch in active matrix panels
Abstract
The invention provides a GOA circuit for LTPS-TFT, by adding the twelfth and thirteenth TFTs (T12, T13) controlled by output ends (G(n−1), G(n+1)) of (n−1)-th and (n+1)-th GOA units, the drain of twelfth TFT T12 connected through the fourth node (W1(n)) to source of first TFT (T1), the drain of first TFT (T1) connected to output end of (n−1)-th GOA unit, the drain of thirteenth TFT (T13) connected through the fifth node W2(n) to source of third TFT (T3), the drain of third TFT (T3) connected to output end of (n+1)-th GOA unit; the first and third TFTs (T1, T3) controlled respectively by the forward and backward scan DC control signals (U2D, D2U) to reduce leakage of twelfth TFT (T12) in forward scanning and leakage of thirteenth TFT (T13) in backward scanning. As such, the leakage in key TFTs is reduced and GOA circuit stability is improved.
Description
The present invention relates to the field of display, and in particular to a gate driver on array (GOA) circuit for thin film transistor (TFT) based on low temperature poly-silicon (LTPS) semiconductor.
As the liquid crystal display (LCD) shows the advantages of being thin, low power-consumption, and no radiation, the LCD is widely used in various devices, such as, liquid crystal TV, mobile phones, PDA, digital camera, PC monitors or notebook PC screens as well as the leading technology in tablet PCs.
The gate driver on array (GOA) technology is the array substrate column drive technology, by using the array substrate process for the LCD panel to manufacture the driver circuit for the horizontal scan line in the area around the active area on the substrate to replace the external integrated circuit (IC) to perform driving the horizontal scan lines. GOA technology can reduce the bonding process for the external IC and reduce cost, as well as the ability to realize narrow-border or borderless panels, and is used by many types of displays.
As the low temperature poly-silicon (LTPS) semiconductor TFT develops, the LTPS-TFT LCD gains much attention. The LTPS-TFT LCD has the advantages of high resolution, fast response, high luminance, and high opening ratio. Because the LTPS has a more orderly arrangement than the a-Si, the LTPS has ultra-high electron migration rate, 100 times higher than the a-Si. The LTPS can use GOA technology to manufacture the gate driver circuit on the TFT substrate to achieve system integration, save space and the cost for driver IC.
Refer to FIG. 1 . The known GOA circuit for LTPS-TFT comprises: a plurality of cascade GOA units, for a positive integer n, the n-th stage GOA unit comprising: a first TFT T1, with the gate connected to the output end G(n−1) of the (n−1)-th stage GOA unit, drain connected to the forward scan direct current (DC) control signal U2D, and the source connected to the third node H(n); a second TFT T2, with the gate connected to the first node Q(n), drain connected to the output end G(n), and the source connected to the M-th clock signal CK(M); a third TFT T3, with the gate connected to the output end G(n+1) of the (n+1)-th stage GOA unit, source connected to the third node H(n), and drain connected to the backward scan DC control signal D2U; a fourth TFT T4, with the gate connected to the (M+1)-th clock signal CK(M+1), source connected to the output end G(n), and drain connected to a constant low voltage VGL; a fifth TFT T5, with the gate connected to a constant high voltage VGH, source connected to the third node H(n), and drain connected to first node Q(n); a sixth TFT T6, with the gate connected to the (M+1)-th clock signal CK(M+1), source connected to the third node H(n), and drain connected to a constant low voltage VGL; a seventh TFT T7, with the gate connected to the second node P(n), source connected to the third node H(n), and drain connected to a constant low voltage VGL; an eighth TFT T8, with the gate connected to the second node P(n), source connected to the output end G(n), and drain connected to a constant low voltage VGL; a ninth TFT T9, with the gate connected to the (M+1)-th clock signal CK(M+1), source connected to the second node P(n), and drain connected to a constant low voltage VGL; a tenth TFT T10, with the gate connected to the M-th clock signal CK(M), source connected to the constant high voltage VGH, and drain connected to the second node P(n); a eleventh TFT T11, with the gate connected to the third node H(n), source connected to the second node P(n), and drain connected to a constant low voltage VGL; a first capacitor C1, with one end connected to the first node Q(n) and the other end connected to the output end G(n); and a second capacitor C2, with one end connected to the second node P(n) and the other end connected to the constant low voltage VGL.
The known GOA circuit can scan forward or backward. During forward scanning, as shown in FIG. 2 , the forward scan DC control signal U2D is high and the backward scan DC control signal D2U is low; during backward scanning, the forward scan DC control signal U2D is low and the backward scan DC control signal D2U is high.
In the known GOA circuit in FIG. 1 , the first TFT T1 and the third TFT T3 form the control unit for forward or backward scanning. Al referring to FIG. 2 , when the forward scanning reaches the time that the output end G(n) and the first node Q(n) remaining at low level, the output end G(n+1) of the (n+1)-th GOA unit, the output end G(n−1) of the (n−1)-th GOA unit, and the first node Q(n) are all at low level, the forward scan DC control signal U2D is at high level, then the voltage Vgs between the gate and the source of the first TFT T1 is Vgs=0V, and the voltage Vgs between the drain and the source is Vgs=VGH−VGL; the voltage Vgs between the gate and the source of the third TFT T3 is Vgs=0V, and the voltage Vgs between the drain and the source is Vgs=0V. Also referring to FIG. 3 of the I-V relation of TFT under different gate-to-drain voltage, when the voltage Vgs between the gate and source is Vgs=0V, the higher the drain-to-source voltage Vgs is, the larger the current of the TFT. With respect to the TFT T1 and TFT T3, the current in the first TFT T1 is larger than the current in the third TFT T3. At this point, the first TFT T1 and the third TFT T3 are both turned off, wherein a high current in a TFT in turn-off state will cause leakage. That is, the first TFT T1 is leaking the current. On the other hand, when the GOA circuit is in backward scanning and reaches the time that the output end G(n) and the first node Q(n) remaining at low level, the current in the third TFT T3 is larger than the current in the first TFT T1, and the third TFT T3 is in the leakage state. The leakage will cause the instability in the known GOA circuit.
The object of the present invention is to provide a GOA circuit for LTPS-TFT, able to reduce the leakage current in the key TFT to enhance the GOA circuit stability.
To achieve the above object, the present invention provides a GOA circuit for LTPS-TFT, which comprises: a plurality of cascade GOA units, each GOA unit comprising: a forward and backward scan control unit, an output unit and a node control unit; for a positive integer n, other than the GOA unit in the first and the last stages, in the n-th GOA unit, the forward and backward scan control unit comprising: a first TFT, with a gate connected to a forward scan DC control signal, a drain connected to an output end of the (n−1)-th GOA unit, and a source connected to a fourth node; a twelfth TFT, with a gate connected to the output end of the (n−1)-th GOA unit, a drain connected to the fourth node, and a source connected to a third node; a third TFT, with a gate connected to the backward scan DC control signal, a source connected to a fifth node, and a drain connected to an output end of the (n+1)-th GOA unit; and a thirteenth TFT, with a gate connected to the output end of the (n+1)-th GOA unit, a drain connected to the fifth node, and a source connected to the third node; the output unit comprising: a second TFT, with a gate connected to a first node, a source connected to an M-th clock signal, and a drain connected to an output end; and a first capacitor, with one end connected to the first node and the other end connected to the output end; the node control unit comprising: a fourth TFT, with a gate connected to the (M+1)-th clock signal, a source connected to the output end, and a drain connected to a constant low voltage; a fifth TFT, with a gate connected to a constant high voltage, a source connected to the third node, and a drain connected to the first node; a sixth TFT, with a gate connected to the (M+1)-th clock signal, a source connected to the third node, and a drain connected to the constant low voltage; a seventh TFT, with a gate connected to a second node, a source connected to the third node, and a drain connected to the constant low voltage; an eighth TFT, with a gate connected to the second node, a source connected to the output end, and a drain connected to the constant low voltage; a ninth TFT, with a gate connected to the (M+1)-th clock signal, a source connected to the second node, and a drain connected to the constant low voltage; a tenth TFT, with a gate connected to the M-th clock signal, a source connected to the constant high voltage, and a drain connected to the second node; an eleventh TFT, with a gate connected to the third node, a source connected to the second node, and a drain connected to the constant low voltage; and a second capacitor, with one end connected to the second end and the other end connected to the constant low voltage; the forward scan DC control signal and the backward scan DC control signal having opposite voltage levels.
The GOA circuit for LTPS-TFT has both forward scanning and backward scanning capabilities; when the forward scanning entering the time of the output end and the first node maintaining low level, the voltage between the gate and the source of the twelfth TFT is 0V and the voltage between the drain and the source is 0V, and the third TFT and the thirteenth TFT are both turned off; when the backward scanning entering the time of the output end and the first node maintaining low level, the voltage between the gate and the source of the thirteenth TFT is 0V and the voltage between the drain and the source is 0V, and the first TFT and the twelfth TFT are both turned off.
In the first GOA unit, the drain of the first TFT is connected to a circuit activation signal.
In the last GOA unit, the drain of the third TFT is connected to a circuit activation signal.
When the forward scan DC control signal is high and the backward scan DC control signal is low, the forward scanning is performed.
When the forward scan DC control signal is low and the backward scan DC control signal is high, the backward scanning is performed.
The clock signal comprises two signals: a first clock signal and a second clock signal, when the M-th clock signal is the second clock signal, the (M+1)-th clock signal is the first signal.
The TFTs are all of the N-type LTPS-TFTs.
The present invention also provides a GOA circuit for LTPS-TFT, which comprises: a plurality of cascade GOA units, each GOA unit comprising: a forward and backward scan control unit, an output unit and a node control unit; for a positive integer n, other than the GOA unit in the first and the last stages, in the n-th GOA unit, the forward and backward scan control unit comprising: a first TFT, with a gate connected to a forward scan DC control signal, a drain connected to an output end of the (n−1)-th GOA unit, and a source connected to a fourth node; a twelfth TFT, with a gate connected to the output end of the (n−1)-th GOA unit, a drain connected to the fourth node, and a source connected to a third node; a third TFT, with a gate connected to a backward scan DC control signal, a source connected to a fifth node, and a drain connected to an output end of the (n+1)-th GOA unit; and a thirteenth TFT, with a gate connected to the output end of the (n+1)-th GOA unit, a drain connected to the fifth node, and a source connected to the third node; the output unit comprising: a second TFT, with a gate connected to a first node, a source connected to an M-th clock signal, and a drain connected to an output end; and a first capacitor, with one end connected to the first node and the other end connected to the output end; the node control unit comprising: a fourth TFT, with a gate connected to the (M+1)-th clock signal, a source connected to the output end, and a drain connected to a constant low voltage; a fifth TFT, with a gate connected to a constant high voltage, a source connected to the third node, and a drain connected to the first node; a sixth TFT, with a gate connected to the (M+1)-th clock signal, a source connected to the third node, and a drain connected to the constant low voltage; a seventh TFT, with a gate connected to a second node, a source connected to the third node, and a drain connected to the constant low voltage; an eighth TFT, with a gate connected to the second node, a source connected to the output end, and a drain connected to the constant low voltage; a ninth TFT, with a gate connected to the (M+1)-th clock signal, a source connected to the second node, and a drain connected to the constant low voltage; a tenth TFT, with a gate connected to the M-th clock signal, a source connected to the constant high voltage, and a drain connected to the second node; an eleventh TFT, with a gate connected to the third node, a source connected to the second node, and a drain connected to the constant low voltage; and a second capacitor, with one end connected to the second end and the other end connected to the constant low voltage; the forward scan DC control signal and the backward scan DC control signal having opposite voltage levels; wherein the GOA circuit for LTPS-TFT has both forward scanning and backward scanning capabilities; when the forward scanning entering the time of the output end and the first node maintaining low level, the voltage between the gate and the source of the twelfth TFT is 0V and the voltage between the drain and the source is 0V, and the third TFT and the thirteenth TFT are both turned off; when the backward scanning entering the time of the output end and the first node maintaining low level, the voltage between the gate and the source of the thirteenth TFT is 0V and the voltage between the drain and the source is 0V, and the first TFT and the twelfth TFT are both turned off; in the first GOA unit, the drain of the first TFT is connected to a circuit activation signal; in the last GOA unit, the drain of the third TFT is connected to a circuit activation signal.
Compared to the known techniques, the present invention provides the following advantages: the present invention provides a GOA circuit for LTPS-TFT, by adding the twelfth and thirteenth TFTs controlled by output ends of (n−1)-th and (n+1)-th GOA units, the drain of twelfth TFT connected through the fourth node to the source of first TFT, the drain of first TFT connected to output end of (n−1)-th GOA unit, the drain of thirteenth TFT connected through the fifth node to the source of third TFT, the drain of third TFT connected to the output end of (n+1)-th GOA unit; the first and the third TFTs being controlled respectively by the forward and backward scan DC control signals; when the forward scanning entering the time of output end and first node maintaining low, the fourth being low and able to reduce leakage in twelfth TFT; when the backward scanning entering the time of output end and first node maintaining low, the fifth being low and able to reduce leakage in thirteenth TFT. As such, the leakage in key TFTs is reduced and GOA circuit stability is improved.
To make the technical solution of the embodiments according to the present invention, a brief description of the drawings that are necessary for the illustration of the embodiments will be given as follows. Apparently, the drawings described below show only example embodiments of the present invention and for those having ordinary skills in the art, other drawings may be easily obtained from these drawings without paying any creative effort. In the drawings:
To further explain the technical means and effect of the present invention, the following refers to embodiments and drawings for detailed description.
Refer to FIG. 4 . The present invention provides a GOA circuit for LTPS-TFT, which comprises: a plurality of cascade GOA units, each GOA unit comprising: a forward and backward scan control unit 100, an output unit 200 and a node control unit 300.
For a positive integer n, other than the GOA unit in the first and the last stages, in the n-th GOA unit, the forward and backward scan control unit 100 comprises: a first TFT T1, with a gate connected to a forward scan DC control signal U2D, a drain connected to an output end G(n−1) of the (n−1)-th GOA unit, and a source connected to a fourth node W1(n); a twelfth TFT T12, with a gate connected to the output end G(n−1) of the (n−1)-th GOA unit, a drain connected to the fourth node W1(n), and a source connected to a third node H(n); a third TFT T3, with a gate connected to a backward scan DC control signal D2U, a source connected to a fifth node W2(n), and a drain connected to an output end G(n+1) of the (n+1)-th GOA unit; and a thirteenth TFT T13, with a gate connected to the output end G(n+1) of the (n+1)-th GOA unit, a drain connected to the fifth node W2(n), and a source connected to the third node H(n).
The output unit 200 comprises: a second TFT T2, with a gate connected to a first node the Q(n), a source connected to an M-th clock signal CK(M), and a drain connected to an output end G(n); and a first capacitor C1, with one end connected to the first node Q(n) and the other end connected to the output end G(n).
The node control unit 300 comprises: a fourth TFT T4, with a gate connected to the (M+1)-th clock signal CK(M+1), a source connected to the output end G(n), and a drain connected to the constant low voltage VGL; a fifth TFT T5, with a gate connected to a constant high voltage VGH, a source connected to the third node H(n), and a drain connected to the first node Q(n); a sixth TFT T6, with a gate connected to the (M+1)-th clock signal CK(M+1), a source connected to the third node H(n), and a drain connected to the constant low voltage VGL; a seventh TFT T7, with a gate connected to a second node P(n), a source connected to the third node H(n), and a drain connected to the constant low voltage VGL; an eighth TFT T8, with a gate connected to the second node P(n), a source connected to the output end G(n), and a drain connected to the constant low voltage VGL; a ninth TFT T9, with a gate connected to the (M+1)-th clock signal CK(M+1), a source connected to the second node P(n), and a drain connected to the constant low voltage VGL; a tenth TFT T10, with a gate connected to the M-th clock signal CK(M), a source connected to the constant high voltage VGH, and a drain connected to the second node P(n); an eleventh TFT T11, with a gate connected to the third node H(n), a source connected to the second node P(n), and a drain connected to the constant low voltage VGL; and a second capacitor C2, with one end connected to the second end P(n) and the other end connected to the constant low voltage VGL.
Specifically, the TFTs are all of the N-type LTPS-TFTs.
It should be noted that, referring to FIG. 7 and FIG. 8 , in the first GOA unit, the drain of the first TFT T1 is connected to a circuit activation signal STV; and in the last GOA unit, the drain of the third TFT T3 is connected to the circuit activation signal STV.
The GOA circuit for LTPS-TFT has both forward scanning and backward scanning capabilities. The forward scan DC control signal U2D and the backward scan DC control signal D2U have opposite voltage levels. When the forward scan DC control signal U2D is high and the backward scan DC control signal D2U is low, the GOA circuit performs forward scanning; when the forward scan DC control signal U2D is low and the backward scan DC control signal D2U is high, the GOA circuit backward scanning.
Refer to FIG. 5 and FIG. 6 . The clock signal comprises two signals: a first clock signal CK(1) and a second clock signal CK(2), when the M-th clock signal is the second clock signal CK(2), the (M+1)-th clock signal is the first signal CK(1). The output end G(n) of each GOA unit corresponds to a clock signal, for example, the output end of the first GOA unit corresponds to the first clock signal CK(1); the output end of the second GOA unit corresponds to the second clock signal CK(2); the output end of the third GOA unit corresponds to the first clock signal CK(1); the output end of the fourth GOA unit corresponds to the second clock signal CK(2); and so on.
Refer to FIG. 4 and FIG. 5 . When the forward scan DC control signal U2D is high and the backward scan DC control signal D2U is low, the GOA circuit performs forward scanning. Specifically, the process is as follows.
Phase 3, low voltage output phase: the (M+1)-th clock signal provides a high level voltage, the sixth TFT T6 and the fourth TFT T4 are conductive, the third node H(n), the first node Q(n) and the output end G(n) are all pulled down to the constant low voltage VGL.
Phase 4, the output end G(n) and the first node Q(n) low voltage maintaining phase: the third node H(n) becomes low, and the eleventh TFT T11 controlled by the third node H(n) is turned off; the M-th clock signal CK(M) and the (M+1)-th clock signal CK(M+1) provides a high level voltage alternatingly: when the M-th clock signal CK(M) provides a high level voltage, the tenth TFT T10 is conductive, the second node P(n) is pulled up to the constant high voltage VGH, the seventh TFT T7 and the eighth TFT T8 controlled by the second node P(n) become conductive to maintain the third node H(n), the first node Q(n), and the output end G(n) at low voltage; when the (M+1)-th clock signal CK(M+1) provides a high level voltage, the fourth TFT T4 and the sixth TFT T6 are conductive to maintain the third node H(n), the first node Q(n), and the output end G(n) at low voltage, at the same time, the ninth TFT T9 is also conductive, the second node P(n) is pulled down to the low level to turn off the seventh TFT T7 and the eighth TFT T8 to prevent the second node P(n) from staying at high level, which may lead to the instability of the seventh TFT T7 and the eighth TFT T8 due to long time under stress.
It should be noted that in the output end G(n) and the first node Q(n) low voltage maintaining phase in forward scanning, because the output end G(n−1) of the (n−1)-th GOA unit provides a low level voltage, the forward scan DC control signal U2D is high, the first TFT T1 is conductive, the fourth node W1(n), i.e., the drain of the twelfth TFT T12, is low, the third node H(n), i.e., the source of the twelfth TFT T12, is low, the gate of the twelfth TFT T12 connected to the output end G(n−1) of the (n−1)-th GOA unit is also low, therefore, the voltage between the gate and the source of twelfth TFT T12 Vgs=0V, and the voltage between the drain and the source Vgs=0V. Also referring to FIG. 3 , the leakage of the twelfth TFT T12 is clearly smaller than the known technology. Moreover, in the output end G(n) and the first node Q(n) low voltage maintaining phase, the serially connected third TFT T3 and the thirteenth TFT T13 are both turned off, which also reduce the leakage occurring compared to the known GOA circuit.
Refer to FIG. 4 and FIG. 6 . When the backward scan DC control signal D2U is high and the forward scan DC control signal U2D is low, the GOA circuit performs backward scanning. Specifically, the process is as follows.
Phase 3, low voltage output phase: the (M+1)-th clock signal provides a high level voltage, the sixth TFT T6 and the fourth TFT T4 are conductive, the third node H(n), the first node Q(n) and the output end G(n) are all pulled down to the constant low voltage VGL.
Phase 4, the output end G(n) and the first node Q(n) low voltage maintaining phase: the third node H(n) becomes low, and the eleventh TFT T11 controlled by the third node H(n) is turned off; the M-th clock signal CK(M) and the (M+1)-th clock signal CK(M+1) provides a high level voltage alternatingly: when the M-th clock signal CK(M) provides a high level voltage, the tenth TFT T10 is conductive, the second node P(n) is pulled up to the constant high voltage VGH, the seventh TFT T7 and the eighth TFT T8 controlled by the second node P(n) become conductive to maintain the third node H(n), the first node Q(n), and the output end G(n) at low voltage; when the (M+1)-th clock signal CK(M+1) provides a high level voltage, the fourth TFT T4 and the sixth TFT T6 are conductive to maintain the third node H(n), the first node Q(n), and the output end G(n) at low voltage, at the same time, the ninth TFT T9 is also conductive, the second node P(n) is pulled down to the low level to turn off the seventh TFT T7 and the eighth TFT T8 to prevent the second node P(n) from staying at high level, which may lead to the instability of the seventh TFT T7 and the eighth TFT T8 due to long time under stress.
It should be noted that in the output end G(n) and the first node Q(n) low voltage maintaining phase in backward scanning, because the output end G(n+1) of the (n+1)-th GOA unit provides a low level voltage, the backward scan DC control signal D2U is high, the third TFT T3 is conductive, the fifth node W2(n), i.e., the drain of the thirteenth TFT T13, is low, the third node H(n), i.e., the source of the thirteenth TFT T13, is low, the gate of the thirteenth TFT T13 connected to the output end G(n+1) of the (n+1)-th GOA unit is also low, therefore, the voltage between the gate and the source of thirteenth TFT T13 Vgs=0V, and the voltage between the drain and the source Vgs=0V. Also referring to FIG. 3 , the leakage of the thirteenth TFT T13 is clearly smaller than the known technology. Moreover, in the output end G(n) and the first node Q(n) low voltage maintaining phase in backward scanning, the serially connected first TFT T1 and the twelfth TFT T12 are both turned off, which also reduce the leakage occurring compared to the known GOA circuit
In summary, the present invention provides a GOA circuit for LTPS-TFT, by adding the twelfth and thirteenth TFTs controlled by output ends of (n−1)-th and (n+1)-th GOA units, the drain of twelfth TFT connected through the fourth node to the source of first TFT, the drain of first TFT connected to output end of (n−1)-th GOA unit, the drain of thirteenth TFT connected through the fifth node to the source of third TFT, the drain of third TFT connected to the output end of (n+1)-th GOA unit; the first and the third TFTs being controlled respectively by the forward and backward scan DC control signals; when the forward scanning entering the time of output end and first node maintaining low, the fourth being low and able to reduce leakage in twelfth TFT; when the backward scanning entering the time of output end and first node maintaining low, the fifth being low and able to reduce leakage in thirteenth TFT. As such, the leakage in key TFTs is reduced and GOA circuit stability is improved.
It should be noted that in the present disclosure the terms, such as, first, second are only for distinguishing an entity or operation from another entity or operation, and does not imply any specific relation or order between the entities or operations. Also, the terms “comprises”, “include”, and other similar variations, do not exclude the inclusion of other non-listed elements. Without further restrictions, the expression “comprises a . . . ” does not exclude other identical elements from presence besides the listed elements.
Embodiments of the present invention have been described, but not intending to impose any unduly constraint to the appended claims. Any modification of equivalent structure or equivalent process made according to the disclosure and drawings of the present invention, or any application thereof, directly or indirectly, to other related fields of technique, is considered encompassed in the scope of protection defined by the clams of the present invention.
Claims (13)
1. A gate driver on array (GOA) circuit for low temperature poly-silicon (LTPS) thin film transistor (TFT), which comprises: a plurality of cascade GOA units, each GOA unit comprising: a forward and backward scan control unit, an output unit and a node control unit;
for a positive integer n, other than the GOA unit in the first and the last stages, in the n-th GOA unit:
the forward and backward scan control unit comprising: a first TFT, with a gate connected to a forward scan DC control signal, a drain connected to an output end of the (n−1)-th GOA unit, and a source connected to a fourth node; a twelfth TFT, with a gate connected to the output end of the (n−1)-th GOA unit, a drain connected to the fourth node, and a source connected to a third node; a third TFT, with a gate connected to a backward scan DC control signal, a source connected to a fifth node, and a drain connected to an output end of the (n+1)-th GOA unit; and a thirteenth TFT, with a gate connected to the output end of the (n+1)-th GOA unit, a drain connected to the fifth node, and a source connected to the third node;
the output unit comprising: a second TFT, with a gate connected to a first node, a source connected to an M-th clock signal, and a drain connected to an output end; and a first capacitor, with one end connected to the first node and the other end connected to the output end;
the node control unit comprising: a fourth TFT, with a gate connected to the (M+1)-th clock signal, a source connected to the output end, and a drain connected to a constant low voltage; a fifth TFT, with a gate connected to a constant high voltage, a source connected to the third node, and a drain connected to the first node; a sixth TFT, with a gate connected to the (M+1)-th clock signal, a source connected to the third node, and a drain connected to the constant low voltage; a seventh TFT, with a gate connected to a second node, a source connected to the third node, and a drain connected to the constant low voltage; an eighth TFT, with a gate connected to the second node, a source connected to the output end, and a drain connected to the constant low voltage; a ninth TFT, with a gate connected to the (M+1)-th clock signal, a source connected to the second node, and a drain connected to the constant low voltage; a tenth TFT, with a gate connected to the M-th clock signal, a source connected to the constant high voltage, and a drain connected to the second node; an eleventh TFT, with a gate connected to the third node, a source connected to the second node, and a drain connected to the constant low voltage; and a second capacitor, with one end connected to the second end and the other end connected to the constant low voltage; and
the forward scan DC control signal and the backward scan DC control signal having opposite voltage levels.
2. The GOA circuit for LTPS-TFT as claimed in claim 1 , wherein the GOA circuit for LTPS-TFT has both forward scanning and backward scanning capabilities;
when the forward scanning entering the time of the output end and the first node maintaining low level, the voltage between the gate and the source of the twelfth TFT is 0V and the voltage between the drain and the source is 0V, and the third TFT and the thirteenth TFT are both turned off;
when the backward scanning entering the time of the output end and the first node maintaining low level, the voltage between the gate and the source of the thirteenth TFT is 0V and the voltage between the drain and the source is 0V, and the first TFT and the twelfth TFT are both turned off.
3. The GOA circuit for LTPS-TFT as claimed in claim 2 , wherein when the forward scan DC control signal is high and the backward scan DC control signal is low, the forward scanning is performed.
4. The GOA circuit for LTPS-TFT as claimed in claim 2 , wherein when the forward scan DC control signal is low and the backward scan DC control signal is high, the backward scanning is performed.
5. The GOA circuit for LTPS-TFT as claimed in claim 1 , wherein in the first GOA unit, the drain of the first TFT is connected to a circuit activation signal.
6. The GOA circuit for LTPS-TFT as claimed in claim 1 , wherein in the last GOA unit, the drain of the third TFT is connected to a circuit activation signal.
7. The GOA circuit for LTPS-TFT as claimed in claim 1 , wherein the clock signal comprises two signals: a first clock signal and a second clock signal, when the M-th clock signal is the second clock signal, the (M+1)-th clock signal is the first signal.
8. The GOA circuit for LTPS-TFT as claimed in claim 1 , wherein the TFTs are all of the N-type LTPS-TFTs.
9. A gate driver on array (GOA) circuit for low temperature poly-silicon (LTPS) thin film transistor (TFT), which comprises: a plurality of cascade GOA units, each GOA unit comprising: a forward and backward scan control unit, an output unit and a node control unit;
for a positive integer n, other than the GOA unit in the first and the last stages, in the n-th GOA unit:
the forward and backward scan control unit comprising: a first TFT, with a gate connected to a forward scan DC control signal, a drain connected to an output end of the (n−1)-th GOA unit, and a source connected to a fourth node; a twelfth TFT, with a gate connected to the output end of the (n−1)-th GOA unit, a drain connected to the fourth node, and a source connected to a third node; a third TFT, with a gate connected to a backward scan DC control signal, a source connected to a fifth node, and a drain connected to an output end of the (n+1)-th GOA unit; and a thirteenth TFT, with a gate connected to the output end of the (n+1)-th GOA unit, a drain connected to the fifth node, and a source connected to the third node;
the output unit comprising: a second TFT, with a gate connected to a first node, a source connected to an M-th clock signal, and a drain connected to an output end; and a first capacitor, with one end connected to the first node and the other end connected to the output end;
the node control unit comprising: a fourth TFT, with a gate connected to the (M+1)-th clock signal, a source connected to the output end, and a drain connected to a constant low voltage; a fifth TFT, with a gate connected to a constant high voltage, a source connected to the third node, and a drain connected to the first node; a sixth TFT, with a gate connected to the (M+1)-th clock signal, a source connected to the third node, and a drain connected to the constant low voltage; a seventh TFT, with a gate connected to a second node, a source connected to the third node, and a drain connected to the constant low voltage; an eighth TFT, with a gate connected to the second node, a source connected to the output end, and a drain connected to the constant low voltage; a ninth TFT, with a gate connected to the (M+1)-th clock signal, a source connected to the second node, and a drain connected to the constant low voltage; a tenth TFT, with a gate connected to the M-th clock signal, a source connected to the constant high voltage, and a drain connected to the second node; an eleventh TFT, with a gate connected to the third node, a source connected to the second node, and a drain connected to the constant low voltage; and a second capacitor, with one end connected to the second end and the other end connected to the constant low voltage; and
the forward scan DC control signal and the backward scan DC control signal having opposite voltage levels;
wherein the GOA circuit for LTPS-TFT has both forward scanning and backward scanning capabilities;
when the forward scanning entering the time of the output end and the first node maintaining low level, the voltage between the gate and the source of the twelfth TFT is 0V and the voltage between the drain and the source is 0V, and the third TFT and the thirteenth TFT are both turned off;
when the backward scanning entering the time of the output end and the first node maintaining low level, the voltage between the gate and the source of the thirteenth TFT is 0V and the voltage between the drain and the source is 0V, and the first TFT and the twelfth TFT are both turned off;
wherein in the first GOA unit, the drain of the first TFT is connected to a circuit activation signal;
wherein in the last GOA unit, the drain of the third TFT is connected to a circuit activation signal.
10. The GOA circuit for LTPS-TFT as claimed in claim 9 , wherein when the forward scan DC control signal is high and the backward scan DC control signal is low, the forward scanning is performed.
11. The GOA circuit for LTPS-TFT as claimed in claim 9 , wherein when the forward scan DC control signal is low and the backward scan DC control signal is high, the backward scanning is performed.
12. The GOA circuit for LTPS-TFT as claimed in claim 9 , wherein the clock signal comprises two signals: a first clock signal and a second clock signal, when the M-th clock signal is the second clock signal, the (M+1)-th clock signal is the first signal.
13. The GOA circuit for LTPS-TFT as claimed in claim 9 , wherein the TFTs are all of the N-type LTPS-TFTs.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510954368.6A CN105469760B (en) | 2015-12-17 | 2015-12-17 | GOA circuits based on LTPS semiconductor thin-film transistors |
| CN201510954368.6 | 2015-12-17 | ||
| CN201510954368 | 2015-12-17 | ||
| PCT/CN2016/072428 WO2017101200A1 (en) | 2015-12-17 | 2016-01-28 | Ltps semiconductor thin-film transistor-based goa circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| US20180033389A1 US20180033389A1 (en) | 2018-02-01 |
| US9916805B2 true US9916805B2 (en) | 2018-03-13 |
Family
ID=55607391
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US14/913,991 Active 2036-10-25 US9916805B2 (en) | 2015-12-17 | 2016-01-28 | GOA circuit for LTPS-TFT |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US9916805B2 (en) |
| CN (1) | CN105469760B (en) |
| WO (1) | WO2017101200A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10403210B2 (en) * | 2016-03-16 | 2019-09-03 | Boe Technology Group Co., Ltd. | Shift register and driving method, driving circuit, array substrate and display device |
| US11315512B2 (en) * | 2020-02-12 | 2022-04-26 | Wuhan China Star Optoelectronics Technology Co., Ltd. | GOA circuit and display panel thereof |
Families Citing this family (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105976775B (en) | 2016-05-18 | 2019-01-15 | 武汉华星光电技术有限公司 | GOA circuit based on LTPS semiconductor thin-film transistor |
| CN106409243B (en) * | 2016-07-13 | 2019-02-26 | 武汉华星光电技术有限公司 | A kind of GOA driving circuit |
| CN105976781B (en) * | 2016-07-14 | 2018-08-14 | 武汉华星光电技术有限公司 | GOA circuits |
| CN106098002B (en) * | 2016-08-05 | 2018-10-19 | 武汉华星光电技术有限公司 | Scan drive circuit and flat display apparatus with the circuit |
| CN106297630B (en) * | 2016-08-22 | 2019-08-02 | 武汉华星光电技术有限公司 | Scan drive circuit and flat display apparatus with the circuit |
| CN106782365B (en) | 2016-12-15 | 2019-05-03 | 武汉华星光电技术有限公司 | A kind of gate driving circuit and driving method, display device |
| CN106486075B (en) * | 2016-12-27 | 2019-01-22 | 武汉华星光电技术有限公司 | GOA circuit |
| CN107068074B (en) * | 2016-12-27 | 2019-04-30 | 武汉华星光电技术有限公司 | GOA circuit |
| CN108682380B (en) * | 2018-07-26 | 2021-01-08 | 京东方科技集团股份有限公司 | Shift register and driving method thereof, grid driving circuit and display device |
| CN109979370A (en) | 2018-11-28 | 2019-07-05 | 武汉华星光电技术有限公司 | GOA circuit and display panel |
| CN109509443A (en) * | 2018-12-04 | 2019-03-22 | 昆山龙腾光电有限公司 | Gate driving circuit and display device |
| CN109584799A (en) * | 2019-02-02 | 2019-04-05 | 京东方科技集团股份有限公司 | A kind of pixel-driving circuit, pixel circuit, display panel and display device |
| CN111326096A (en) * | 2020-04-07 | 2020-06-23 | 武汉华星光电技术有限公司 | GOA circuit and display panel |
| CN112037721B (en) * | 2020-08-06 | 2022-02-22 | 武汉华星光电技术有限公司 | GOA circuit, display panel and display device thereof |
| CN113643641A (en) * | 2021-08-03 | 2021-11-12 | 武汉华星光电技术有限公司 | Grid driving circuit and display panel |
| CN113643640B (en) * | 2021-08-03 | 2023-06-02 | 武汉华星光电技术有限公司 | Gate driving circuit and display panel |
| CN114596828B (en) * | 2022-04-25 | 2022-12-09 | 福建华佳彩有限公司 | Load-reducing 12T1C GIP circuit and driving method thereof |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130077736A1 (en) * | 2011-09-23 | 2013-03-28 | Hydis Technologies Co., Ltd. | Shift Register and Driving Circuit Using the Same |
| US20140049712A1 (en) * | 2012-08-17 | 2014-02-20 | Hannstar Display Corporation | Liquid crystal display and bidirectional shift register device thereof |
| CN104485079A (en) * | 2014-12-31 | 2015-04-01 | 深圳市华星光电技术有限公司 | GOA (Gate Driver On Array) circuit for liquid crystal display device |
| US20150187323A1 (en) * | 2013-12-30 | 2015-07-02 | Shanghai Avic Optoelectronics Co., Ltd. | Gate drive apparatus and display apparatus |
| US9190170B1 (en) * | 2014-06-18 | 2015-11-17 | Boe Technology Group Co., Ltd | Shift register unit, gate driving device, display panel and display device |
| US20160019976A1 (en) * | 2014-07-21 | 2016-01-21 | Au Optronics Corp. | Shift register and flat panel display using the same |
| US20160189795A1 (en) * | 2014-12-30 | 2016-06-30 | Shanghai Avic Optoelectronics Co., Ltd | Shift register, method and system for operating shift register |
| US20160187917A1 (en) * | 2014-12-29 | 2016-06-30 | Shanghai Tianma Micro-electronics Co., Ltd. | Gate drive circuit, array substrate, display panel and display device |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007317288A (en) * | 2006-05-25 | 2007-12-06 | Mitsubishi Electric Corp | Shift register circuit and image display equipped therewith |
| JP5618821B2 (en) * | 2010-12-28 | 2014-11-05 | 株式会社ジャパンディスプレイ | Bidirectional shift register and image display apparatus using the same |
| KR101980753B1 (en) * | 2012-07-26 | 2019-05-21 | 엘지디스플레이 주식회사 | Shift register |
| CN102945651B (en) * | 2012-10-31 | 2015-02-25 | 京东方科技集团股份有限公司 | Shift register, grid driving circuit and display device |
| KR102072214B1 (en) * | 2013-07-09 | 2020-02-03 | 삼성디스플레이 주식회사 | Scan driver and display device comprising the same |
| TWI541779B (en) * | 2014-07-18 | 2016-07-11 | 友達光電股份有限公司 | Shift register and method of driving shift register |
| CN104318908A (en) * | 2014-10-22 | 2015-01-28 | 友达光电股份有限公司 | Gate drive circuit capable of enhancing circuit drive ability |
| CN104409054B (en) * | 2014-11-03 | 2017-02-15 | 深圳市华星光电技术有限公司 | Low temperature polycrystalline SiTFT GOA circuit |
| CN104318909B (en) * | 2014-11-12 | 2017-02-22 | 京东方科技集团股份有限公司 | Shift register unit, gate drive circuit, drive method thereof, and display panel |
| CN104537992B (en) * | 2014-12-30 | 2017-01-18 | 深圳市华星光电技术有限公司 | GOA circuit for liquid crystal display device |
-
2015
- 2015-12-17 CN CN201510954368.6A patent/CN105469760B/en active Active
-
2016
- 2016-01-28 US US14/913,991 patent/US9916805B2/en active Active
- 2016-01-28 WO PCT/CN2016/072428 patent/WO2017101200A1/en active Application Filing
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130077736A1 (en) * | 2011-09-23 | 2013-03-28 | Hydis Technologies Co., Ltd. | Shift Register and Driving Circuit Using the Same |
| US20140049712A1 (en) * | 2012-08-17 | 2014-02-20 | Hannstar Display Corporation | Liquid crystal display and bidirectional shift register device thereof |
| US20150187323A1 (en) * | 2013-12-30 | 2015-07-02 | Shanghai Avic Optoelectronics Co., Ltd. | Gate drive apparatus and display apparatus |
| US9190170B1 (en) * | 2014-06-18 | 2015-11-17 | Boe Technology Group Co., Ltd | Shift register unit, gate driving device, display panel and display device |
| US20160019976A1 (en) * | 2014-07-21 | 2016-01-21 | Au Optronics Corp. | Shift register and flat panel display using the same |
| US20160187917A1 (en) * | 2014-12-29 | 2016-06-30 | Shanghai Tianma Micro-electronics Co., Ltd. | Gate drive circuit, array substrate, display panel and display device |
| US20160189795A1 (en) * | 2014-12-30 | 2016-06-30 | Shanghai Avic Optoelectronics Co., Ltd | Shift register, method and system for operating shift register |
| CN104485079A (en) * | 2014-12-31 | 2015-04-01 | 深圳市华星光电技术有限公司 | GOA (Gate Driver On Array) circuit for liquid crystal display device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10403210B2 (en) * | 2016-03-16 | 2019-09-03 | Boe Technology Group Co., Ltd. | Shift register and driving method, driving circuit, array substrate and display device |
| US11315512B2 (en) * | 2020-02-12 | 2022-04-26 | Wuhan China Star Optoelectronics Technology Co., Ltd. | GOA circuit and display panel thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| US20180033389A1 (en) | 2018-02-01 |
| CN105469760A (en) | 2016-04-06 |
| WO2017101200A1 (en) | 2017-06-22 |
| CN105469760B (en) | 2017-12-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9916805B2 (en) | GOA circuit for LTPS-TFT | |
| US9875709B2 (en) | GOA circuit for LTPS-TFT | |
| US10043477B2 (en) | GOA circuit | |
| US10043473B2 (en) | GOA circuit | |
| US9922997B2 (en) | GOA circuit | |
| US10127875B2 (en) | Shift register unit, related gate driver and display apparatus, and method for driving the same | |
| US10019949B2 (en) | Shift register unit, gate driving circuit, display panel and display device | |
| US9922611B2 (en) | GOA circuit for narrow border LCD panel | |
| US10796656B1 (en) | GOA circuit | |
| US9875706B1 (en) | GOA circuit of reducing feed-through voltage | |
| US10497454B2 (en) | Shift register, operation method thereof, gate driving circuit and display device | |
| US9841620B2 (en) | GOA circuit based on LTPS semiconductor thin film transistor | |
| US20180268768A1 (en) | Gate driver on array driving circuit and lcd device | |
| US9837019B2 (en) | Pixel circuit, organic electroluminescent display panel and display device | |
| US10311783B2 (en) | Pixel circuit, method for driving the same, display panel and display device | |
| US10339870B2 (en) | GOA circuit | |
| US9972245B2 (en) | Pixel circuit, driving method for the pixel circuit, display panel, and display device | |
| US11107381B2 (en) | Shift register and method for driving the same, gate driving circuit and display device | |
| US10339871B2 (en) | Scan driving curcuit and display panel | |
| US20180218682A1 (en) | Goa circuit | |
| US20180218685A1 (en) | Goa circuit | |
| US10102820B2 (en) | GOA circuit | |
| US20190385552A1 (en) | Gate driving circuit and display device | |
| US10484655B2 (en) | Gate driving circuit and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| AS | Assignment |
Owner name: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., L Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LI, YAFENG;WU, JINFANG;REEL/FRAME:037805/0324 Effective date: 20160128 |
|
| STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
| MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 4 |