CN106297630B - Scan drive circuit and flat display apparatus with the circuit - Google Patents
Scan drive circuit and flat display apparatus with the circuit Download PDFInfo
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- CN106297630B CN106297630B CN201610704661.1A CN201610704661A CN106297630B CN 106297630 B CN106297630 B CN 106297630B CN 201610704661 A CN201610704661 A CN 201610704661A CN 106297630 B CN106297630 B CN 106297630B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The invention discloses a kind of scan drive circuit and flat display apparatus, scan drive circuit includes cascade multiple scan drive cells, each scan drive cell include it is positive and negative sweep circuit, receive first and second scan-control voltage, driving signal and junior's scanning drive signal and export forward and reverse control signal and scanned forward or backwards with controlling；Input circuit receives the first clock signal and forward and reverse control signal and exports input signal；Pull-down circuit receives input signal and the first clock signal and exports pulldown signal and drop-down control signaling point is pulled down or charged；Control circuit receives input signal and charges to pull-up control signaling point, or receives pulldown signal and pull down to pull-up control signaling point；Output circuit, receives second clock signal and generates scanning drive signal and export to scan line and drive pixel unit, and the circuit of simplified flat display apparatus is realized with this, saves space, and then be conducive to the narrow frame design of flat display apparatus.
Description
Technical field
The present invention relates to field of display technology, aobvious more particularly to a kind of scan drive circuit and plane with the circuit
Showing device.
Background technique
Scan drive circuit is used in current flat display apparatus, that is, is shown using existing thin film transistor (TFT) plane
Scan drive circuit is produced in array substrate by device array process, realizes the driving method to progressive scan.Existing plane
Each scan drive cell only drives a scan line in display device, and each scan drive cell is required to setting clock and believes
Number selection circuit selects different clock signals, all multi-strip scanning lines is arranged in general plane display device, this sets needs
Many scan drive cells are counted, is bound to so that complex circuit designs, and occupied space, is unfavorable for the narrow frame of flat display apparatus
Design.
Summary of the invention
The invention mainly solves the technical problem of providing a kind of scan drive circuits and plane with the circuit to show
Device saves space, and then be conducive to the narrow frame design of flat display apparatus to simplify the circuit of flat display apparatus.
In order to solve the above technical problems, one technical scheme adopted by the invention is that: a kind of scan drive circuit, institute are provided
Stating scan drive circuit includes cascade multiple scan drive cells, and each scan drive cell includes:
It is positive and negative to sweep circuit, it is swept for receiving the first scan-control voltage, the second scan-control voltage, driving signal and junior
It retouches driving signal and exports forward and reverse control signal and carry out forward scan or reverse scan to control the scan drive circuit；
Input circuit, for receiving the first clock signal and receiving forward and reverse control signal from the positive and negative circuit of sweeping
And export input signal；
Pull-down circuit, for receiving the input signal and first clock signal and exporting pulldown signal and to drop-down
Control signaling point is pulled down or is charged；
Control circuit, for receiving the input signal from the input circuit and being controlled according to the input signal to pull-up
Signaling point processed charges, or receives the pulldown signal and according to the pulldown signal on described from the pull-down circuit
Control signaling point is drawn to be pulled down；And
Output circuit, it is defeated for receiving second clock signal and generating scanning drive signal according to the second clock signal
Pixel unit is driven to scan line out；
The pull-down circuit includes the 4th to the 8th controllable switch and first and second capacitor, the 4th controllable switch
Control terminal connects the second end of the 5th controllable switch, the first end of the 7th controllable switch and the 8th controllable switch
Control terminal, the first end of the 4th controllable switch connects the first end of the 5th controllable switch and the described 8th controllably opens
The first end of pass, which simultaneously receives, closes voltage end signal, and the second end of the 4th controllable switch connects the input circuit, described
The control terminal and the control circuit of the control terminal of 5th controllable switch, the 6th controllable switch, the 6th controllable switch
First end receive the closing voltage end signal, the second end of the 6th controllable switch connects the 7th controllable switch
The first end of control terminal and the first capacitor, the second end of the first capacitor receive first clock signal, and described the
The second end of seven controllable switches connects the control circuit and receives cut-in voltage end signal, and the second of the 8th controllable switch
End connects the output circuit, and second capacitance connection is between the control terminal and first end of the 8th controllable switch；Or
The pull-down circuit includes the 4th to the 8th controllable switch and first and second capacitor, the 4th controllable switch
Control terminal connects the second end of the 5th controllable switch, the first end of the 7th controllable switch and the 8th controllable switch
Control terminal, the first end of the 4th controllable switch connects the first end of the 5th controllable switch and the described 8th controllably opens
The first end of pass, which simultaneously receives, closes voltage end signal, and the second end of the 4th controllable switch connects the input circuit, described
The control terminal and the control circuit of the control terminal of 5th controllable switch, the 6th controllable switch, the 6th controllable switch
First end receive the closing voltage end signal, the second end of the 6th controllable switch connects the 7th controllable switch
The first end of control terminal and the first capacitor, the second end of the first capacitor receive the second clock signal, and described the
The second end of seven controllable switches connects the control circuit and receives cut-in voltage end signal, and the second of the 8th controllable switch
End connects the output circuit, and second capacitance connection is between the control terminal and first end of the 8th controllable switch.
Wherein, the positive and negative circuit of sweeping includes first and second controllable switch, the control termination of first controllable switch
Receive first scan-control voltage, the first end of first controllable switch connect second controllable switch first end and
The second end of the input circuit, first controllable switch receives the driving signal, the control of second controllable switch
End receives second scan-control voltage, and second end connection junior's scan line of second controllable switch is swept with receiving junior
Retouch driving signal.
Wherein, the input circuit includes third controllable switch, and the control terminal of the third controllable switch receives described the
One clock signal, the first end of the third controllable switch connect the second end of the 4th controllable switch, and the third is controllable
The second end of switch connects the first end of first and second controllable switch.
Wherein, the control circuit includes the 9th controllable switch, the control terminal connection described the of the 9th controllable switch
The second end of seven controllable switches simultaneously receives the cut-in voltage end signal, the first end of the 9th controllable switch connection described the
The control terminal of six controllable switches, the control terminal of the 5th controllable switch, the second end of the 4th controllable switch and described
The second end of the first end of three controllable switches, the 9th controllable switch connects the output circuit.
Wherein, the output circuit includes the tenth controllable switch and third capacitor, the control terminal of the tenth controllable switch
The second end of the 9th controllable switch is connected, the first end of the tenth controllable switch connects the scan line and the described 8th
The second end of controllable switch, the second end of the tenth controllable switch receive the second clock signal, and the third capacitor connects
It connects between the control terminal and first end of the tenth controllable switch.
Wherein, the described first to the tenth controllable switch is N-type TFT, the control of the described first to the tenth controllable switch
End, first end and second end processed respectively correspond grid, drain electrode and the source electrode of the N-type TFT.
Wherein, the described first to the tenth controllable switch is P-type TFT, the control of the described first to the tenth controllable switch
End, first end and second end processed respectively correspond grid, drain electrode and the source electrode of the P-type TFT.
In order to solve the above technical problems, another technical solution used in the present invention is: a kind of flat display apparatus is provided,
The flat display apparatus includes any of the above-described scan drive circuit.
The beneficial effects of the present invention are: being in contrast to the prior art, scan drive circuit of the invention passes through positive and negative
It sweeps circuit to be scanned forward or backwards, is charged, passed through to pull-up control signaling point by input circuit and control circuit
Pull-down circuit to drop-down control signaling point carry out drop-down and by output circuit generate scanning drive signal export to scan line come
Pixel unit is driven, two clock signals are used only in the present invention, the circuit of simplified flat display apparatus is realized with this, save
Save space, and then it is conducive to the narrow frame design of flat display apparatus.
Detailed description of the invention
Fig. 1 is the circuit diagram of a scan drive cell of scan drive circuit in the prior art；
Fig. 2 is the forward scan working timing figure of the scan drive cell of Fig. 1；
Fig. 3 is the reverse scan working timing figure of the scan drive cell of Fig. 1；
Fig. 4 is the driving configuration diagram of the scan drive circuit of the prior art；
Fig. 5 is the circuit diagram of the first embodiment of a scan drive cell of scan drive circuit of the invention；
Fig. 6 is the forward scan working timing figure of the scan drive cell of Fig. 5；
Fig. 7 is the reverse scan working timing figure of the scan drive cell of Fig. 5；
Fig. 8 is the circuit diagram of the second embodiment of a scan drive cell of scan drive circuit of the invention；
Fig. 9 is the forward scan working timing figure of the scan drive cell of Fig. 8；
Figure 10 is the reverse scan working timing figure of the scan drive cell of Fig. 8；
Figure 11 and Figure 12 is the simulation waveform timing diagram of scan drive cell of the invention；
Figure 13 is the driving configuration diagram of scan drive circuit of the invention；
Figure 14 is the 3rd embodiment of a scan drive cell of scan drive circuit of the invention
Circuit diagram；
Figure 15 is the fourth embodiment of a scan drive cell of scan drive circuit of the invention
Circuit diagram；
Figure 16 is the structural schematic diagram of flat display apparatus of the invention.
Specific embodiment
Referring to Fig. 1, being provided with several scan lines in flat display apparatus in the prior art, also just need to correspond to these
Corresponding scan drive cell is arranged in scan line, and existing each scan drive cell only drives a scan line, often sweeps
Retouch driving unit include it is positive and negative sweep circuit 10, input circuit 20, pull-down circuit 30, control circuit 40 and output circuit 50, and
Each scan drive cell is required to four clock signals of setting, this complex circuit designs that will make in flat display apparatus.
It is the forward scan working timing figure of scan drive cell in the prior art please continue to refer to Fig. 2, Fig. 2.Wherein, when the first scanning
When control voltage U2D is high level and the second scan-control voltage D2U is low level, transistor T1 and T3 conducting, turntable driving
Circuit is in forward scanning state, when the high level of clock signal CK1 come it is interim, driving signal STV by transistor T1, T5 and
T9 charges to pull-up control signaling point Q, and pull-up control signaling point Q is charged to high level, and capacitor C1 maintains high level；Together
When, transistor T7 conducting realizes that the drop-down to drop-down control signaling point P controls, and capacitor C2 maintains low level；At this point, transistor
T6 and T11 is in off state.When the high level of clock signal CK3 comes temporarily, scan line Gate1 exports high level signal, i.e.,
Produce the scanning drive signal of the same level.After clock signal CK3 becomes low level, the high level signal of clock signal CK4 comes
Face；At this point, transistor T8 is connected, drop-down control signaling point P is charged to high level, and capacitor C2 maintains high level；Later, transistor
T6 and T11 conducting, pull-up control signaling point Q are pulled down to low level, and the output signal of scan line Gate1 is pulled down to low electricity
Flat, entire circuit is in stable state.
Referring to Fig. 3, Fig. 3 is the reverse scan working timing figure of scan drive cell in the prior art.Wherein, when first
When scan-control voltage U2D is low level and the second scan-control voltage D2U is high level, transistor T2 and T4 conducting, scanning
Driving circuit is in reverse scan state, and when the high level of clock signal CK1 comes temporarily, junior scanning drive signal Gate3 is logical
It crosses transistor T2, T5 and T9 to charge to pull-up control signaling point Q, pull-up control signaling point Q is charged to high level, capacitor C1
Maintain high level；Meanwhile transistor T7 is connected, and realizes that the drop-down to drop-down control signaling point P controls, capacitor C2 maintains low electricity
It is flat；At this point, transistor T6 and T11 are in off state.When the high level of clock signal CK3 carrys out interim, scan line Gate1 output
High level signal produces the scanning drive signal of the same level.After clock signal CK3 becomes low level, clock signal CK2's
High level signal arrives；At this point, transistor T8 is connected, drop-down control signaling point P is charged to high level, and capacitor C2 maintains high electricity
It is flat；Later, transistor T6 and T11 conducting, pull-up control signaling point Q are pulled down to low level, the output signal of scan line Gate1
It is pulled down to low level, entire circuit is in stable state, and the working principle of remaining scan drive circuit is same as described above, herein
It repeats no more.Referring to Fig. 4, be the driving configuration diagram of the scan drive cell of the prior art, figure 4, it is seen that
The two sides of flat display apparatus are arranged in the scan drive cell, using interleaved driving method, each of every side
Scan drive cell is required to using four clock signal CK1-CK4, this will be so that complex circuit designs, occupied space be unfavorable
In the narrow frame design of flat display apparatus.
Referring to Fig. 5, being the circuit of the first embodiment of a scan drive cell of scan drive circuit of the invention
Figure.In the present embodiment, it is only illustrated by taking a scan drive cell as an example.As shown in figure 5, turntable driving of the invention
Circuit includes cascade multiple scan drive cells, and each scan drive cell includes:
It is positive and negative to sweep circuit 100, for receive the first scan-control voltage, the second scan-control voltage, driving signal and under
Grade scanning drive signal simultaneously exports forward and reverse control signal and carries out forward scan or reversely to control the scan drive circuit
Scanning；
Input circuit 200, for receiving the first clock signal and receiving forward and reverse control from the positive and negative circuit 100 of sweeping
Signal processed simultaneously exports input signal；
Pull-down circuit 300, for receiving the input signal and first clock signal and exporting pulldown signal and right
Drop-down control signaling point is pulled down or is charged；
Control circuit 400, for receiving the input signal from the input circuit 200 and according to the input signal pair
Pull-up control signaling point charges, or receives the pulldown signal from the pull-down circuit 300 and believed according to the drop-down
Number to the pull-up control signaling point pull down；And
Output circuit 500, for receiving second clock signal and generating turntable driving letter according to the second clock signal
Number output drives pixel unit to scan line.
Specifically, the positive and negative circuit 100 of sweeping includes first and second controllable switch T1, T2, first controllable switch
The control terminal of T1 receives the first scan-control voltage U2D, the first end connection described second of the first controllable switch T1
The second end of controllable switch T2 and the input circuit 200, the second end of the first controllable switch T1 receive the driving letter
The control terminal of number STV, the second controllable switch T2 receive the second scan-control voltage D2U, second controllable switch
The second end of T2 receives junior's scanning drive signal.
The input circuit 200 includes third controllable switch T3, described in the control terminal of the third controllable switch T3 receives
The first end of first clock signal, the third controllable switch T3 connects the pull-down circuit 300, the third controllable switch T3
Second end connect the first end of the first controllable switch T1 and the first end of the second controllable switch T2.
The pull-down circuit 300 includes the 4th to the 8th controllable switch T4-T8 and first and second capacitor C1-C2, described
The control terminal of 4th controllable switch T4 connect the second end of the 5th controllable switch T5, the 7th controllable switch T7 first
The first end of the control terminal of end and the 8th controllable switch T8, the 4th controllable switch T4 connects the 5th controllable switch
The first end of T5 and the first end of the 8th controllable switch T8 simultaneously receive closing voltage end signal VGL, and the described 4th controllably opens
The second end for closing T4 connects the first end of the third controllable switch T3, the control terminal of the 5th controllable switch T5, described the
The first end of the control terminal and the control circuit 400 of six controllable switch T6, the 6th controllable switch T6 receives the closing
Voltage end signal VGL, the second end of the 6th controllable switch T6 connect the control terminal of the 7th controllable switch T7 and described
The second end of the first end of first capacitor C1, the first capacitor C1 receives first clock signal, and the described 7th controllably opens
The second end for closing T7 connects the control circuit 400 and simultaneously receives cut-in voltage end signal VGH, and the of the 8th controllable switch T8
Two ends connect the output circuit 500, and the second capacitor C2 is connected to the control terminal and first of the 8th controllable switch T8
Between end.
The control circuit 400 include the 9th controllable switch T9, the 9th controllable switch T9 control terminal connection described in
The second end of 7th controllable switch T7 simultaneously receives the cut-in voltage end signal VGH, the first end of the 9th controllable switch T9
Connect control terminal, the control terminal of the 5th controllable switch T5, the 4th controllable switch T4 of the 6th controllable switch T6
Second end and the third controllable switch T3 first end, it is electric that the second end of the 9th controllable switch T9 connects the output
Road 500.
The output circuit 500 includes the tenth controllable switch T10 and third capacitor C3, the tenth controllable switch T10's
Control terminal connects the second end of the 9th controllable switch T9, and the first end of the tenth controllable switch T10 connects the scanning
The second end of line and the 8th controllable switch T8, the second end of the tenth controllable switch T10 receive the second clock letter
Number, the third capacitor C3 is connected between the control terminal and first end of the tenth controllable switch T10.
In the present embodiment, the described first to the tenth controllable switch T1-T10 is N-type TFT, described first to the
Control terminal, first end and the second end of ten controllable switch T1-T10 respectively correspond the N-type TFT grid, drain electrode and
Source electrode.In other embodiments, the described first to the tenth controllable switch can also be other kinds of switch, as long as being able to achieve this hair
Bright purpose.
In the present embodiment, first clock signal is the first clock signal CK1, and the second clock signal is second
Clock signal CK3, first scan-control voltage are the first scan-control voltage U2D, and second scan-control voltage is
Second scan-control voltage D2U, the pull-up control signaling point are pull-up control signaling point Q1, and the drop-down control signaling point is
Drop-down control signaling point P1, the driving signal are driving signal STV, and the scan line is scan line Gate1, and the junior sweeps
Retouching line is junior's scan line Gate3.
Referring to Fig. 6, being the forward scan working timing figure of the first embodiment of scan drive cell of the present invention.According to figure
The working principle of the 6 available scan drive cells is as follows: with a scan drive cell, (such as first order scanning is driven below
Moving cell) for be illustrated.When the first scan-control voltage U2D is high level and second scan-control voltage
When D2U is low level, the scan drive cell is in forward scanning state, and the first controllable switch T1 conducting, second controllably opens
T2 cut-off is closed, when the high level of driving signal STV and the first clock signal CK1 come interim, third controllable switch T3 conducting, pull-up
Control signaling point Q1 is charged to high level；5th controllable switch T5 and the 6th controllable switch T6 conducting, drop-down control signaling point P1
Low level, the 4th controllable switch T4 and the 8th controllable switch T8 cut-off are pulled low to H1.When the height electricity of second clock signal CK3
Ordinary mail number comes interim, scan line Gate1 output high level signal, the i.e. scanning drive signal of the generation first order.Later second when
Clock signal CK3 is low level, and when the first clock signal CK1 rising edge comes temporarily, pull-up control signaling point Q1 is pulled low to low electricity
Flat, the 5th controllable switch T5 and the 6th controllable switch T6 cut-off, drop-down control signaling point H1 point are in suspended state.At this point, the
The rising edge of one clock signal CK1 will cause the bootstrap effect of first capacitor C3, and drop-down control signaling point H1 can be booted supreme
Level, the 7th controllable switch T7 conducting, drop-down control signaling point P1 be charged to high level, later, the 4th controllable switch T4 and
8th controllable switch T8 conducting, pull-up control signaling point Q1 and scan line Gate1 stablize output low level signal.
Referring to Fig. 7, being the reverse scan working timing figure of the first embodiment of scan drive cell of the present invention.According to figure
The working principle of the 7 available scan drive cells is as follows: with a scan drive cell, (such as first order scanning is driven below
Moving cell) for be illustrated.When the first scan-control voltage U2D is low level and second scan-control voltage
When D2U is high level, the scan drive cell is in reverse scan state, and the first controllable switch T1 cut-off, second controllably opens
T2 conducting is closed, when the high level of junior scanning drive signal Gate3 and the first clock signal CK1 carry out interim, third controllable switch
T3 conducting, pull-up control signaling point Q1 are charged to high level；5th controllable switch T5 and the 6th controllable switch T6 conducting, drop-down control
Signaling point P1 and H1 processed is pulled low to low level, the 4th controllable switch T4 and the 8th controllable switch T8 cut-off.When second clock is believed
The high level signal of number CK3 comes interim, and scan line Gate1 exports high level signal, that is, generates the scanning drive signal of the first order.
Second clock signal CK3 is low level later, when the first clock signal CK1 rising edge carrys out interim, pull-up control signaling point Q1 quilt
It is pulled low to low level, the 5th controllable switch T5 and the 6th controllable switch T6 cut-off, drop-down control signaling point H1 point is in suspension
State.At this point, the rising edge of the first clock signal CK1 will cause the bootstrap effect of first capacitor C3, drop-down control signaling point H1 meeting
It is booted to high level, the 7th controllable switch T7 conducting, drop-down control signaling point P1 is charged to high level, and later, the 4th can
Switch T4 and the 8th controllable switch T8 conducting is controlled, pull-up control signaling point Q1 and scan line Gate1 stablizes output low level signal.
The working principle of remaining scan drive cell is same as described above, and details are not described herein.
Referring to Fig. 8, being the circuit of the second embodiment of a scan drive cell of scan drive circuit of the invention
Figure.It is in place of the second embodiment of the scan drive cell and the difference of the first embodiment of above-mentioned scan drive cell:
The pull-down circuit 300 includes the 4th to the 8th controllable switch T4-T8 and first and second capacitor C1-C2, and the described 4th is controllable
The control terminal of switch T4 connects the second end of the 5th controllable switch T5, the first end of the 7th controllable switch T7 and described
The first end of the control terminal of 8th controllable switch T8, the 4th controllable switch T4 connects the first of the 5th controllable switch T5
The first end of end and the 8th controllable switch T8 simultaneously receive and close voltage end signal VGL, and the of the 4th controllable switch T4
Two ends connect the first end of the third controllable switch T3, the control terminal of the 5th controllable switch T5, the described 6th controllably open
The control terminal and the control circuit 400 of T6 are closed, the first end of the 6th controllable switch T6 receives the closing voltage end letter
Number VGL, the second end of the 6th controllable switch T6 connect the control terminal and the first capacitor of the 7th controllable switch T7
The first end of C1, the second end of the first capacitor C1 receive the second clock signal, and the of the 7th controllable switch T7
Two ends connect the control circuit 400 and receive cut-in voltage end signal VGH, the second end connection of the 8th controllable switch T8
The output circuit 500, the second capacitor C2 are connected between the control terminal and first end of the 8th controllable switch T8.
Referring to Fig. 9, being the forward scan working timing figure of the second embodiment of scan drive cell of the invention.According to
The working principle of the available scan drive cell of Fig. 9 is as follows: with a scan drive cell, (such as the first order is scanned below
Driving unit) for be illustrated.When the first scan-control voltage U2D is high level and the second scan-control voltage D2U is low
When level, the scan drive cell is in forward scanning state, the first controllable switch T1 conducting, and the second controllable switch T2 is cut
Only, when the high level of driving signal STV and the first clock signal CK1 come interim, third controllable switch T3 conducting, pull-up control letter
Number point Q1 is charged to high level, the 5th controllable switch T5 and the 6th controllable switch T6 conducting, drop-down control signaling point P1 and H1 quilt
It is pulled low to low level, the 4th controllable switch T4 and the 8th controllable switch T8 cut-off.When the high level signal of second clock signal CK3
Come interim, scan line Gate1 output high level signal, the i.e. scanning drive signal of the generation first order.Second clock signal later
CK3 is low level, and when the rising edge of the first clock signal CK1 comes temporarily, pull-up control signaling point Q1 is pulled low to low level, the
Five controllable switch T5 and the 6th controllable switch T6 cut-off, drop-down control signaling point H1 are in suspended state, drop-down control signaling point
P1 continues to low level signal.When the rising edge of next second clock signal CK3 come it is interim, first capacitor C1 booted to
High level, the 7th controllable switch T7 conducting, drop-down control signaling point P1 are charged to high level.Later, the 4th controllable switch T4
It is connected with the 8th controllable switch T8, pull-up control signaling point Q1 and scan line Gate1 stablizes output low level signal.
Referring to Fig. 10, being the reverse scan working timing figure of the second embodiment of scan drive cell of the invention.Root
Working principle according to the available scan drive cell of Figure 10 is as follows: below with a scan drive cell (such as first order
Scan drive cell) for be illustrated.When the first scan-control voltage U2D is low level and the second scan-control voltage D2U
When for high level, the scan drive cell is in reverse scan state, the first controllable switch T1 cut-off, the second controllable switch T2
Conducting, when the high level of junior scan line Gate3 and the first clock signal CK1 come interim, third controllable switch T3 conducting, pull-up
Control signaling point Q1 is charged to high level, the 5th controllable switch T5 and the 6th controllable switch T6 conducting, drop-down control signaling point P1
Low level, the 4th controllable switch T4 and the 8th controllable switch T8 cut-off are pulled low to H1.When the height electricity of second clock signal CK3
Ordinary mail number comes interim, scan line Gate1 output high level signal, the i.e. scanning drive signal of the generation first order.Later second when
Clock signal CK3 is low level, and when the rising edge of the first clock signal CK1 comes temporarily, pull-up control signaling point Q1 is pulled low to low
Level, the 5th controllable switch T5 and the 6th controllable switch T6 cut-off, drop-down control signaling point H1 are in suspended state, drop-down control
Signaling point P1 continues to low level signal.When the rising edge of next second clock signal CK3 carrys out interim, first capacitor C1 quilt
Bootstrapping to high level, the 7th controllable switch T7 conducting, drop-down controls signaling point P1 and is charged to high level.Later, the 4th is controllable
Switch T4 and the 8th controllable switch T8 conducting, pull-up control signaling point Q1 and scan line Gate1 stablize output low level signal.Its
The working principle of remaining scan drive cell is same as described above, and details are not described herein.
Figure 11 to Figure 13 is please referred to, is the simulation waveform timing diagram and scan drive circuit of scan drive cell of the invention
Driving configuration diagram.Can be seen that from Figure 11 and Figure 12 the function of scan drive circuit of the invention and the consistent of description and
It also can be carried out good work in the intercaste biography of multistage.As can be seen from Figure 13, each scan drive cell on the left side is by first
Clock signal CK1 and second clock signal CK3 are operated alone, and each scan drive cell on the right is by third clock signal
CK2 and the 4th clock signal CK4 are operated alone, and the flat display apparatus uses interleaved driving method, certainly
Scan drive circuit provided by the invention can also be used for double drives driving of panel.
Figure 14 is please referred to, is the circuit of the 3rd embodiment of a scan drive cell of scan drive circuit of the invention
Figure.The 3rd embodiment of the scan drive cell is in the difference of the first embodiment of scan drive cell described above
In: the described first to the tenth controllable switch T1-T10 is P-type TFT, the described first to the tenth controllable switch T1-T10's
Control terminal, first end and second end respectively correspond grid, drain electrode and the source electrode of the P-type TFT.In other embodiments
In, the described first to the tenth controllable switch can also be other kinds of switch, as long as being able to achieve the purpose of the present invention.
Figure 15 is please referred to, is the circuit of the fourth embodiment of a scan drive cell of scan drive circuit of the invention
Figure.The fourth embodiment of the scan drive cell is in the difference of the second embodiment of scan drive cell described above
In: the described first to the tenth controllable switch T1-T10 is P-type TFT, the described first to the tenth controllable switch T1-T10's
Control terminal, first end and second end respectively correspond grid, drain electrode and the source electrode of the P-type TFT.In other embodiments
In, the described first to the tenth controllable switch can also be other kinds of switch, as long as being able to achieve the purpose of the present invention.
Figure 16 is please referred to, for a kind of schematic diagram of flat display apparatus of the present invention.The flat display apparatus includes aforementioned
Scan drive circuit, the two sides of the flat display apparatus are arranged in the scan drive circuit.The flat display apparatus
In other devices and function it is identical as the device of existing flat display apparatus and function, details are not described herein.Wherein, described flat
Flat-panel display device is LCD or OLED.
Scan drive circuit of the invention is scanned forward or backwards by positive and negative circuit of sweeping, and passes through input circuit and control
Circuit processed charges to pull-up control signaling point, is pulled down and passed through output to drop-down control signaling point by pull-down circuit
Circuit generation scanning drive signal, which is exported to scan line, drives pixel unit, and two clock signals are used only in the present invention and are
Can, the circuit of simplified flat display apparatus is realized with this, saves space, and then be conducive to the narrow frame design of flat display apparatus.
Mode the above is only the implementation of the present invention is not intended to limit the scope of the invention, all to utilize this
Equivalent structure or equivalent flow shift made by description of the invention and accompanying drawing content, it is relevant to be applied directly or indirectly in other
Technical field is included within the scope of the present invention.
Claims (8)
1. a kind of scan drive circuit, which is characterized in that the scan drive circuit includes cascade multiple scan drive cells,
Each scan drive cell includes:
It is positive and negative to sweep circuit, it is driven for receiving the first scan-control voltage, the second scan-control voltage, driving signal and junior's scanning
Dynamic signal simultaneously exports forward and reverse control signal to control the scan drive circuit progress forward scan or reverse scan；
Input circuit, for receiving the first clock signal and receiving forward and reverse control signal and defeated from the positive and negative circuit of sweeping
Input signal out；
Pull-down circuit, for receive the input signal and first clock signal and export pulldown signal and to drop-down control
Signaling point is pulled down or is charged；
Control circuit, for receiving the input signal and according to the input signal to pull-up control letter from the input circuit
Number point charges, or receives the pulldown signal from the pull-down circuit and controlled according to the pulldown signal to the pull-up
Signaling point processed is pulled down；And
Output circuit, for receive second clock signal and according to the second clock signal generate scanning drive signal export to
Scan line drives pixel unit；
The pull-down circuit includes the 4th to the 8th controllable switch and first and second capacitor, the control of the 4th controllable switch
End connects second end, the first end of the 7th controllable switch and the control of the 8th controllable switch of the 5th controllable switch
End processed, the first end of the 4th controllable switch connect the 5th controllable switch first end and the 8th controllable switch
First end simultaneously receives closing voltage end signal, and the second end of the 4th controllable switch connects the input circuit, the described 5th
The control terminal and the control circuit of the control terminal of controllable switch, the 6th controllable switch, the of the 6th controllable switch
One end receives the closing voltage end signal, and the second end of the 6th controllable switch connects the control of the 7th controllable switch
The second end of the first end of end and the first capacitor, the first capacitor receives first clock signal, and the described 7th can
The second end of control switch connects the control circuit and receives cut-in voltage end signal, and the second end of the 8th controllable switch connects
The output circuit is connect, second capacitance connection is between the control terminal and first end of the 8th controllable switch；Or
The pull-down circuit includes the 4th to the 8th controllable switch and first and second capacitor, the control of the 4th controllable switch
End connects second end, the first end of the 7th controllable switch and the control of the 8th controllable switch of the 5th controllable switch
End processed, the first end of the 4th controllable switch connect the 5th controllable switch first end and the 8th controllable switch
First end simultaneously receives closing voltage end signal, and the second end of the 4th controllable switch connects the input circuit, the described 5th
The control terminal and the control circuit of the control terminal of controllable switch, the 6th controllable switch, the of the 6th controllable switch
One end receives the closing voltage end signal, and the second end of the 6th controllable switch connects the control of the 7th controllable switch
The second end of the first end of end and the first capacitor, the first capacitor receives the second clock signal, and the described 7th can
The second end of control switch connects the control circuit and receives cut-in voltage end signal, and the second end of the 8th controllable switch connects
The output circuit is connect, second capacitance connection is between the control terminal and first end of the 8th controllable switch.
2. scan drive circuit according to claim 1, which is characterized in that the positive and negative circuit of sweeping includes first and second
The control terminal of controllable switch, first controllable switch receives first scan-control voltage, first controllable switch
First end connects the first end of second controllable switch and the input circuit, the second end of first controllable switch receive
The control terminal of the driving signal, second controllable switch receives second scan-control voltage, and described second controllably opens
Second end connection junior's scan line of pass is to receive junior's scanning drive signal.
3. scan drive circuit according to claim 2, which is characterized in that the input circuit includes that third is controllably opened
It closes, the control terminal of the third controllable switch receives first clock signal, the first end connection of the third controllable switch
The second end of 4th controllable switch, the second end of the third controllable switch connect first and second controllable switch
First end.
4. scan drive circuit according to claim 3, which is characterized in that the control circuit is controllably opened including the 9th
It closes, the control terminal of the 9th controllable switch connects the second end of the 7th controllable switch and receives the cut-in voltage end letter
Number, the first end of the 9th controllable switch connects the control of the control terminal, the 5th controllable switch of the 6th controllable switch
End, the second end of the 4th controllable switch and the first end of the third controllable switch processed, the of the 9th controllable switch
Two ends connect the output circuit.
5. scan drive circuit according to claim 4, which is characterized in that the output circuit includes the tenth controllable switch
And third capacitor, the control terminal of the tenth controllable switch connect the second end of the 9th controllable switch, the described tenth is controllable
The first end of switch connects the second end of the scan line and the 8th controllable switch, the second end of the tenth controllable switch
The second clock signal is received, the third capacitance connection is between the control terminal and first end of the tenth controllable switch.
6. scan drive circuit according to claim 5, which is characterized in that the described first to the tenth controllable switch is N-type
Thin film transistor (TFT), it is brilliant that control terminal, first end and the second end of the described first to the tenth controllable switch respectively correspond the N-type film
Grid, drain electrode and the source electrode of body pipe.
7. scan drive circuit according to claim 5, which is characterized in that the described first to the tenth controllable switch is p-type
Thin film transistor (TFT), it is brilliant that control terminal, first end and the second end of the described first to the tenth controllable switch respectively correspond the p-type film
Grid, drain electrode and the source electrode of body pipe.
8. a kind of flat display apparatus, which is characterized in that the flat display apparatus includes as claimed in claim 1
Scan drive circuit.
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| CN201610704661.1A CN106297630B (en) | 2016-08-22 | 2016-08-22 | Scan drive circuit and flat display apparatus with the circuit |
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| CN201610704661.1A CN106297630B (en) | 2016-08-22 | 2016-08-22 | Scan drive circuit and flat display apparatus with the circuit |
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20180081196A (en) * | 2017-01-05 | 2018-07-16 | 삼성디스플레이 주식회사 | Scan driver and display device including the same |
| US10839751B2 (en) | 2018-01-19 | 2020-11-17 | Kunshan Go-Visionox Opto-Electronics Co., Ltd. | Scan driving circuit, scan driver and display device |
| CN108447448B (en) * | 2018-01-19 | 2020-10-30 | 昆山国显光电有限公司 | Scanning drive circuit, scanning driver and display device |
| CN109243357B (en) * | 2018-11-12 | 2021-11-12 | 中国科学院微电子研究所 | Driving circuit and method for pixel scanning |
| CN113763865B (en) * | 2021-10-25 | 2023-10-13 | 福建华佳彩有限公司 | Novel gate driving circuit and application method thereof |
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| KR101641171B1 (en) * | 2010-02-17 | 2016-07-21 | 삼성디스플레이 주식회사 | Gate driving circuit and display device having the gate driving circuit |
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| CN103474017A (en) * | 2013-09-12 | 2013-12-25 | 北京京东方光电科技有限公司 | Shift register unit, gate drive circuit and display device |
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