CN106297630A - Scan drive circuit and there is the flat display apparatus of this circuit - Google Patents
Scan drive circuit and there is the flat display apparatus of this circuit Download PDFInfo
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- CN106297630A CN106297630A CN201610704661.1A CN201610704661A CN106297630A CN 106297630 A CN106297630 A CN 106297630A CN 201610704661 A CN201610704661 A CN 201610704661A CN 106297630 A CN106297630 A CN 106297630A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The invention discloses a kind of scan drive circuit and flat display apparatus, scan drive circuit includes multiple scan drive cells of cascade, each scan drive cell includes positive and negative sweeping circuit, receives first and second scan-control voltage, drives signal and subordinate's scanning drive signal and export forward and reverse control signal to control to scan forward or backwards；Input circuit, receives the first clock signal and forward and reverse control signal and exports input signal；Pull-down circuit, receives input signal and the first clock signal and exports pulldown signal and drop-down control signal point carries out drop-down or charging；Control circuit, receives input signal and is charged pull-up control signal point, or receive pulldown signal and carry out drop-down to pull-up control signal point；Output circuit, receives second clock signal and produces scanning drive signal and export to scan line to drive pixel cell, the circuit realizing simplifying flat display apparatus with this, saves space, and then the narrow frame design of beneficially flat display apparatus.
Description
Technical field
The present invention relates to Display Technique field, particularly relate to a kind of scan drive circuit and have this circuit plane show
Showing device.
Background technology
Current flat display apparatus uses scan drive circuit, namely utilizes existing thin film transistor (TFT) plane to show
Scan drive circuit is produced on array base palte by device array process, it is achieved the type of drive to progressive scan.Existing plane
In display device, each scan drive cell only drives a scan line, and each scan drive cell is required to arrange clock letter
Number selection circuit selects different clock signals, arranges all a plurality of scan lines in general closed planar display device, and needs are set by this
Count many scan drive cells, complex circuit designs certainly will be made, and take up room, be unfavorable for the narrow frame of flat display apparatus
Design.
Summary of the invention
The technical problem that present invention mainly solves is to provide a kind of scan drive circuit and has the plane of this circuit and show
Device, to simplify the circuit of flat display apparatus, saves space, and then the narrow frame design of beneficially flat display apparatus.
For solving above-mentioned technical problem, the technical scheme that the present invention uses is: provide a kind of scan drive circuit, institute
Stating scan drive circuit and include multiple scan drive cells of cascade, each described scan drive cell includes:
Positive and negative sweep circuit, for receiving the first scan-control voltage, the second scan-control voltage, driving signal and subordinate to sweep
Retouch to drive signal and export forward and reverse control signal and carry out forward scan or reverse scan to control described scan drive circuit；
Input circuit, for receiving the first clock signal and receiving described forward and reverse control signal from described positive and negative circuit of sweeping
And export input signal；
Pull-down circuit, is used for receiving described input signal and described first clock signal and exporting pulldown signal and to drop-down
Control signal point carries out drop-down or charging；
Control circuit, for receiving described input signal and according to described input signal to pull-up control from described input circuit
Signaling point processed is charged, or receives described pulldown signal and according to described pulldown signal to described from described pull-down circuit
Control signal point is drawn to carry out drop-down；And
Output circuit, is used for receiving second clock signal and produces scanning drive signal according to described second clock signal defeated
Go out to scan line to drive pixel cell.
Wherein, described positive and negative circuit of sweeping includes first and second gate-controlled switch, the control termination of described first gate-controlled switch
Receive described first scan-control voltage, described first gate-controlled switch first end connect described second gate-controlled switch the second end and
Described input circuit, the second end of described first gate-controlled switch receives described driving signal, the control of described second gate-controlled switch
End receives described second scan-control voltage, and the second end of described second gate-controlled switch connects subordinate's scan line and sweeps to receive subordinate
Retouch driving signal.
Wherein, described input circuit includes the 3rd gate-controlled switch, and the control end of described 3rd gate-controlled switch receives described the
One clock signal, the first end of described 3rd gate-controlled switch connects described pull-down circuit, the second end of described 3rd gate-controlled switch
Connect the first end of first and second gate-controlled switch described.
Wherein, described pull-down circuit includes the 4th to the 8th gate-controlled switch and first and second electric capacity, described 4th controlled
The control end of switch connects the second end of described 5th gate-controlled switch, first end and the described 8th of described 7th gate-controlled switch can
The control end of control switch, the first end of described 4th gate-controlled switch connects first end and the described 8th of described 5th gate-controlled switch
First end of gate-controlled switch also receives closedown voltage end signal, and the second end of described 4th gate-controlled switch connects described 3rd controlled
First end of switch, control end, the control end of described 6th gate-controlled switch and the described control circuit of described 5th gate-controlled switch,
First end of described 6th gate-controlled switch receives described closedown voltage end signal, and the second end of described 6th gate-controlled switch connects institute
That states the 7th gate-controlled switch controls end and the first end of described first electric capacity, and the second end of described first electric capacity receives described first
Clock signal, the second end of described 7th gate-controlled switch connects described control circuit receive cut-in voltage end signal, and described the
Second end of eight gate-controlled switches connects described output circuit, and described second electric capacity is connected to the control end of described 8th gate-controlled switch
And between the first end.
Wherein, described pull-down circuit includes the 4th to the 8th gate-controlled switch and first and second electric capacity, described 4th controlled
The control end of switch connects the second end of described 5th gate-controlled switch, first end and the described 8th of described 7th gate-controlled switch can
The control end of control switch, the first end of described 4th gate-controlled switch connects first end and the described 8th of described 5th gate-controlled switch
First end of gate-controlled switch also receives closedown voltage end signal, and the second end of described 4th gate-controlled switch connects described 3rd controlled
First end of switch, control end, the control end of described 6th gate-controlled switch and the described control circuit of described 5th gate-controlled switch,
First end of described 6th gate-controlled switch receives described closedown voltage end signal, and the second end of described 6th gate-controlled switch connects institute
That states the 7th gate-controlled switch controls end and the first end of described first electric capacity, and the second end of described first electric capacity receives described second
Clock signal, the second end of described 7th gate-controlled switch connects described control circuit receive cut-in voltage end signal, and described the
Second end of eight gate-controlled switches connects described output circuit, and described second electric capacity is connected to the control end of described 8th gate-controlled switch
And between the first end.
Wherein, described control circuit includes the 9th gate-controlled switch, and the control end of described 9th gate-controlled switch connects described the
Second end of seven gate-controlled switches also receives described cut-in voltage end signal, and the first end of described 9th gate-controlled switch connects described the
Six gate-controlled switches control end, described 5th gate-controlled switch control end, the second end of described 4th gate-controlled switch and described the
First end of three gate-controlled switches, the second end of described 9th gate-controlled switch connects described output circuit.
Wherein, described output circuit includes the tenth gate-controlled switch and the 3rd electric capacity, the control end of described tenth gate-controlled switch
Connecting the second end of described 9th gate-controlled switch, the first end of described tenth gate-controlled switch connects described scan line and the described 8th
Second end of gate-controlled switch, the second end of described tenth gate-controlled switch receives described second clock signal, and described 3rd electric capacity is even
It is connected between control end and first end of described tenth gate-controlled switch.
Wherein, described first to the tenth gate-controlled switch is N-type TFT, the control of described first to the tenth gate-controlled switch
Grid, drain electrode and the source electrode of end processed, the first end and the second end corresponding described N-type TFT respectively.
Wherein, described first to the tenth gate-controlled switch is P-type TFT, the control of described first to the tenth gate-controlled switch
Grid, drain electrode and the source electrode of end processed, the first end and the second end corresponding described P-type TFT respectively.
For solving above-mentioned technical problem, another technical solution used in the present invention is: provide a kind of flat display apparatus,
Described flat display apparatus includes any of the above-described described scan drive circuit.
The invention has the beneficial effects as follows: be different from the situation of prior art, the scan drive circuit of the present invention is by positive and negative
Sweep circuit to scan forward or backwards, by input circuit and control circuit, pull-up control signal point is charged, passes through
Drop-down control signal point is carried out drop-down and exports to come to scan line by output circuit generation scanning drive signal by pull-down circuit
Drive pixel cell, the present invention only uses two clock signals, the circuit realizing simplifying flat display apparatus with this, joint
Save space, and then the narrow frame design of beneficially flat display apparatus.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of a scan drive cell of scan drive circuit in prior art；
Fig. 2 is the forward scan working timing figure of the scan drive cell of Fig. 1；
Fig. 3 is the reverse scan working timing figure of the scan drive cell of Fig. 1；
Fig. 4 is the driving configuration diagram of the scan drive circuit of prior art；
Fig. 5 is the circuit diagram of the first embodiment of a scan drive cell of the scan drive circuit of the present invention；
Fig. 6 is the forward scan working timing figure of the scan drive cell of Fig. 5；
Fig. 7 is the reverse scan working timing figure of the scan drive cell of Fig. 5；
Fig. 8 is the circuit diagram of the second embodiment of a scan drive cell of the scan drive circuit of the present invention；
Fig. 9 is the forward scan working timing figure of the scan drive cell of Fig. 8；
Figure 10 is the reverse scan working timing figure of the scan drive cell of Fig. 8；
Figure 11 and Figure 12 is the simulation waveform sequential chart of the scan drive cell of the present invention；
Figure 13 is the driving configuration diagram of the scan drive circuit of the present invention；
Figure 14 is the 3rd embodiment of a scan drive cell of the scan drive circuit of the present invention
Circuit diagram；
Figure 15 is the 4th embodiment of a scan drive cell of the scan drive circuit of the present invention
Circuit diagram；
Figure 16 is the structural representation of the flat display apparatus of the present invention.
Detailed description of the invention
Refer to Fig. 1, prior art midplane display device be provided with some scan lines, be also accomplished by corresponding these
Scan line arranges corresponding scan drive cell, and existing each scan drive cell only drives a scan line, often sweeps
Retouch driver element and include positive and negative circuit 10, input circuit 20, pull-down circuit 30, control circuit 40 and the output circuit 50 swept, and
Each scan drive cell is required to arrange four clock signals, and this will make the complex circuit designs in flat display apparatus.
Please continue to refer to the forward scan working timing figure that Fig. 2, Fig. 2 are scan drive cell in prior art.Wherein, when the first scanning
Controlling voltage U2D and be high level and time the second scan-control voltage D2U is low level, transistor T1 and T3 turns on, turntable driving
Circuit is in forward scan state, when the high level of clock signal CK1 comes interim, drive signal STV by transistor T1, T5 and
Pull-up control signal point Q is charged by T9, and pull-up control signal point Q is charged to high level, and electric capacity C1 maintains high level；With
Time, transistor T7 turns on, it is achieved the drop-down control to drop-down control signal point P, electric capacity C2 maintains low level；Now, transistor
T6 and T11 is in cut-off state.When the high level of clock signal CK3 comes interim, scan line Gate1 output high level signal, i.e.
Create the scanning drive signal of this grade.After clock signal CK3 becomes low level, the high level signal of clock signal CK4 comes
Face；Now, transistor T8 turns on, and drop-down control signal point P is charged to high level, and electric capacity C2 maintains high level；Afterwards, transistor
T6 and T11 turns on, and pull-up control signal point Q is pulled down to low level, and the output signal of scan line Gate1 is pulled down to low electricity
Flat, whole circuit is in steady statue.
Refer to the reverse scan working timing figure that Fig. 3, Fig. 3 are scan drive cell in prior art.Wherein, when first
Scan-control voltage U2D is low level and time the second scan-control voltage D2U is high level, and transistor T2 and T4 turns on, scanning
Drive circuit is in reverse scan state, when the high level of clock signal CK1 comes interim, and subordinate's scanning drive signal Gate3 is led to
Crossing transistor T2, T5 and T9 to be charged pull-up control signal point Q, pull-up control signal point Q is charged to high level, electric capacity C1
Maintain high level；Meanwhile, transistor T7 conducting, it is achieved the drop-down control to drop-down control signal point P, electric capacity C2 maintains low electricity
Flat；Now, transistor T6 and T11 is in cut-off state.When the high level of clock signal CK3 comes interim, and scan line Gate1 exports
High level signal, i.e. creates the scanning drive signal of this grade.After clock signal CK3 becomes low level, clock signal CK2
High level signal arrives；Now, transistor T8 turns on, and drop-down control signal point P is charged to high level, and electric capacity C2 maintains high electricity
Flat；Afterwards, transistor T6 and T11 turns on, and pull-up control signal point Q is pulled down to low level, the output signal of scan line Gate1
Being pulled down to low level, whole circuit is in steady statue, and the operation principle of remaining scan drive circuit is same as described above, at this
Repeat no more.Refer to Fig. 4, be the driving configuration diagram of the scan drive cell of prior art, figure 4, it is seen that
Described scan drive cell is arranged on the both sides of flat display apparatus, uses interleaved type of drive, every side each
Scan drive cell is required to use four clock signals CK1-CK4, and this will make complex circuit designs, and take up room, unfavorable
Narrow frame design in flat display apparatus.
Refer to Fig. 5, be the circuit of the first embodiment of a scan drive cell of the scan drive circuit of the present invention
Figure.In the present embodiment, only illustrate as a example by a scan drive cell.As it is shown in figure 5, the turntable driving of the present invention
Circuit includes multiple scan drive cells of cascade, and each described scan drive cell includes:
Positive and negative sweep circuit 100, for receive the first scan-control voltage, the second scan-control voltage, drive signal and under
Level scanning drive signal also exports forward and reverse control signal and carries out forward scan or reversely to control described scan drive circuit
Scanning；
Input circuit 200, for receiving the first clock signal and receiving described forward and reverse control from described positive and negative circuit 100 of sweeping
Signal processed also exports input signal；
Pull-down circuit 300, is used for receiving described input signal and described first clock signal and exports pulldown signal and right
Drop-down control signal point carries out drop-down or charging；
Control circuit 400, for receiving described input signal and according to described input signal pair from described input circuit 200
Pull-up control signal point is charged, or receives described pulldown signal and according to described drop-down letter from described pull-down circuit 300
Number described pull-up control signal point is carried out drop-down；And
Output circuit 500, is used for receiving second clock signal and producing turntable driving letter according to described second clock signal
Number output drives pixel cell to scan line.
Specifically, described positive and negative circuit 100 of sweeping includes first and second gate-controlled switch T1, T2, described first gate-controlled switch
The control end of T1 receives first end of described first scan-control voltage U2D, described first gate-controlled switch T1 and connects described second
Second end of gate-controlled switch T2 and described input circuit 200, second end of described first gate-controlled switch T1 receives described driving to be believed
The control end of number STV, described second gate-controlled switch T2 receives described second scan-control voltage D2U, described second gate-controlled switch
Second end of T2 receives described subordinate scanning drive signal.
It is described that described input circuit 200 includes that the control end of the 3rd gate-controlled switch T3, described 3rd gate-controlled switch T3 receives
First clock signal, first end of described 3rd gate-controlled switch T3 connects described pull-down circuit 300, described 3rd gate-controlled switch T3
The second end connect first end of described first gate-controlled switch T1 and first end of the second gate-controlled switch T2.
Described pull-down circuit 300 includes the 4th to the 8th gate-controlled switch T4-T8 and first and second electric capacity C1-C2, described
4th gate-controlled switch T4 control end connect second end of described 5th gate-controlled switch T5, the first of described 7th gate-controlled switch T7
End and the control end of described 8th gate-controlled switch T8, first end of described 4th gate-controlled switch T4 connects described 5th gate-controlled switch
First end of T5 and first end of described 8th gate-controlled switch T8 also receive closedown voltage end signal VGL, and the described 4th controlled opens
Close second end of T4 connect first end of described 3rd gate-controlled switch T3, the control end of described 5th gate-controlled switch T5, described the
The control end of six gate-controlled switch T6 and described control circuit 400, first end of described 6th gate-controlled switch T6 receives described closedown
Second end of voltage end signal VGL, described 6th gate-controlled switch T6 connects the control end of described 7th gate-controlled switch T7 and described
First end of the first electric capacity C1, second end of described first electric capacity C1 receives described first clock signal, and the described 7th controlled opens
The second end closing T7 connects described control circuit 400 receive cut-in voltage end signal VGH, the of described 8th gate-controlled switch T8
Two ends connect described output circuit 500, and described second electric capacity C2 is connected to the control end and first of described 8th gate-controlled switch T8
Between end.
It is described that described control circuit 400 includes that the control end of the 9th gate-controlled switch T9, described 9th gate-controlled switch T9 connects
Second end of the 7th gate-controlled switch T7 also receives described cut-in voltage end signal VGH, first end of described 9th gate-controlled switch T9
Connect described 6th gate-controlled switch T6 controls end, the control end of described 5th gate-controlled switch T5, described 4th gate-controlled switch T4
The second end and first end of described 3rd gate-controlled switch T3, described 9th gate-controlled switch T9 second end connect described output electricity
Road 500.
Described output circuit 500 includes the tenth gate-controlled switch T10 and the 3rd electric capacity C3, described tenth gate-controlled switch T10's
Controlling the second end that end connects described 9th gate-controlled switch T9, first end of described tenth gate-controlled switch T10 connects described scanning
Line and second end of described 8th gate-controlled switch T8, second end of described tenth gate-controlled switch T10 receives described second clock letter
Number, described 3rd electric capacity C3 is connected between control end and first end of described tenth gate-controlled switch T10.
In the present embodiment, described first to the tenth gate-controlled switch T1-T10 is N-type TFT, described first to
Ten gate-controlled switch T1-T10 control end, the first end and the second end grid of corresponding described N-type TFT respectively, drain electrode and
Source electrode.In other embodiments, described first to the tenth gate-controlled switch is alternatively other kinds of switch, as long as this can be realized
Bright purpose.
In the present embodiment, described first clock signal is the first clock signal CK1, and described second clock signal is second
Clock signal CK3, described first scan-control voltage is the first scan-control voltage U2D, and described second scan-control voltage is
Second scan-control voltage D2U, described pull-up control signal point is pull-up control signal point Q1, and described drop-down control signal point is
Drop-down control signal point P1, described driving signal is for driving signal STV, and described scan line is scan line Gate1, and described subordinate sweeps
Retouching line is subordinate's scan line Gate3.
Refer to Fig. 6, be the forward scan working timing figure of the first embodiment of scan drive cell of the present invention.According to figure
6 can to obtain the operation principle of described scan drive cell as follows: below with a scan drive cell (as first order scanning is driven
Moving cell) as a example by illustrate.When described first scan-control voltage U2D is high level and described second scan-control voltage
When D2U is low level, described scan drive cell is in forward scan state, the first gate-controlled switch T1 conducting, and second controlled opens
Close T2 cut-off, when the high level driving signal STV and the first clock signal CK1 comes interim, the 3rd gate-controlled switch T3 conducting, pull-up
Control signal point Q1 is charged to high level；5th gate-controlled switch T5 and the 6th gate-controlled switch T6 conducting, drop-down control signal point P1
It is pulled low to low level, the 4th gate-controlled switch T4 and the 8th gate-controlled switch T8 cut-off with H1.High electricity as second clock signal CK3
Ordinary mail number comes interim, scan line Gate1 output high level signal, i.e. produces the scanning drive signal of the first order.Afterwards second time
Clock signal CK3 is low level, when the first clock signal CK1 rising edge comes interim, and pull-up control signal point Q1 is pulled low to low electricity
Flat, the 5th gate-controlled switch T5 and the 6th gate-controlled switch T6 cut-off, drop-down control signal point H1 point is in suspended state.Now,
The rising edge of one clock signal CK1 can cause the bootstrap effect of the first electric capacity C3, and drop-down control signal point H1 can be paramount by bootstrapping
Level, the 7th gate-controlled switch T7 conducting, drop-down control signal point P1 is charged to high level, afterwards, the 4th gate-controlled switch T4 and
8th gate-controlled switch T8 conducting, pull-up control signal point Q1 and scan line Gate1 stablize output low level signal.
Refer to Fig. 7, be the reverse scan working timing figure of the first embodiment of scan drive cell of the present invention.According to figure
7 can to obtain the operation principle of described scan drive cell as follows: below with a scan drive cell (as first order scanning is driven
Moving cell) as a example by illustrate.When described first scan-control voltage U2D is low level and described second scan-control voltage
When D2U is high level, described scan drive cell is in reverse scan state, the first gate-controlled switch T1 cut-off, and second controlled opens
Close T2 conducting, when the high level of subordinate's scanning drive signal Gate3 and the first clock signal CK1 comes interim, the 3rd gate-controlled switch
T3 turns on, and pull-up control signal point Q1 is charged to high level；5th gate-controlled switch T5 and the 6th gate-controlled switch T6 conducting, drop-down control
Signaling point P1 and H1 processed is pulled low to low level, the 4th gate-controlled switch T4 and the 8th gate-controlled switch T8 cut-off.When second clock is believed
The high level signal of number CK3 comes interim, scan line Gate1 output high level signal, i.e. produces the scanning drive signal of the first order.
Second clock signal CK3 is low level afterwards, when the first clock signal CK1 rising edge comes interim, pulls up control signal point Q1 quilt
Being pulled low to low level, the 5th gate-controlled switch T5 and the 6th gate-controlled switch T6 cut-off, drop-down control signal point H1 point is in suspension
State.Now, the rising edge of the first clock signal CK1 can cause the bootstrap effect of the first electric capacity C3, drop-down control signal point H1 meeting
By bootstrapping to high level, the 7th gate-controlled switch T7 conducting, drop-down control signal point P1 is charged to high level, and afterwards, the 4th can
Control switch T4 and the 8th gate-controlled switch T8 conducting, pull-up control signal point Q1 and scan line Gate1 stablize output low level signal.
The operation principle of remaining scan drive cell is same as described above, does not repeats them here.
Refer to Fig. 8, be the circuit of the second embodiment of a scan drive cell of the scan drive circuit of the present invention
Figure.Second embodiment of described scan drive cell is in place of the difference of the first embodiment of above-mentioned scan drive cell:
Described pull-down circuit 300 includes the 4th to the 8th gate-controlled switch T4-T8 and first and second electric capacity C1-C2, described 4th controlled
The end that controls of switch T4 connects second end of described 5th gate-controlled switch T5, first end of described 7th gate-controlled switch T7 and described
The control end of the 8th gate-controlled switch T8, first end of described 4th gate-controlled switch T4 connects the first of described 5th gate-controlled switch T5
End and first end of described 8th gate-controlled switch T8 also receive and close the of voltage end signal VGL, described 4th gate-controlled switch T4
Two ends connect first ends of described 3rd gate-controlled switch T3, the control end of described 5th gate-controlled switch T5, the described 6th controlled open
Closing control end and the described control circuit 400 of T6, first end of described 6th gate-controlled switch T6 receives described closedown voltage end letter
Second end of number VGL, described 6th gate-controlled switch T6 connects the control end of described 7th gate-controlled switch T7 and described first electric capacity
First end of C1, second end of described first electric capacity C1 receives described second clock signal, the of described 7th gate-controlled switch T7
Two ends connect described control circuit 400 and receive cut-in voltage end signal VGH, and second end of described 8th gate-controlled switch T8 connects
Described output circuit 500, described second electric capacity C2 is connected between control end and first end of described 8th gate-controlled switch T8.
Refer to Fig. 9, be the forward scan working timing figure of the second embodiment of the scan drive cell of the present invention.According to
The operation principle that Fig. 9 can obtain described scan drive cell is as follows: below with a scan drive cell (as the first order scans
Driver element) as a example by illustrate.When the first scan-control voltage U2D is high level and the second scan-control voltage D2U is low
During level, described scan drive cell is in forward scan state, and the first gate-controlled switch T1 conducting, the second gate-controlled switch T2 cuts
Only, when the high level driving signal STV and the first clock signal CK1 comes interim, the 3rd gate-controlled switch T3 conducting, pull-up controls letter
Number some Q1 is charged to high level, the 5th gate-controlled switch T5 and the 6th gate-controlled switch T6 conducting, drop-down control signal point P1 and H1 quilt
It is pulled low to low level, the 4th gate-controlled switch T4 and the 8th gate-controlled switch T8 cut-off.High level signal as second clock signal CK3
Come interim, scan line Gate1 output high level signal, i.e. produce the scanning drive signal of the first order.Second clock signal afterwards
CK3 is low level, when the rising edge of the first clock signal CK1 comes interim, and pull-up control signal point Q1 is pulled low to low level, the
Five gate-controlled switch T5 and the 6th gate-controlled switch T6 cut-off, drop-down control signal point H1 is in suspended state, drop-down control signal point
P1 continues to low level signal.When the rising edge of next second clock signal CK3 comes interim, the first electric capacity C1 booted to
High level, the 7th gate-controlled switch T7 conducting, drop-down control signal point P1 is charged to high level.Afterwards, the 4th gate-controlled switch T4
With the 8th gate-controlled switch T8 conducting, pull-up control signal point Q1 and scan line Gate1 stablize output low level signal.
Refer to Figure 10, be the forward scan working timing figure of the second embodiment of the scan drive cell of the present invention.Root
The operation principle that can obtain described scan drive cell according to Figure 10 is as follows: below with a scan drive cell (such as the first order
Scan drive cell) as a example by illustrate.When the first scan-control voltage U2D is low level and the second scan-control voltage D2U
During for high level, described scan drive cell is in reverse scan state, the first gate-controlled switch T1 cut-off, the second gate-controlled switch T2
Conducting, when the high level of subordinate's scan line Gate3 and the first clock signal CK1 comes interim, the 3rd gate-controlled switch T3 conducting, pull-up
Control signal point Q1 is charged to high level, the 5th gate-controlled switch T5 and the 6th gate-controlled switch T6 conducting, drop-down control signal point P1
It is pulled low to low level, the 4th gate-controlled switch T4 and the 8th gate-controlled switch T8 cut-off with H1.High electricity as second clock signal CK3
Ordinary mail number comes interim, scan line Gate1 output high level signal, i.e. produces the scanning drive signal of the first order.Afterwards second time
Clock signal CK3 is low level, when the rising edge of the first clock signal CK1 comes interim, and pull-up control signal point Q1 is pulled low to low
Level, the 5th gate-controlled switch T5 and the 6th gate-controlled switch T6 cut-off, drop-down control signal point H1 is in suspended state, drop-down control
Signaling point P1 continues to low level signal.When the rising edge of next second clock signal CK3 comes interim, the first electric capacity C1 quilt
Bootstrapping is to high level, and the 7th gate-controlled switch T7 conducting, drop-down control signal point P1 is charged to high level.Afterwards, the 4th is controlled
Switch T4 and the 8th gate-controlled switch T8 conducting, pull-up control signal point Q1 and scan line Gate1 stablize output low level signal.Its
The operation principle of remaining scan drive cell is same as described above, does not repeats them here.
Refer to Figure 11 to Figure 13, be simulation waveform sequential chart and the scan drive circuit of the scan drive cell of the present invention
Driving configuration diagram.Can be seen that from Figure 11 and Figure 12 the function of scan drive circuit of the present invention and the consistent of description and
Pass at multistage intercaste and also can well work.As can be seen from Figure 13, each scan drive cell on the left side is by first
Clock signal CK1 and second clock signal CK3 are operated alone, and each scan drive cell on the right is by the 3rd clock signal
CK2 and the 4th clock signal CK4 are operated alone, and described flat display apparatus uses interleaved type of drive, certainly
The scan drive circuit that the present invention provides can also be used for double drivings of panel.
Refer to Figure 14, be the circuit of the 3rd embodiment of a scan drive cell of the scan drive circuit of the present invention
Figure.3rd embodiment of described scan drive cell is in the difference of the first embodiment of scan drive cell described above
In: described first to the tenth gate-controlled switch T1-T10 is P-type TFT, described first to the tenth gate-controlled switch T1-T10's
Control grid, drain electrode and the source electrode of end, the first end and the second end corresponding described P-type TFT respectively.In other embodiments
In, described first to the tenth gate-controlled switch is alternatively other kinds of switch, as long as the purpose of the present invention can be realized.
Refer to Figure 15, be the circuit of the 4th embodiment of a scan drive cell of the scan drive circuit of the present invention
Figure.4th embodiment of described scan drive cell is in the difference of the second embodiment of scan drive cell described above
In: described first to the tenth gate-controlled switch T1-T10 is P-type TFT, described first to the tenth gate-controlled switch T1-T10's
Control grid, drain electrode and the source electrode of end, the first end and the second end corresponding described P-type TFT respectively.In other embodiments
In, described first to the tenth gate-controlled switch is alternatively other kinds of switch, as long as the purpose of the present invention can be realized.
Refer to Figure 16, for the schematic diagram of a kind of flat display apparatus of the present invention.Described flat display apparatus includes aforementioned
Scan drive circuit, described scan drive circuit is arranged on the both sides of described flat display apparatus.Described flat display apparatus
In other devices and function identical with the device of existing flat display apparatus and function, do not repeat them here.Wherein, described flat
Flat-panel display device is LCD or OLED.
The scan drive circuit of the present invention is scanned, by input circuit and control forward or backwards by positive and negative circuit of sweeping
Pull-up control signal point is charged by circuit processed, carries out drop-down by pull-down circuit to drop-down control signal point and passes through output
Circuit produces scanning drive signal and exports to scan line to drive pixel cell, only uses two clock signals i.e. in the present invention
Can, the circuit realizing simplifying flat display apparatus with this, save space, and then the narrow frame design of beneficially flat display apparatus.
The foregoing is only embodiments of the present invention, not thereby limit the scope of the claims of the present invention, every utilization is originally
Equivalent structure or equivalence flow process that description of the invention and accompanying drawing content are made convert, or are directly or indirectly used in what other were correlated with
Technical field, is the most in like manner included in the scope of patent protection of the present invention.
Claims (10)
1. a scan drive circuit, it is characterised in that described scan drive circuit includes multiple scan drive cells of cascade,
Each described scan drive cell includes:
Positive and negative sweep circuit, for receiving the first scan-control voltage, the second scan-control voltage, driving signal and subordinate's scanning to drive
Dynamic signal also exports forward and reverse control signal and carries out forward scan or reverse scan to control described scan drive circuit；
Input circuit, for receiving the first clock signal and receiving described forward and reverse control signal defeated from described positive and negative circuit of sweeping
Go out input signal；
Pull-down circuit, is used for receiving described input signal and described first clock signal and exporting pulldown signal and to drop-down control
Signaling point carries out drop-down or charging；
Control circuit, for receiving described input signal from described input circuit and according to described input signal, pull-up being controlled letter
Number point is charged, or receives described pulldown signal and according to described pulldown signal to described pull-up control from described pull-down circuit
Signaling point processed carries out drop-down；And
Output circuit, be used for receiving second clock signal and according to described second clock signal produce scanning drive signal export to
Scan line drives pixel cell.
Scan drive circuit the most according to claim 1, it is characterised in that described positive and negative circuit of sweeping includes first and second
Gate-controlled switch, the control end of described first gate-controlled switch receives described first scan-control voltage, described first gate-controlled switch
First end connects the second end of described second gate-controlled switch and described input circuit, and the second end of described first gate-controlled switch receives
Described driving signal, the control end of described second gate-controlled switch receives described second scan-control voltage, and described second controlled opens
The second end closed connects subordinate's scan line to receive subordinate's scanning drive signal.
Scan drive circuit the most according to claim 2, it is characterised in that described input circuit includes that the 3rd controlled opens
Closing, the control end of described 3rd gate-controlled switch receives described first clock signal, and the first end of described 3rd gate-controlled switch connects
Described pull-down circuit, the second end of described 3rd gate-controlled switch connects the first end of first and second gate-controlled switch described.
Scan drive circuit the most according to claim 3, it is characterised in that described pull-down circuit includes that the 4th can to the 8th
Control switch and first and second electric capacity, described 4th gate-controlled switch control end connect described 5th gate-controlled switch the second end,
First end of described 7th gate-controlled switch and the control end of described 8th gate-controlled switch, the first end of described 4th gate-controlled switch is even
Connect the first end of described 5th gate-controlled switch and the first end of described 8th gate-controlled switch and receive closedown voltage end signal, described
Second end of the 4th gate-controlled switch connects the first end of described 3rd gate-controlled switch, the control end of described 5th gate-controlled switch, institute
Stating the control end of the 6th gate-controlled switch and described control circuit, the first end of described 6th gate-controlled switch receives described closedown voltage
End signal, what the second end of described 6th gate-controlled switch connected described 7th gate-controlled switch controls the of end and described first electric capacity
One end, the second end of described first electric capacity receives described first clock signal, and the second end of described 7th gate-controlled switch connects institute
Stating control circuit and receive cut-in voltage end signal, the second end of described 8th gate-controlled switch connects described output circuit, described
Second electric capacity is connected between control end and first end of described 8th gate-controlled switch.
Scan drive circuit the most according to claim 3, it is characterised in that described pull-down circuit includes that the 4th can to the 8th
Control switch and first and second electric capacity, described 4th gate-controlled switch control end connect described 5th gate-controlled switch the second end,
First end of described 7th gate-controlled switch and the control end of described 8th gate-controlled switch, the first end of described 4th gate-controlled switch is even
Connect the first end of described 5th gate-controlled switch and the first end of described 8th gate-controlled switch and receive closedown voltage end signal, described
Second end of the 4th gate-controlled switch connects the first end of described 3rd gate-controlled switch, the control end of described 5th gate-controlled switch, institute
Stating the control end of the 6th gate-controlled switch and described control circuit, the first end of described 6th gate-controlled switch receives described closedown voltage
End signal, what the second end of described 6th gate-controlled switch connected described 7th gate-controlled switch controls the of end and described first electric capacity
One end, the second end of described first electric capacity receives described second clock signal, and the second end of described 7th gate-controlled switch connects institute
Stating control circuit and receive cut-in voltage end signal, the second end of described 8th gate-controlled switch connects described output circuit, described
Second electric capacity is connected between control end and first end of described 8th gate-controlled switch.
6. according to the scan drive circuit described in claim 4 or 5, it is characterised in that described control circuit includes that the 9th is controlled
Switch, the end that controls of described 9th gate-controlled switch connects the second end of described 7th gate-controlled switch and receives described cut-in voltage end
Signal, what the first end of described 9th gate-controlled switch connected described 6th gate-controlled switch controls end, described 5th gate-controlled switch
Control end, the second end of described 4th gate-controlled switch and the first end of described 3rd gate-controlled switch, described 9th gate-controlled switch
Second end connects described output circuit.
Scan drive circuit the most according to claim 6, it is characterised in that described output circuit includes the tenth gate-controlled switch
And the 3rd electric capacity, the end that controls of described tenth gate-controlled switch connects the second end of described 9th gate-controlled switch, described tenth controlled
First end of switch connects described scan line and the second end of described 8th gate-controlled switch, the second end of described tenth gate-controlled switch
Receiving described second clock signal, described 3rd electric capacity is connected between control end and first end of described tenth gate-controlled switch.
Scan drive circuit the most according to claim 7, it is characterised in that described first to the tenth gate-controlled switch is N-type
Thin film transistor (TFT), the control end of described first to the tenth gate-controlled switch, the first end and the second end corresponding described N-type thin film respectively is brilliant
The grid of body pipe, drain electrode and source electrode.
Scan drive circuit the most according to claim 7, it is characterised in that described first to the tenth gate-controlled switch is p-type
Thin film transistor (TFT), the control end of described first to the tenth gate-controlled switch, the first end and the second end corresponding described p-type thin film respectively is brilliant
The grid of body pipe, drain electrode and source electrode.
10. a flat display apparatus, it is characterised in that described flat display apparatus includes as described in claim 1-9 is arbitrary
Scan drive circuit.
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| CN201610704661.1A CN106297630B (en) | 2016-08-22 | 2016-08-22 | Scan drive circuit and flat display apparatus with the circuit |
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| CN201610704661.1A CN106297630B (en) | 2016-08-22 | 2016-08-22 | Scan drive circuit and flat display apparatus with the circuit |
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| US10839751B2 (en) | 2018-01-19 | 2020-11-17 | Kunshan Go-Visionox Opto-Electronics Co., Ltd. | Scan driving circuit, scan driver and display device |
| CN113763865A (en) * | 2021-10-25 | 2021-12-07 | 福建华佳彩有限公司 | Novel gate driving circuit and use method thereof |
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| CN106297630B (en) | 2019-08-02 |
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