KR101980753B1 - Shift register - Google Patents

Abstract

The present invention relates to a shift register capable of changing the output order of stages, and includes a plurality of stages for sequentially outputting scan pulses and sequentially supplying the scan pulses to a plurality of gate lines; The nth (n is a natural number) stage is controlled in accordance with a scan pulse from a first start pulse or npth (p is a natural number smaller than n) stage, and is connected between a forward power supply line for transmitting a forward voltage and a set node A forward control switching element; And a reverse control switching element connected between the set node and a reverse power supply line for transmitting a reverse voltage, the reverse control switching element being controlled according to a scan pulse from a second start pulse or an (n + q) th (n is a natural number) .

Description

SHIFT REGISTER {SHIFT REGISTER}

The present invention relates to a shift register, and more particularly to a shift register capable of changing the output order of stages.

A conventional liquid crystal display device displays an image by adjusting the light transmittance of a liquid crystal using an electric field. To this end, a liquid crystal display device includes a liquid crystal panel in which pixel regions are arranged in a matrix form, and a driving circuit for driving the liquid crystal panel.

In the liquid crystal panel, a plurality of gate lines and a plurality of data lines are arranged in an intersecting manner, and a pixel region is located in an area defined by vertically intersecting the gate lines and the data lines. Pixel electrodes and a common electrode for applying an electric field to each of the pixel regions are formed on the liquid crystal panel.

Each of the pixel electrodes is connected to the data line via a source terminal and a drain terminal of a thin film transistor (TFT) as a switching element. The thin film transistor is turned on by a scan pulse applied to a gate terminal via the gate line so that a data signal of the data line is charged to the pixel voltage.

The driving circuit includes a gate driver for driving the gate lines, a data driver for driving the data lines, a timing controller for supplying a control signal for controlling the gate driver and the data driver, And a power supply unit for supplying various driving voltages used in the plasma display apparatus.

The gate driver sequentially supplies scan pulses to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal panel by one line. Here, the gate driver includes a shift register for sequentially outputting the scan pulses as described above.

Conventional shift registers include a plurality of stages that sequentially output scan pulses. The stages output scan pulses in the order of the stages located in one direction, that is, the most upper stage to the lowermost stage. That is, the conventional shift register outputs the scan pulse in only one direction. Accordingly, the conventional shift register shows many problems to be used in various models of liquid crystal display devices.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a shift register capable of controlling the output order of scan pulses.

According to an aspect of the present invention, there is provided a shift register including a plurality of stages sequentially outputting scan pulses and sequentially supplying the scan pulses to a plurality of gate lines; The nth (n is a natural number) stage is controlled in accordance with a scan pulse from a first start pulse or npth (p is a natural number smaller than n) stage, and is connected between a forward power supply line for transmitting a forward voltage and a set node A forward control switching element; A reverse control switching element connected between the set node and a reverse power supply line for transmitting a reverse voltage, the reverse control switching element being controlled according to a scan pulse from a second start pulse or an (n + q) th (n is a natural number) stage; A first switching element connected between a reset node and a first discharging power supply line for transmitting a first discharging voltage, the first switching element being controlled according to a voltage of the set node; A second switching element controlled in accordance with the voltage of the reset node and connected between the set node and an output terminal of the nth stage; A pull-up switching element connected between the output terminal and one clock transmission line, which is controlled according to a voltage of the set node and transmits any one of a plurality of clock pulses having different phases; A pull-down switching element connected between the output terminal and a second discharging power supply line for transmitting a second discharging voltage, the pull-down switching element being controlled according to the voltage of the reset node; And a first capacitor connected between the one clock transmission line and the reset node; Wherein the forward voltage and the reverse voltage have phases opposite to each other; The clock pulses include forward clock pulses and reverse clock pulses; The forward clock pulses are supplied to all stages including the n-th stage when the forward voltage is in an active state; And the backward clock pulses are supplied to all stages including the n-th stage when the reverse voltage is in the active state.

And the first start pulse and the second start pulse are the same.

And the first discharge voltage is smaller than or equal to the second discharge voltage.

And the first discharge voltage is greater than or equal to the second discharge voltage.

The nth stage may further include a second capacitor connected between the set node and the output terminal.

The nth stage further includes a third switching element connected between the output terminal and a third discharging power line for transmitting a third discharging voltage, the third switching element being controlled according to any one of the clock pulses; A clock pulse supplied to the third switching device and a clock pulse supplied to the pull-up switching device are different from each other.

The nth stage further comprises a fourth switching element controlled according to any one of the clock pulses and connected between the output terminal and any one of the clock transmission lines; A clock pulse supplied to the gate electrode of the fourth switching element and a clock pulse supplied to the pull-up switching element are different from each other; A clock pulse supplied to the source electrode or the drain electrode of the fourth switching element and a clock pulse supplied to the pull-up switching element are equal to each other.

The nth stage further comprises a fifth switching element controlled according to the voltage of the output terminal and connected between the output terminal and any one of the clock transmission lines; A clock pulse supplied to the fifth switching element and a clock pulse supplied to the pull-up switching element are equal to each other.

The nth stage is controlled according to a scan pulse from an (n + r) th (r is a natural number) stage, and a sixth switch connected between the output terminal and a third discharge power supply line for transmitting a third discharge voltage Further comprising a device.

The nth stage may further include a seventh switching device connected between the output terminal and a third discharging power supply line for transmitting a third discharging voltage, the seventh switching device being controlled according to the voltage of the reset node, do.

The nth stage may further include an eighth switching element connected between the set node and a third discharging power line for transmitting a third discharging voltage, in accordance with a control signal from the outside .

The nth stage further comprises a ninth switching element controlled in accordance with a control signal from the outside and connected between the set node and any one of the clock transmission lines; A clock pulse supplied to the ninth switching element and a clock pulse supplied to the pull-up switching element are equal to each other.

And the control signal is any one of a first start pulse and a second start pulse.

And the ninth switching element is provided in each of the remaining stages except the stage to which the first start pulse or the second start pulse is supplied.

The odd-numbered stages of the plurality of stages being located at one side of the display portion; The even-numbered stages of the plurality of stages are located on the other side of the display unit.

And p and q are the same.

The shift register according to the present invention has the following effects.

The shift register in the present invention can change the output order of the stages through the forward control switching element and the reverse control switching element. Accordingly, the shift register according to the present invention can be applied to display devices of various models.

1 is a view showing a shift register according to an embodiment of the present invention;
FIG. 2A shows timing charts of output of various signals supplied to the shift register of FIG. 1 and various signals output therefrom during forward driving
FIG. 2B is a timing chart of various signals supplied to the shift register of FIG. 1 during reverse driving and various signals output therefrom
Fig. 3 is a diagram showing the configuration of the first embodiment for the n-th stage of Fig. 1
4 is a view showing the configuration of the second embodiment for the n-th stage of Fig. 1
5 is a diagram showing the configuration of the third embodiment for the n-th stage of Fig. 1
6 is a diagram showing the configuration of the fourth embodiment for the n-th stage of Fig. 1
7 is a view showing the configuration of the fifth embodiment for the n-th stage of Fig. 1
8 is a diagram showing the configuration of the sixth embodiment for the n-th stage of Fig. 1
9 is a diagram showing the configuration of the seventh embodiment for the n-th stage of Fig. 1
10 is a view showing a configuration of an eighth embodiment of the n-th stage of Fig. 1
11 is a view showing the configuration of the ninth embodiment of the n-th stage of Fig. 1
12A shows another output timing diagram of various signals supplied to the shift register of FIG. 1 and various signals output therefrom during forward driving. FIG.
12B shows another output timing diagram of various signals supplied to the shift register of FIG. 1 and various signals output therefrom during reverse driving
13 is a view illustrating a display panel to which a shift register according to the present invention is applied
14 is a diagram showing the configuration of stages provided in the first shift register and the second shift register of FIG. 13;

FIG. 1 is a diagram illustrating a shift register according to an embodiment of the present invention. FIG. 2 (a) is an output timing diagram of various signals supplied to the shift register of FIG. 1 and various signals output therefrom during forward driving, 1 is an output timing diagram of various signals supplied to the shift register of FIG. 1 and various signals output therefrom. FIG.

The shift register according to the present invention includes a plurality of stages ST_1 to ST_k, as shown in FIG. Here, each stage outputs one scan pulse (Vg_1 to Vg_k) for one frame period through each output terminal (OT).

Each of the stages ST_1 to ST_k drives a gate line connected thereto by using a scan pulse. The scan pulse output from each stage is also supplied to the stage located at the subsequent stage. In other words, each stage is controlled by the scan pulses from the stages located at the previous stage. For example, the second stage ST_2 is controlled by the scan pulse Vg_1 from the first stage ST_1. However, since there is no stage at the previous stage of the first stage (not shown), this first stage ST_1 is controlled by the start pulse Vst from the timing controller.

The stages ST_1 to ST_k sequentially output scan pulses from the first stage ST_1 or scan pulses sequentially from the kth stage ST_k.

Such a shift register can be incorporated in the liquid crystal panel. That is, the liquid crystal panel has a display portion for displaying an image and a non-display portion surrounding the display portion, and the shift register is embedded in the non-display portion.

The entire stage of the shift register constructed as described above is supplied with the forward voltage V_F, the reverse voltage V_R, and the discharge voltage (at least any one of the first through third discharge voltages) And one of the first to fourth clock pulses CLK_1 to CLK_4 which are circulated. On the other hand, the first stage ST_1 and the last (kth) stage ST_k of the stages are further supplied with the start pulse Vst.

The forward voltage V_F and the reverse voltage V_R are voltages for determining the driving direction of the shift register and are set so that any voltage is in an active state (for example, a high state) as shown in Figs. 2A and 2B, The other one of the voltages has an inactive state (for example, a low state). For example, as shown in FIG. 2A, the forward voltage V_F indicates a high state while the reverse voltage V_R indicates a low state. In addition, as shown in FIG. 2B, the forward voltage V_F indicates a low state while the reverse voltage V_R indicates a high state.

The forward voltage V_F and the reverse voltage V_R of the active state (e.g., high state) are used to charge the nodes of each stage. On the other hand, a forward voltage V_F and an inverse voltage V_R in an inactive state (e.g., a low state) and a discharging voltage are used to discharge the nodes of each stage and the output terminal OT.

The forward voltage V_F and the reverse voltage V_R in the active state can be set to positive voltages. On the other hand, a forward voltage V_F in an inactive state, an inverse voltage V_R in an inactive state, and a discharge voltage can be set to a negative voltage. Here, the discharge voltage is a constant voltage.

The first to fourth clock pulses CLK_1 to CLK_4 are used for the output operation of each stage. For example, when four-phase clock pulses are used as shown in FIG. 1, the 4x + 1th (x is a natural number including 0) stage receives a first clock pulse CLK_1 and outputs a 4x + And the (4x + 2) th stage receives the second clock pulse CLK_2 and outputs the 4x + 2 th scan pulse. The (4x + 3) th stage receives the third clock pulse CLK_3, And the 4x + 4th stage receives the fourth clock pulse CLK_4 and outputs the 4x + 4th scan pulse.

Each of the clock pulses CLK_1 to CLK_4 is output several times during one frame period, but the start pulse Vst is output only once during one frame period. In other words, each of the clock pulses CLK_1 to CLK_4 exhibits a plurality of active states (high state) periodically for one frame period, but the start pulse Vst shows only one active state for one frame period. This start pulse Vst is outputted first before any of the clock pulses CLK_1 to CLK_4 in one frame period.

During forward driving, as shown in FIG. 2A, the clock pulses CLK_1 to CLK_4 are output in the order of the first clock pulse CLK_1 to the fourth clock pulse CLK_4. 2B, the clock pulses CLK_1 to CLK_4 are output from the fourth clock pulse CLK_4 to the first clock pulse CLK_1 in the reverse direction.

Accordingly, as the first to fourth clock pulses CLK_1 to CLK_4 are outputted in the order as shown in FIG. 2A during forward driving, the sheet register that receives these clock pulses is the same as the one shown in FIG. 2A And outputs the scan pulses in the order (forward order). That is, the k stages provided in the shift register sequentially output the scan pulses Vg_1 to Vg_k from the first stage ST_1 to the kth stage ST_k.

On the other hand, as the first to fourth clock pulses CLK_1 to CLK_4 are outputted in the order as shown in FIG. 2B during the backward driving, the sheet register that receives these clock pulses has the same structure as shown in FIG. 2B And outputs scan pulses in the order (reverse order). That is, the k stages provided in the shift register sequentially output the scan pulses Vg_k to Vg_1 from the k-th stage ST_k to the first stage ST_1.

On the other hand, the first start pulse may always be supplied to the first stage ST_1, and the second start pulse may be supplied to the kth stage ST_k. At this time, at the time of forward driving, a first start pulse is generated at the start time of every frame period, and a second start pulse may be generated after every scan pulse is output once. On the other hand, at the time of the reverse driving, the first start pulse is generated after every scan pulse is output once, and the second start pulse may be generated at the start time of every frame period.

And, according to p at n-p, the first and second start pulses can be supplied to the first stage and the kth stage, as well as to a greater number of stages located at the previous stage and the latter stage.

The stage provided in the shift register of the present invention described above may have the following configuration.

3 is a diagram showing the configuration of the nth stage of the first embodiment shown in Fig.

3, the n-th stage includes a forward control switching element Tr_F, a reverse control switching element Tr_R, a first switching element Tr1, a second switching element Tr2, a pull-up switching element Pu ), A pull-down switching device (Pd), and a first capacitor (C1).

The forward control switching element Tr_F provided in the n-th stage (n is a natural number) is controlled according to the scan pulse from the (n-1) -th stage and is connected between the forward power line and the set node Q. That is, the forward control switching element Tr_F is turned on or off according to a scan pulse from the (n-1) -th stage, and connects the forward power supply line and the set node Q at turn-on. Here, the forward voltage V_F is supplied to the forward power line.

On the other hand, the forward control switching element Tr_F provided in the first stage ST_1 located at the uppermost position is turned on or off according to the start pulse Vst from the timing controller, and the turn- And connects the set node Q. On the other hand, the start pulse supplied to the forward control switching device Tr_F provided in the first stage ST_1 may be the above-described first start pulse.

The reverse control switching element Tr_R provided in the n-th stage is controlled according to the scan pulse from the (n + 1) -th stage and is connected between the set node Q and the reverse power supply line for transmitting the reverse voltage V_R . That is, the reverse-direction control switching element Tr_R is turned on or off according to the scan pulse from the (n + 1) -th stage, and connects the set node Q and the reverse power line to each other at the turn-on time. Here, the reverse voltage V_R is supplied to the reverse power line.

On the other hand, the reverse control switching element Tr_R provided in the k-th stage ST_k located at the lowermost position is turned on or off according to the start pulse Vst from the timing controller, And connects the set node Q. Here, the start pulse Vst supplied to the reverse control switching element Tr_R and the start pulse Vst supplied to the forward control switch element Tr_F may be different from each other. For example, the above-described first start pulse is used as the forward control switching element Tr_F of the first stage ST_1 and the above described second start pulse is used as the reverse control switching element Tr_R of the kth stage ST_k Can be supplied. The opposite is also possible.

The first switching element Tr1 provided in the nth stage is controlled according to the voltage of the set node Q and is connected between the reset node QB and the first discharging power supply line. That is, the first switching element Tr1 is turned on or off according to the voltage of the set node Q, and connects the reset node QB and the first discharge power supply line to each other. Here, the first discharge voltage VSS1 is supplied to the first discharge power line.

The second switching element Tr2 provided in the nth stage is controlled according to the voltage of the reset node QB and is connected between the set node Q and the output terminal OT of the nth stage. That is, the second switching device Tr2 is turned on or off according to the voltage of the reset node QB, and the set node Q and the output terminal OT of the nth stage at the turn- .

The pull-up switching element Pu provided in the n-th stage is controlled according to the voltage of the set node Q and is connected between any one of the clock transmission lines and the output terminal OT of the n-th stage. That is, the pull-up switching element Pu is turned on or off according to the voltage of the set node Q, and when one of the clock transmission lines and the output terminal OT of the n-th stage is turned on . Here, any one of a plurality of clock pulses having different phases is supplied to any one of the clock transmission lines. For example, the n < th > stage may be supplied with the A < th > clock pulse.

Here, the value of A is substantially the same as the value of n, but the value of A is influenced by the phase of the clock pulse. That is, when the value of A is less than or equal to the phase of the clock pulse, the value of A and the value of n are the same. However, if the value of A is larger than the phase of the clock pulse, the value of A becomes the remaining value generated when the A is divided by the phase of the clock pulse. For example, when a four-phase clock pulse is used as shown in FIG. 2A, if A is four, then A remains at a value of four. On the other hand, if A is 5, then A has a value of 1 finally. As another example, if A is 6, then A has a value of 2 in the end.

The pull-down switching device Pd provided in the n-th stage is controlled according to the voltage of the reset node QB and is connected between the output terminal OT of the n-th stage and the second discharging power supply line. That is, the pull-down switching element Pd is turned on or off according to the voltage of the reset node QB, and the output terminal OT of the n-th stage in the turn- . Here, the second discharge voltage VSS2 is supplied to the second discharge power line. The second discharge-specific voltage VSS2 can be set to a negative constant voltage as a DC voltage as described above. At this time, the first discharge voltage VSS1 may be less than or equal to the second discharge voltage VSS2. On the other hand, the first discharge voltage VSS1 may have a value equal to or greater than the second discharge voltage VSS2.

The first capacitor C1 provided in the n-th stage is connected between the clock transmission line for transmitting the clock pulse applied to the pull-up switching element Pu and the reset node QB.

Referring to FIGS. 2A and 3, the operation of the first stage in the forward driving operation will be described in detail.

1) Set point ( TS )

The start pulse Vst from the timing controller is supplied to the forward control switching element Tr_F of the first stage ST_1 at the set time TS of the first stage. This forward control switching element Tr_F is turned on and the forward voltage V_F in the high state is applied to the set node Q_1 of the first stage ST_1 through the turned on forward control switching element Tr_F, ). Therefore, the voltage V1-Q of the set node Q rises and the pull-up switching element Pu and the first switching element Tr1 connected to the set node Q through the gate electrode are turned on do.

The first discharging voltage VSS1 is supplied to the reset node QB of the first stage ST_1 through the turned-on first switching element Tr1. As a result, the voltage (V1_QB) of the reset node (QB) of the first stage is held in a low state. Accordingly, the pull-down switching element Pd and the second switching element Tr2 connected to the reset node QB via the gate electrode are turned off.

2) Output point ( CTR )

At the output time TO of the first stage ST_1, the clock pulse CLK_A (i.e., the first clock pulse CLK_1) starts to transition to the high state, at which time the set node Q is turned on by the bootstrapping phenomenon, The voltage of the capacitor C1 increases. The clock pulse CLK_1 is applied to the output terminal OT through the pull-up switching element Pu which is turned on. A clock pulse (first clock pulse CLK_1) applied to the output terminal OT is used as a scan pulse Vg_1 of the first stage ST_1.

3) Reset  Point of view ( TR )

The scan pulse Vg_2 from the second stage ST_2 becomes a high state at the reset time TR of the first stage ST_1. Accordingly, the reverse control switching element Tr_R of the first stage ST_1 supplied with the scan pulse Vg_2 is turned on. This reverse control switching element Tr_R is turned on and the reverse voltage V_R in the low state is applied to the set node Q_1 of the first stage ST_1 through the turned on reverse control switching element Tr_R ). Accordingly, the voltage V1_Q of the set node Q falls and the pull-up switching element Pu and the first switching element Tr1 connected to the set node Q through the gate electrode are turned off.

On the other hand, after the reset time TR, the second switching element Tr2 of the first stage ST_1 is turned on every time the first clock pulse CLK_1 again periodically shows a high state, Is turned on. Then, the set node Q of the first stage ST_1 is periodically discharged at that time, so that the voltage accumulation to the set node Q due to the coupling phenomenon can be prevented. That is, multi-output can be prevented.

The remaining stages also operate in the same manner as the first stage ST_1 described above. However, these stages are supplied with the scan pulse from the front stage, not the timing controller, as a start pulse.

Referring to FIG. 2B and FIG. 3, the operation of the k-th stage during reverse driving will be described in detail.

1) Set point ( TS )

the start pulse from the timing controller is supplied to the reverse control switching element Tr_R of the k-th stage ST_k at the set time TS of the k-th stage ST_k. This reverse control switching element Tr_R is turned on and the high state reverse voltage V_R is applied to the set node Q of the kth stage ST_k via the turned on reverse control switching element Tr_R ). Therefore, the voltage Vk-Q of the set node Q rises and the pull-up switching element Pu and the first switching element Tr1 connected to the set node Q through the gate electrode are turned on do.

The first discharging voltage VSS1 is supplied to the reset node QB of the k-th stage ST_k through the first switching element Tr1 turned on. Thus, the voltage (Vk_QB) of the reset node (QB) of the k-th stage (ST_k) is kept in a low state. Accordingly, the pull-down switching element Pd and the second switching element Tr2 connected to the reset node QB via the gate electrode are turned off.

2) Output point ( CTR )

the clock pulse CLK_A (i.e., the fourth clock pulse CLK_4) starts to transition to the high state at the output time TO of the kth stage ST_k, at which time the set node Q is turned on by the bootstrapping phenomenon, The voltage of the capacitor C1 increases. This clock pulse CLK_4 is applied to the output terminal OT through the pull-up switching element Pu which is turned on. The clock pulse (fourth clock pulse CLK_4) applied to this output terminal OT is used as the scan pulse Vg_k of the k-th stage ST_k.

3) Reset  Point of view ( TR )

the scan pulse Vg_k-1 from the (k-1) -th stage ST_k-1 becomes a high state at the reset time TR of the k-th stage ST_k. Accordingly, the forward control switching element Tr_F of the k-th stage ST_k receiving the scan pulse Vg_k-1 is turned on. This forward control switching element Tr_F is turned on and the forward voltage V_F in the low state is supplied to the set node Q_k of the k-th stage ST_k via the turn- ). Therefore, the voltage Vk-Q of the set node Q falls and the pull-up switching element Pu and the first switching element Tr1 connected to the set node Q through the gate electrode are turned off do.

On the other hand, after the reset time TR, the second switching element Tr2 of the k-th stage ST_k is turned on every time the fourth clock pulse CLK_4 again periodically indicates a high state, Is turned on. Then, the set node Q of the k-th stage ST_k is periodically discharged at that time to prevent the voltage accumulation to the set node Q due to the coupling phenomenon. That is, multi-output can be prevented.

The remaining stages are also operated in the same manner as the k-th stage ST_k described above. However, these stages are supplied with the scan pulse from the front stage, not the timing controller, as a start pulse.

4 is a diagram showing a configuration of a second embodiment of the n-th stage of FIG.

4, the n-th stage includes a forward control switching element Tr_F, a reverse control switching element Tr_R, a first switching element Tr1, a second switching element Tr2, a pull-up switching element Pu ), A pull-down switching device Pd, a first capacitor C1, and a second capacitor C2.

Here, the forward control switching element Tr_F, the reverse control switching element Tr_R, the first switching element Tr1, the second switching element Tr2, the pull-up switching element Pu, the pull- The first switch Pd and the first capacitor C1 are connected to the forward control switching element Tr_F, the reverse control switching element Tr_R, the first switching element Tr1 and the second switching element Tr2 in the above- Up switching element Pu, the pull-down switching element Pd, and the first capacitor C1, and therefore, a description thereof will be given with reference to FIG.

The second capacitor C2 provided in the n-th stage is connected between the set node Q and the output terminal OT of the n-th stage.

5 is a diagram showing a configuration of a third embodiment of the n-th stage of FIG.

5, the n-th stage includes a forward control switching element Tr_F, a reverse control switching element Tr_R, a first switching element Tr1, a second switching element Tr2, a third switching element Tr2, Tr3, a pull-up switching element Pu, a pull-down switching element Pd and a first capacitor C1.

Here, the forward control switching element Tr_F, the reverse control switching element Tr_R, the first switching element Tr1, the second switching element Tr2, the pull-up switching element Pu, the pull- The first switch Pd and the first capacitor C1 are connected to the forward control switching element Tr_F, the reverse control switching element Tr_R, the first switching element Tr1 and the second switching element Tr2 in the above- Up switching element Pu, the pull-down switching element Pd, and the first capacitor C1, and therefore, a description thereof will be given with reference to FIG.

The third switching device Tr3 provided in the nth stage is controlled according to one of the clock pulses CLK_B and is connected between the output terminal OT of the nth stage and the third discharging power supply line. That is, the third switching device Tr3 turns on or off according to any one of the clock pulses, and connects the output terminal OT of the nth stage to the third discharge power supply line at the turn-on time . Here, the third discharge voltage VSS3 is applied to the third discharge power line.

The third discharging voltage VSS3 may be equal to the first discharging voltage VSS1 or the second discharging voltage VSS2. Alternatively, the third discharge voltage VSS3 may be larger or smaller than the first discharge voltage VSS1. In addition, the third discharge voltage VSS3 may be larger or smaller than the second discharge voltage VSS2.

In addition, the first to third discharge voltages VSS1 to VSS3 may be all the same.

On the other hand, a clock pulse supplied to the third switching device Tr3 and a clock pulse supplied to the pull-up switching device Pu may be different from each other. For example, if the first clock pulse (CLK_1) is supplied to the pull-up switching element (Pu) of the first stage, the third switching element (Tr3) of the first stage (ST_1) Any one of the fourth clock pulses CLK_2 to CLK_4 may be supplied.

6 is a diagram showing a configuration of a fourth embodiment for the n-th stage of FIG.

6, the n-th stage includes a forward control switching element Tr_F, a reverse control switching element Tr_R, a first switching element Tr1, a second switching element Tr2, a fourth switching element Tr2, Tr4), a pull-up switching device (Pu), a pull-down switching device (Pd) and a first capacitor (C1).

Here, the forward control switching element Tr_F, the reverse control switching element Tr_R, the first switching element Tr1, the second switching element Tr2, the pull-up switching element Pu, the pull- The first switch Pd and the first capacitor C1 are connected to the forward control switching element Tr_F, the reverse control switching element Tr_R, the first switching element Tr1 and the second switching element Tr2 in the above- Up switching element Pu, the pull-down switching element Pd, and the first capacitor C1, and therefore, a description thereof will be given with reference to FIG.

The fourth switching device Tr4 provided in the nth stage is controlled according to one of the clock pulses CLK_B and is connected between the output terminal OT of the nth stage and any one of the clock transmission lines. That is, the fourth switching device Tr4 turns on or off according to any one of the clock pulses, and connects the output terminal OT of the n-th stage to any one of the clock transmission lines when turned on .

Here, a clock pulse supplied to the gate electrode of the fourth switching device Tr4 and a clock pulse supplied to the pull-up switching device Pu are different from each other. The clock pulses supplied to the source electrode (or the drain electrode) of the fourth switching element Tr4 and the clock pulses supplied to the pull-up switching element Pu are equal to each other. For example, if the first clock pulse is supplied to the pull-up switching element Pu of the first stage, the gate electrode of the fourth switching element Tr4 provided in the first stage is connected to the second, Any one of the fourth clock pulses CLK_2 to CLK_4 may be supplied. The first clock pulse CLK_1 may be supplied to the source electrode of the fourth switching device Tr4 included in the first stage ST_1.

7 is a diagram showing a configuration of a fifth embodiment for the n-th stage of FIG.

The n-th stage includes a forward control switching element Tr_F, a reverse control switching element Tr_R, a first switching element Tr1, a second switching element Tr2, a fifth switching element Tr2, A pull-up switching element Pd, and a first capacitor C1.

Here, the forward control switching element Tr_F, the reverse control switching element Tr_R, the first switching element Tr1, the second switching element Tr2, the pull-up switching element Pu, the pull- The first switch Pd and the first capacitor C1 are connected to the forward control switching element Tr_F, the reverse control switching element Tr_R, the first switching element Tr1 and the second switching element Tr2 in the above- Up switching element Pu, the pull-down switching element Pd, and the first capacitor C1, and therefore, a description thereof will be given with reference to FIG.

The fifth switching element Tr5 provided in the nth stage is controlled in accordance with the voltage applied to the output terminal OT of the nth stage and is connected to the output terminal OT of the nth stage and a clock transmission line Respectively. That is, the fifth switching element Tr5 is turned on or off according to the voltage applied to the output terminal OT of the n-th stage, and is turned on or off according to the voltage applied to the output terminal OT of the n- To each other. Here, the clock pulse supplied to the fifth switching element Tr5 and the clock pulse supplied to the pull-up switching element Pu may be the same.

8 is a diagram showing the configuration of the nth stage of the sixth embodiment shown in Fig.

8, the n-th stage includes a forward control switching element Tr_F, a reverse control switching element Tr_R, a first switching element Tr1, a second switching element Tr2, a sixth switching element Tr2, Tr6, a pull-up switching element Pu, a pull-down switching element Pd and a first capacitor C1.

Here, the forward control switching element Tr_F, the reverse control switching element Tr_R, the first switching element Tr1, the second switching element Tr2, the pull-up switching element Pu, the pull- The first switch Pd and the first capacitor C1 are connected to the forward control switching element Tr_F, the reverse control switching element Tr_R, the first switching element Tr1 and the second switching element Tr2 in the above- Up switching element Pu, the pull-down switching element Pd, and the first capacitor C1, and therefore, a description thereof will be given with reference to FIG.

The sixth switching device Tr6 provided in the nth stage is controlled according to a scan pulse from the (n + 1) th stage and is connected between the output terminal OT of the nth stage and the third power line. That is, the sixth switching element Tr6 is turned on or off according to the scan pulse from the (n + 1) -th stage, and the output terminal OT of the nth stage at the turn- To each other. Here, the sixth switching element Tr6 can be supplied with the scan pulse from the (n + r) th stage, and r is a natural number.

9 is a diagram showing a configuration of a seventh embodiment for the n-th stage of Fig.

9, the n-th stage includes a forward control switching element Tr_F, a reverse control switching element Tr_R, a first switching element Tr1, a second switching element Tr2, a seventh switching element Tr2, Tr7, a pull-up switching element Pu, a pull-down switching element Pd and a first capacitor C1.

Here, the forward control switching element Tr_F, the reverse control switching element Tr_R, the first switching element Tr1, the second switching element Tr2, the pull-up switching element Pu, the pull- The first switch Pd and the first capacitor C1 are connected to the forward control switching element Tr_F, the reverse control switching element Tr_R, the first switching element Tr1 and the second switching element Tr2 in the above- Up switching element Pu, the pull-down switching element Pd, and the first capacitor C1, and therefore, a description thereof will be given with reference to FIG.

The seventh switching device Tr7 provided in the nth stage is controlled according to the voltage of the reset node QB and is connected between the output terminal OT of the nth stage and the third discharging power supply line. That is, the seventh switching device Tr7 is turned on or off according to the voltage of the reset node QB, and the output terminal OT of the nth stage and the third discharge power supply line are turned on To each other.

10 is a diagram showing a configuration of an eighth embodiment of the n-th stage of FIG.

10, the n-th stage includes a forward control switching element Tr_F, a reverse control switching element Tr_R, a first switching element Tr1, a second switching element Tr2, an eighth switching element Tr2, Tr8, a pull-up switching element Pu, a pull-down switching element Pd and a first capacitor C1.

Here, the forward control switching element Tr_F, the reverse control switching element Tr_R, the first switching element Tr1, the second switching element Tr2, the pull-up switching element Pu, the pull- The first switch Pd and the first capacitor C1 are connected to the forward control switching element Tr_F, the reverse control switching element Tr_R, the first switching element Tr1 and the second switching element Tr2 in the above- Up switching element Pu, the pull-down switching element Pd, and the first capacitor C1, and therefore, a description thereof will be given with reference to FIG.

The eighth switching element Tr8 provided in the nth stage is controlled according to the control signal CS from the outside and is connected between the set node Q and the third discharging power supply line. That is, the eighth switch Tr8 turns on or off according to the control signal CS, and connects the set node Q and the third discharge power supply line to each other at the turn-on time.

The eighth switching device Tr8 in Fig. 10 is supplied to the stages except the stage to which the start pulse (Vst; or the first start pulse or the second start pulse) is supplied. For example, the start pulse Vst is supplied to the first stage ST_1 and the kth stage ST_k in the structure shown in FIG. 1, and the eighth switching device Tr8 described above is supplied to the first stage ST_1, (The second stage ST_2 to the (k-1) th stage ST_k-1) except for the k-th stage ST_k.

11 is a diagram showing the configuration of the ninth embodiment of the n-th stage of Fig.

11, the n-th stage includes a forward control switching element Tr_F, a reverse control switching element Tr_R, a first switching element Tr1, a second switching element Tr2, a ninth switching element Tr2, Tr9, a pull-up switching element Pu, a pull-down switching element Pd and a first capacitor C1.

Here, the forward control switching element Tr_F, the reverse control switching element Tr_R, the first switching element Tr1, the second switching element Tr2, the pull-up switching element Pu, the pull- The first switch Pd and the first capacitor C1 are connected to the forward control switching element Tr_F, the reverse control switching element Tr_R, the first switching element Tr1 and the second switching element Tr2 in the above- Up switching element Pu, the pull-down switching element Pd, and the first capacitor C1, and therefore, a description thereof will be given with reference to FIG.

The ninth switching element Tr9 provided in the nth stage is controlled according to a control signal from the outside and is connected between the set node Q and any one of the clock transmission lines. That is, the ninth switching element Tr9 is turned on or off according to the control signal CS, and connects the set node Q and any one of the clock transmission lines to each other. Here, a clock pulse supplied to the ninth switching element Tr9 and a clock pulse supplied to the pull-up switching element Pu are equal to each other.

The ninth switching element Tr9 in Fig. 11 is supplied to the stages other than the stage to which the start pulse Vst (or the first start pulse or the second start pulse) is supplied. For example, in the structure shown in FIG. 1, the start pulse is supplied to the first stage ST_1 and the kth stage ST_k, and the ninth switching transistor Tr9 described above is connected to the first stage ST_1 and the kth (Second stage to (k-1) th stage) except for the stage ST_k.

On the other hand, the control signal CS in Figs. 10 and 11 can be replaced by the above-described start pulse (Vst) or the first start pulse or the second start pulse.

12A is another output timing chart of various signals supplied to the shift register of FIG. 1 and various signals outputted therefrom during forward driving, and FIG. 12B is a timing chart of various signals supplied to the shift register of FIG. And Fig.

As shown in FIGS. 12A and 12B, 8-phase clock pulses superimposed for a certain period of the pulse width can be used. For example, each of the first to eighth clock pulses CLK_1 to CLK_8 has a pulse width of 3.5 magnitude, and the overlap pulse width period of the adjacent clock pulses CLK_1 to CLK_8 may have a magnitude of 2.5 .

The scan pulses Vg_1 to Vg_8 output from the shift register supplied with the clock pulses CLK_1 to CLK_8 are also output in a superposed state by a predetermined pulse width.

13 is a view illustrating a display panel to which a shift register according to the present invention is applied.

As shown in FIG. 13, the shift register according to the present invention can be divided into two. That is, the shift register of the present invention is divided into a first shift register SR1 formed on the display panel so as to be positioned on one side of the display section and a second shift register SR2 formed on the display panel so as to be positioned on the other side of the display section .

The first shift register SR1 drives the odd gate lines while the second shift register SR2 drives the even gate lines.

On the other hand, the data driver drives data lines not shown.

FIG. 14 is a diagram showing the configuration of stages included in the first shift register SR1 and the second shift register SR2 of FIG.

As shown in FIG. 14, the first shift register SR1 includes odd-numbered stages and the second shift register SR2 includes even-numbered stages.

The odd-numbered clock pulses CLK_1 and CLK_3 are supplied to the odd-numbered stages ST_1, ST_3, ..., ST_k-1 when the above-described four clock pulses CLK_1 to CLK_4 are used, Th clock pulses CLK_2 and CLK_4 are supplied to the even-numbered stages ST_2, ST_4, ..., ST_k.

When such a four-phase clock pulse is used, the scan pulse from the n-th stage can be supplied to the (n-2) -th and (n + 2) -th stages. For example, the scan pulse Vg_3 from the third stage ST_3 is supplied to the first stage ST_1 and the fifth stage ST_5, and the scan pulse Vg_4 from the fourth stage ST_4 is supplied to the The second stage ST_2 and the sixth stage ST_6. On the other hand, the scan pulse (Vg_1) from the first stage (ST_1) provided at the uppermost side of the first shift register (SR1) is supplied only to the third stage (ST_3) The scan pulse Vg_2 from the second stage ST_2 provided in the fourth stage ST_4 is supplied only to the fourth stage ST_4.

On the other hand, when the 8-phase clock pulses CLK_1 to CLK_8 as described above are used, the scan pulse from the n-th stage can be supplied to the (n-4) th and (n + 4) th stages. For example, in the fifth stage ST_5, the negative scan pulse Vg_5 is supplied to the first stage ST_1 and the ninth stage ST_9, and the scan pulse Vg_6 from the sixth stage ST_6 is supplied to the The second stage ST_2 and the tenth stage. On the other hand, the scan pulse (Vg_1) from the first stage (ST_1) provided on the uppermost side of the first shift register (SR1) is supplied only to the fifth stage (ST_5) The scan pulse Vg_2 from the second stage ST_2 provided in the second stage ST_6 is supplied only to the sixth stage ST_6.

The start pulse Vst is input to the first stage ST_1 and the k-1st stage ST_k-1 located in the first shift register SR1 and the second stage ST_2 located in the second shift register SR2. And the k < th > stage ST_k.

As another embodiment, the first start pulse described above is supplied to the first stage ST_1 and the second stage ST_2, and the first start pulse is supplied to the k-1st stage ST_k-1 and the kth stage ST_k, A second start pulse may be supplied. The first start pulse described above is supplied to the first stage ST_1 and the second start pulse is supplied to the (k-1) th stage ST_k-1, and the third start signal is supplied to the second stage ST_2. A pulse may be supplied, and a fourth start pulse may be supplied to the kth stage ST_k. Here, the third start pulse is outputted later than the first start pulse, and the fourth start pulse is outputted later than the second start pulse. At this time, the third start pulse and the first start pulse may overlap each other for a certain period of time, and the fourth start pulse and the second start pulse may overlap each other for a certain period of time.

Each stage ST_1 to ST_k in FIG. 14 may have any one of the configurations shown in FIGS. 3 to 11 described above.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of.

Vg_ #: 1st scan pulse V_F: forward voltage
V_R: reverse voltage C1: first capacitor
CLK_ #: Clock pulse # Tr #: Clock #
Pu: Pull-up switching element Pd: Pull-down switching element
VSS #: Nominal discharge voltage Tr_F: Forward control switching element
Tr_R: Reverse control switching element OT: Output terminal
Q: set node QB: reset node

Claims (16)

A plurality of stages sequentially outputting scan pulses and sequentially supplying the scan pulses to the plurality of gate lines;
The n-th (n is a natural number)
A forward control switching element controlled in accordance with a scan pulse from a first start pulse or an npth (p is a natural number smaller than n) stage and connected between a set power source line and a set node for transmitting a forward voltage;
A reverse control switching element connected between the set node and a reverse power supply line for transmitting a reverse voltage, the reverse control switching element being controlled according to a scan pulse from a second start pulse or an (n + q) th (n is a natural number) stage;
A first switching element connected between a reset node and a first discharging power supply line for transmitting a first discharging voltage, the first switching element being controlled according to a voltage of the set node;
A second switching element controlled in accordance with the voltage of the reset node and connected between the set node and an output terminal of the nth stage;
A pull-up switching element connected between the output terminal and one clock transmission line, which is controlled according to a voltage of the set node and transmits any one of a plurality of clock pulses having different phases;
A pull-down switching element connected between the output terminal and a second discharging power supply line for transmitting a second discharging voltage, the pull-down switching element being controlled according to the voltage of the reset node;
And a first capacitor connected between the one clock transmission line and the reset node;
Wherein the forward voltage and the reverse voltage have phases opposite to each other;
The clock pulses include forward clock pulses and reverse clock pulses;
The forward clock pulses are supplied to all stages including the n-th stage when the forward voltage is in an active state;
The reverse clock pulses are supplied to all stages including the n-th stage when the reverse voltage is in an active state,
Wherein the first discharge voltage and the second discharge voltage are different voltages. The method according to claim 1,
Wherein the first start pulse and the second start pulse are the same. The method according to claim 1,
Wherein the first discharge voltage is smaller than the second discharge voltage. The method according to claim 1,
Wherein the first discharge voltage is greater than the second discharge voltage. The method according to claim 1,
The n < th >
And a second capacitor connected between the set node and the output terminal. The method according to claim 1,
The nth stage further includes a third switching element connected between the output terminal and a third discharging power line for transmitting a third discharging voltage, the third switching element being controlled according to any one of the clock pulses; And,
Wherein a clock pulse supplied to the third switching element and a clock pulse supplied to the pull-up switching element are different from each other. The method according to claim 1,
The nth stage further comprises a fourth switching element controlled according to any one of the clock pulses and connected between the output terminal and any one of the clock transmission lines;
A clock pulse supplied to the gate electrode of the fourth switching element and a clock pulse supplied to the pull-up switching element are different from each other; And,
Wherein a clock pulse supplied to the source electrode or the drain electrode of the fourth switching element and a clock pulse supplied to the pull-up switching element are equal to each other. The method according to claim 1,
The nth stage further comprises a fifth switching element controlled according to the voltage of the output terminal and connected between the output terminal and any one of the clock transmission lines; And,
Wherein a clock pulse supplied to the fifth switching element and a clock pulse supplied to the pull-up switching element are equal to each other. The method according to claim 1,
The n < th >
and a sixth switching device connected between the output terminal and a third power supply line for transmitting a third discharge voltage, the sixth switch being controlled according to a scan pulse from the n + rth (r is a natural number) stage, Features a shift register. The method according to claim 1,
The n < th >
Further comprising a seventh switching element connected between the output terminal and a third discharging power line for transmitting a third discharging voltage, the seventh switching element being controlled according to the voltage of the reset node. The method according to claim 1,
The n < th >
Further comprising an eighth switching element connected between the set node and a third power supply line for transmitting a third discharge voltage, the eighth switch being controlled according to a control signal from the outside. The method according to claim 1,
The nth stage further comprises a ninth switching element controlled in accordance with a control signal from the outside and connected between the set node and any one of the clock transmission lines; And,
Wherein a clock pulse supplied to the ninth switching element and a clock pulse supplied to the pull-up switching element are equal to each other. The method according to any one of claims 11 to 12,
Wherein the control signal is any one of a first start pulse and a second start pulse. 13. The method of claim 12,
Wherein the ninth switching element is provided in each of the remaining stages except the stage supplied with the first start pulse or the second start pulse. The method according to claim 1,
The odd-numbered stages of the plurality of stages being located at one side of the display portion; And,
And the even-numbered stages of the plurality of stages are located on the other side of the display unit. The method according to claim 1,
And p and q are the same.

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