CN105355179B - A kind of scan drive circuit and its display device - Google Patents
A kind of scan drive circuit and its display device Download PDFInfo
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- CN105355179B CN105355179B CN201510875133.8A CN201510875133A CN105355179B CN 105355179 B CN105355179 B CN 105355179B CN 201510875133 A CN201510875133 A CN 201510875133A CN 105355179 B CN105355179 B CN 105355179B
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Abstract
The invention discloses a kind of scan drive circuit and its display device.The scan drive circuit of the present invention includes input block, latch unit, NAND gate signal processing unit and output buffer cell, wherein, the input block is configured to pass control signal, when the output of prime level biography control signal and the different input combination controls input block of next stage level biography control signal passes control signal to export the prime level of working as of next sequential by the upper level level of current sequential.Compared with prior art, scan drive circuit of the invention and its display device can depart from it is positive and negative sweep signal realize it is positive and negative sweep function, the signal wire and device of circuit are greatly reduced, and not only beneficial to narrow frame design, and reduce the power consumption of circuit；Also, the scan drive circuit of the present invention need not change existing substrate integrated circuit unit structure, realize that difficulty is low, have higher promotional value.
Description
Technical field
The present invention relates to field of liquid crystal display, in particulars relate to a kind of scan drive circuit and its display device.
Background technology
With the development of low temperature polycrystalline silicon (LTPS) semiconductor thin-film transistor, and due to superelevation of LTPS semiconductors itself
The characteristic of carrier mobility, corresponding panel periphery integrated circuit also turn into everybody focus of attention, and many people's inputs
To onboard system (System on Panel, SOP) relation technological researching, and a variety of SOP are done step-by-step.
In the prior art, generally use substrate integrated technology (Gate Driver On Array, abbreviation GOA) construction is thin
Film transistor (Thin-film transistor, TFT) liquid crystal display.It will be realized namely in substrate (Array) processing procedure
The Gate line-scanning drive circuits of (Gate) progressive scan are produced on Array substrates on the door.
Function all is swept with positive and negative using GOA circuit drives Gate control panel (Panel) is general, in the prior art,
Positive and negative circuit of sweeping is typically all to sweep signal (U2D/D2U signals) and corresponding TFT devices by positive/negative and positive and negative sweep work(to realize
Energy.This requires that corresponding U2D/D2U signal sources must be constructed.The presence of U2D/D2U signal sources adds the signal wire of circuit
And device, not only bad for narrow frame design, and the power consumption of circuit can be increased.
Therefore, in order to simplify circuit design, it is necessary to a kind of new scan drive circuit.
The content of the invention
In order to simplify circuit design, the invention provides a kind of scan drive circuit, the circuit includes input block, lock
Storage unit, NAND gate signal processing unit and output buffer cell, wherein：
The input block include be connected respectively to upper level level pass control signal, when prime level pass control signal and under
One-level level passes the input of the first control signal, the input of the second control signal, the input of the 3rd control signal of control signal, the input
Unit is configured to by first control signal input of current sequential, second control signal input, the described 3rd
The different input combinations that signal inputs control the outputs of the input block to believe to export the prime level transmission control system of working as of next sequential
Number；
The latch unit is used for the latch that level passes signal, and the output end of the latch unit, which is used to export, works as prime
Level passes control signal, and an input of the latch unit is connected to the output of the input block, the latch list
Another input of member is connected to the first sequential input of the drive circuit；
One input of the NAND gate signal processing unit is connected to the second sequential input of the drive circuit, separately
One input is connected to the output end of the latch unit, and the NAND gate signal processing unit is configured to from described
The signal of second sequential input is carried out with non-process to export the grid when prime with the described of latch when prime level passes control signal
Pole drive signal；
The input of output buffer cell is connected to the output end of the NAND gate signal processing unit, the output buffering
Unit is used for the driving force for increasing the gate drive signal, reduces the phase shift of transmission signal.
In one embodiment：
There is one when the next stage level passes control signal or the upper level level and passes control signal to be high and described work as
When prime level biography control signal is low, the input block exports high level；
When described when it is high that prime level, which passes control signal, the input block exports low level.
In one embodiment, the input block also include high potential open the first transistor, second transistor, the 3rd
The 4th transistor that transistor and low potential are opened, wherein：
The grid of the first transistor and the second transistor connects the first control signal input and institute respectively
State the 3rd control signal to input, the grid of the third transistor and the 4th transistor connects second control jointly
Signal inputs；
The source electrode of the first transistor and the second transistor is connected to high potential, the first transistor and institute jointly
The drain electrode for stating second transistor is connected to the source electrode of the 4th transistor jointly；
The source electrode of the third transistor is connected to low potential, the drain electrode of the third transistor and the 4th transistor
The output of the input block is connected to jointly.
In one embodiment, the input block also includes being connected to the third transistor and the 4th transistor
Drain electrode and the output of the input block between the 5th transistor opened of low potential, wherein：
The source electrode of 5th transistor is connected to the drain electrode of the third transistor and the 4th transistor；
The drain electrode of 5th transistor is connected to the output of the input block；
The grid of 5th transistor is connected to the first sequential input.
In one embodiment, the input block also includes the 6th transistor that low potential is opened, wherein：
The source electrode of 6th transistor is connected to low potential；
The drain electrode of 6th transistor is connected to the output of the input block；
The grid of 6th transistor is connected to reset signal.
The invention also provides a kind of display device, described device includes multiple as any one of claim 1-4
Scan drive circuit and crystal liquid substrate, wherein：
The corresponding scan drive circuit of each liquid crystal pixel row on the crystal liquid substrate；
The output end of the output buffer cell of each scan drive circuit is connected to the corresponding liquid crystal pixel row
Turntable driving input on；
Multiple scan drive circuits according to the liquid crystal pixel row corresponding to it the mutual cascade that puts in order.
In one embodiment：
First control signal input connection of the scan drive circuit corresponding to liquid crystal pixel row described in any row
To corresponding to liquid crystal pixel row described in lastrow in the output of the latch unit of the scan drive circuit；
Second control signal input connection of the scan drive circuit corresponding to liquid crystal pixel row described in any row
To corresponding to liquid crystal pixel row described in current line in the output of the latch unit of the scan drive circuit；
The 3rd control signal input connection of the scan drive circuit corresponding to liquid crystal pixel row described in any row
To corresponding to liquid crystal pixel row described in next line in the output of the latch unit of the scan drive circuit.
In one embodiment：
The first sequential input of the scan drive circuit corresponding to liquid crystal pixel row described in any row and the institute of adjacent lines
The the second sequential input for stating the scan drive circuit corresponding to liquid crystal pixel row is together connected to the first sequential of described device
On signal；
The second sequential input of the scan drive circuit corresponding to liquid crystal pixel row described in any row and the institute of adjacent lines
The the first sequential input for stating the scan drive circuit corresponding to liquid crystal pixel row is together connected to the second sequential of described device
On signal.
In one embodiment：
First control signal input connection of the scan drive circuit corresponding to liquid crystal pixel row described in the first row
To just sweeping up beginning trigger signal；
The 3rd control signal input of the scan drive circuit corresponding to liquid crystal pixel row described in last column connects
It is connected to and counter sweeps up beginning trigger signal.
Compared with prior art, scan drive circuit of the invention and its display device can depart from U2D/D2U signals reality
Now positive and negative to sweep function, the signal wire and device of circuit are greatly reduced, and not only beneficial to narrow frame design, and reduce circuit
Power consumption；Also, the scan drive circuit of the present invention need not change existing GOA circuit units structure, realize that difficulty is low, have
Higher promotional value.
The further feature or advantage of the present invention will illustrate in the following description.Also, the present invention Partial Feature or
Advantage will be become apparent by specification, or be appreciated that by implementing the present invention.The purpose of the present invention and part
Advantage can be realized or obtained by specifically noted step in specification, claims and accompanying drawing.
Brief description of the drawings
Accompanying drawing is used for providing a further understanding of the present invention, and a part for constitution instruction, the reality with the present invention
Apply example to be provided commonly for explaining the present invention, be not construed as limiting the invention.In the accompanying drawings：
Fig. 1 is the circuit structure sketch of scan drive circuit in the prior art；
Fig. 2 is the cascade structure sketch of the scan drive circuit of display device in the prior art；
Fig. 3 be in the prior art display device respectively in the positive and negative signal timing diagram swept under state；
Fig. 4 is the circuit structure sketch of scan drive circuit according to an embodiment of the invention；
Fig. 5 is the cascade structure sketch of the scan drive circuit of display device according to an embodiment of the invention；
Fig. 6 is display device according to an embodiment of the invention respectively in the positive and negative signal timing diagram swept under state.
Embodiment
Embodiments of the present invention are described in detail below with reference to drawings and Examples, whereby implementation personnel of the invention
Can fully understand how application technology means solve technical problem to the present invention, and reach the implementation process of technique effect and according to
The present invention is embodied according to above-mentioned implementation process.If it should be noted that do not form conflict, each embodiment in the present invention
And each feature in each embodiment can be combined with each other, the technical scheme formed protection scope of the present invention it
It is interior.
In the prior art, generally use GOA technology humanizeds TFT LCD.Namely in Array basal plate making process
The Gate line-scanning drive circuits of Gate progressive scans are produced on Array substrates by realizing.
Function all typically is swept with positive and negative using GOA circuit drives Gate control panel Panel, in the prior art, just
Anti- circuit of sweeping is typically all to realize positive and negative to sweep function by U2D/D2U signals and corresponding TFT devices.For a certain Gate rows
Scan drive circuit as shown in figure 1, st [n-1], st [n] and st [n+1] be respectively upper level level pass control signal, work as prime
Level biography control signal and next stage level pass control signal, and (n is Gate line numbers, is included in signal numbering in this manual
N all refer to Gate line numbers corresponding to the signal)；CK1And CK2Respectively two clock signals；RST (Reset) believes to reset
Number；VGH is high potential；U2D and D2U is respectively just sweeping signal and is sweeping signal with counter.
GOA circuit units are by latch (Latch) unit 200, NAND gate signal processing unit 300 and buffering
(Buffer) unit 400 is formed.It is connected with the input of GOA circuit units and positive and negative sweep control unit 100 (U2D/D2U is mono-
Member).It is positive and negative sweep control unit 100 export next sequential when prime level pass control signal；Latch unit 200 sweeps control by positive and negative
Next sequential that unit 100 processed exports works as prime level transmission control signal latch；NAND gate signal processing unit 300 is by latch
When prime level passes control signal and clock signal (CK2) do with non-process so as to which the output when next sequential arrives should prime level
Pass control signal (gate drive signal for producing this grade)；Final buffer unit 400 will work as prime level and pass at control signal buffering
(utilizing cmos circuit) is managed to increase the driving force of gate drive signal, reduces the phase shift (RC Loading) of transmission signal,
OUT [n] (Output [n]) is the final output of scan drive circuit.
During actual scanning, for the Gate rows of liquid crystal panel, scanning signal is with the propulsion edge of scanning sequence
The numbering Up/Down (positive/negative to sweep) of Gate rows.With three row Gate row (the (n-1)th row, line n and (n+1)th of arbitrary continuation
Exemplified by OK).Assuming that it is respectively st [n-1], st [n] and st [n that the level that above-mentioned three row is corresponded in arbitrary scan sequential, which passes control signal,
+1].If just sweeping under environment st [n-1], st [n] and st [n+1] in certain one scan sequence be respectively low potential, high potential,
Low potential, then st [n-1], st [n] and st [n+1] are respectively that low potential, low potential, high potential are (anti-in lower one scan sequence
Sweep, be high potential, low potential, low potential).
To realize above-mentioned function, in the embodiment shown in fig. 1, the positive and negative control unit 100 of sweeping is according to positive and negative situation of sweeping
The different upper level levels using current sequential pass control signal st [n-1] or next stage level passes control signal st [n+1] as next
The prime level of working as of sequential passes control signal st [n].Specifically, it is positive and negative sweep control unit 100 comprising two be respectively intended to receive work as
The upper level level of preceding sequential pass control signal st [n-1] and next stage level biography control signal st [n+1] input and two
The positive and negative input for sweeping control signal U2D signals and D2U signals is received respectively.It is positive and negative to sweep control unit 100 by current potential just
Opposite U2D/D2U signals control output, to realize that the st [n-1] of input and st [n+1] signal only have one can export.
For the scan drive circuit cascade structure of multiple liquid crystal pixel rows (Gate rows), n-th grade of level passes control signal
St [n] passes through (n-1)th grade and (n+1)th grade of the positive and negative GOA circuit lists swept control unit and be connected into (n-1)th grade or (n+1)th grade respectively
First input.And order hop jump (the 1st grade of CK step by step of CK signals (CK1 and CK2) access circuit1/CK2For CK1/CK2, the 2nd
Level CK1/CK2For CK2/CK1,3rd level CK1/CK2For CK1/CK2 ...).
(corresponding 1st row, the 2nd by taking the 1st grade, the 2nd grade, 3rd level and the 4th grade four scan drive circuits cascaded as an example
Row, the 3rd row and the 4th row Gate rows), as shown in Fig. 2 STV is start trigger signal；OUT [1], OUT [2], OUT [3] and
OUT [4] is respectively the output of 4 level scan drive circuits.By the 1st grade of input, (now STV signals is just to STV signals when just sweeping
Sweep up beginning trigger signal), it is anti-when sweeping by (the 4th grade) input of afterbody (now STV signals sweep up beginning trigger signal to be counter).
The driver' s timing of GOA circuits as shown in Figure 3 can be realized based on circuits cascading structure shown in Fig. 2.In figure 3, it is left
Figure and right figure are respectively just being swept and the anti-signal timing diagram swept under state.
To sum up, scan drive circuit sweeps function by the cooperation of U2D/D2U signals and CK signals to realize that circuit is positive and negative.This
Require that corresponding U2D/D2U signal sources must be constructed.The presence of U2D/D2U signal sources adds the signal wire and device of circuit
Part, not only bad for narrow frame design, and the power consumption of circuit can be increased.
In view of the above-mentioned problems, the present invention proposes a kind of scan drive circuit.It is not required in the scan drive circuit of the present invention
To rely on U2D/D2U signals can to export the prime level of working as of next sequential and pass control signal, i.e., turntable driving of the invention electricity
Control unit is swept in road without setting comprising the positive and negative of U2D/D2U signal sources, so as to reduce the signal wire of circuit and device, not only
Beneficial to narrow frame design, and reduce the power consumption of circuit.
As shown in figure 4, scan drive circuit includes input block 500 and GOA circuits.GOA circuits include latch
(Latch) unit 200, NOT gate signal processing unit 300 and buffering (Buffer) unit 400.
Input block 500 includes three control signal inputs and a signal output.The signal output of input block 500
It is connected on the signal input IN [n] (the signal input of latch unit 200) of GOA circuits.Three control signal inputs point
The upper level level for not receiving current sequential passes control signal (st [n-1]), when prime level passes control signal (st [n]) and next
Level level passes control signal (st [n+1]).
In the present embodiment, input block 500 relies on st [n-1], st [n] and the st [n+1] of the current sequential of input
Unlike signal input combination control output end output to obtain the st of next sequential [n].When current sequential st [n+1] or
St [n-1] have a st [n] for being high and current sequential for it is low when, output end output high level (In [n] is high level)；When
When the st [n] of current sequential is high, In [n] is low level.
Input block 500 include high potential open the first transistor 501, second transistor 502, third transistor 503
And the 4th transistor 504 that low potential is opened, wherein：
The grid of the first transistor 501 and second transistor 502 connect respectively upper level level pass control signal st [n-1] and
Next stage level passes control signal st [n+1], and prime is worked as in the common connection of grid of the 4th transistor 504 and third transistor 503
Level passes control signal st [n]；The source electrode of the first transistor 501 and second transistor 502 is connected to high potential VGH jointly, and first is brilliant
The drain electrode of body pipe 501 and second transistor 502 is connected to the source electrode of the 4th transistor 504 jointly；The source electrode of third transistor 503 connects
To low potential VGL, the drain electrode of the transistor 504 of third transistor 503 and the 4th is connected to output end jointly.
So, when st [n] is low potential, the 4th transistor 504 turns on and third transistor 503 turns off.Now if
When st [n-1] or st [n+1] is high potential, the first transistor 501 or second transistor 502 turn on, and high potential VGH passes through first
Transistor 501 or second transistor 502, are exported via the 4th transistor 504.When st [n] is high potential, third transistor
503 conducting and the 4th transistor 504 turn off, low potential VGH exports via third transistor 503.
Further, in the present embodiment, high potential VGH is TFT-LCD cut-in voltages, and low potential VGL closes for TFT-LCD
Close voltage.
Further, in order to ensure that the output signal of input block 500 is synchronous with scanning sequence, input block 500 is also
Low potential including being connected between the drain electrode of the transistor 504 of third transistor 503 and the 4th and output end open the 5th
Transistor 505, wherein：The source electrode of 5th transistor 505 is connected to the drain electrode of the transistor 504 of third transistor 503 and the 4th；
The drain electrode of 5th transistor 505 is connected to output end；The grid of 5th transistor 505 is connected to clock signal CK1。
Further, input block 500 is also configured with reset circuit.Specifically, input block 500 is also opened including low potential
The 6th logical transistor 506, wherein：The source electrode of 6th transistor 506 is connected to low potential VGL；The drain electrode of 6th transistor 506
It is connected to output end；The grid of 6th transistor 506 is connected to reset signal RST.
According to the scan drive circuit of the present invention, input block does not need U2D/D2U signals, so as to simplify circuit structure,
The signal wire and device of circuit are reduced, not only beneficial to narrow frame design, and reduces the power consumption of circuit.Compare Fig. 4 and Fig. 1
Understand, the structure of existing GOA circuit units need not be changed (shown in Fig. 1 and Fig. 4 according to the scan drive circuit of the present invention
Latch (Latch) unit 200, NAND gate signal processing unit 300 and buffering (Buffer) unit 400).Therefore this hair
Bright scan drive circuit realizes that difficulty is very low, has higher promotional value.
Based on the scan drive circuit of the present invention, the invention also provides a kind of display device.The display device of the present invention
Include crystal liquid substrate and multiple scan drive circuits.Multirow liquid crystal pixel row, each liquid crystal picture are configured with crystal liquid substrate
The corresponding scan drive circuit of plain row.The output end of the output buffer cell of each scan drive circuit is connected to corresponding liquid
In the turntable driving input of brilliant pixel column.Multiple scan drive circuits put in order mutually according to its corresponding liquid crystal pixel row
Cascade.
In the structure similar to Figure 2 of the scan drive circuit cascade structure according to the present invention, wherein：
The first control signal input of scan drive circuit corresponding to any row (line n) liquid crystal pixel row (receives upper one
Level level passes control signal st [n-1] port) it is connected to lastrow (the (n-1)th row) scan drive circuit corresponding to liquid crystal pixel row
Latch unit output on；
The second control signal input of scan drive circuit corresponding to any row (line n) liquid crystal pixel row (receives current
Level level passes control signal st [n] port) it is connected to the lock of scan drive circuit corresponding to current line (line n) liquid crystal pixel row
In the output of storage unit；
The 3rd control signal input of scan drive circuit corresponding to any row (line n) liquid crystal pixel row (receives next
Level level passes control signal st [n+1] port) it is connected to next line (the (n+1)th row) scan drive circuit corresponding to liquid crystal pixel row
Latch unit output on.
That is, n-th grade of level pass control signal st [n] be connected into n-th by (n-1)th grade and (n+1)th grade of input block respectively-
1 grade or (n+1)th grade of GOA circuit unit inputs.
Further, (CK is inputted for the clock signal of each scan drive circuit1And CK2)：
The first sequential input (CK of scan drive circuit corresponding to any row (line n) liquid crystal pixel row1) and adjacent lines
The second sequential input (CK of scan drive circuit corresponding to the liquid crystal pixel row of (the (n-1)th row or n+1 rows)2) be together connected to it is aobvious
On the first clock signal (CK1) of showing device；
The second sequential input (CK of scan drive circuit corresponding to any row (line n) liquid crystal pixel row2) and adjacent lines
The first sequential input (CK of scan drive circuit corresponding to the liquid crystal pixel row of (the (n-1)th row or n+1 rows)1) be together connected to it is aobvious
On the first clock signal (CK2) of showing device.
That is, order hop jump (the 1st grade of CK step by step of CK signals (CK1 and CK2) access circuit1/CK2For CK1/CK2, the 2nd
Level CK1/CK2For CK2/CK1,3rd level CK1/CK2For CK1/CK2 ...).
In addition, the first control signal input of scan drive circuit corresponding to the first row liquid crystal pixel row is connected to and just swept up
Beginning trigger signal (STV)；The 3rd control signal input of scan drive circuit corresponding to last column liquid crystal pixel row is connected to
It is counter to sweep up beginning trigger signal (STV).
(corresponding 1st row, the 2nd by taking the 1st grade, the 2nd grade, 3rd level and the 4th grade four scan drive circuits cascaded as an example
Row, the 3rd row and the 4th row Gate rows), as shown in Figure 5.Input block per one-level is all connected to reset signal RST, sequential letter
Number CK1 or CK2, high potential VGH and low potential VGL.
The prime level of working as that 1st grade of level transmission control signal output St [1] is connected into the 1st grade passes control signal reception and the 2nd
The upper level level of level passes control signal and received；The next stage level that 2nd grade of level transmission control signal output St [2] is connected into the 1st grade passes
Control signal receives, the 2nd grade of the upper level level biography control signal that control signal reception and 3rd level are passed when prime level receives；
The level transmission control signal output St [3] of 3rd level is connected into the 2nd grade of next stage level and passes that control signal receives, 3rd level works as prime level
Pass control signal reception and the 4th grade of upper level level passes control signal and received；4th grade of level transmission control signal output St [4]
It is connected into the next stage level biography control signal reception of 3rd level and the 4th grade received when prime level passes control signal.
STV signals pass control signal by the 1st grade of upper level level and receive input (now STV signals is just are sweeping up when just sweeping
Beginning trigger signal), it is anti-control signal is passed by the next stage level of afterbody (the 4th grade) when sweeping to receive input (now STV signals are
It is counter to sweep up beginning trigger signal).
(the 1st grade is CK1/CK2 to the order of clock signal (CK1 and CK2) access circuit, and the 2nd grade is CK2/ for hop jump step by step
CK1,3rd level CK1/CK2 ...).When the driving of GOA circuits as shown in Figure 6 can be realized based on circuits cascading structure shown in Fig. 4
Sequence.In figure 6, left figure and right figure are respectively just being swept and the anti-signal timing diagram swept under state.
To sum up, according to the present invention scan drive circuit and display device, can depart from U2D/D2U signals realize it is positive and negative
Sweep function.The signal wire and device of circuit are greatly reduced, and not only beneficial to narrow frame design, and reduce the power consumption of circuit.
Also, the method for the present invention need not change existing GOA circuit units structure, realize that difficulty is low, have higher promotion price
Value.
While it is disclosed that embodiment as above, but described content only to facilitate understand the present invention and adopt
Embodiment, it is not limited to the present invention.Method of the present invention can also have other various embodiments.Without departing substantially from
In the case of essence of the present invention, those skilled in the art, which work as, can make various corresponding changes or become according to the present invention
Shape, but these corresponding changes or deformation should all belong to the scope of the claims of the present invention.
Claims (9)
1. a kind of scan drive circuit, it is characterised in that the circuit includes input block, latch unit, NAND gate signal
Processing unit and output buffer cell, wherein：
The input block passes control signal, when prime level passes control signal and next stage including being connected respectively to upper level level
Level passes the input of the first control signal, the input of the second control signal, the input of the 3rd control signal of control signal, the input block
It is configured to by first control signal input of current sequential, second control signal input, the 3rd control
The different input combinations that signal inputs control the outputs of the input block to believe to export the prime level transmission control system of working as of next sequential
Number；
The latch unit is used for the latch that level passes signal, and the output end of the latch unit is used to export when prime level passes
Control signal, an input of the latch unit are connected to the output of the input block, the latch unit
Another input is connected to the first sequential input of the scan drive circuit；
One input of the NAND gate signal processing unit is connected to the second sequential input of the scan drive circuit, separately
One input is connected to the output end of the latch unit, and the NAND gate signal processing unit is configured to from described
The signal of second sequential input is carried out with non-process to export the grid when prime with the described of latch when prime level passes control signal
Pole drive signal；
The input of output buffer cell is connected to the output end of the NAND gate signal processing unit, the output buffer cell
For increasing the driving force of the gate drive signal, reduce the phase shift of transmission signal.
2. scan drive circuit according to claim 1, it is characterised in that：
There is one when the next stage level passes control signal or the upper level level and passes control signal to be high and described work as prime
When level biography control signal is low, the input block exports high level；
When described when it is high that prime level, which passes control signal, the input block exports low level.
3. scan drive circuit according to claim 2, it is characterised in that it is open-minded that the input block also includes high potential
The 4th transistor opened of the first transistor, second transistor, third transistor and low potential, wherein：
The grid of the first transistor and the second transistor connects first control signal input and described the respectively
Three control signals input, and the grid of the third transistor and the 4th transistor connects second control signal jointly
Input；
The source electrode of the first transistor and the second transistor is connected to high potential, the first transistor and described jointly
The drain electrode of two-transistor is connected to the source electrode of the 4th transistor jointly；
The source electrode of the third transistor is connected to low potential, and the drain electrode of the third transistor and the 4th transistor is common
It is connected to the output of the input block.
4. scan drive circuit according to claim 3, it is characterised in that the input block is also described including being connected to
Low potential between the drain electrode and the output of the input block of third transistor and the 4th transistor open the 5th
Transistor, wherein：
The source electrode of 5th transistor is connected to the drain electrode of the third transistor and the 4th transistor；
The drain electrode of 5th transistor is connected to the output of the input block；
The grid of 5th transistor is connected to the first sequential input.
5. scan drive circuit according to claim 4, it is characterised in that it is open-minded that the input block also includes low potential
The 6th transistor, wherein：
The source electrode of 6th transistor is connected to low potential；
The drain electrode of 6th transistor is connected to the output of the input block；
The grid of 6th transistor is connected to reset signal.
6. a kind of display device, it is characterised in that the display device includes multiple as any one of claim 1-4
Scan drive circuit and crystal liquid substrate, wherein：
The corresponding scan drive circuit of each liquid crystal pixel row on the crystal liquid substrate；
The output end of the output buffer cell of each scan drive circuit is connected to sweeping for the corresponding liquid crystal pixel row
Retouch in driving input；
Multiple scan drive circuits according to the liquid crystal pixel row corresponding to it the mutual cascade that puts in order.
7. display device according to claim 6, it is characterised in that：
First control signal input of the scan drive circuit corresponding to liquid crystal pixel row described in any row is connected to
Corresponding to liquid crystal pixel row described in a line in the output of the latch unit of the scan drive circuit；
Second control signal input of the scan drive circuit corresponding to liquid crystal pixel row described in any row, which is connected to, works as
Move ahead corresponding to the liquid crystal pixel row in the output of the latch unit of the scan drive circuit；
The 3rd control signal input of the scan drive circuit corresponding to liquid crystal pixel row described in any row is connected to down
Corresponding to liquid crystal pixel row described in a line in the output of the latch unit of the scan drive circuit.
8. display device according to claim 7, it is characterised in that：
The first sequential input of the scan drive circuit corresponding to liquid crystal pixel row described in any row and the liquid of adjacent lines
The second sequential input of the scan drive circuit corresponding to brilliant pixel column is together connected to the first sequential of the display device
On signal；
The second sequential input of the scan drive circuit corresponding to liquid crystal pixel row described in any row and the liquid of adjacent lines
The first sequential input of the scan drive circuit corresponding to brilliant pixel column is together connected to the second sequential of the display device
On signal.
9. display device according to claim 8, it is characterised in that：
First control signal input of the scan drive circuit corresponding to liquid crystal pixel row described in the first row is connected to just
Sweep up beginning trigger signal；
The 3rd control signal input of the scan drive circuit corresponding to liquid crystal pixel row described in last column is connected to
It is counter to sweep up beginning trigger signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
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| CN105702223B (en) * | 2016-04-21 | 2018-01-30 | 武汉华星光电技术有限公司 | Reduce the CMOS GOA circuits of load clock signal |
| CN105788557B (en) | 2016-05-20 | 2018-06-19 | 武汉华星光电技术有限公司 | GOA driving circuits |
| CN105810165B (en) * | 2016-05-20 | 2018-09-28 | 武汉华星光电技术有限公司 | A kind of CMOS GOA circuit structures and liquid crystal display panel |
| CN106057131B (en) * | 2016-05-27 | 2018-11-23 | 武汉华星光电技术有限公司 | Scan drive circuit and flat display apparatus with the circuit |
| CN105869590B (en) * | 2016-05-30 | 2018-12-11 | 武汉华星光电技术有限公司 | Liquid crystal display and its demultiplexer circuit |
| CN106098015B (en) * | 2016-08-23 | 2018-11-23 | 武汉华星光电技术有限公司 | Gate driving circuit |
| CN106128349B (en) * | 2016-08-29 | 2019-01-22 | 武汉华星光电技术有限公司 | Flat display apparatus and its scan drive circuit |
| US10373578B2 (en) | 2016-11-28 | 2019-08-06 | Wuhan China Star Optoelectronics Technology Co., Ltd. | GOA driving circuit |
| CN106409261B (en) * | 2016-11-29 | 2020-09-04 | 武汉华星光电技术有限公司 | GOA drive circuit |
| CN106782358B (en) * | 2016-11-29 | 2020-01-17 | 武汉华星光电技术有限公司 | GOA drive circuit |
| CN106935181A (en) * | 2017-05-22 | 2017-07-07 | 厦门天马微电子有限公司 | Gate driving circuit |
| CN107657927B (en) * | 2017-09-27 | 2019-07-12 | 武汉华星光电技术有限公司 | Scan drive circuit and display device |
| CN107424582B (en) * | 2017-09-27 | 2019-08-30 | 武汉华星光电技术有限公司 | Scan drive circuit and display device |
| WO2020073231A1 (en) * | 2018-10-10 | 2020-04-16 | 深圳市柔宇科技有限公司 | Goa circuit and display device |
| CN111429828A (en) * | 2020-04-13 | 2020-07-17 | 深圳市华星光电半导体显示技术有限公司 | Display panel and display device |
| CN111477153A (en) * | 2020-05-08 | 2020-07-31 | 武汉华星光电技术有限公司 | GOA circuit and display panel |
| CN115862509A (en) * | 2022-11-29 | 2023-03-28 | 厦门天马微电子有限公司 | Display panel, driving method of display panel and display device |
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