CN110111831A - Shift register, gate driving circuit and display device - Google Patents
Shift register, gate driving circuit and display device Download PDFInfo
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- CN110111831A CN110111831A CN201910336072.6A CN201910336072A CN110111831A CN 110111831 A CN110111831 A CN 110111831A CN 201910336072 A CN201910336072 A CN 201910336072A CN 110111831 A CN110111831 A CN 110111831A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Liquid Crystal Display Device Control (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Shift Register Type Memory (AREA)
Abstract
The invention discloses a kind of shift register, gate driving circuit and display devices, wherein shift register includes: output module, node control module, node charging module, scan control module and reseting module；Scan control module is used in the case where just sweeping the control of signal at input signal end, the signal for just sweeping control signal end is supplied to input node, or under the control of the anti-signal for sweeping input signal end, the anti-signal for sweeping control signal end is supplied to input node.Since scan control module is by the control at input signal end, therefore during Non-scanning mode, scan control module can make input node at floating state, and then keep first node at floating state by node charging module, the current potential of first node would not be leaked electricity by input node in this way, so that the current potential of first node be made to be maintained.
Description
Technical field
The present invention relates to field of display technology, espespecially a kind of shift register, gate driving circuit and display device.
Background technique
In panel display board, usually by each thin film transistor (TFT) from gate driving circuit to pixel region (TFT,
Thin Film Transistor) grid provide grid open signal.Gate driving circuit can be formed by array processes
In the array substrate of panel display board, i.e., array substrate row drives (Gate Driver on Array, GOA) technique, this
Kind integrated technique not only saves cost, and can accomplish the symmetrical design for aesthetic in the both sides panel display board (Panel), together
When, it also eliminates the binding region (Bonding) of grid integrated circuits (IC, Integrated Circuit) and is fanned out to
(Fan-out) wiring space, so as to realize the design of narrow frame.
Existing gate driving circuit, as shown in Figure 1, by multiple cascade shift registers: SR (1), SR (2) ... SR
(n), SR (n+1) ... SR (N-1), SR (N) (N number of shift register altogether, 1≤n≤N) composition, shift register SR (n) at different levels are used
The signal output end Output_n of this grade of shift register SR (n) of Yu Xiangyu connected grid line provides grid open signal to open
The TFT of the pixel region of corresponding row.Wherein, in addition to first order shift register SR (1), remaining shift register SR at different levels
(n) input signal end Input_n respectively with the signal output end Output_n-1 phase of upper level shift register SR (n-1)
Even.It wherein include the pull-up node of control signal output output grid open signal in shift register SR (n) at different levels, and
When the current potential of pull-up node is further pulled up, signal output end exports grid open signal.
Currently, in touch-control and the touch-control display panel of display timesharing driving, i.e., in the temporal interpolation for showing a frame picture
Enter multiple touch-control periods, and general each touch-control period needs the time interval of certain time length, it is assumed that shift at n-th grade
Enter the touch-control period after the completion of the signal output end output grid open signal of register, at this time (n+1)th grade of shift register
In the current potential of pull-up node have been changed to high level, since touch-control period interval time is longer, (n+1)th grade during this period
Pull-up node in shift register drain conditions can occur by TFT connected to it, to make the electricity of the pull-up node
Potential drop is low, and after the touch-control period, (n+1)th grade of shift register is started to work, since the current potential of its pull-up node declines
Subtract, the grid open signal that will cause the shift register output generates decaying, and when serious, corresponding row grid line, which can not receive, to be swept
Signal is retouched, corresponding pixel can not execute display function, to the concealed wire phenomenon that one-row pixels do not work occur, reduce display
Quality.
Summary of the invention
In view of this, the embodiment of the invention provides a kind of shift register, gate driving circuit and display device, to
Solve the problems, such as that there are concealed wires in display picture in the prior art.
A kind of shift register provided in an embodiment of the present invention, comprising: output module, node control module, node charging
Module, scan control module and reseting module；
The output module is used under the control of the signal of first node, and the signal of the first clock signal terminal is supplied to
Grid signal output end, or under the control of the signal of second node, the signal of the first reference voltage end is supplied to described
Grid signal output end；
The node control module is used for according to the signal of the first node or the signal of the second node, control
The level of the signal of the first node and the second node is opposite；
The node charging module includes the first control terminal, and the node charging module is used in first control terminal
The signal of input node is supplied to the first node under the control of signal；
The scan control module is used in the case where just sweeping the control of signal at input signal end, will just sweep control signal end
Signal is supplied to the input node, or under the control of the anti-signal for sweeping input signal end, by anti-control signal end of sweeping
Signal is supplied to the input node；
The reseting module includes reseting controling end, and the reseting module is for right under the control of the reseting controling end
The current potential of the first node is resetted, and the signal of the second reference voltage end is supplied to the second node.
Correspondingly, the embodiment of the invention also provides a kind of gate driving circuits, including N number of cascade embodiment of the present invention
Any of the above-described kind of shift register provided, wherein N is the integer greater than 2.
Correspondingly, the embodiment of the invention also provides a kind of display devices, comprising:
Viewing area and non-display area；
The viewing area includes a plurality of grid line, insulate the multiple data lines intersected with the grid line；
The non-display area includes above-mentioned gate driving circuit provided in an embodiment of the present invention, each shift register
The grid signal output end be electrically connected with a grid line.
The present invention has the beneficial effect that:
Above-mentioned shift register, gate driving circuit and display device provided in an embodiment of the present invention, wherein shift LD
Device includes: output module, node control module, node charging module, scan control module and reseting module；Scan control module
For in the case where just sweeping the control of signal at input signal end, the signal for just sweeping control signal end to be supplied to input node, or
Under the control of the anti-signal for sweeping input signal end, the anti-signal for sweeping control signal end is supplied to input node.Due to scanning
Control module is by the control at input signal end, therefore during Non-scanning mode, scan control module can make input node be in floating
State is set, and then keeps first node at floating state by node charging module, the current potential of such first node would not lead to
It crosses input node to leak electricity, so that the current potential of first node be made to be maintained.When shift register restores from during Non-scanning mode
To during scanning, when working normally to export scanning signal to grid line, output module can be in the control of the signal of first node
It is supplied to grid signal output end under system, by the signal of the first clock signal terminal, so that shift register is normally to grid line
Scanning signal is exported, so as to improve the problem of output signal exception, improvement when shift register is again introduced into during scanning
Concealed wire phenomenon.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of existing gate driving circuit；
Fig. 2 is the structural schematic diagram for the shift register that an embodiment of the present invention provides；
Fig. 3 is the structural schematic diagram for the shift register that another embodiment of the invention provides；
Fig. 4 is the structural schematic diagram for the shift register that another embodiment of the present invention provides；
Fig. 5 is the structural schematic diagram for the shift register that another embodiment of the present invention provides；
Fig. 6 is the structural schematic diagram for the shift register that another embodiment of the present invention provides；
Fig. 7 is a kind of corresponding circuit timing diagram of shift register shown in fig. 6；
Fig. 8 is the corresponding another circuit timing diagram of shift register shown in fig. 6；
Fig. 9 is the structural schematic diagram of gate driving circuit provided in an embodiment of the present invention；
Figure 10 is the structural schematic diagram of display device provided in an embodiment of the present invention.
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with attached drawing to the present invention make into
It is described in detail to one step, it is clear that the described embodiment is only a part of the embodiment of the present invention, instead of all the embodiments.
Based on the embodiments of the present invention, obtained by those of ordinary skill in the art without making creative efforts all
Other embodiments shall fall within the protection scope of the present invention.
The shapes and sizes of each component do not reflect actual proportions in attached drawing, and purpose is schematically illustrate the content of present invention
A kind of shift register provided in an embodiment of the present invention, as shown in Figure 2, comprising: output module 03, node control mould
Block 01, node charging module 02, scan control module 04 and reseting module 05；
Output module 03 is used under the control of the signal of first node N1, and the signal of the first clock signal terminal CK1 is mentioned
Grid signal output end GOUT is supplied, or under the control of the signal in second node N2, by the letter of the first reference voltage end VGL
Number it is supplied to grid signal output end GOUT；
Node control module 01 is used to control first segment according to the signal of first node N1 or the signal of second node N2
The level of the signal of point N1 and second node N2 is opposite；
Node charging module 02 includes the first control terminal SET, and node charging module 02 is used for the letter in the first control terminal SET
Number control under the signal of input node IN is supplied to first node N1；
Scan control module 04 is used in the case where just sweeping the control of signal of input signal end INF, will just sweep control signal end
The signal of U2D is supplied to input node IN, or under the control of the anti-signal for sweeping input signal end INB, sweeps control letter for counter
Number end D2U signal be supplied to input node IN；
Reseting module 05 includes reseting controling end RST, and reseting module 05 is used under the control of reseting controling end RST to the
The current potential of one node N1 is resetted, and the signal of the second reference voltage end VGH is supplied to second node N2.
Shift register provided in this embodiment, scan control module 04 are used in the signal for just sweeping input signal end INF
Control under, the signal for just sweeping control signal end U2D is supplied to input node IN, or sweep input signal end INB's counter
Under the control of signal, the anti-signal for sweeping control signal end D2U is supplied to input node IN, in this way, during Non-scanning mode, scanning
Control module 04 makes input node IN be in floating under the control just swept input signal end INF or counter and sweep input signal end INB
State, and then keep first node N1 at floating state by node charging module 02, lead to the current potential of first node N1 will not
It crosses input node IN to leak electricity, so that the current potential of first node N1 be made to be maintained.When shift register is from during Non-scanning mode
Restore to during scanning, when working normally to export scanning signal to grid line, output module 03 can be first node N1's
It is supplied to grid signal output end GOUT under the control of signal, by the signal of the first clock signal terminal CK1, so that shift register
Scanning signal normally is exported to grid line, output signal is different when so as to improve during shift register is again introduced into scanning
Normal problem improves concealed wire phenomenon.
In the present embodiment, during the Non-scanning mode of shift register, as shift register suspends to export to grid line and scan
During signal.
Specifically, in a display device, when forward scan, general first order shift register just sweeps input signal end
For INF for receiving commencing signal, the other grades of shift registers other than first order shift register just sweep input signal
End INF is used to receive the signal of the grid signal output end GOUT output of previous stage shift register.When reverse scan, generally most
The anti-input signal end INB that sweeps of rear stage shift register for receiving commencing signal, in addition to afterbody shift register it
The anti-input signal end INB that sweeps of other grades of outer shift registers is for receiving the grid signal output of rear stage shift register
Hold the signal of GOUT output.
Optionally, in shift register provided in an embodiment of the present invention, as shown in figure 3, further including discharge module 06；
Discharge module 06 includes discharge control terminal GAS, and discharge module 06 is used under the control of discharge control terminal GAS, will
The signal of first reference voltage end VGL is respectively supplied to first node N1 and second node N2, by the second reference voltage end VGH's
Signal is supplied to grid signal output end GOUT.
In the specific implementation, discharge module 06 is under the control of discharge control terminal GAS, by the first reference voltage end VGL's
Signal is respectively supplied to first node N1 and second node N2, to make the first node N1 and second node N2 of shift register
It discharges, realizes the internal discharge of shift register.Discharge module 06 is under the control of discharge control terminal GAS, by the second ginseng
The signal for examining voltage end VGH is supplied to grid signal output end GOUT, and what grid signal output end GOUT was generally connected is one
Row pixel, so as to realize the electric discharge of corresponding row pixel.
Optionally, in shift register provided in an embodiment of the present invention, as shown in figure 4, further including resetting control module
07；
It resets control module 07 to be used in the case where just sweeping the control of signal of control signal end U2D, by second clock signal end
The signal of CK2 is supplied to reseting controling end RST, or under the control of the anti-signal for sweeping control signal end D2U, by third clock
The signal of signal end CK3 is supplied to reseting controling end RST.To be further ensured that shift register in grid signal output end
It can be resetted in time after GOUT output grid signal.
Combined with specific embodiments below, the present invention is described in detail.It should be noted that be in the present embodiment in order to
It preferably explains the present invention, but does not limit the present invention.
It should be noted that in specific implementation, it can be according to the type of transistor and the signal of its grid, by crystal
First pole of pipe is as its source electrode, and the second pole is as its drain electrode；Alternatively, conversely, using the first pole of transistor as its drain electrode, the
Specific differentiation is not done herein as its source electrode in two poles.
It should be noted that common, transistor is divided into N-type transistor and P-type transistor.Wherein, N-type transistor is in height
It is connected under the control of level signal, ends under the control of low level signal；P-type transistor is led under the control of low level signal
It is logical, end under the control of high level signal.
Optionally, in shift register provided in an embodiment of the present invention, as shown in Figure 5 and Figure 6,
Node control module 01 includes the first transistor T1, second transistor T2 and third transistor T3；
The grid of the first transistor T1 is connect with second node N2, the first pole of the first transistor T1 and the first reference voltage
VGL connection is held, the second pole of the first transistor T1 is connect with first node N1；
The grid of second transistor T2 is connect with input node IN, the first pole of second transistor T2 and the first reference voltage
VGL connection is held, the second pole of second transistor T2 is connect with second node N2；
The grid of third transistor T3 is connect with first node N1, the first pole of third transistor T3 and the first reference voltage
VGL connection is held, the second pole of third transistor T3 is connect with second node N2.
In the present embodiment, second node N2 is used to control the on or off of the first transistor T1, works as first crystal
When pipe T1 is connected, the signal of the first reference voltage end VGL can be transmitted to first node N1；Input node IN is for controlling second
The on or off of transistor T2, when second transistor T2 conducting, the signal of the first reference voltage end VGL can be transmitted to
Second node N2；First node N1 is used to control the on or off of third transistor T3, when third transistor T3 conducting,
The signal of first reference voltage end VGL can be transmitted to second node N2.
Optionally, in shift register provided in an embodiment of the present invention, as shown in Figure 5 and Figure 6, node charging module 02
Including the 4th transistor T4；
The grid of 4th transistor T4 is connect with the first control terminal SET, the first pole of the 4th transistor T4 and input node
IN connection, the second pole of the 4th transistor T4 are connect with first node N1.
In embodiment, the first control terminal SET is used to control the on or off of the 4th transistor T4, when the 4th crystal
When pipe T4 is connected, the signal of input node IN can be transmitted to first node N1.
Optionally, in shift register provided in an embodiment of the present invention, as shown in Figure 4 and Figure 5, output module 03 includes
5th transistor T5, the 6th transistor T6, first capacitor C1 and the second capacitor C2；
The grid of 5th transistor T5 is connect with second node N2, the first pole of the 5th transistor T5 and the first reference voltage
VGL connection is held, the second pole of the 5th transistor T5 is connect with grid signal output end GOUT；
The grid of 6th transistor T6 is connect with first node N1, the first pole of the 6th transistor T6 and the first clock signal
CK1 connection is held, the second pole of the 6th transistor T6 is connect with grid signal output end GOUT；
The first pole of first capacitor C1 is connect with the first reference voltage end VGL, and the second pole is connect with second node N2；
The first pole of second capacitor C2 is connect with first node N1, and the second pole is connect with grid signal output end GOUT.
In the present embodiment, second node N2 is used to control the on or off of the 5th transistor T5, when the 5th crystal
When pipe T5 is connected, the signal of the first reference voltage end VGL can be transmitted to grid signal output end GOUT；First node N1 is used for
The on or off for controlling the 6th transistor T6, when the 6th transistor T6 conducting, the signal of the first clock signal terminal CK1 can
To be transmitted to grid signal output end GOUT；First capacitor C1 and the second capacitor C2 has coupling, can be used for stablizing the
The current potential of one node N1 and second node N2.In the present embodiment, due to node control module 01 can control first node N1 and
The current potential of second node N2 on the contrary, to by first node N1 the 6th transistor T6 controlled and controlled by second node N2 the
One of five transistor T5 conducting, another one cut-off, correspondingly, grid signal output end GOUT exports the first reference voltage end
The signal of the signal of VGL or the first clock signal terminal CK1, to guarantee that grid signal output end GOUT will not export simultaneously
The signal of the signal of one reference voltage end VGL and the first clock signal terminal CK1.
Optionally, in shift register provided in an embodiment of the present invention, as shown in Figure 5 and Figure 6, scan control module 04
Including the 7th transistor T7 and the 8th transistor T8；
The grid of 7th transistor T7 is connect with input signal end INF is just swept, the first pole of the 7th transistor T7 with just sweep
Control signal end U2D connection, the second pole of the 7th transistor T7 is connect with input node IN；
The grid of 8th transistor T8 is connect with the anti-input signal end INB that sweeps, and the first pole of the 8th transistor T8 is swept with counter
Control signal end D2U connection, the second pole of the 8th transistor T8 is connect with input node IN.
In the present embodiment, input signal end INF is just being swept for controlling the on or off of the 7th transistor T7, when the
When seven transistor T7 are connected, the signal for just sweeping control signal end U2D can be transmitted to input node IN；It is counter to sweep input signal end
INB is used to control the on or off of the 8th transistor T8, counter to sweep control signal end D2U when the 8th transistor T8 conducting
Signal can be transmitted to input node IN.7th transistor T7 or the 8th transistor T8 are only just led when there is input signal
It is logical, i.e. input node IN in addition to that can be connected when just sweeping input signal end INF or counter and sweeping input signal end INB and have input signal,
It is at floating state when other time, it is equivalent to the electric leakage along the direction input node IN for having blocked first node N1, thus
The current potential of first node N1 can be made to be maintained.
Optionally, in shift register provided in an embodiment of the present invention, as shown in Figure 5 and Figure 6, reseting module 05 includes
9th transistor T9 and the tenth transistor T10；
The grid of 9th transistor T9 is connect with reseting controling end RST, the first pole of the 9th transistor T9 and input node
IN connection, the second pole of the 9th transistor T9 are connect with first node N1；
The grid of tenth transistor T10 is connect with reseting controling end RST, the first pole of the tenth transistor T10 and the second ginseng
Voltage end VGH connection is examined, the second pole of the tenth transistor T10 is connect with second node N2.
In the present embodiment, reseting controling end RST is used to control the on or off of the 9th transistor T9, when the 9th crystalline substance
When body pipe T9 is connected, the current potential of input node IN can be transmitted to first node N1；Reseting controling end RST is brilliant for controlling the tenth
The on or off of body pipe T10, when the tenth transistor T10 conducting, the signal of the second reference voltage end VGH can be transmitted to
Second node N2.
Optionally, in shift register provided in an embodiment of the present invention, the channel width-over-length ratio of the tenth transistor T10 is distinguished
The channel width-over-length ratio of channel width-over-length ratio and third transistor T3 greater than second transistor T2.This is in order in reseting stage
The current potential of two node N2 is controlled by the tenth transistor T10, to guarantee that the current potential of second node N2 is the second reference voltage end VGH
Current potential.
Optionally, in shift register provided in an embodiment of the present invention, as shown in Figure 5 and Figure 6, control module 07 is resetted
Including the 11st transistor T11 and the tenth two-transistor T12；
The grid of 11st transistor T11 is connect with control signal end U2D is just swept, the first pole of the 11st transistor T11
It is connect with second clock signal end CK2, the second pole of the 11st transistor T11 is connect with reseting controling end RST；
The grid of tenth two-transistor T12 is connect with the anti-control signal end D2U that sweeps, the first pole of the tenth two-transistor T12
It is connect with third clock signal terminal CK3, the second pole of the tenth two-transistor T12 is connect with reseting controling end RST.
In the present embodiment, the on or off that control signal end U2D is used to control the 11st transistor T11 is just being swept,
When the 11st transistor T11 conducting, the signal of second clock signal end CK2 can be transmitted to reseting controling end RST；It is counter to sweep control
Signal end D2U processed is used to control the on or off of the tenth two-transistor T12, when the tenth two-transistor T12 conducting, third
The signal of clock signal terminal CK3 can be transmitted to reseting controling end RST.
Optionally, in shift register provided in an embodiment of the present invention, as shown in Figure 5 and Figure 6,
Discharge module 06 includes the 13rd transistor T13, the 14th transistor T14 and the 15th transistor T15；
The grid of 13rd transistor T13 is connect with discharge control terminal GAS, the first pole of the 13rd transistor T13 and the
One reference voltage end VGL connection, the second pole of the 13rd transistor T13 is connect with first node N1；
The grid of 14th transistor T14 is connect with discharge control terminal GAS, the first pole of the 14th transistor T14 and the
One reference voltage end VGL connection, the second pole of the 14th transistor T14 is connect with second node N2；
The grid of 15th transistor T15 is connect with discharge control terminal GAS, the first pole of the 15th transistor T15 and the
Two reference voltage end VGH connections, the second pole of the 15th transistor T15 is connect with grid signal output end GOUT.
In the present embodiment, discharge control terminal GAS is used for while controlling the 13rd transistor T13, the 14th transistor T14
With the on or off of the 15th transistor T15, when the 13rd transistor T13 conducting, the signal of the first reference voltage end VGL
It can be transmitted to first node N1, when the 14th transistor T14 conducting, the signal of the first reference voltage end VGL can be transmitted
To second node N2, when the 15th transistor T15 conducting, the signal of the second reference voltage end VGH can be transmitted to grid letter
Number output end GOUT.
Optionally, in shift register provided in an embodiment of the present invention, as shown in fig. 6, further including the 16th transistor
T16；
First node N1 is cycle of sixty years node N1a and second child node N1b by the 16th transistor T16 points；
The first pole of 16th transistor T16 is connect with cycle of sixty years node N1a, the second pole of the 16th transistor T16 and second
Child node N1b connection, the grid of the 16th transistor T16 are connect with the second reference voltage end VGH, the second reference voltage end VGH
Signal control the 16th transistor T16 conducting.
In the present embodiment, the second reference voltage end VGH controls the 16th transistor T16 conducting, to make cycle of sixty years node
N1a is connected with second child node N1b.
The above is only the specific structures for illustrating each module in shift register, in the specific implementation, the tool of each module
Body structure is not limited to above structure provided in an embodiment of the present invention, can also be skilled person will appreciate that other structures,
It is not limited here.
It should be noted that in shift register provided in an embodiment of the present invention, when all transistors are N-type crystal
The signal of Guan Shi, the first reference voltage end VGL are low level signal, and the signal of the second reference voltage end VGH is high level signal；
When all transistors are P-type transistor, the signal of the first reference voltage end VGL is high level signal, the second reference voltage
The signal for holding VGH is low level signal.
In shift register provided in an embodiment of the present invention, the first clock signal terminal CK1, second clock signal end CK2,
The signal of third clock signal terminal CK3 is pulse signal, also, the signal of the first control terminal SET may be pulse signal.
Below with reference to Fig. 7 and circuit timing diagram shown in Fig. 8, by taking shift register shown in fig. 6 as an example, to of the invention real
Course of work when applying the shift register progress forward scan of example offer is described.High level is indicated in described below with 1,
0 indicates low level.It should be noted that 1 and 0 is logic level, merely to preferably explaining the tool of the embodiment of the present invention
Body running process, rather than specific voltage value.
Specifically, by taking forward scan as an example, when during shift register being constantly in scanning, corresponding timing such as Fig. 7
It is shown.
In forward scan, D2U=0, the tenth two-transistor T12 cut-off；GAS=0, the 13rd transistor T13, the 14th
Transistor T14 and the 15th transistor T15 are turned off；U2D=1, the 11st transistor T11 conducting.
In t1 stage (i.e. input phase), INF=1, SET=1, CK1=0, CK2=0, CK3=0.
The anti-signal for sweeping input signal end INB controls the 8th transistor T8 cut-off, the 4th transistor T4, the 7th transistor T7
It is connected with the 16th transistor T16, the high level signal for just sweeping control signal end U2D is transmitted to input by the 7th transistor T7
Node IN, therefore the current potential of input node IN is high potential.The high potential of input node IN is transmitted to by the 4th transistor T4
Cycle of sixty years node N1a, after through the 16th transistor T16 be transmitted to second child node N1b；Therefore the current potential of first node N1 is height
Current potential, third transistor T3 and the 6th transistor T6 conducting under the control of first node N1, the first reference voltage end VGL's is low
Level signal is transmitted to second node N2 by third transistor T3, and the current potential of second node N2 is low potential.First clock letter
The low level signal of number end CK1 is transmitted to grid signal output end GOUT by the 6th transistor T6, therefore grid signal output
The current potential for holding GOUT is low potential.Input node IN controls second transistor T2 conducting, the low level of the first reference voltage end VGL
Signal is transmitted to second node N2 by second transistor T2, is further ensured that the current potential of second node N2 is low potential.?
Under the control of two node N2, the first transistor T1 and the 5th transistor T5 cut-off.The low level signal of second clock signal end CK2
It is transmitted to reseting controling end RST by the 11st transistor T11, the current potential of reseting controling end RST is low potential, reseting controling end
RST controls the 9th transistor T9 and the tenth transistor T10 cut-off.The current potential phase of the stage, first node N1 and second node N2
Instead.
In the t2 stage, INF=0, SET=0, CK1=0, CK2=0, CK3=1.
The anti-signal for sweeping input signal end INB controls the 8th transistor T8 cut-off.7th transistor T7 and the 4th transistor
T4 cut-off, the cycle of sixty years, node N1a was at floating state, and the cycle of sixty years current potential of node N1a still keeps high potential, passed through the 16th transistor
T16 makes the current potential of second child node N1b still be high potential, and cycle of sixty years node N1a controls third transistor T3 conducting, the first reference voltage
The low level signal of VGL is held to be transmitted to second node N2 by third transistor T3, the current potential of second node N2 is low potential.Second
Child node N1b controls the 6th transistor T6 conducting, and the low level signal of the first clock signal terminal CK1 is passed by the 6th transistor T6
Grid signal output end GOUT is transported to, therefore the current potential of grid signal output end GOUT is still low potential.Input node IN control
Second transistor T2 conducting, the low level signal of the first reference voltage end VGL are transmitted to second node by second transistor T2
N2 is further ensured that the current potential of second node N2 is low potential.Under the control of second node N2, the first transistor T1 and the 5th
Transistor T5 cut-off.The low level signal of second clock signal end CK2 is transmitted to reseting controling end by the 11st transistor T11
The current potential of RST, reseting controling end RST are low potential, and reseting controling end RST controls the 9th transistor T9 and the tenth transistor T10
Cut-off.The current potential of the stage, first node N1 and second node N2 are opposite.
In t3 stage (i.e. output stage), INF=0, SET=0, CK1=1, CK2=0, CK3=0.
The anti-signal for sweeping input signal end INB controls the 8th transistor T8 cut-off, the 7th transistor T7 and the 4th transistor
T4 cut-off, the cycle of sixty years, node N1a was at floating state, and the cycle of sixty years current potential of node N1a still keeps high potential, passed through the 16th transistor
T16 makes the current potential of second child node N1b still be high potential, and cycle of sixty years node N1a controls third transistor T3 conducting, the first reference voltage
The low level signal of VGL is held to be transmitted to second node N2 by third transistor T3, the current potential of second node N2 is low potential.Second
Child node N1b controls the 6th transistor T6 conducting, and the high level signal of the first clock signal terminal CK1 is passed by the 6th transistor T6
Grid signal output end GOUT is transported to, therefore the current potential of grid signal output end GOUT becomes high potential.Due to the second capacitor C2
Boot strap, the current potential of second child node N1b is further pulled up, to guarantee the stability of output.Input node IN control
Second transistor T2 conducting, the low level signal of the first reference voltage end VGL are transmitted to second node by second transistor T2
N2 is further ensured that the current potential of second node N2 is low potential.Under the control of second node N2, the first transistor T1 and the 5th
Transistor T5 cut-off.The low level signal of second clock signal end CK2 is transmitted to reseting controling end by the 11st transistor T11
RST, the current potential of reseting controling end RST are still low potential, and reseting controling end RST controls the 9th transistor T9 and the tenth transistor
T10 cut-off.The current potential of the stage, first node N1 and second node N2 are opposite.
In t4 stage (i.e. reseting stage), INF=0, SET=0, CK1=0, CK2=1, CK3=0.
Second clock signal end CK2 controls the 11st transistor T11 conducting, is just sweeping the high level letter of control signal end U2D
Number reseting controling end RST is transmitted to by the 11st transistor T11, reseting controling end RST you control the 9th transistor T9 and
Ten transistor T10 conducting, the high level signal of the second reference voltage end VGH are transmitted to second node by the tenth transistor T10
N2, the current potential of second node N2 become high potential, and second node N2 controls the 5th transistor T5 and the first transistor T1 conducting, the
The low level signal of one reference voltage end VGL is transmitted to cycle of sixty years node N1a, the electricity of cycle of sixty years node N1a by the first transistor T1
Position becomes low potential, after through the 16th transistor T16 be transmitted to second child node N1b, the current potential of second child node N1b becomes low electricity
Position.Cycle of sixty years node N1a controls third transistor T3 cut-off, and second child node N1b controls the 6th transistor T6 cut-off.First with reference to electricity
The low level signal of pressure side VGL is transmitted to grid signal output end GOUT, grid signal output end by the 5th transistor T5
The current potential of GOUT becomes low potential.It is just sweeping input signal end INF and is controlling the 7th transistor T7 cut-off, the low electricity of cycle of sixty years node N1a
Ordinary mail number is transmitted to input node IN by the 9th transistor T9, and the current potential of input node IN becomes low potential, the first control terminal
SET controls the 4th transistor T4 cut-off.The current potential of the stage, first node N1 and second node N2 are opposite.
After the t4 stage, input signal is just swept until being received again by, the current potential of first node N1 is always maintained at high potential, the
The current potential of two node N2 is always maintained at low potential, and the current potential of grid signal output end GOUT always remains as low potential.
Specifically, when shift register during Non-scanning mode from when restoring to during scanning, corresponding timing is as shown in Figure 8.
In forward scan, D2U=0, the tenth two-transistor T12 cut-off；GAS=0, the 13rd transistor T13, the 14th
Transistor T14 and the 15th transistor T15 are turned off；U2D=1, the 11st transistor T11 conducting.
The working principle in t1, t2, t3 and t4 stage is identical in the working principle in t1, t2, t3 and t4 stage as above-mentioned Fig. 7,
Therefore not to repeat here.
In t0 stage (i.e. non-scanning phase).INF=0, SET=0, CK1=0, CK2=0, CK3=0, CK4=0.
7th transistor T7 and the 4th transistor T4 cut-off, the cycle of sixty years, node N1a was at floating state, cycle of sixty years node N1a's
Current potential still keeps high potential, and it is still high potential, cycle of sixty years node N1a that the current potential of second child node N1b is made by the 16th transistor T16
Third transistor T3 conducting is controlled, the low level signal of the first reference voltage end VGL is transmitted to second by third transistor T3
The current potential of node N2, second node N2 are low potential.Second child node N1b controls the 6th transistor T6 conducting, the first clock signal
The low level signal of end CK1 is transmitted to grid signal output end GOUT, therefore grid signal output end by the 6th transistor T6
The current potential of GOUT is still low potential.Under the control of second node N2, the first transistor T1 and the 5th transistor T5 cut-off.Input
Node IN controls second transistor T2 cut-off, and the low level signal of second clock signal end CK2 is passed by the 11st transistor T11
Reseting controling end RST is transported to, the current potential of reseting controling end RST is still low potential, and reseting controling end RST controls the 9th transistor T9
End with the tenth transistor T10.The current potential of the stage, first node N1 and second node N2 are opposite.
At this stage, since the 7th transistor T7 and the 8th Chengdu transistor T8 are in off state, input node
IN is floating state, and the 4th transistor T4 is off state, therefore is equivalent to and has blocked first node N1 along the 4th crystal
The electric leakage in the direction pipe T4, so as to so that the current potential of first node N1 is maintained.When shift register is from extensive during Non-scanning mode
During multiple extremely scanning, when working normally to export scanning signal to grid line, output module 03 can be in the letter of first node N1
Number control under, the signal of the first clock signal terminal CK1 is supplied to grid signal output end GOUT so that shift register is just
Normal exports scanning signal to grid line, and output signal is abnormal when so as to improve during shift register is again introduced into scanning
The problem of, improve concealed wire phenomenon.
In the specific implementation, similar when the working principle of reverse scan time shift bit register is to forward scan, do not make herein
It is described in detail.
Based on the same inventive concept, the embodiment of the invention also provides a kind of gate driving circuits, including N number of cascade
Invent the shift register that any of the above-described embodiment provides, wherein N is the positive integer greater than 2.Grid provided in this embodiment drives
Dynamic circuit can be applied to display panel, to drive a plurality of grid line in display panel.
Optionally, as shown in figure 9, the 1st grade of shift register just sweeps input signal end INF and just sweep frame trigger signal end
STVF coupling；In addition to the 1st grade of shift register, n-th grade of shift register just sweeps input signal end INF and (n-1)th grade of shifting
The grid signal output end GOUT of bit register is coupled；N grades of shift registers just sweep input signal end INF and N-1 grades
The grid signal output end GOUT of shift register is coupled；Wherein, n is the integer more than or equal to 1 and less than or equal to N-1.
Forward scan driving may be implemented in this way.
Alternatively, it is optional, as shown in figure 9, N grades of the counter of shift register sweep input signal in gate driving circuit
End INB and the anti-frame trigger signal end STVB that sweeps are coupled；In addition to N grades of shift registers, (n-1)th grade of the counter of shift register is swept
The grid signal output end GOUT of input signal end INB and n-th grade of shift register is coupled；1st grade of the counter of shift register is swept
The grid signal output end GOUT coupling of input signal end INB and the 2nd grade of shift register.Reverse scan drive may be implemented in this way
It is dynamic.
Further, in order to be switched under forward scan and reverse scan driving both of which, specific real
Shi Shi, as shown in figure 9, the input signal end INF that just sweeps of the 1st grade of shift register is coupled with frame trigger signal end STVF is just swept；
In addition to the 1st grade of shift register, n-th grade of shift register just sweeps input signal end INF and (n-1)th grade of shift register
Grid signal output end GOUT coupling；N grades of shift registers just sweep input signal end INF and N-1 grades of shift registers
Grid signal output end GOUT coupling.Also, the anti-input signal end INB that sweeps of N grades of shift registers is triggered with anti-frame of sweeping
Signal end STVB coupling；In addition to N grades of shift registers, (n-1)th grade of the counter of shift register sweeps input signal end INB and
The grid signal output end GOUT coupling of n grades of shift registers；1st grade of the counter of shift register sweeps input signal end INB and the 2nd
The grid signal output end GOUT coupling of grade shift register.It can be cut between forward scan and reverse scan in this way
It changes.
Further, in gate driving circuit provided in an embodiment of the present invention, as shown in figure 9, further including 4 clock letters
Number line: clk1, clk2, clk3 and clk4,4 clock cables are connect with shift registers at different levels respectively.
Specifically, the specific structure of each shift register in above-mentioned gate driving circuit is posted with the above-mentioned displacement of the present invention
Storage is all the same in function and structure, and overlaps will not be repeated.
Based on the same inventive concept, the present invention also provides a kind of display devices, incorporated by reference to reference Fig. 9 and Figure 10, comprising:
Viewing area AA and non-display area BB；Viewing area AA includes a plurality of gate lines G, insulate the multiple data lines S intersected with gate lines G；
Non-display area BB includes the driving circuit gr that any of the above-described embodiment of the present invention provides, and the grid signal of each shift register is defeated
Outlet GOUT is electrically connected with a gate lines G.
In the specific implementation, in the present invention is implemented, display device may include 2 driving circuits.Optionally, such as Figure 10
It is shown, the grid line in shift register connection display panel in each gate driving circuit, and this 2 grids
The shift register of same level-one in driving circuit connects same grid line.Alternatively, optional, 1 driving circuit connection is aobvious
Show the grid line of the odd-numbered line in panel, the grid line of the even number line in another 1 driving circuit connection display panel.
In the specific implementation, in the present invention is implemented, display device may include 1 driving circuit.
Display device provided in this embodiment, can be array substrate, be also possible to terminal display device, such as mobile phone,
Other display devices having a display function such as computer, TV, the present invention are not specifically limited this.The embodiment of the present invention provides
Display device, with driving circuit provided in an embodiment of the present invention beneficial effect, can specifically refer to the various embodiments described above.
For illustrating for driving circuit, details are not described herein for the present embodiment.
Above-mentioned shift register, gate driving circuit and display device provided in an embodiment of the present invention, wherein shift LD
Device includes: output module, node control module, node charging module, scan control module and reseting module；Scan control module
For in the case where just sweeping the control of signal at input signal end, the signal for just sweeping control signal end to be supplied to input node, or
Under the control of the anti-signal for sweeping input signal end, the anti-signal for sweeping control signal end is supplied to input node.Due to scanning
Control module is by the control at input signal end, therefore during Non-scanning mode, scan control module can make input node be in floating
State is set, and then keeps first node at floating state by node charging module, the current potential of such first node would not lead to
It crosses input node to leak electricity, so that the current potential of first node be made to be maintained.When shift register restores from during Non-scanning mode
To during scanning, when working normally to export scanning signal to grid line, output module can be in the control of the signal of first node
It is supplied to grid signal output end under system, by the signal of the first clock signal terminal, so that shift register is normally to grid line
Scanning signal is exported, so as to improve the problem of output signal exception, improvement when shift register is again introduced into during scanning
Concealed wire phenomenon.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
Mind and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (14)
1. a kind of shift register, which is characterized in that
It include: output module, node control module, node charging module, scan control module and reseting module；
The output module is used under the control of the signal of first node, and the signal of the first clock signal terminal is supplied to grid
Signal output end, or under the control of the signal of second node, the signal of the first reference voltage end is supplied to the grid
Signal output end；
The node control module is used for according to the signal of the first node or the signal of the second node, described in control
The level of the signal of first node and the second node is opposite；
The node charging module includes the first control terminal, and the node charging module is used for the signal in first control terminal
Control under the signal of input node is supplied to the first node；
The scan control module is used in the case where just sweeping the control of signal at input signal end, will just sweep the signal of control signal end
It is supplied to the input node, or under the control of the anti-signal for sweeping input signal end, by the anti-signal for sweeping control signal end
It is supplied to the input node；
The reseting module includes reseting controling end, and the reseting module is used under the control of the reseting controling end to described
The current potential of first node is resetted, and the signal of the second reference voltage end is supplied to the second node.
2. shift register as described in claim 1, which is characterized in that
It further include discharge module；
The discharge module includes discharge control terminal, and the discharge module is used under the control of the discharge control terminal, by institute
The signal for stating the first reference voltage end is respectively supplied to the first node and the second node, by second reference voltage
The signal at end is supplied to the grid signal output end.
3. shift register as described in claim 1, which is characterized in that
It further include resetting control module；
The reset control module is used under the control of the signal for just sweeping control signal end, by second clock signal end
Signal is supplied to the reseting controling end, or under the control of the anti-signal for sweeping control signal end, third clock is believed
Number end signal be supplied to the reseting controling end.
4. shift register as described in claim 1, which is characterized in that
The node control module includes the first transistor, second transistor and third transistor；
The grid of the first transistor is connect with the second node, the first pole of the first transistor and first ginseng
Voltage end connection is examined, the second pole of the first transistor is connect with the first node；
The grid of the second transistor is connect with the input node, the first pole of the second transistor and first ginseng
Voltage end connection is examined, the second pole of the second transistor is connect with the second node；
The grid of the third transistor is connect with the first node, the first pole of the third transistor and first ginseng
Voltage end connection is examined, the second pole of the third transistor is connect with the second node.
5. shift register as described in claim 1, which is characterized in that
The node charging module includes the 4th transistor；
The grid of 4th transistor is connect with first control terminal, the first pole of the 4th transistor and the input
Node connection, the second pole of the 4th transistor is connect with the first node.
6. shift register as described in claim 1, which is characterized in that
The output module includes the 5th transistor, the 6th transistor, first capacitor and the second capacitor；
The grid of 5th transistor is connect with the second node, the first pole of the 5th transistor and first ginseng
Voltage end connection is examined, the second pole of the 5th transistor is connect with the grid signal output end；
The grid of 6th transistor is connect with the first node, when the first pole of the 6th transistor is with described first
The connection of clock signal end, the second pole of the 6th transistor is connect with the grid signal output end；
First pole of the first capacitor is connect with first reference voltage end, and the second pole is connect with the second node；
First pole of second capacitor is connect with the first node, and the second pole is connect with the grid signal output end.
7. shift register as described in claim 1, which is characterized in that
The scan control module includes the 7th transistor and the 8th transistor；
The grid of 7th transistor is connect with the input signal end of just sweeping, the first pole of the 7th transistor with it is described
Control signal end connection is just being swept, the second pole of the 7th transistor is connect with the input node；
The grid of 8th transistor is connect with the anti-input signal end of sweeping, the first pole of the 8th transistor with it is described
Counter to sweep control signal end connection, the second pole of the 8th transistor is connect with the input node.
8. shift register as claimed in claim 4, which is characterized in that
The reseting module includes the 9th transistor and the tenth transistor；
The grid of 9th transistor is connect with the reseting controling end, the first pole of the 9th transistor and the input
Node connection, the second pole of the 9th transistor is connect with the first node；
The grid of tenth transistor is connect with the reseting controling end, the first pole of the tenth transistor with it is described
The connection of second reference voltage end, the second pole of the tenth transistor is connect with second node.
9. shift register as claimed in claim 8, which is characterized in that
The channel width-over-length ratio of tenth transistor is respectively greater than the channel width-over-length ratio and third crystalline substance of the second transistor
The channel width-over-length ratio of body pipe.
10. shift register as claimed in claim 3, which is characterized in that
The reset control module includes the 11st transistor and the tenth two-transistor；
The grid of 11st transistor is connect with the control signal end of just sweeping, the first pole of the 11st transistor with
The second clock signal end connection, the second pole of the 11st transistor is connect with the reseting controling end；
The grid of tenth two-transistor is connect with the anti-control signal end of sweeping, the first pole of the tenth two-transistor with
The third clock signal terminal connection, the second pole of the tenth two-transistor is connect with the reseting controling end.
11. shift register as claimed in claim 2, which is characterized in that
The discharge module includes the 13rd transistor, the 14th transistor and the 15th transistor；
The grid of 13rd transistor is connect with the discharge control terminal, the first pole of the 13rd transistor with it is described
The connection of first reference voltage end, the second pole of the 13rd transistor is connect with the first node；
The grid of 14th transistor is connect with the discharge control terminal, the first pole of the 14th transistor with it is described
The connection of first reference voltage end, the second pole of the 14th transistor is connect with the second node；
The grid of 15th transistor is connect with the discharge control terminal, the first pole of the 15th transistor with it is described
The connection of second reference voltage end, the second pole of the 15th transistor is connect with the grid signal output end.
12. shift register as described in claim 1, which is characterized in that
It further include the 16th transistor；
The first node is divided into cycle of sixty years node and second child node by the 16th transistor；
First pole of the 16th transistor is connect with the cycle of sixty years node, the second pole of the 16th transistor with it is described
The connection of second child node, the grid of the 16th transistor are connect with second reference voltage end, second reference voltage
The signal at end controls the 16th transistor turns.
13. a kind of gate driving circuit, which is characterized in that
Including N number of cascade such as described in any item shift registers of claim 1-12, wherein N is the integer greater than 2.
14. a kind of display device characterized by comprising
Viewing area and non-display area；
The viewing area includes a plurality of grid line, insulate the multiple data lines intersected with the grid line；
The non-display area includes the gate driving circuit provided such as claim 13, the institute of each shift register
Grid signal output end is stated to be electrically connected with a grid line.
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| CN111243490B (en) * | 2020-03-31 | 2022-08-30 | 厦门天马微电子有限公司 | Shifting register and driving method thereof, grid driving circuit and display device |
| CN111462675A (en) * | 2020-05-13 | 2020-07-28 | 京东方科技集团股份有限公司 | Shifting register, grid driving circuit and display device |
| CN111462675B (en) * | 2020-05-13 | 2023-06-27 | 京东方科技集团股份有限公司 | Shifting register, grid driving circuit and display device |
| CN111739475A (en) * | 2020-06-16 | 2020-10-02 | 昆山国显光电有限公司 | Shift register and display panel |
| CN111696469A (en) * | 2020-06-18 | 2020-09-22 | 昆山国显光电有限公司 | Shift register, scanning circuit and display panel |
| CN112530501A (en) * | 2020-12-04 | 2021-03-19 | 京东方科技集团股份有限公司 | Shifting register unit, grid driving circuit and display device |
| CN112735320A (en) * | 2021-01-12 | 2021-04-30 | 福建华佳彩有限公司 | GIP circuit for improving output waveform stability and driving method |
| CN112735320B (en) * | 2021-01-12 | 2024-01-16 | 福建华佳彩有限公司 | GIP circuit for improving stability of output waveform and driving method |
| CN113299222A (en) * | 2021-06-07 | 2021-08-24 | 厦门天马微电子有限公司 | Display panel and display device |
| CN113299222B (en) * | 2021-06-07 | 2024-02-27 | 厦门天马微电子有限公司 | Display panel and display device |
| CN113920914A (en) * | 2021-10-13 | 2022-01-11 | 京东方科技集团股份有限公司 | GOA circuit, driving method thereof and display device |
| CN113920914B (en) * | 2021-10-13 | 2023-11-28 | 京东方科技集团股份有限公司 | GOA circuit, driving method thereof and display device |
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