CN112530501A

CN112530501A - Shifting register unit, grid driving circuit and display device

Info

Publication number: CN112530501A
Application number: CN202011408935.5A
Authority: CN
Inventors: 孙杰; 丁爱宇; 刘雨生; 张永强; 黄波; 王国栋; 韩帅; 徐敬义
Original assignee: BOE Technology Group Co Ltd; Ordos Yuansheng Optoelectronics Co Ltd
Current assignee: BOE Technology Group Co Ltd; Ordos Yuansheng Optoelectronics Co Ltd
Priority date: 2020-12-04
Filing date: 2020-12-04
Publication date: 2021-03-19

Abstract

The invention discloses a shift register unit, a grid drive circuit and a display device. A signal of the anti-sweep input signal terminal is supplied to the first node through the reset circuit. And controlling the signal of the second node, the signal of the third node and the signal of the cascade output end by the control circuit according to the signal of the first node, the signal of the control clock signal end, the signal of the first reference signal end, the signal of the second reference signal end and the signal of the enable signal end. And simultaneously providing the signals of each output clock signal end to the corresponding driving output end through the output circuit; and simultaneously providing the signal of the second reference signal terminal to each driving output terminal; one shift register unit may be caused to output a plurality of signals.

Description

Shifting register unit, grid driving circuit and display device

Technical Field

The invention relates to the technical field of display, in particular to a shift register unit, a grid driving circuit and a display device.

Background

With the rapid development of display technology, display devices are increasingly developed toward high integration and low cost. In the GOA (Gate Driver on Array) technology, a TFT (Thin Film Transistor) Gate Driver circuit is integrated on an Array substrate of a display device to form a scan Driver for the display device. The gate driver circuit is generally composed of a plurality of cascaded shift registers.

Disclosure of Invention

The embodiment of the invention provides a shift register unit, a grid driving circuit and a display device, which are used for enabling one shift register unit to output a plurality of signals.

An embodiment of the present invention provides a shift register unit, including: an input circuit, a reset circuit, a control circuit, and an output circuit;

the input circuit is configured to supply a signal of a normal scan input signal terminal to a first node in response to a signal of a normal scan control signal terminal;

the reset circuit is configured to supply a signal of an anti-scan input signal terminal to the first node in response to a signal of an anti-scan control signal terminal;

the control circuit is configured to control a signal of the second node, a signal of the third node and a signal of the cascade output end according to the signal of the first node, the signal of the control clock signal end, the signal of the first reference signal end, the signal of the second reference signal end and the signal of the enable signal end;

the output circuit is electrically connected with a plurality of different output clock signal terminals, and the output circuit is configured to respond to the signal of the second node and simultaneously provide the signal of each output clock signal terminal to the corresponding drive output terminal; and in response to the signal at the third node, providing the signal at the second reference signal terminal to each of the drive output terminals simultaneously; wherein one of the output clock signal terminals corresponds to one of the driving output terminals.

In some examples, the output circuit includes: output sub-circuits corresponding to the output clock signal terminals one to one;

each of the output sub-circuits is configured to provide a signal of the corresponding output clock signal terminal to the corresponding driving output terminal in response to the signal of the second node; and providing the signal of the second reference signal terminal to the corresponding driving output terminal in response to the signal of the third node.

In some examples, each of the output sub-circuits includes a first transistor and a second transistor;

the grid electrode of the first transistor is electrically connected with the second node, the first electrode of the first transistor is electrically connected with the corresponding output clock signal end, and the second electrode of the first transistor is electrically connected with the corresponding driving output end;

the grid electrode of the second transistor is electrically connected with the third node, the first electrode of the second transistor is electrically connected with the second reference signal end, and the second electrode of the second transistor is electrically connected with the driving output end.

In some examples, the control circuit includes: a first output control circuit;

the first output control circuit includes: a first adjustment control unit, a second adjustment control unit, a third adjustment control unit, a fourth adjustment control unit and a fifth adjustment control unit;

the first adjustment control unit is configured to adjust a signal of a first control node according to a signal of the first node, a signal of a fourth control node, a signal of the first reference signal terminal, and a signal of the second reference signal terminal;

the second adjustment control unit is configured to adjust a signal of a second control node according to the signal of the first control node, the signal of the first reference signal terminal, and the signal of the second reference signal terminal;

the third adjustment control unit is configured to adjust a signal of a third control node according to the signal of the second control node, the signal of the control clock signal terminal, the signal of the first reference signal terminal, and the signal of the second reference signal terminal; and the cascade output is electrically connected with the third control node;

the fourth adjustment control unit is configured to adjust a signal of a fourth control node according to the signal of the third control node, the signal of the first reference signal terminal, and the signal of the second reference signal terminal;

the fifth adjustment control unit is configured to adjust the signal of the second node and the signal of the third node according to the signal of the third control node, the signal of the fourth control node, the signal of the enable signal terminal, the signal of the first reference signal terminal, and the signal of the second reference signal terminal.

In some examples, the first adjustment control unit includes: a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a first capacitor; a gate of the third transistor is electrically connected to the first node, a first electrode of the third transistor is electrically connected to the second reference signal terminal, and a second electrode of the third transistor is electrically connected to the first control node; a gate and a first electrode of the fourth transistor are both electrically connected with the first reference signal terminal, and a second electrode of the fourth transistor is electrically connected with a gate of the fifth transistor; a first electrode of the fifth transistor is electrically connected with the first reference signal end, and a second electrode of the fifth transistor is electrically connected with the first control node; a gate of the sixth transistor is electrically connected to the fourth control node, a first electrode of the sixth transistor is electrically connected to the second reference signal terminal, and a second electrode of the sixth transistor is electrically connected to the first control node; the first capacitor is electrically connected between the grid electrode of the fifth transistor and the first control node; and/or the presence of a gas in the gas,

the second adjustment control unit includes: a seventh transistor, an eighth transistor, a ninth transistor, and a second capacitor; a gate and a first electrode of the seventh transistor are both electrically connected to the first reference signal terminal, and a second electrode of the seventh transistor is electrically connected to a gate of the eighth transistor; a first electrode of the eighth transistor is electrically connected to the first reference signal terminal, and a second electrode of the eighth transistor is electrically connected to the second control node; a gate of the ninth transistor is electrically connected to the first control node, a first electrode of the ninth transistor is electrically connected to the second reference signal terminal, and a second electrode of the ninth transistor is electrically connected to the second control node; the second capacitor is electrically connected between the gate of the eighth transistor and the second control node; and/or the presence of a gas in the gas,

the third adjustment control unit includes: a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a third capacitor; a gate and a first electrode of the tenth transistor are both electrically connected to the first reference signal terminal, and a second electrode of the tenth transistor is electrically connected to a gate of the eleventh transistor; a first electrode of the eleventh transistor is electrically connected to the first reference signal terminal, and a second electrode of the eleventh transistor is electrically connected to the third control node; a gate of the twelfth transistor is electrically connected to the control clock signal terminal, a first electrode of the twelfth transistor is electrically connected to a second electrode of the thirteenth transistor, and the second electrode of the twelfth transistor is electrically connected to the third control node; a gate of the thirteenth transistor is electrically connected to the second control node, and a first electrode of the thirteenth transistor is electrically connected to the second reference signal terminal; the third capacitor is electrically connected between the gate of the eleventh transistor and the third control node; and/or the presence of a gas in the gas,

the fourth adjustment control unit includes: a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, and a fourth capacitor; a gate and a first electrode of the fourteenth transistor are both electrically connected to the first reference signal terminal, and a second electrode of the fourteenth transistor is electrically connected to the gate of the fifteenth transistor; a first electrode of the fifteenth transistor is electrically connected with the first reference signal end, and a second electrode of the fifteenth transistor is electrically connected with the fourth control node; a gate of the sixteenth transistor is electrically connected to the third control node, a first electrode of the sixteenth transistor is electrically connected to the second reference signal terminal, and a second electrode of the sixteenth transistor is electrically connected to the fourth control node; the fourth capacitor is electrically connected between the gate of the fifteenth transistor and the fourth control node; and/or the presence of a gas in the gas,

the fifth adjustment control unit includes: a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty-first transistor, and a fifth capacitor; the grid electrode and the first electrode of the seventeenth transistor are both electrically connected with the first reference signal end, and the second electrode of the seventeenth transistor is electrically connected with the grid electrode of the eighteenth transistor; a first electrode of the eighteenth transistor is electrically connected with the first reference signal end, and a second electrode of the eighteenth transistor is electrically connected with the second node; a gate of the twentieth transistor is electrically connected to the third control node, a first electrode of the twentieth transistor is electrically connected to the enable signal terminal, and a second electrode of the twentieth transistor is electrically connected to the third node; a gate of the nineteenth transistor is electrically connected to the third node, a first electrode of the nineteenth transistor is electrically connected to the second reference signal terminal, and a second electrode of the nineteenth transistor is electrically connected to the second node; a grid electrode of the twenty-first transistor is electrically connected with the fourth control node, a first electrode of the twenty-first transistor is electrically connected with the second reference signal end, and a second electrode of the twenty-first transistor is electrically connected with the third node; the fifth capacitor is electrically connected between the gate of the eighteenth transistor and the second node.

In some examples, the control circuit includes: a second output control circuit;

the second output control circuit includes: a sixth adjustment control unit, a seventh adjustment control unit, an eighth adjustment control unit, and a ninth adjustment control unit;

the sixth adjustment control unit is configured to adjust a signal of a sixth control node according to the signal of the first node, the signal of a seventh control node, the signal of the first reference signal terminal, and the signal of the second reference signal terminal;

the seventh adjustment control unit is configured to adjust a signal of a seventh control node according to the signal of the sixth control node, the signal of the control clock signal terminal, the signal of the first reference signal terminal, and the signal of the second reference signal terminal;

the eighth adjustment control unit is configured to adjust a signal of an eighth control node according to the signal of the seventh control node, the signal of the first reference signal terminal, and the signal of the second reference signal terminal; the cascade output end is electrically connected with the eighth control node;

the ninth adjustment control unit is configured to adjust the signal of the second node and the signal of the third node according to the signal of the seventh control node, the signal of the eighth control node, the signal of the enable signal terminal, the signal of the first reference signal terminal, and the signal of the second reference signal terminal.

In some examples, the sixth adjustment control unit includes: a twenty-second transistor, a twenty-third transistor, a twenty-fourth transistor, a twenty-fifth transistor, and a sixth capacitor; wherein a gate of the twenty-second transistor is electrically connected to the first node, a first pole of the twenty-second transistor is electrically connected to a second pole of the twenty-fifth transistor, and a second pole of the twenty-second transistor is electrically connected to the sixth control node; a gate and a first electrode of the twenty-third transistor are both electrically connected to the first reference signal terminal, and a second electrode of the twenty-third transistor is electrically connected to a gate of the twenty-fourth transistor; a first electrode of the twenty-fourth transistor is electrically connected to the first reference signal terminal, and a second electrode of the twenty-fourth transistor is electrically connected to the sixth control node; a grid electrode of the twenty-fifth transistor is electrically connected with the seventh control node, and a first electrode of the twenty-fifth transistor is electrically connected with the second reference signal end; the sixth capacitor is electrically connected between the gate of the twenty-fourth transistor and the sixth control node; and/or the presence of a gas in the gas,

the seventh adjustment control unit includes: a twenty-sixth transistor, a twenty-seventh transistor, a twenty-eighth transistor, and a seventh capacitor; the grid electrode and the first electrode of the twenty-sixth transistor are both electrically connected with the first reference signal end, and the second electrode of the twenty-sixth transistor is electrically connected with the grid electrode of the twenty-seventh transistor; a first electrode of the twenty-seventh transistor is electrically connected with the first reference signal end, and a second electrode of the twenty-seventh transistor is electrically connected with the seventh control node; a gate of the twenty-eighth transistor is electrically connected to the sixth control node, a first electrode of the twenty-eighth transistor is electrically connected to the control clock signal terminal, and a second electrode of the twenty-eighth transistor is electrically connected to the seventh control node; the seventh capacitor is electrically connected between the gate of the twenty-seventh transistor and the seventh control node; and/or the presence of a gas in the gas,

the eighth adjustment control unit includes: a twenty-ninth transistor, a thirty-eighth transistor, a thirty-seventh transistor, and a twenty-eighth capacitor; a gate and a first electrode of the twenty-ninth transistor are both electrically connected with the first reference signal end, and a second electrode of the twenty-ninth transistor is electrically connected with a gate of the thirtieth transistor; a first electrode of the thirtieth transistor is electrically connected to the first reference signal terminal, and a second electrode of the thirtieth transistor is electrically connected to the eighth control node; a gate of the thirty-first transistor is electrically connected to the seventh control node, a first electrode of the thirty-first transistor is electrically connected to the second reference signal terminal, and a second electrode of the thirty-first transistor is electrically connected to the eighth control node; the eighth capacitor is electrically connected between the gate of the thirtieth transistor and the eighth control node; and/or the presence of a gas in the gas,

the ninth adjustment control unit includes: a thirty-second transistor, a thirty-third transistor, a thirty-fourth transistor, a thirty-fifth transistor, a thirty-sixth transistor, and a ninth capacitor; a gate and a first electrode of the thirty-second transistor are both electrically connected to the first reference signal terminal, and a second electrode of the thirty-second transistor is electrically connected to a gate of the thirty-third transistor; a first electrode of the thirty-third transistor is electrically connected to the first reference signal terminal, and a second electrode of the thirty-third transistor is electrically connected to the second node; a gate of the thirty-fifth transistor is electrically connected to the eighth control node, a first electrode of the thirty-fifth transistor is electrically connected to the first reference signal terminal, and a second electrode of the thirty-fifth transistor is electrically connected to the third node; a gate of the thirty-fourth transistor is electrically connected to the third node, a first electrode of the thirty-fourth transistor is electrically connected to the second reference signal terminal, and a second electrode of the thirty-fourth transistor is electrically connected to the second node; a gate of the thirty-sixth transistor is electrically connected with the seventh control node, a first electrode of the thirty-sixth transistor is electrically connected with the enable signal terminal, and a second electrode of the thirty-sixth transistor is electrically connected with the third node; the ninth capacitor is electrically connected between the gate of the thirty-third transistor and the second node.

In some examples, the input circuit includes: a thirty-seventh transistor; a gate of the thirty-seventh transistor is electrically connected to the positive scan control signal terminal, a first electrode of the thirty-seventh transistor is electrically connected to the positive scan input signal terminal, and a second electrode of the thirty-seventh transistor is electrically connected to the first node;

the reset circuit comprises a thirty-eighth transistor; the gate of the thirty-eighth transistor is electrically connected to the anti-scan control signal terminal, the first electrode of the thirty-seventh transistor is electrically connected to the anti-scan input signal terminal, and the second electrode of the thirty-seventh transistor is electrically connected to the first node.

The gate driving circuit provided by the embodiment of the invention comprises: a plurality of the shift register units are cascaded;

the positive scanning input signal end of the first stage shift register unit is electrically connected with the positive scanning frame trigger signal end;

the reverse scanning input signal end of the last stage of shift register unit is electrically connected with the reverse scanning frame trigger signal end;

in each adjacent two-stage shift register unit, the forward scanning input signal end of the next-stage shift register unit is electrically connected with the cascade output end of the previous-stage shift register unit, and the reverse scanning input signal end of the previous-stage shift register unit is electrically connected with the cascade output end of the next-stage shift register unit.

In some examples, the control circuit in the odd-stage shift register unit includes a first output control circuit;

the control circuit in the even-numbered stage shift register unit comprises a second output control circuit;

the control clock signal end of each stage of shift register unit is electrically connected with a first control signal line;

the first control signal line transmits a clock signal;

the high level maintaining time of the clock signal transmitted by the first control signal line is MB; wherein M represents the total number of output clock signal terminals to which the output circuit is electrically connected, and B represents a high level sustain period of one of the output clock signal terminals.

The display device provided by the embodiment of the invention comprises the gate drive circuit.

In some examples, the display device further includes: a plurality of gate lines;

one of the gate lines is electrically connected with a driving output end of one of the shift register units in the gate driving circuit.

The invention has the following beneficial effects:

according to the shift register unit, the gate driving circuit and the display device provided by the embodiment of the invention, the input circuit is configured to respond to the signal of the positive scanning control signal end and provide the signal of the positive scanning input signal end to the first node. The reset circuit is configured to supply a signal of the anti-sweep input signal terminal to the first node in response to a signal of the anti-sweep control signal terminal. And controlling the signal of the second node, the signal of the third node and the signal of the cascade output end by the control circuit according to the signal of the first node, the signal of the control clock signal end, the signal of the first reference signal end, the signal of the second reference signal end and the signal of the enable signal end. Responding to the signal of the second node through an output circuit, and simultaneously providing the signal of each output clock signal end to the corresponding drive output end; and in response to a signal of the third node, simultaneously providing a signal of the second reference signal terminal to each of the driving output terminals; one output clock signal end corresponds to one driving output end. This enables one shift register unit to output a plurality of signals. When the shift register unit is applied to a display device, one shift register unit can be electrically connected with a plurality of grid lines, so that the number of the shift register units can be reduced, the frame space of the display device occupied by the shift register units is reduced, and a narrow frame is realized.

Drawings

FIG. 1 is a diagram illustrating some structures of a shift register unit according to an embodiment of the present invention;

FIG. 2 is a diagram illustrating further structures of shift register units according to an embodiment of the present invention;

FIG. 3 is a diagram illustrating some specific structures of a shift register unit according to an embodiment of the present invention;

FIG. 4 is a timing diagram of some signals of a shift register unit according to an embodiment of the present invention;

FIG. 5 is a diagram illustrating further structures of shift register units according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of some further embodiments of shift register units according to the present invention;

FIG. 7 is a timing diagram of some other signals of the shift register unit according to the embodiment of the present invention;

FIG. 8 is a block diagram of a gate driver circuit according to an embodiment of the present invention;

FIG. 9 is a schematic diagram of some structures of a display device according to an embodiment of the invention;

FIG. 10 is a timing diagram illustrating some signals of the display device according to the embodiment of the present invention;

FIG. 11 is a timing diagram of still other signals of the display device according to the embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the drawings of the embodiments of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. And the embodiments and features of the embodiments may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the invention without any inventive step, are within the scope of protection of the invention.

Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. As used herein, "second," "third," and the like do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

It should be noted that the sizes and shapes of the figures in the drawings are not to be considered true scale, but are merely intended to schematically illustrate the present invention. And the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

An embodiment of the present invention provides a shift register unit, as shown in fig. 1, an input circuit 10, a reset circuit 20, a control circuit 30, and an output circuit 40;

the input circuit 10 is configured to supply a signal of the normal scan input signal terminal CNIP to the first node N1 in response to a signal of the normal scan control signal terminal CN;

the reset circuit 20 is configured to supply the signal of the reverse scan input signal terminal CNBIP to the first node N1 in response to the signal of the reverse scan control signal terminal CNB;

the control circuit 30 is configured to control the signal of the second node N2, the signal of the third node N3, and the signal of the cascade output terminal GSO according to the signal of the first node N1, the signal of the control clock signal terminal CK0, the signal of the first reference signal terminal VREF1, the signal of the second reference signal terminal VREF2, and the signal of the enable signal terminal EN;

the output circuit 40 is electrically connected to a plurality of different output clock signal terminals CK1_ K (1 ≦ K, and K are integers, fig. 2 taking K ≦ 4 as an example), and the output circuit 40 is configured to simultaneously supply the signal of each output clock signal terminal CK1_ K to the corresponding driving output terminal OT _ K in response to the signal of the second node N2; and simultaneously providing the signal of the second reference signal terminal VREF2 to the respective driving output terminals OT _ k in response to the signal of the third node N3; one output clock signal terminal CK1_ k corresponds to one driving output terminal OT _ k.

The shift register unit provided by the embodiment of the invention is configured to respond to the signal of the positive scan control signal terminal through the input circuit, and provide the signal of the positive scan input signal terminal to the first node. The reset circuit is configured to supply a signal of the anti-sweep input signal terminal to the first node in response to a signal of the anti-sweep control signal terminal. And controlling the signal of the second node, the signal of the third node and the signal of the cascade output end by the control circuit according to the signal of the first node, the signal of the control clock signal end, the signal of the first reference signal end, the signal of the second reference signal end and the signal of the enable signal end. Responding to the signal of the second node through an output circuit, and simultaneously providing the signal of each output clock signal end to the corresponding drive output end; and in response to a signal of the third node, simultaneously providing a signal of the second reference signal terminal to each of the driving output terminals; one output clock signal end corresponds to one driving output end. This enables one shift register unit to output a plurality of signals. When the shift register unit is applied to a display device, one shift register unit can be electrically connected with a plurality of grid lines, so that the number of the shift register units can be reduced, the frame space of the display device occupied by the shift register units is reduced, and a narrow frame is realized.

In practical implementation, in the embodiment of the present invention, as shown in fig. 2, the control circuit 30 includes: a first output control circuit 31; wherein, the first output control circuit 31 includes: a first adjustment control unit 311, a second adjustment control unit 312, a third adjustment control unit 313, a fourth adjustment control unit 314, and a fifth adjustment control unit 315;

the first adjustment control unit 311 is configured to adjust the signal of the first control node C01 according to the signal of the first node N1, the signal of the fourth control node C04, the signal of the first reference signal terminal VREF1, and the signal of the second reference signal terminal VREF 2;

the second adjustment control unit 312 is configured to adjust the signal of the second control node C02 according to the signal of the first control node C01, the signal of the first reference signal terminal VREF1, and the signal of the second reference signal terminal VREF 2;

the third adjustment control unit 313 is configured to adjust the signal of the third control node C03 according to the signal of the second control node C02, the signal of the control clock signal terminal CK0, the signal of the first reference signal terminal VREF1, and the signal of the second reference signal terminal VREF 2; and the cascade output terminal GSO is electrically connected to the third control node C03;

the fourth adjustment control unit 314 is configured to adjust the signal of the fourth control node C04 according to the signal of the third control node C03, the signal of the first reference signal terminal VREF1, and the signal of the second reference signal terminal VREF 2;

the fifth adjustment control unit 315 is configured to adjust the signal of the second node N2 and the signal of the third node N3 according to the signal of the third control node C03, the signal of the fourth control node C04, the signal of the enable signal terminal EN, the signal of the first reference signal terminal VREF1, and the signal of the second reference signal terminal VREF 2.

Illustratively, the control of the signals of the second node N2 and the third node N3 may be achieved by the above-described first adjustment control unit 311, second adjustment control unit 312, third adjustment control unit 313, fourth adjustment control unit 314, and fifth adjustment control unit 315.

In practical implementation, in the embodiment of the present invention, as shown in fig. 2, the output circuit 40 may include: output sub-circuits 41_ k corresponding one-to-one to the respective output clock signal terminals CK1_ k; wherein each output sub-circuit 41_ k is configured to provide a signal of a corresponding output clock signal terminal CK1_ k to a corresponding driving output terminal OT _ k in response to a signal of the second node N2; and providing the signal of the second reference signal terminal VREF2 to the corresponding driving output terminal OT _ k in response to the signal of the third node N3.

For example, K may be 2, the output circuit 40 may be electrically connected to two different output clock signal terminals, and the output circuit 40 may output two signals with different timings. This allows one output circuit 40 to include 2 output sub-circuits. Alternatively, K may be 3, the output circuit 40 may be electrically connected to three different output clock signal terminals, and the output circuit 40 may output three signals with different timings. This allows one output circuit 40 to include 3 output sub-circuits. Alternatively, K may be 4, the output circuit 40 may be electrically connected to four different output clock signal terminals, and the output circuit 40 may output four signals with different timings. This allows one output circuit 40 to include 4 output sub-circuits. Of course, in practical applications, the number of the output clock signal terminals electrically connected to the output circuit 40 may be determined according to the requirements of practical applications, and is not limited herein.

In practical implementation, in the embodiment of the present invention, as shown in fig. 3, the input circuit 10 may include: a thirty-seventh transistor M37; the gate of the thirty-seventh transistor M37 is electrically connected to the positive scan control signal terminal CN, the first pole of the thirty-seventh transistor M37 is electrically connected to the positive scan input signal terminal CNIP, and the second pole of the thirty-seventh transistor M37 is electrically connected to the first node N1.

In practical implementation, in the embodiment of the present invention, as shown in fig. 3, the reset circuit 20 may include: a thirty-eighth transistor M38; a gate of the thirty-eighth transistor M38 is electrically connected to the reverse scan control signal terminal CNB, a first pole of the thirty-seventh transistor M37 is electrically connected to the reverse scan input signal terminal CNBIP, and a second pole of the thirty-seventh transistor M37 is electrically connected to the first node N1.

In specific implementation, in the embodiment of the present invention, as shown in fig. 3, the first adjustment control unit 311 may include: a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, and a first capacitor C1; a gate of the third transistor M3 is electrically connected to the first node N1, a first pole of the third transistor M3 is electrically connected to the second reference signal terminal VREF2, and a second pole of the third transistor M3 is electrically connected to the first control node C01; a gate and a first pole of the fourth transistor M4 are electrically connected to the first reference signal terminal VREF1, and a second pole of the fourth transistor M4 is electrically connected to the gate of the fifth transistor M5; a first pole of the fifth transistor M5 is electrically connected to the first reference signal terminal VREF1, and a second pole of the fifth transistor M5 is electrically connected to the first control node C01; a gate of the sixth transistor M6 is electrically connected to the fourth control node C04, a first pole of the sixth transistor M6 is electrically connected to the second reference signal terminal VREF2, and a second pole of the sixth transistor M6 is electrically connected to the first control node C01; the first capacitor C1 is electrically connected between the gate of the fifth transistor M5 and the first control node C01.

In practical implementation, in the embodiment of the present invention, as shown in fig. 3, the second adjustment control unit 312 may include: a seventh transistor M6, an eighth transistor M8, a ninth transistor M9, and a second capacitor C2; wherein, the gate and the first pole of the seventh transistor M6 are both electrically connected with the first reference signal terminal VREF1, and the second pole of the seventh transistor M6 is electrically connected with the gate of the eighth transistor M8; a first pole of the eighth transistor M8 is electrically connected to the first reference signal terminal VREF1, and a second pole of the eighth transistor M8 is electrically connected to the second control node C02; a gate of the ninth transistor M9 is electrically connected to the first control node C01, a first pole of the ninth transistor M9 is electrically connected to the second reference signal terminal VREF2, and a second pole of the ninth transistor M9 is electrically connected to the second control node C02; the second capacitor C2 is electrically connected between the gate of the eighth transistor M8 and the second control node C02.

In specific implementation, in the embodiment of the present invention, as shown in fig. 3, the third adjustment control unit 313 may include: a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, and a third capacitor C3; wherein a gate and a first pole of the tenth transistor M10 are electrically connected to the first reference signal terminal VREF1, and a second pole of the tenth transistor M10 is electrically connected to the gate of the eleventh transistor M11; a first pole of the eleventh transistor M11 is electrically connected to the first reference signal terminal VREF1, and a second pole of the eleventh transistor M11 is electrically connected to the third control node C03; a gate of the twelfth transistor M12 is electrically connected to the control clock signal terminal CK0, a first pole of the twelfth transistor M12 is electrically connected to a second pole of the thirteenth transistor M13, and a second pole of the twelfth transistor M12 is electrically connected to the third control node C03; a gate of the thirteenth transistor M13 is electrically connected to the second control node C02, and a first pole of the thirteenth transistor M13 is electrically connected to the second reference signal terminal VREF 2; the third capacitor C3 is electrically connected between the gate of the eleventh transistor M11 and the third control node C03.

In practical implementation, in the embodiment of the present invention, as shown in fig. 3, the fourth adjustment control unit 314 may include: a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, and a fourth capacitor C4; a gate and a first pole of the fourteenth transistor M14 are both electrically connected to the first reference signal terminal VREF1, and a second pole of the fourteenth transistor M14 is electrically connected to the gate of the fifteenth transistor M15; a first pole of the fifteenth transistor M15 is electrically connected to the first reference signal terminal VREF1, and a second pole of the fifteenth transistor M15 is electrically connected to the fourth control node C04; a gate of the sixteenth transistor M16 is electrically connected to the third control node C03, a first pole of the sixteenth transistor M16 is electrically connected to the second reference signal terminal VREF2, and a second pole of the sixteenth transistor M16 is electrically connected to the fourth control node C04; the fourth capacitor C4 is electrically connected between the gate of the fifteenth transistor M15 and the fourth control node C04.

In specific implementation, in the embodiment of the present invention, as shown in fig. 3, the fifth adjustment control unit 315 may include: a seventeenth transistor M17, an eighteenth transistor M18, a nineteenth transistor M19, a twentieth transistor M20, a twenty-first transistor M21, and a fifth capacitor C5; wherein, the gate and the first pole of the seventeenth transistor M17 are both electrically connected with the first reference signal terminal VREF1, and the second pole of the seventeenth transistor M17 is electrically connected with the gate of the eighteenth transistor M18; a first pole of the eighteenth transistor M18 is electrically connected to the first reference signal terminal VREF1, and a second pole of the eighteenth transistor M18 is electrically connected to the second node N2; a gate of the twentieth transistor M20 is electrically connected to the third control node C03, a first pole of the twentieth transistor M20 is electrically connected to the enable signal terminal EN, and a second pole of the twentieth transistor M20 is electrically connected to the third node N3; a gate of the nineteenth transistor M19 is electrically connected to the third node N3, a first pole of the nineteenth transistor M19 is electrically connected to the second reference signal terminal VREF2, and a second pole of the nineteenth transistor M19 is electrically connected to the second node N2; a gate of the twenty-first transistor M21 is electrically connected to the fourth control node C04, a first pole of the twenty-first transistor M21 is electrically connected to the second reference signal terminal VREF2, and a second pole of the twenty-first transistor M21 is electrically connected to the third node N3; the fifth capacitor C5 is electrically connected between the gate of the eighteenth transistor M18 and the second node N2.

In particular implementation, in the embodiment of the present invention, as shown in fig. 3, each output sub-circuit 31_ k may include a first transistor M1_ k and a second transistor M2_ k;

a gate of the first transistor M1_ k is electrically connected to the second node N2, a first pole of the first transistor M1_ k is electrically connected to the corresponding output clock signal terminal CK1_ k, and a second pole of the first transistor M1_ k is electrically connected to the corresponding driving output terminal OT _ k;

the gate of the second transistor M2_ k is electrically connected to the third node N3, the first pole of the second transistor M2_ k is electrically connected to the second reference signal terminal VREF2, and the second pole of the second transistor M2_ k is electrically connected to the driving output terminal OT _ k.

The specific structure of each circuit in the shift register unit is only illustrated, and in the specific implementation, the specific structure of each circuit is not limited to the structure provided in the embodiment of the present invention, and may be other structures known to those skilled in the art, and is not limited herein.

In some examples, the transistors are generally made of the same material, and in practical implementation, all the transistors may be N-type transistors, and the signal of the first reference signal terminal VREF1 may be a high-level signal, and the signal of the second reference signal terminal VREF2 may be a low-level signal. Alternatively, all the transistors may be P-type transistors, and the signal of the first reference signal terminal VREF1 may be a low-level signal, and the signal of the second reference signal terminal VREF2 may be a high-level signal.

In a specific implementation, after the shift register unit is applied to the display device, when all the transistors are N-type transistors, if the display device is to perform normal display, the signal of the enable signal terminal EN may be controlled to be a high level signal, and if the display device is to perform touch operation, the signal of the enable signal terminal EN may be controlled to be a low level signal. Or, when all the transistors are P-type transistors, if the display device is to perform normal display, the signal of the enable signal terminal EN may be controlled to be a low level signal, and if the display device is to perform touch operation, the signal of the enable signal terminal EN may be controlled to be a high level signal.

In one embodiment, the signal controlling the clock signal terminal CK0 may be a clock signal having a period T0. The signal at the output clock signal terminal may be a clock signal having a period T1. And, T0 ═ 2T 1. And when the high level maintaining time of the clock signal of the control clock signal terminal CK0 is t0 and the high level maintaining time of the clock signal of the output clock signal terminal is t1, t0 is K × t 1.

Furthermore, in specific implementation, the N-type transistor is turned on under the action of a high level and turned off under the action of a low level; the P-type transistor is turned off under the action of a high level and turned on under the action of a low level.

It should be noted that the transistors mentioned in the above embodiments of the present invention may be all Metal Oxide semiconductor field effect transistors (MOS), or may also be Thin Film Transistors (TFT). In a specific implementation, the first pole of these transistors may serve as their source and the second pole may serve as their drain. Alternatively, the first pole may be used as its drain and the second pole as its source, which are not specifically distinguished herein.

Further, in the shift register unit provided in the embodiment of the present invention, the input circuit 10 and the reset circuit 20 are designed symmetrically, and functions can be interchanged, so that the shift register unit provided in the embodiment of the present invention can implement bidirectional scanning. In forward scanning, taking the transistor as an N-type transistor as an example, the forward scanning control signal terminal CN loads a high level signal, and the reverse scanning control signal terminal CNB loads a low level signal. In the reverse direction scanning, the functions of the input circuit 10 and the reset circuit 20 of the shift register are interchanged, that is, the reset circuit 20 functions as the input circuit 10 and the input circuit 10 functions as the reset circuit 20 with respect to the forward direction scanning. In addition, taking the transistor as an N-type transistor as an example, the positive scan control signal terminal CN is loaded with a low level signal, and the negative scan control signal terminal CNB is loaded with a high level signal. It should be noted that the working process of the reverse scanning is basically the same as that of the forward scanning, and is not described herein again.

The following describes the operation process of the shift register unit provided in the embodiment of the present disclosure with reference to the signal timing diagram shown in fig. 4 by taking the shift register unit shown in fig. 3 and forward scanning as an example. In the following description, a high level signal is denoted by 1, a low level signal is denoted by 0, and it should be noted that 1 and 0 are logic levels, which are only used to better explain the specific operation process of the embodiment of the present disclosure, and are not voltages applied to the gates of the transistors in specific implementation.

In the period T11, the thirty-seventh transistor M37 is turned on under the control of the high level signal of the positive scan control signal terminal CN to provide the high level signal of the positive scan input terminal to the first node N1, so that the signal of the first node N1 is a high level signal to control the third transistor M3 to be turned on. The turned-on third transistor M3 provides the low level signal of the second reference signal terminal VREF2 to the first control node C01, so that the signal of the first control node C01 is a low level signal, thereby controlling the ninth transistor M9 to be turned off. The high level of the first reference signal terminal VREF1 is supplied to the second control node C02 due to the functions of the seventh transistor M6 and the eighth transistor M8, so that the signal of the second control node C02 can be made a high level signal to control the thirteenth transistor M13 to be turned on. The twelfth transistor M12 is also turned on by the high level signal of the control clock signal terminal CK0, and the signal of the third control node C03 is a low level signal, thereby controlling both the sixteenth transistor M16 and the twentieth transistor M20 to be turned off. The high level of the first reference signal terminal VREF1 is provided to the fourth control node C04 due to the functions of the fourteenth transistor M14 and the fifteenth transistor M15, so that the signal of the fourth control node C04 can be a high level signal, thereby controlling both the sixth transistor M6 and the twenty-first transistor M21 to be turned on. The turned-on sixth transistor M6 provides a low-level signal of the second reference signal terminal VREF2 to the first control node C01, and further makes the first control node C01 a low-level signal. The twenty-first transistor M21, which is turned on, provides a low level signal of the second reference signal terminal VREF2 to the third node N3, so that the signal of the third node N3 is a low level signal, thereby controlling both the nineteenth transistor M19 and the second transistors M2_1 to M2_4 to be turned off. The seventeenth transistor M17 and the eighteenth transistor M18 provide the high level of the first reference signal terminal VREF1 to the second node N2, so that the signal at the second node N2 can be a high level signal, thereby controlling the first transistors M1_1 to M1_4 to be all turned on. The turned-on first transistor M1_1 outputs the signal of the output clock signal terminal CK1_1 in the T11 stage to the driving output terminal OT _1 so that the driving output terminal OT _1 outputs the signal shown in fig. 4. The turned-on first transistor M1_2 outputs the signal of the output clock signal terminal CK1_2 in the T11 stage to the driving output terminal OT _2 so that the driving output terminal OT _2 outputs the signal shown in fig. 4. The turned-on first transistor M1_3 outputs the signal of the output clock signal terminal CK1_3 in the T11 stage to the driving output terminal OT _3 so that the driving output terminal OT _3 outputs the signal shown in fig. 4. The turned-on first transistor M1_4 outputs the signal of the output clock signal terminal CK1_4 in the T11 stage to the driving output terminal OT _4 so that the driving output terminal OT _4 outputs the signal shown in fig. 4. And, the cascade output terminal GSO outputs a low level signal.

In the period T12, the thirty-seventh transistor M37 is turned on under the control of the high level signal of the positive scan control signal terminal CN to provide the low level signal of the positive scan input terminal to the first node N1, so that the signal of the first node N1 is a low level signal to control the third transistor M3 to be turned off. Due to the functions of the fourth transistor M4 and the fifth transistor M5, a high level signal of the first reference signal terminal VREF1 may be provided to the first control node C01 to make the first control node C01 a high level signal, thereby controlling the ninth transistor M9 to be turned on. The turned-on ninth transistor M9 provides the low level signal of the second reference signal terminal VREF2 to the second control node C02, so that the signal of the second control node C02 is a low level signal, thereby controlling the thirteenth transistor M13 to be turned off. The high level of the first reference signal terminal VREF1 is supplied to the second control node C02 due to the functions of the tenth transistor M10 and the eleventh transistor M11, so that the signal of the third control node C03 can be made a high level signal, thereby controlling both the sixteenth transistor M16 and the twentieth transistor M20 to be turned on. The turned-on sixteenth transistor M16 provides the low level signal of the second reference signal terminal VREF2 to the fourth control node C04, and the signal of the fourth control node C04 may be made to be a low level signal to control both the sixth transistor M6 and the twenty-first transistor M21 to be turned off. The twenty-first transistor M21 that is turned on provides the high level signal of the enable signal terminal EN to the third node N3, so that the signal of the third node N3 can be a high level signal to control the nineteenth transistor M19 and the second transistors M2_1 to M2_4 to be turned on. The turned-on nineteenth transistor M19 may provide the low level signal of the second reference signal terminal VREF2 to the second node N2, and may make the signal of the second node N2 be a low level signal, thereby controlling the first transistors M1_1 to M1_4 to be turned off. The turned-on second transistor M2_1 outputs a low level signal of the second reference signal terminal VREF2 to the driving output terminal OT _1, so that the driving output terminal OT _1 outputs a signal shown in fig. 4. The turned-on second transistor M2_1 outputs a low level signal of the second reference signal terminal VREF2 to the driving output terminal OT _2, so that the driving output terminal OT _2 outputs a signal shown in fig. 4. The turned-on second transistor M2_1 outputs a low level signal of the second reference signal terminal VREF2 to the driving output terminal OT _3, so that the driving output terminal OT _3 outputs a signal shown in fig. 4. The turned-on second transistor M2_1 outputs a low level signal of the second reference signal terminal VREF2 to the driving output terminal OT _4, so that the driving output terminal OT _4 outputs a signal shown in fig. 4. And, the cascade output terminal GSO outputs a high level signal.

The embodiment of the present disclosure further provides other schematic structural diagrams of the shift register unit, as shown in fig. 5, which are modified from the foregoing embodiments. Only the differences between the present embodiment and the above embodiments will be described below, and the descriptions of the same parts will be omitted.

In specific implementation, in the embodiment of the present invention, as shown in fig. 5, the control circuit 30 may include: a second output control circuit 32; wherein the second output control circuit 32 includes: a sixth adjustment control unit 326, a seventh adjustment control unit 327, an eighth adjustment control unit 328, and a ninth adjustment control unit 329;

the sixth adjustment control unit 326 is configured to adjust the signal of the sixth control node C06 according to the signal of the first node N1, the signal of the seventh control node C07, the signal of the first reference signal terminal VREF1, and the signal of the second reference signal terminal VREF 2;

the seventh adjustment control unit 327 is configured to adjust a signal of the seventh control node C07 according to a signal of the sixth control node C06, a signal of the control clock signal terminal CK0, a signal of the first reference signal terminal VREF1, and a signal of the second reference signal terminal VREF 2;

the eighth adjustment control unit 328 is configured to adjust the signal of the eighth control node C08 according to the signal of the seventh control node C07, the signal of the first reference signal terminal VREF1, and the signal of the second reference signal terminal VREF 2; and the cascade output terminal GSO is electrically connected to the eighth control node C08;

the ninth adjustment control unit 329 is configured to adjust the signal of the second node N2 and the signal of the third node N3 according to the signal of the seventh control node C07, the signal of the eighth control node C08, the signal of the enable signal terminal EN, the signal of the first reference signal terminal VREF1, and the signal of the second reference signal terminal VREF 2.

In practical implementation, in the embodiment of the present invention, as shown in fig. 6, the sixth adjustment control unit 326 may include: a twentieth transistor M22, a twenty-third transistor M23, a twenty-fourth transistor M24, a twenty-fifth transistor M25, and a sixth capacitor C6; a gate of the twentieth transistor M22 is electrically connected to the first node N1, a first pole of the twentieth transistor M22 is electrically connected to a second pole of the twenty-fifth transistor M25, and the second pole of the twentieth transistor M22 is electrically connected to the sixth control node C06; a gate and a first pole of the twenty-third transistor M23 are electrically connected to the first reference signal terminal VREF1, and a second pole of the twenty-third transistor M23 is electrically connected to a gate of the twenty-fourth transistor M24; a first pole of the twenty-fourth transistor M24 is electrically connected to the first reference signal terminal VREF1, and a second pole of the twenty-fourth transistor M24 is electrically connected to the sixth control node C06; a gate of the twenty-fifth transistor M25 is electrically connected to the seventh control node C07, and a first pole of the twenty-fifth transistor M25 is electrically connected to the second reference signal terminal VREF 2; the sixth capacitor C6 is electrically connected between the gate of the twenty-fourth transistor M24 and the sixth control node C06.

In specific implementation, in the embodiment of the present invention, as shown in fig. 6, the seventh adjustment control unit 327 may include: a twenty-sixth transistor M26, a twenty-seventh transistor M27, a twenty-eighth transistor M28, and a seventh capacitor C7; the grid and the first pole of the twenty-sixth transistor M26 are both electrically connected with the first reference signal end VREF1, and the second pole of the twenty-sixth transistor M26 is electrically connected with the grid of the twenty-seventh transistor M27; a first pole of the twenty-seventh transistor M27 is electrically connected to the first reference signal terminal VREF1, and a second pole of the twenty-seventh transistor M27 is electrically connected to the seventh control node C07; a gate of the twenty-eighth transistor M28 is electrically connected to the sixth control node C06, a first pole of the twenty-eighth transistor M28 is electrically connected to the control clock signal terminal CK0, and a second pole of the twenty-eighth transistor M28 is electrically connected to the seventh control node C07; the seventh capacitor C7 is electrically connected between the gate of the twenty-seventh transistor M27 and the seventh control node C07.

In practical implementation, in the embodiment of the present invention, as shown in fig. 6, the eighth adjusting and controlling unit 328 may include: a twenty-ninth transistor M29, a thirtieth transistor M30, a thirty-first transistor M31, and an eighth capacitor C8; the gate and the first pole of the twenty-ninth transistor M29 are both electrically connected with the first reference signal terminal VREF1, and the second pole of the twenty-ninth transistor M29 is electrically connected with the gate of the thirtieth transistor M30; a first pole of the thirtieth transistor M30 is electrically connected to the first reference signal terminal VREF1, and a second pole of the thirtieth transistor M30 is electrically connected to the eighth control node C08; a gate of the thirty-first transistor M31 is electrically connected to the seventh control node C07, a first pole of the thirty-first transistor M31 is electrically connected to the second reference signal terminal VREF2, and a second pole of the thirty-first transistor M31 is electrically connected to the eighth control node C08; the eighth capacitor C8 is electrically connected between the gate of the thirtieth transistor M30 and the eighth control node C08.

In practical implementation, in the embodiment of the present invention, as shown in fig. 6, the ninth adjusting and controlling unit 329 may include: a thirty-second transistor M32, a thirty-third transistor M33, a thirty-fourth transistor M34, a thirty-fifth transistor M35, a thirty-sixth transistor M36, and a ninth capacitor C9; a gate and a first pole of the thirty-second transistor M32 are electrically connected to the first reference signal terminal VREF1, and a second pole of the thirty-second transistor M32 is electrically connected to a gate of the thirty-third transistor M33; a first pole of the thirty-third transistor M33 is electrically connected to the first reference signal terminal VREF1, and a second pole of the thirty-third transistor M33 is electrically connected to the second node N2; a gate of the thirty-fifth transistor M35 is electrically connected to the eighth control node C08, a first pole of the thirty-fifth transistor M35 is electrically connected to the first reference signal terminal VREF1, and a second pole of the thirty-fifth transistor M35 is electrically connected to the third node N3; a gate of the thirty-fourth transistor M34 is electrically connected to the third node N3, a first pole of the thirty-fourth transistor M34 is electrically connected to the second reference signal terminal VREF2, and a second pole of the thirty-fourth transistor M34 is electrically connected to the second node N2; a gate of the thirty-sixth transistor M36 is electrically connected to the seventh control node C07, a first pole of the thirty-sixth transistor M36 is electrically connected to the enable signal terminal EN, and a second pole of the thirty-sixth transistor M36 is electrically connected to the third node N3; the ninth capacitor C9 is electrically connected between the gate of the thirty-third transistor M33 and the second node N2.

The following describes the operation process of the shift register unit provided in the embodiment of the present disclosure with reference to the signal timing diagram shown in fig. 7 by taking the shift register unit shown in fig. 6 and forward direction scanning as an example. In the following description, a high level signal is denoted by 1, a low level signal is denoted by 0, and it should be noted that 1 and 0 are logic levels, which are only used to better explain the specific operation process of the embodiment of the present disclosure, and are not voltages applied to the gates of the transistors in specific implementation.

In the period T21, the thirty-seventh transistor M37 is turned on under the control of the high level signal of the positive scan control signal terminal CN to provide the high level signal of the positive scan input terminal to the first node N1, so that the signal of the first node N1 is a high level signal to control the twenty-second transistor M22 to be turned on. However, the twenty-fifth transistor M25 is turned off under the control of the seventh control node C07, which is maintained at a low level, and thus the signal of the sixth control node C06 may be a high level signal due to the effects of the twenty-fourth transistor M24 and the twenty-fourth transistor M24 by supplying the signal of the first reference signal terminal VREF1 to the sixth control node C06, thereby controlling the twenty-eighth transistor M28 to be turned on. The turned-on twenty-eighth transistor M28 provides a low level signal of the control signal terminal to the seventh control node C07, and the signal of the seventh control node C07 may be made a low level signal to control both the thirty-first transistor M31 and the thirty-sixth transistor M36 to be turned off.

Due to the twenty-ninth transistor M29 and the third transistor M3, the high level of the first reference signal terminal VREF1 is provided to the eighth control node C08, so that the signal of the eighth control node C08 can be a high level signal, thereby controlling the thirty-fifth transistor M35 to be turned on. The turned-on thirty-fifth transistor M35 provides the low level signal of the second reference signal terminal VREF2 to the third node N3, so that the signal of the third node N3 is a low level signal, thereby controlling the thirty-fourth transistor M34 and the second transistors M2_1 to M2_4 to be turned off. The high level of the first reference signal terminal VREF1 is provided to the second node N2 due to the actions of the thirty-second transistor M32 and the thirty-third transistor M33, so that the signal at the second node N2 can be a high level signal, and thus the first transistors M1_1 to M1_4 are all controlled to be turned on. The turned-on first transistor M1_1 outputs the signal of the output clock signal terminal CK1_1 in the T11 stage to the driving output terminal OT _1 so that the driving output terminal OT _1 outputs the signal shown in fig. 4. The turned-on first transistor M1_2 outputs the signal of the output clock signal terminal CK1_2 in the T11 stage to the driving output terminal OT _2 so that the driving output terminal OT _2 outputs the signal shown in fig. 4. The turned-on first transistor M1_3 outputs the signal of the output clock signal terminal CK1_3 in the T11 stage to the driving output terminal OT _3 so that the driving output terminal OT _3 outputs the signal shown in fig. 4. The turned-on first transistor M1_4 outputs the signal of the output clock signal terminal CK1_4 in the T11 stage to the driving output terminal OT _4 so that the driving output terminal OT _4 outputs the signal shown in fig. 4. And, the cascade output terminal GSO outputs a high level signal.

In the period T22, the thirty-seventh transistor M37 is turned on under the control of the high level signal of the positive scan control signal terminal CN to provide the high level signal of the positive scan input terminal to the first node N1, so that the signal of the first node N1 is a high level signal to control the twenty-second transistor M22 to be turned on. Since the signal of the sixth control node C06 is a high level signal in the previous stage, the twenty-eighth transistor M28 is controlled to be turned on. The turned-on twenty-eighth transistor M28 supplies a high level signal of the control clock signal terminal CK0 to the seventh control node C07 to make the signal of the seventh control node C07 a high level signal, thereby controlling both the thirty-first transistor M31 and the thirty-sixth transistor M36 to be turned on. The turned-on thirty-first transistor M31 supplies the low-level signal of the second reference signal terminal VREF2 to the eighth control node C08 to make the signal of the eighth control node C08 a low-level signal, thereby controlling the thirty-fifth transistor M35 to be turned off. The thirty-sixth transistor M36 that is turned on provides the high level signal of the enable signal terminal EN to the third node N3, so that the signal of the third node N3 can be a high level signal to control the thirty-fourth transistor M34 and the second transistors M2_1 to M2_4 to be turned on. The turned-on thirty-fourth transistor M34 may provide the low level signal of the second reference signal terminal VREF2 to the second node N2, and may make the signal of the second node N2 be a low level signal, thereby controlling the first transistors M1_1 to M1_4 to be turned off. The turned-on second transistor M2_1 outputs a low level signal of the second reference signal terminal VREF2 to the driving output terminal OT _1, so that the driving output terminal OT _1 outputs a signal shown in fig. 4. The turned-on second transistor M2_1 outputs a low level signal of the second reference signal terminal VREF2 to the driving output terminal OT _2, so that the driving output terminal OT _2 outputs a signal shown in fig. 4. The turned-on second transistor M2_1 outputs a low level signal of the second reference signal terminal VREF2 to the driving output terminal OT _3, so that the driving output terminal OT _3 outputs a signal shown in fig. 4. The turned-on second transistor M2_1 outputs a low level signal of the second reference signal terminal VREF2 to the driving output terminal OT _4, so that the driving output terminal OT _4 outputs a signal shown in fig. 4. And, the cascade output terminal GSO outputs a low level signal.

The embodiment of the present invention further provides a gate driving circuit, as shown in fig. 8, including a plurality of cascaded shift register units SR (1), SR (2) … SR (n-1), SR (n) … …, SR (P) (P shift register units, P is equal to or greater than 1 and equal to or less than P, P is an integer); the positive scanning input signal end CNIP of the first stage shift register unit is electrically connected with the positive scanning frame trigger signal end STVCN;

the reverse scanning input signal end CNBIP of the last stage of shift register unit is electrically connected with the reverse scanning frame trigger signal end STVCNB;

in each adjacent two-stage shift register unit, the forward scanning input signal end CNIP of the next-stage shift register unit is electrically connected with the cascade output end GSO of the previous-stage shift register unit, and the reverse scanning input signal end CNBIP of the previous-stage shift register unit is electrically connected with the cascade output end GSO of the next-stage shift register unit.

Illustratively, the control circuit 30 in the shift register unit of the odd stage may be made to include a first output control circuit 31; the control circuit 30 in the even-numbered stage shift register unit includes a second output control circuit 32. As shown in fig. 8, the control clock signal terminal CK0 of each stage of the shift register unit is electrically connected to the first control signal line clk 1; the first control signal line clk1 transmits a clock signal, that is, the clock signal transmitted by the first control signal line clk1 is a signal loaded on the control clock signal terminal CK 0. Moreover, the duration of the high level of the clock signal transmitted by the first control signal line is MB; where M represents the total number of output clock signal terminals to which the output circuit 40 is electrically connected, and B represents the duration of a high level of one output clock signal terminal.

For example, the specific structure of each shift register unit in the gate driving circuit is the same as that of the shift register unit of the present invention in function and structure, and repeated descriptions are omitted. The gate driving circuit may be configured in a liquid crystal display panel or an electroluminescence display panel, and is not limited thereto.

For example, in the gate driving circuit provided in the embodiment of the present invention, the first reference signal terminals VREF1 of the shift register units of each stage are electrically connected to the same first dc signal line, and the second reference signal terminals VREF2 of the shift register units of each stage are electrically connected to the same second dc signal line.

For example, in the gate driving circuit provided in the embodiment of the present invention, the forward scan control signal terminals CN of the shift register units of each stage are electrically connected to the same forward scan control line, and the reverse scan control signal terminals CNB of the shift register units of each stage are electrically connected to the same reverse scan control line.

Illustratively, in the gate driving circuit provided by the embodiment of the invention, the output clock signal terminals CK1_ k of the shift register units of each stage are electrically connected to the same output clock line CK _ k.

Based on the same inventive concept, the embodiment of the invention also provides a display device, which comprises the gate driving circuit provided by the embodiment of the invention. The principle of the display device to solve the problem is similar to the gate driving circuit, so the implementation of the display device can be referred to the implementation of the gate driving circuit, and repeated details are not repeated herein.

In one embodiment, the display device may include a plurality of pixel units, a plurality of gate lines and data lines, and each pixel unit may include a plurality of sub-pixels, such as a red sub-pixel, a green sub-pixel, and a blue sub-pixel. The display device provided in the embodiments of the present disclosure may be an organic light emitting display device, or may also be a liquid crystal display device, and is not limited herein.

In specific implementation, one row of sub-pixels can be electrically connected with one gate line correspondingly, and one column of sub-pixels can be electrically connected with one data line correspondingly. In the embodiment of the present invention, as shown in fig. 9, one gate line GA1 to GA4P may be electrically connected to the driving output terminal of one shift register unit in the gate driving circuit. For example, when the control circuit 30 in the odd-numbered stage shift register unit includes the first output control circuit 31 and the control circuit 30 in the even-numbered stage shift register unit includes the second output control circuit 32, K adjacent gate lines may be made to be one gate line group so that the odd-numbered stage shift register unit is electrically connected to the gate lines in the odd-numbered gate line group and the even-numbered stage shift register unit is electrically connected to the gate lines in the even-numbered gate line group.

In a specific implementation, taking gate lines GA 1-GA 8 as an example, when the gate driving circuit performs a forward scan, as shown in fig. 10, GA1 represents a signal output from the driving output terminal OT _1 of the first stage shift register unit to the gate line GA1, GA2 represents a signal output from the driving output terminal OT _2 of the first stage shift register unit to the gate line GA2, GA3 represents a signal output from the driving output terminal OT _3 of the first stage shift register unit to the gate line GA3, GA4 represents a signal output from the driving output terminal OT _4 of the first stage shift register unit to the gate line GA4, GA5 represents a signal output from the driving output terminal OT _1 of the second stage shift register unit to the gate line GA5, GA6 represents a signal output from the driving output terminal OT _2 of the second stage shift register unit to the gate line GA6, GA7 represents a signal output from the driving output terminal OT _3 of the second stage shift register unit to the gate line GA7, GA8 represents a signal output from the driving output terminal OT _4 of the second stage shift register unit to the gate line GA 8.

In a specific implementation, taking the gate lines GA 1-GA 8 as an example, when the gate driving circuit performs a reverse scan, as shown in fig. 11, GA1 represents a signal output from the driving output terminal OT _1 of the first stage shift register unit to the gate line GA1, GA2 represents a signal output from the driving output terminal OT _2 of the first stage shift register unit to the gate line GA2, GA3 represents a signal output from the driving output terminal OT _3 of the first stage shift register unit to the gate line GA3, GA4 represents a signal output from the driving output terminal OT _4 of the first stage shift register unit to the gate line GA4, GA5 represents a signal output from the driving output terminal OT _1 of the second stage shift register unit to the gate line GA5, GA6 represents a signal output from the driving output terminal OT _2 of the second stage shift register unit to the gate line GA6, GA7 represents a signal output from the driving output terminal OT _3 of the second stage shift register unit to the gate line GA7, GA8 represents a signal output from the driving output terminal OT _4 of the second stage shift register unit to the gate line GA 8.

In specific implementation, in the embodiment of the present invention, the display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. Other essential components of the display device are understood by those skilled in the art, and are not described herein or should not be construed as limiting the invention.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims

1. A shift register cell, comprising: an input circuit, a reset circuit, a control circuit, and an output circuit;

2. The shift register cell of claim 1, wherein the output circuit comprises: output sub-circuits corresponding to the output clock signal terminals one to one;

3. The shift register cell of claim 2, wherein each of said output sub-circuits includes a first transistor and a second transistor;

4. The shift register cell of any one of claims 1-3, wherein the control circuit comprises: a first output control circuit;

5. The shift register cell of claim 4, wherein the first adjustment control unit comprises: a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a first capacitor; a gate of the third transistor is electrically connected to the first node, a first electrode of the third transistor is electrically connected to the second reference signal terminal, and a second electrode of the third transistor is electrically connected to the first control node; a gate and a first electrode of the fourth transistor are both electrically connected with the first reference signal terminal, and a second electrode of the fourth transistor is electrically connected with a gate of the fifth transistor; a first electrode of the fifth transistor is electrically connected with the first reference signal end, and a second electrode of the fifth transistor is electrically connected with the first control node; a gate of the sixth transistor is electrically connected to the fourth control node, a first electrode of the sixth transistor is electrically connected to the second reference signal terminal, and a second electrode of the sixth transistor is electrically connected to the first control node; the first capacitor is electrically connected between the grid electrode of the fifth transistor and the first control node; and/or the presence of a gas in the gas,

6. The shift register cell of any one of claims 1-3, wherein the control circuit comprises: a second output control circuit;

7. The shift register cell of claim 6, wherein the sixth adjustment control unit comprises: a twenty-second transistor, a twenty-third transistor, a twenty-fourth transistor, a twenty-fifth transistor, and a sixth capacitor; wherein a gate of the twenty-second transistor is electrically connected to the first node, a first pole of the twenty-second transistor is electrically connected to a second pole of the twenty-fifth transistor, and a second pole of the twenty-second transistor is electrically connected to the sixth control node; a gate and a first electrode of the twenty-third transistor are both electrically connected to the first reference signal terminal, and a second electrode of the twenty-third transistor is electrically connected to a gate of the twenty-fourth transistor; a first electrode of the twenty-fourth transistor is electrically connected to the first reference signal terminal, and a second electrode of the twenty-fourth transistor is electrically connected to the sixth control node; a grid electrode of the twenty-fifth transistor is electrically connected with the seventh control node, and a first electrode of the twenty-fifth transistor is electrically connected with the second reference signal end; the sixth capacitor is electrically connected between the gate of the twenty-fourth transistor and the sixth control node; and/or the presence of a gas in the gas,

8. The shift register cell of any of claims 1-3, wherein the input circuit comprises: a thirty-seventh transistor; a gate of the thirty-seventh transistor is electrically connected to the positive scan control signal terminal, a first electrode of the thirty-seventh transistor is electrically connected to the positive scan input signal terminal, and a second electrode of the thirty-seventh transistor is electrically connected to the first node;

9. A gate drive circuit, comprising: a plurality of shift register cells as claimed in any one of claims 1 to 8 in cascade;

10. The gate drive circuit according to claim 9, wherein the control circuit in the shift register unit of the odd-numbered stage includes a first output control circuit; the control circuit in the even-numbered stage shift register unit comprises a second output control circuit;

the first control signal line transmits a clock signal;

11. A display device comprising the gate driver circuit according to claim 9 or 10.

12. The display device according to claim 11, wherein the display device further comprises: a plurality of gate lines;