CN108257574B - Pixel circuit, array substrate, driving method thereof and related device - Google Patents
Pixel circuit, array substrate, driving method thereof and related device Download PDFInfo
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- CN108257574B CN108257574B CN201810247668.4A CN201810247668A CN108257574B CN 108257574 B CN108257574 B CN 108257574B CN 201810247668 A CN201810247668 A CN 201810247668A CN 108257574 B CN108257574 B CN 108257574B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
Abstract
The invention discloses a pixel circuit, an array substrate, a driving method thereof and a related device, wherein a charging and discharging module and a control module are added on the basis of a driving module, two effective pulse signals loaded by each grid line in sequence are utilized, the m-k grade grid line connected with the input end of the control module loads a first effective pulse signal while the m-k grade grid line connected with the control end of the control module loads a second effective pulse signal, and the m-th grade grid line connected with the input end of the charging and discharging module loads an interval time interval between the two effective pulse signals. The potential of the control end of the driving module can be improved through the bootstrap action of the charging and discharging module, so that the driving module is fully opened to charge the pixel electrode, and high charging rate is realized. And moreover, the control module is matched with the bootstrap action of the charge and discharge module to quickly discharge the control end of the driving module, so that the GOE is not limited by the descending time, the charging time is prolonged, and the charging capacity is further improved.
Description
Technical Field
The invention relates to the technical field of display, in particular to a pixel circuit, an array substrate, a driving method of the pixel circuit and a related device.
Background
The liquid Crystal Display panel (L CD, <tttransition = L "&tttL <t/T >gttacquired Crystal Display) has many advantages of thin body, power saving, no radiation, etc., and is widely used, for example, a liquid Crystal television, a mobile phone, a Personal Digital Assistant (PDA), a digital camera, a computer screen, a notebook computer screen, etc.
In the L CD product with high resolution, as the resolution is increased, the charging time of each row of pixel structures is relatively reduced, and the requirement for the charging capability of each row of pixel structures is more strict.
Disclosure of Invention
Embodiments of the present invention provide a pixel circuit, an array substrate, a driving method thereof and a related device, so as to improve a charging capability of the pixel circuit.
Accordingly, an embodiment of the present invention provides a pixel circuit, including: the device comprises a driving module, a charge-discharge module and a control module; wherein the content of the first and second substances,
the input end of the driving module is connected with the data signal line, the output end of the driving module is connected with the pixel electrode, and the control end of the driving module is connected with the first node; the driving module is used for conducting the data signal line and the pixel electrode under the control of the first node;
the input end of the charge-discharge module is connected with the mth stage grid line, and the output end of the charge-discharge module is connected with the first node; the charge and discharge module is used for keeping the voltage between the first node and the mth stage grid line stable when the first node is in floating connection;
the input end of the control module is connected with the m-k stage grid line, the output end of the control module is connected with the first node, the control end of the control module is connected with the m + k stage grid line, and the control module is used for conducting the m-k stage grid line and the first node under the control of the m + k stage grid line;
wherein, M is 1 and 2 … … M, M is a positive integer greater than 2, k is a positive integer less than M, and each grid line is loaded with two effective pulse signals in sequence; and loading a second effective pulse signal on the m-k stage grid line, loading a first effective pulse signal on the m + k stage grid line, and loading an interval time interval between two effective pulse signals on the m + k stage grid line.
In a possible implementation manner, in the pixel circuit provided in an embodiment of the present invention, the control module includes: a first switching transistor;
and the grid electrode of the first switch transistor is connected with the (m + k) th stage grid line, the source electrode of the first switch transistor is connected with the (m-k) th stage grid line, and the drain electrode of the first switch transistor is connected with the first node.
In a possible implementation manner, in the pixel circuit provided in an embodiment of the present invention, the charge and discharge module includes: a capacitor;
and the first end of the capacitor is connected with the m-th stage grid line, and the second end of the capacitor is connected with the first node.
In a possible implementation manner, in the pixel circuit provided in an embodiment of the present invention, the driving module includes: a second switching transistor; and the grid electrode of the second switching transistor is connected with the first node, the source electrode of the second switching transistor is connected with the data signal line, and the drain electrode of the second switching transistor is connected with the pixel electrode.
On the other hand, the embodiment of the invention also provides an array substrate, which comprises M × N pixel circuits arranged in an array, M grid lines connected with the input ends of the charge and discharge modules of each row of the pixel circuits in a one-to-one correspondence manner, N data signal lines connected with the input ends of the drive modules of each row of the pixel circuits in a one-to-one correspondence manner, and M cascaded shift registers connected with the M grid lines in a one-to-one correspondence manner; wherein the content of the first and second substances,
the M shift registers are connected with 2k clock signal lines;
the signal input end of the mth shift register is connected with the signal output end of the (m-k) th shift register;
and the signal reset end of the mth shift register is connected with the signal output end of the (m + 3) k shift register.
In a possible implementation manner, in the array substrate provided in the embodiment of the present invention, a plurality of pixel circuits in each row of the pixel circuits share the same control module.
In a possible implementation manner, in the array substrate provided in an embodiment of the present invention, three pixel circuits in each row of the pixel circuits form a pixel structure, and one pixel structure shares the same charge-discharge module.
On the other hand, an embodiment of the present invention further provides a driving method of the array substrate, including:
and loading two effective pulse signals to the signal input end of the first-stage shift register.
On the other hand, an embodiment of the present invention further provides a liquid crystal display panel, including: the array substrate provided by the embodiment of the invention.
On the other hand, the embodiment of the invention also provides a display device, which comprises the liquid crystal display panel provided by the embodiment of the invention.
The embodiment of the invention has the beneficial effects that:
according to the pixel circuit, the array substrate, the driving method thereof and the related device, the charging and discharging module and the control module are added on the basis of the driving module, two effective pulse signals loaded by each grid line in sequence are utilized, the m-k-th-stage grid line connected with the input end of the control module loads a first effective pulse signal while the m-k-th-stage grid line connected with the control end of the control module loads a second effective pulse signal, and the m-th-stage grid line connected with the input end of the charging and discharging module loads an interval time between the two effective pulse signals. The potential of the control end of the driving module can be improved through the bootstrap action of the charging and discharging module, so that the driving module is fully opened to charge the pixel electrode, and high charging rate is realized. And moreover, the control module is matched with the bootstrap action of the charge and discharge module to quickly discharge the control end of the driving module, so that the GOE is not limited by the descending time, the charging time is prolonged, and the charging capacity is further improved.
Drawings
Fig. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention;
FIG. 2 is a timing diagram of signals corresponding to FIG. 1;
FIG. 3 is a diagram of simulation results corresponding to FIG. 1;
fig. 4 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of an array substrate according to an embodiment of the present invention;
FIG. 6 is a diagram illustrating the specific connection relationship of the shift register shown in FIG. 5;
FIG. 7 is a timing diagram of GOA m in FIG. 6;
fig. 8 is a schematic partial structure diagram of an array substrate according to an embodiment of the present invention;
fig. 9 is a schematic partial structure view of an array substrate according to an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the present invention will be described in further detail with reference to the accompanying drawings, and it is apparent that the described embodiments are only a part of the embodiments of the present invention, not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The shapes and sizes of the various elements in the drawings are not to scale and are merely intended to illustrate the invention.
A pixel circuit provided in an embodiment of the present invention, as shown in fig. 1, includes: the device comprises a driving module 1, a charging and discharging module 2 and a control module 3; wherein the content of the first and second substances,
the input end of the driving module 1 is connected with a data signal line D, the output end of the driving module is connected with a pixel electrode P, and the control end of the driving module is connected with a first node A; the driving module 1 is used for conducting the data signal line D with the pixel electrode P under the control of the first node a;
the input end of the charge and discharge module 2 is connected with the mth stage grid line G m, and the output end is connected with the first node A; the charge and discharge module 2 is used for keeping the voltage between the first node a and the mth stage grid line G m stable when the first node a is in floating connection;
the input end of the control module 3 is connected to the m-k th gate line G m-k, the output end is connected to the first node a, the control end is connected to the m + k th gate line G m + k, and the control module 3 is configured to conduct the m-k th gate line Gm-k to the first node a under the control of the m + k th gate line G m + k;
wherein M is 1 and 2 … … M, M is a positive integer greater than 2, and k is a positive integer less than M, as shown in fig. 2, each gate line G is sequentially loaded with two effective pulse signals; and the m + k stage gate line G m + k is loaded with the first valid pulse signal while the m-k stage gate line G m-k is loaded with the second valid pulse signal, and the m stage gate line G m is loaded with an interval period between two valid pulse signals.
Specifically, the value of k is related to the shift register that provides the effective pulse signal to the gate lines connected to the pixel circuit, 2k is the number of clock signal lines connected to all the shift registers, and the number of clock signal lines is related to the displacement of the effective pulse signal loaded on each gate line G. For example, a minimum of 2 clock signal lines can be connected to all shift registers, the two clock signal lines alternately supplying clock signals. As another example, all shift registers may be connected to 4 clock signal lines, each two of which provide clock signals staggered by half a pulse.
The following describes in detail specific operation timings of the pixel circuit provided in the embodiment of the present invention. As shown in fig. 2, three consecutive time periods are included:
in a time period of t1, the m-k stage gate line is loaded with a second effective pulse signal, the m + k stage gate line is loaded with a first effective pulse signal, and the m stage gate line is in an interval period between loading two effective pulse signals. When the m + k-th gate line G m + k is loaded with the first active pulse signal, the control module 3 turns on the m-k-th gate line G m-k and the first node a, and charges the first node a, i.e., the control terminal of the driving module 1, so that the first node a is at the potential of the active pulse signal. When the potential of the first node a is an effective pulse signal, the driving module 1 connects the data signal line D with the pixel electrode P.
And a time period t2, wherein the m + k stage grid line is in an interval period between loading two effective pulse signals, and the m stage grid line is loaded with a second effective pulse signal. The control module 3 disconnects the m-k th stage gate line G m-k from the first node a, which is floating under the control of the m + k th stage gate line G m + k. When the first node a is in floating connection, the charge-discharge module 2 keeps the voltage between the first node a and the mth stage gate line G m stable, and because the mth stage gate line is loaded with the second effective pulse signal, the potential of the first node a, that is, the control end of the driving module 1, can be raised through the bootstrap action of the charge-discharge module 2, so that the driving module 1 is fully opened to charge the pixel electrode P, and the signal of the data signal line D is rapidly transmitted to the pixel electrode P, thereby realizing high charging rate.
In the period t3, the gate line of the (m + k) th stage is loaded with the second valid pulse signal. When the m + k-th gate line G m + k receives the second active pulse signal, the control module 3 turns on the m-k-th gate line G m-k and the first node a to discharge the first node a. Meanwhile, the m-th-stage grid line is changed from an effective pulse signal into an invalid signal, the potential of the first node A can be coupled downwards through the bootstrap action of the charging and discharging module 2, the first node A, namely the voltage of the control end of the driving module 1, can be rapidly discharged, the Falling time (Falling time) of the first node A can be reduced, the discharging speed of the first node A is improved, the Output capacity (GOE) of the grid line is not limited by the Falling time of the grid line any more, the charging time is increased, and the charging capacity is further improved.
Based on the above description, it can be seen that the pixel circuit provided in the embodiment of the present invention adds the charge and discharge module 2 and the control module 3 on the basis of the driving module 1, and uses two effective pulse signals sequentially loaded on each gate line to increase the potential of the control end of the driving module 1, and specifically, as shown in fig. 3, when the voltage of the effective pulse signal loaded on the gate line G is 22V, the potential of the first node a can reach approximately 40V, so that the driving module 1 can be fully turned on to charge the pixel electrode P, thereby implementing a high charging rate. Furthermore, as shown in fig. 3, the falling time of the effective pulse signal loaded on the gate line is 4.27 μ s, and the falling time of the first node a is only 1.1 μ s, which can quickly discharge the control terminal of the driving module 1, so that the GOE is not limited by the falling time, thereby increasing the charging time and further improving the charging capability.
Optionally, in the pixel circuit provided in the embodiment of the present invention, as shown in fig. 4, the control module 3 may include: a first switching transistor T1;
the first switching transistor T1 has a gate connected to the m + k-th stage gate line G m + k, a source connected to the m-k-th stage gate line G m-k, and a drain connected to the first node a.
Specifically, in the pixel circuit according to the embodiment of the present invention, the first switching transistor T1 is turned on when the m + k-th gate line G m + k is applied with the active pulse signal, and the signal applied to the m-k-th gate line G m-k is provided to the first node a. When the first switching transistor T1 is an N-type transistor, the active pulse signal is a high level signal; when the first switching transistor T1 is a P-type transistor, the active pulse signal is a low level signal.
Optionally, in the pixel circuit provided in the embodiment of the present invention, as shown in fig. 4, the charge-discharge module 2 includes: a capacitor C;
the capacitor C has a first terminal connected to the mth stage gate line G m and a second terminal connected to the first node a.
Specifically, in the pixel circuit provided in the embodiment of the present invention, when the first node a is in a floating state, the capacitor C uses a bootstrap action to maintain a voltage difference between the first node a and the mth stage gate line G m.
Optionally, in the pixel circuit provided in the embodiment of the present invention, as shown in fig. 4, the driving module 1 includes: a second switching transistor T2; the second switching transistor T2 has a gate connected to the first node a, a source connected to the data signal line D, and a drain connected to the pixel electrode P.
Specifically, in the above-described pixel circuit provided by the embodiment of the present invention, the second switching transistor T2 is in a conducting state under the control of the first node a, and the data signal applied to the data signal line D is supplied to the pixel electrode P. When the second switching transistor T2 is an N-type transistor, the second switching transistor T2 is in a conducting state when the first node a is at a high level; when the second switching transistor T2 is a P-type transistor, the second switching transistor T2 is turned on when the first node a is at a low level.
Based on the same inventive concept, an embodiment of the present invention further provides an array substrate, as shown in fig. 5, including M × N pixel circuits 01 arranged in an array, M gate lines G connected to input ends of charge and discharge modules of the pixel circuits 01 in respective rows in a one-to-one correspondence manner, N data signal lines D connected to input ends of driving modules of the pixel circuits 01 in respective rows in a one-to-one correspondence manner, and M cascaded shift registers GOA connected to the M gate lines G in a one-to-one correspondence manner; wherein the content of the first and second substances,
as shown in fig. 6, the M shift registers GOA are connected to 2K clock signal lines C L K;
as shown in fig. 6, the signal Input terminal Input of the mth shift register GOA m is connected to the signal Output terminal Output of the m-k shift register GOAm-k;
as shown in fig. 6, the signal Reset terminal Reset of the mth shift register GOA m is connected to the signal Output terminal Output of the (m + 3) k-th shift register GOA m +3 k.
Fig. 5 and 6 illustrate an example where M is 5, N is 6, and k is 1. Correspondingly, fig. 7 shows a signal timing diagram of the mth shift register GOA m.
Specifically, in the shift array substrate provided in the embodiment of the present invention, the cascade relation between the shift registers is changed to meet the requirement of the pixel circuit for the signal timing, so as to improve the charging capability.
In particular, the internal structure of each shift register GOA may have various implementations, and is not limited herein.
Optionally, in the array substrate provided in the embodiment of the present invention, as shown in fig. 8, a plurality of pixel circuits in each row of pixel circuits may share the same control module 3, so as to reduce the complicated length of the wiring. Fig. 8 illustrates an example in which six pixel circuits share one control block 3. Specifically, it can be seen from the simulation result that the fall time of the effective pulse signal loaded on the gate line is 4.27 μ s, and after the six pixel circuits 01 share one control module 3, the fall time of the first node a is 1.4 μ s, which is greater than the simulation result of not sharing the control module 3, but still has a significant charge boosting effect. Also, the fall time can be reduced by increasing the size of the control module 3.
Optionally, in the array substrate provided in the embodiment of the present invention, as shown in fig. 9, three pixel circuits in each row of pixel circuits form a pixel structure, and one pixel structure may share the same charge and discharge module 2, so as to reduce the complexity of the pixel circuit 01. Alternatively, each pixel circuit 01 may not share the charge and discharge module 2, and is not limited herein.
Based on the same inventive concept, an embodiment of the present invention further provides a driving method of the array substrate, including:
and loading two effective pulse signals to the signal input end of the first stage shift register so that the signal output end of each stage of shift register can shift and output two effective pulse signals.
Based on the same inventive concept, an embodiment of the present invention further provides a liquid crystal display panel, including: the array substrate provided by the embodiment of the invention. Since the principle of solving the problems of the liquid crystal display panel is similar to that of the array substrate, the implementation of the liquid crystal display panel can refer to the implementation of the array substrate, and repeated details are not repeated.
Based on the same inventive concept, the embodiment of the invention also provides a display device, which comprises the liquid crystal display panel provided by the embodiment of the invention. The display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. Since the principle of the display device to solve the problem is similar to the aforementioned array substrate, the display device can be implemented according to the above embodiment of the array substrate, and repeated descriptions are omitted.
In the pixel circuit, the array substrate and the driving method and related device thereof provided by the embodiment of the invention, the charging and discharging module and the control module are added on the basis of the driving module, and two effective pulse signals loaded by each grid line in sequence are utilized, while the second effective pulse signal is loaded on the m-k level grid line connected with the input end of the control module, the first effective pulse signal is loaded on the m + k level grid line connected with the control end of the control module, and the interval time interval between the two effective pulse signals is loaded on the m level grid line connected with the input end of the charging and discharging module.
The potential of the control end of the driving module can be improved through the bootstrap action of the charging and discharging module, so that the driving module is fully opened to charge the pixel electrode, and high charging rate is realized. And moreover, the control module is matched with the bootstrap action of the charge and discharge module to quickly discharge the control end of the driving module, so that the GOE is not limited by the descending time, the charging time is prolonged, and the charging capacity is further improved.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. A pixel circuit, the pixel circuit includes a driving module, an input end of the driving module is connected with a data signal line, and an output end of the driving module is connected with a pixel electrode, the pixel circuit further includes: a charge-discharge module and a control module; wherein the content of the first and second substances,
the control end of the driving module is connected with the first node; the driving module is used for conducting the data signal line and the pixel electrode under the control of the first node;
the input end of the charge-discharge module is connected with the mth stage grid line, and the output end of the charge-discharge module is connected with the first node; the charge and discharge module is used for keeping the voltage between the first node and the mth stage grid line stable when the first node is in floating connection;
the input end of the control module is connected with the m-k stage grid line, the output end of the control module is connected with the first node, the control end of the control module is connected with the m + k stage grid line, and the control module is used for conducting the m-k stage grid line and the first node under the control of the m + k stage grid line;
wherein, M is 1 and 2 … … M, M is a positive integer greater than 2, k is a positive integer less than M, and each grid line is loaded with two effective pulse signals in sequence; and loading a second effective pulse signal on the m-k stage grid line, loading a first effective pulse signal on the m + k stage grid line, and loading an interval time interval between two effective pulse signals on the m + k stage grid line.
2. The pixel circuit of claim 1, wherein the control module comprises: a first switching transistor;
and the grid electrode of the first switch transistor is connected with the (m + k) th stage grid line, the source electrode of the first switch transistor is connected with the (m-k) th stage grid line, and the drain electrode of the first switch transistor is connected with the first node.
3. The pixel circuit according to claim 1, wherein the charge-discharge module comprises: a capacitor;
and the first end of the capacitor is connected with the m-th stage grid line, and the second end of the capacitor is connected with the first node.
4. The pixel circuit of claim 1, wherein the driving module comprises: a second switching transistor; and the grid electrode of the second switching transistor is connected with the first node, the source electrode of the second switching transistor is connected with the data signal line, and the drain electrode of the second switching transistor is connected with the pixel electrode.
5. An array substrate, comprising M × N pixel circuits according to any one of claims 1 to 4 arranged in an array, M gate lines connected to input terminals of charge and discharge modules of the pixel circuits in respective rows in a one-to-one correspondence, N data signal lines connected to input terminals of drive modules of the pixel circuits in respective columns in a one-to-one correspondence, and M cascaded shift registers connected to the M gate lines in a one-to-one correspondence; wherein the content of the first and second substances,
the M shift registers are connected with 2k clock signal lines;
the signal input end of the mth shift register is connected with the signal output end of the (m-k) th shift register;
and the signal reset end of the mth shift register is connected with the signal output end of the (m + 3) k shift register.
6. The array substrate of claim 5, wherein a plurality of pixel circuits in each row of the pixel circuits share a same control module.
7. The array substrate of claim 5, wherein three pixel circuits in each row of the pixel circuits form a pixel structure, and one of the pixel structures shares a same charge-discharge module.
8. A driving method of the array substrate according to any one of claims 5 to 7, comprising:
and loading two effective pulse signals to the signal input end of the first-stage shift register.
9. A liquid crystal display panel, comprising: an array substrate as claimed in any one of claims 5 to 7.
10. A display device comprising the liquid crystal display panel according to claim 9.
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| CN117280403A (en) * | 2022-03-22 | 2023-12-22 | 京东方科技集团股份有限公司 | Display panel driving method and display device |
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