CN111627405A - Display driving circuit, driving method thereof and display device - Google Patents
Display driving circuit, driving method thereof and display device Download PDFInfo
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- CN111627405A CN111627405A CN202010524441.7A CN202010524441A CN111627405A CN 111627405 A CN111627405 A CN 111627405A CN 202010524441 A CN202010524441 A CN 202010524441A CN 111627405 A CN111627405 A CN 111627405A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
Abstract
The application discloses a display driving circuit, a driving method thereof and a display device, wherein the display driving circuit comprises a plurality of pixel units and a plurality of boost lines which are arranged in an array, each of the plurality of boost lines corresponds to one row of pixel units and is electrically connected with a grid electrode of a driving transistor in each pixel unit of the corresponding row of pixel units, two ends of each of the plurality of boost lines are respectively connected with a high potential signal and a low potential signal, one side of each of the plurality of boost lines, which is close to the high potential signal, is provided with a first transistor, and one side of each of the plurality of boost lines, which is close to the low potential signal, is provided with a second transistor; compared with the prior art, the display driving circuit has the advantages that the stability of the display driving circuit is improved, the charging rate is improved, the power consumption is saved, and the loss of the pixel aperture opening ratio is avoided.
Description
Technical Field
The present disclosure relates to display driving technologies, and in particular, to a display driving circuit, a driving method thereof, and a display device.
Background
With the development of display technology, the display requirement is higher and higher, and the requirement can meet the requirements of high-frequency dynamic picture display (smoother image quality) and low power consumption of ordinary display, so the dynamic frame frequency technology is produced, and the requirements of a display area for simultaneously meeting the requirements of ultralow frequency (1-5Hz) and ultrahigh frequency (120-360Hz) display panels have the following points: the charging capability is strong (the charging time of each line in a high-frequency state is extremely short), and the Holding capability of the picture is strong, but the prior art cannot meet the requirements at the same time.
At present, the application of the device can be expanded to the fields of ultra-Low frequency and high frequency display by utilizing an LTPO (Low temperature polycrystalline Oxide) technology, the purpose of optimizing power consumption and improving visual experience is realized, but because the mobility of an Oxide semiconductor is Low, when the high frequency display is carried out, the display area often has the problem of insufficient charging level due to short charging time, so that the current of the display area needs to be improved, and the current is improved on a given active layer structure by two modes: one is to increase the aspect ratio and the other is to increase the gate-source voltage difference; increasing the length-width ratio causes the problem of reducing the panel opening due to the fact that the occupied space of the transistor is too large, increasing the voltage difference between the gate and the source increases the potential of all transistors in the panel, affects the overall stability of the driving circuit, and how to drive the oxide semiconductor in the display area with higher voltage, and simultaneously ensures that the stability of the GOA circuit is not reduced, which becomes a problem to be solved urgently.
Disclosure of Invention
The embodiment of the application provides a display driving circuit, a driving method thereof and a display device, and can solve the technical problem that in the prior art, the display driving circuit is difficult to improve both the charging speed and the circuit stability, and further the display is influenced.
To solve the above technical problem, an embodiment of the present application provides a display driving circuit, including: the pixel structure comprises a plurality of rows of driving lines and a plurality of columns of data lines, wherein the driving lines and the data lines are mutually vertically crossed to form a plurality of pixel units arranged in an array, each pixel unit comprises a driving transistor and a first node, and the first node is electrically connected with a grid electrode of the driving transistor; and each of the plurality of boosting lines corresponds to one row of the pixel units and is electrically connected with the first node in each pixel unit of the corresponding row of the pixel units, two ends of each of the plurality of boosting lines are respectively connected with a high potential signal and a low potential signal, a first transistor is arranged on one side, close to the high potential signal, of each of the plurality of boosting lines, and a second transistor is arranged on one side, close to the low potential signal, of each of the plurality of boosting lines.
In an embodiment of the present application, each of the plurality of pixel units includes a boost capacitor, and one end of the boost capacitor is electrically connected to the first node in the corresponding pixel unit, and the other end of the boost capacitor is electrically connected to the driving line in the corresponding row.
In an embodiment of the present application, the display driving circuit includes a plurality of cascaded GOA units, the plurality of GOA units are alternately disposed on opposite sides of the display driving circuit, and the plurality of GOA units correspond to the plurality of driving lines one to one and are electrically connected to the plurality of driving lines.
In an embodiment of the present application, a source of the first transistor is connected to the high-potential signal, a drain of the first transistor is connected to the first node in the corresponding row of the pixel units, and a gate of the first transistor is connected to a scanning signal output by the GOA unit corresponding to the driving line in the previous row.
In an embodiment of the present application, a source of the second transistor is connected to the low potential signal, a drain of the second transistor is connected to the first node in the corresponding row of the pixel units, and a gate of the second transistor is connected to a scan signal output by the GOA unit corresponding to the driving line in the next row or a clock signal in the GOA unit corresponding to the driving line in the next row.
In an embodiment of the present application, each of the plurality of pixel units includes a liquid crystal capacitor and a storage capacitor, the liquid crystal capacitor is connected in parallel with the storage capacitor, and one end of the liquid crystal capacitor is electrically connected to the drain of the driving transistor, and the other end of the liquid crystal capacitor is electrically connected to a common voltage.
In an embodiment of the present application, each of the plurality of rows of data lines corresponds to one row of the pixel units and is electrically connected to the source of the driving transistor in the corresponding row of the pixel units.
According to the above object of the present application, there is provided a driving method of the display driving circuit, the method comprising: the GOA units corresponding to the driving lines in the upper row output high-potential scanning signals to enable the first transistor to be conducted, and the potential of the first node is pulled up to a first potential; the GOA units corresponding to the driving lines in the row output high-potential scanning signals, the first node potential is pulled up to a second potential through the first capacitor, and the driving transistor is conducted, so that data signals in the data lines are led into the pixel units; and outputting a high-potential scanning signal by the GOA unit corresponding to the driving line in the next row or outputting a high-potential clock signal by the GOA unit corresponding to the driving line in the next row, so that the second transistor is conducted to pull down the first node to be a low potential.
In an embodiment of the present application, the second potential is greater than a potential of the high-potential scan signal or the high-potential clock signal, a potential of the high-potential scan signal or the high-potential clock signal is greater than the first potential, and the first potential is greater than a potential of the low-potential signal.
According to the above object of the present application, there is provided a display device including the display driving circuit.
The beneficial effect of this application: this application is through setting up the line of stepping up that connects the drive transistor in the pixel element of a line, and set up the first transistor of input high potential signal and the second transistor of input low potential signal at the line of stepping up both ends, so that when the pixel element of a line drives, can carry out the preliminary filling through first transistor in advance, with promoting drive transistor gate potential, make drive transistor can promote charge rate when driving, the power consumption has been saved, the stability of showing drive circuit has been improved, and the first transistor and the second transistor that set up do not occupy the pixel district, the loss of aperture ratio has been avoided.
Drawings
The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a schematic diagram of a display driving circuit according to an embodiment of the present disclosure.
Fig. 2 is a schematic circuit diagram of a pixel unit according to an embodiment of the present disclosure.
Fig. 3 is a timing diagram of potential signals according to an embodiment of the present disclosure.
Fig. 4 is a flowchart of a driving method of a display driving circuit according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact of the first and second features, or may comprise contact of the first and second features not directly but through another feature in between. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials.
The embodiment of the application aims at the existing display driving circuit, and the technical problem of display is influenced because the display driving circuit is difficult to give consideration to improvement of the charging speed and the stability of the circuit.
An embodiment of the present application provides a display driving circuit, please refer to fig. 1 and fig. 2, the display driving circuit includes: a plurality of rows of driving lines 102 and a plurality of columns of data lines 101, which are vertically crossed to form a plurality of pixel units 104 arranged in an array, wherein each of the plurality of pixel units 104 includes a driving transistor T0 and a first node Pn, and the first node Pn is electrically connected to a gate of the driving transistor T0; and a plurality of boost lines 103, each of the plurality of boost lines 103 corresponds to one row of the pixel units 104 and is electrically connected to the first node Pn in each of the pixel units 104 of the corresponding row of the pixel units 104, two ends of each of the plurality of boost lines 103 are respectively connected to a high potential signal VGH and a low potential signal VGL, a first transistor T1 is disposed on one side of each of the plurality of boost lines close to the high potential signal VGH, and a second transistor T2 is disposed on one side of each of the plurality of boost lines close to the low potential signal VGL.
In the implementation and application process, the conventional display driving circuit often has the problem of insufficient charging level, so that the current of the display driving circuit needs to be increased, and at present, two ways of increasing the current on an active layer structure are provided: one is to increase the aspect ratio and the other is to increase the gate-source voltage difference; the problem that the length-width ratio is too large in occupied space of transistors and the aperture ratio of a panel is reduced is solved, and the voltage difference between a grid electrode and a source electrode is increased, so that the voltage of all the transistors in the panel is increased and the stability of the whole driving circuit is influenced, in the embodiment of the invention, a boosting line is arranged on each row of pixel units, a high potential signal and a low potential signal are respectively arranged at two ends of the boosting line, a first transistor is arranged at one side close to the high potential signal, a second transistor is arranged at one side close to the low potential signal, so that when one row of pixel units are driven, pre-charging can be carried out through the first transistor in advance to improve the grid electrode potential of the driving transistor, the charging rate of the driving transistor can be improved when the driving transistor is driven, the power consumption is saved, the stability of a display driving circuit is improved, and the arranged, the loss of the aperture ratio is avoided.
Specifically, please continue to refer to fig. 1 and fig. 2, the display driving circuit includes a plurality of columns of data lines 101 and a plurality of rows of scan lines 102, which are perpendicularly crossed with each other, the plurality of columns of data lines 101 and the plurality of rows of scan lines 102 are staggered to form a plurality of pixel units 104 arranged in an array, and the plurality of pixel units 104 include a plurality of columns arranged along the plurality of columns of data lines 101 and a plurality of rows arranged along the plurality of rows of driving lines 102.
The display driving circuit further includes a plurality of boost lines 103, each of the plurality of boost lines 103 corresponds to one row of the pixel units 104, that is, the plurality of boost lines 103 may be arranged in multiple rows, and in addition, two ends of each boost line 103 are equally connected to a high potential signal VGH and a low potential signal VGL, respectively, wherein a first transistor T1 is disposed on one side of each boost line 103 close to the high potential signal VGH, and a second transistor T2 is disposed on one side of each boost line 103 close to the low potential signal VGL.
Furthermore, each pixel unit 104 includes a driving transistor T0, a first node Pn electrically connected to the gate of the driving transistor T0, a liquid crystal capacitor Clc and a storage capacitor Cst electrically connected to the drain of the driving transistor T0 and connected in parallel, wherein one end of the liquid crystal capacitor Clc and the storage capacitor Cst are electrically connected to the drain of the driving transistor T0, the other end of the liquid crystal capacitor Clc and the storage capacitor Cst are electrically connected to a common voltage Vcom, and the source of the driving transistor T0 is electrically connected to a corresponding row of the data lines 101.
Each pixel unit 104 further includes a boost capacitor C0, one end of the boost capacitor C0 is electrically connected to the first node Pn in the corresponding pixel unit, and the other end of the boost capacitor C0 is electrically connected to the corresponding driving line 102, and when the present row scanning signal Gn in the driving line 102 is introduced into the pixel unit 104, due to the bootstrap effect of the boost capacitor C0, the first node Pn can be raised to a higher potential, that is, the gate of the driving transistor T0 is raised to a higher potential, so as to increase the charging rate and improve the display effect.
The display driving circuit further includes a plurality of cascaded GOA units 105, the plurality of GOA units 105 are alternately disposed on two opposite sides of the display driving circuit, and the plurality of GOA units 105 are in one-to-one correspondence with the plurality of rows of driving lines 102 and electrically connected thereto, that is, as shown in fig. 1, a first row of the driving lines 102 is electrically connected to a first GOA unit 105 located on the left side, a second row of the driving lines 102 is electrically connected to a second GOA unit 105 located on the right side, and so on, the plurality of GOA units 105 are alternately disposed on two sides of the display driving circuit and electrically connected to a corresponding row of the driving lines 102.
In the embodiment of the present application, the source of the first transistor T1 is connected to the high voltage signal VGH, the drain of the first transistor T1 is connected to the first node Pn in the corresponding row of the pixel units 104, and the gate of the first transistor T1 is connected to the scanning signal Gn-1 output by the GOA unit 105 corresponding to the driving line 102 in the previous row.
The source of the second transistor T2 is connected to the low potential signal VGL, the drain of the second transistor T2 is connected to the first node Pn in the corresponding row of the pixel units 104, and the gate of the second transistor T2 is connected to the scan signal Gn +1 output by the GOA unit 105 corresponding to the driving line 102 in the next row or the clock signal CKn +1 in the GOA unit corresponding to the driving line in the next row.
Next, a driving method of the display driving circuit provided in the embodiment of the present application is described with reference to fig. 1, fig. 2, fig. 3, and fig. 4.
It should be noted that, in the embodiment of the present application, the high potential signal VGH is VH, the low potential signal VGL is VL, and the high potential of the scan signal Gn-1 output by the GOA unit 105 corresponding to the driving line 102 in the previous row may be VH, the low potential may be VL, the high potential of the scan signal Gn +1 output by the GOA unit 105 corresponding to the driving line 102 in the next row or the high potential of the clock signal CKn +1 in the GOA unit corresponding to the driving line in the next row may be VH, and the low potential may be VL.
When the scanning signal Gn-1 output by the GOA unit 105 corresponding to the driving line 102 in the previous row is a high potential VH, the first transistor T1 is turned on, and the high potential signal VGH is coupled to the first node Pn, so that the potential of the first node Pn is pulled up to a first potential V1.
When the scanning signal Gn output by the GOA unit 105 corresponding to the driving line 102 in the row is a high voltage VH, the high voltage VH is applied to the first capacitor C0, and the voltage level of the first node Pn is pulled up to the second voltage V2 by the bootstrap action of the first capacitor C0, so that the driving transistor T0 is turned on to pass the data signal Vdata in the data line 101 into the pixel unit 104.
When the scanning signal Gn +1 output by the GOA unit 105 corresponding to the next driving line 102 or the clock signal CKn +1 output by the GOA unit 105 corresponding to the next driving line 102 is the high potential VH, the second transistor T2 is turned on to pull down the first node Pn to the low potential VL, thereby completing the data writing.
In the embodiment of the present application, the second potential V2 is greater than the high potential VH, the high potential VH is greater than the first potential V1, and the first potential V1 is greater than the low potential VL, wherein the second potential V2 is greater than the high potential VH due to the bootstrap effect of the boost capacitor C0.
In summary, in the display driving circuit and the driving method thereof provided by the embodiment of the present application, the boost line connected to the driving transistors in a row of pixel units is provided, and the first transistor for inputting a high potential signal and the second transistor for inputting a low potential signal are provided at two ends of the boost line, so that when a row of pixel units is driven, pre-charging can be performed in advance through the first transistor to increase the gate potential of the driving transistor, and the boost capacitor is provided between the driving line and the gate of the driving transistor, so that the gate of the driving transistor can be raised to a higher potential, so that the charging rate of the driving transistor can be increased during driving, power consumption is reduced, the gate-source voltage difference in the display driving circuit is not increased, the stability of the display driving circuit is improved, and the provided first transistor and the second transistor do not occupy the pixel region and do not increase the aspect ratio, the loss of the aperture opening ratio is avoided, and the display effect is improved.
In addition, an embodiment of the present application further provides a display device, and the display device includes the display driving circuit described in the above embodiment, and the structure and principle of the display driving circuit are the same as those described in the above embodiment, and are not described herein again.
The display device provided by the embodiment of the application can be applied to an LTPO (low temperature polycrystalline Oxide) display device, and due to the display driving circuit provided by the embodiment of the application, the driving transistor can be rapidly charged, and the circuit is stable, so that the display device provided by the embodiment of the application can realize ultralow frequency and high frequency display, and has the advantages of strong driving capability and low power consumption.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The display driving circuit, the driving method thereof, and the display device provided in the embodiments of the present application are described in detail above, and specific examples are applied herein to explain the principle and the implementation of the present application, and the description of the embodiments above is only used to help understanding the technical solutions and the core ideas of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.
Claims (10)
1. A display driving circuit, comprising:
the pixel structure comprises a plurality of rows of driving lines and a plurality of columns of data lines, wherein the driving lines and the data lines are mutually vertically crossed to form a plurality of pixel units arranged in an array, each pixel unit comprises a driving transistor and a first node, and the first node is electrically connected with a grid electrode of the driving transistor; and
each of the plurality of boosting lines corresponds to one row of the pixel units and is electrically connected with the first node in each pixel unit of the corresponding row of the pixel units, two ends of each of the plurality of boosting lines are respectively connected with a high potential signal and a low potential signal, a first transistor is arranged on one side, close to the high potential signal, of each of the plurality of boosting lines, and a second transistor is arranged on one side, close to the low potential signal, of each of the plurality of boosting lines.
2. The display driving circuit according to claim 1, wherein each of the plurality of pixel units comprises a boost capacitor, and one end of the boost capacitor is electrically connected to the first node in the corresponding pixel unit, and the other end of the boost capacitor is electrically connected to the driving line in the corresponding row.
3. The display driving circuit according to claim 1, wherein the display driving circuit comprises a plurality of cascaded GOA units, the GOA units are alternately arranged on two opposite sides of the display driving circuit, and the GOA units are in one-to-one correspondence with the plurality of driving lines and are electrically connected with the plurality of driving lines.
4. The display driving circuit according to claim 3, wherein a source of the first transistor is connected to the high-potential signal, a drain of the first transistor is connected to the first node in the corresponding row of the pixel units, and a gate of the first transistor is connected to a scan signal output by the GOA unit corresponding to the driving line in the previous row.
5. The display driving circuit according to claim 4, wherein a source of the second transistor is connected to the low potential signal, a drain of the second transistor is connected to the first node in the corresponding row of the pixel units, and a gate of the second transistor is connected to a scan signal output by the GOA unit corresponding to the driving line in the next row or a clock signal in the GOA unit corresponding to the driving line in the next row.
6. The display driving circuit according to claim 1, wherein each of the plurality of pixel units comprises a liquid crystal capacitor and a storage capacitor, the liquid crystal capacitor is connected in parallel with the storage capacitor, and one end of the liquid crystal capacitor is electrically connected to the drain of the driving transistor, and the other end of the liquid crystal capacitor is electrically connected to a common voltage.
7. The display driving circuit according to claim 1, wherein each of the plurality of rows of data lines corresponds to one row of the pixel units and is electrically connected to the source of the driving transistor in the corresponding row of the pixel units.
8. A method of driving a display driver circuit according to any one of claims 1 to 7, the method comprising:
the GOA units corresponding to the driving lines in the upper row output high-potential scanning signals to enable the first transistor to be conducted, and the potential of the first node is pulled up to a first potential;
the GOA units corresponding to the driving lines in the row output high-potential scanning signals, the first node potential is pulled up to a second potential through the first capacitor, and the driving transistor is conducted, so that data signals in the data lines are led into the pixel units; and
the GOA units corresponding to the driving lines in the next row output high-potential scanning signals or high-potential clock signals, so that the second transistor is conducted to pull down the first node to be low potential.
9. The method for driving the display driver circuit according to claim 8, wherein the second potential is higher than a potential of the high-potential scan signal or the high-potential clock signal, wherein a potential of the high-potential scan signal or the high-potential clock signal is higher than the first potential, and wherein the first potential is higher than a potential of the low-potential signal.
10. A display device characterized by comprising the display drive circuit according to any one of claims 1 to 7.
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