CN101950522A - Shift register circuit - Google Patents
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- CN101950522A CN101950522A CN 201010289603 CN201010289603A CN101950522A CN 101950522 A CN101950522 A CN 101950522A CN 201010289603 CN201010289603 CN 201010289603 CN 201010289603 A CN201010289603 A CN 201010289603A CN 101950522 A CN101950522 A CN 101950522A
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Abstract
The invention discloses a shift register circuit, comprising a multi-level shift register, wherein each-level shift register is used for outputting a corresponding starting pulse signal and a corresponding driving pulse signal. Each-level shift register comprises a pull-up circuit, a first drive circuit, a second drive circuit and a discharging circuit, wherein the pull-up circuit is used for charging a first node; the first drive circuit generates the corresponding starting pulse signal; the second drive circuit generates the corresponding driving pulse signal; and the discharging circuit is used for discharging the first node before discharging the output end of the second drive circuit.
Description
Technical field
The present invention relates to the display technique field, and particularly relevant for a kind of shift register circuit.
Background technology
Existing application is in flat-panel screens, for example the shift register circuit of LCD generally comprises the shift register of a plurality of grades of coupled in series, in order to produce a plurality of drive pulse signals in regular turn, for example in order to the grid level drive pulse signal of the gate line that drives LCD successively; And the starting impulse signal of the correspondence that each shift register produced can transfer to the next stage shift register so that the next stage shift register is started working.
Existing shift register circuit utilizes amorphous silicon (a-Si) or polysilicon (p-Si) technology and is produced on the glass substrate, save whereby grid drive chip cost, simplify the modular segment manufacturing process and increase glass substrate utilization ratio etc.But, therefore need design larger area thin film transistor (TFT) could effectively drive the gate line of LCD because the carrier transport factor of its material is lower.And large-area more its parasitic capacitance effect that is produced of thin film transistor (TFT) is just big more, causes dynamic power consumption significantly to rise, thereby has limited its range of application.
Summary of the invention
Purpose of the present invention is to provide a kind of shift register circuit exactly, and it can reduce relevant dynamic power consumption significantly.
The present invention proposes a kind of shift register circuit, comprises multi-stage shift register, and every grade of shift register is in order to export the starting impulse signal and the drive pulse signal of a correspondence.Moreover every grade of shift register comprises pull-up circuit, first driving circuit, second driving circuit and discharge circuit respectively.The previous starting impulse signal that pull-up circuit reception previous stage shift register is exported and a reference signal are to charge to first node.First driving circuit is in first node place electric property coupling pull-up circuit, and the corresponding clock pulse signal of reception produces corresponding starting impulse signal with the current potential according to first node.Second driving circuit is also in first node place electric property coupling pull-up circuit, and receives high reference potential with in the corresponding drive pulse signal of output terminal output.Discharge circuit comprises the first transistor and transistor seconds.Wherein the first transistor comprises first control end, first path terminal and alternate path end, the first path terminal electric property coupling first node, and alternate path end electric property coupling hangs down reference potential, and first control end receives first control signal in the very first time section first node is discharged.Transistor seconds comprises second control end, the 3rd path terminal and four-way terminal, the output terminal of the 3rd path terminal electric property coupling second driving circuit, and four-way terminal electric property coupling hangs down reference potential, and second control end receives second control signal and discharges with the output terminal to second driving circuit in second time period.Wherein, the startup of the very first time section moment is early than the startup moment of second time period.
In preferred embodiment of the present invention, the back one-level starting impulse signal that first control signal that first control end received of above-mentioned the first transistor is exported for back one-level shift register is to discharge to the current potential on the first node in very first time section; And the back secondary starting impulse signal that second control signal that second control end received of transistor seconds is exported for back two-stage shift register discharges with the output terminal to second driving circuit in second time period.
In preferred embodiment of the present invention, above-mentioned discharge circuit further comprises the 3rd transistor, and it comprises the 3rd control end, five-way terminal and the 6th path terminal.Second control end of five-way terminal electric property coupling transistor seconds, and the low reference potential of the 6th path terminal electric property coupling.Wherein, the 3rd control end receives the back secondary starting impulse signal that the current potential on the first node is received with second control end of revising transistor seconds.
In preferred embodiment of the present invention, the back secondary drive pulse signal that first control signal that first control end received of above-mentioned the first transistor is exported for back two-stage shift register is to discharge to first node in very first time section; And second control signal that second control end of transistor seconds is received is back three drive pulse signals that back three grades of shift registers are exported, and discharges with the output terminal to second driving circuit in second time period.
In preferred embodiment of the present invention, the back secondary drive pulse signal that first control signal that first control end received of above-mentioned the first transistor is exported for back two-stage shift register is to discharge to first node in very first time section; And the back secondary starting impulse signal that second control signal that second control end received of transistor seconds is exported for back two-stage shift register discharges with the output terminal to second driving circuit in second time period.
In preferred embodiment of the present invention, above-mentioned pull-up circuit comprises the 4th transistor, and the 4th transistor comprises the 4th control end, the 7th path terminal and the 8th path terminal.The 4th control end receives the previous starting impulse signal that the previous stage shift register is exported, and the 7th path terminal receives reference signal, and the 8th path terminal electric property coupling first node.
In preferred embodiment of the present invention, above-mentioned reference signal is high reference potential.Perhaps, reference signal is the previous drive pulse signal that the previous stage shift register is exported.Perhaps, reference signal is the previous starting impulse signal that the previous stage shift register is exported.
In preferred embodiment of the present invention, the first above-mentioned driving circuit comprises the 5th transistor and electric capacity.The 5th transistor comprises the 5th control end, the 9th path terminal and the tenth path terminal.The 5th control end electric property coupling first node, the 9th path terminal are in order to receiving corresponding clock pulse signal, and the tenth path terminal is in order to export corresponding starting impulse signal.Electric capacity is electrically coupled between first node and the tenth path terminal.
In preferred embodiment of the present invention, the second above-mentioned driving circuit comprises the 6th transistor, and it comprises the 6th control end, the 11 path terminal and the 12 path terminal.The 6th control end electric property coupling first node, the 11 path terminal are in order to receiving high reference potential, and the 12 path terminal is in order to export corresponding drive pulse signal.
In preferred embodiment of the present invention, every grade of above-mentioned shift register further comprises first mu balanced circuit and first controlling circuit of voltage regulation.First mu balanced circuit is the output terminal of electric property coupling first node and second driving circuit respectively, and whether the first controlling circuit of voltage regulation electric property coupling, first mu balanced circuit and the control that receives at least one control signal discharge to the output terminal of the first node and second driving circuit to determine first mu balanced circuit.
In preferred embodiment of the present invention, the first above-mentioned mu balanced circuit comprises the 7th transistor and the 8th transistor.The 7th transistor comprises the 7th control end, the 13 path terminal and the tenth four-way terminal.The output terminal of the 7th control end electric property coupling first controlling circuit of voltage regulation, the 13 path terminal are used to receive corresponding drive pulse signal, and the tenth four-way terminal electric property coupling first node.The 8th transistor comprises the 8th control end, the tenth five-way terminal and the 16 path terminal.The output terminal of the 8th control end electric property coupling first controlling circuit of voltage regulation, the tenth five-way terminal electric property coupling hangs down reference potential, and the output terminal of the 16 path terminal electric property coupling second driving circuit.
In preferred embodiment of the present invention, the first above-mentioned controlling circuit of voltage regulation comprises the 9th transistor, the tenth transistor, the 11 transistor and the tenth two-transistor.The 9th transistor comprises the 9th control end, the 17 path terminal and the 18 path terminal.The 9th control end electric property coupling reference potential, the 17 path terminal is the electric property coupling reference potential also.The tenth transistor comprises the tenth control end, the 19 path terminal and the 20 path terminal.The tenth control end is used to receive the 3rd control signal, and the 19 path terminal electric property coupling the 18 path terminal and its junction are as Section Point, and the low reference potential of the 20 path terminal electric property coupling.The 11 transistor comprises the 11 control end, the 21 path terminal and the 22 path terminal.The 11 control end electric property coupling Section Point, the 21 path terminal electric property coupling reference potential.The tenth two-transistor comprises the 12 control end, the 23 path terminal and the 20 four-way terminal.The 12 control end also is used to receive the 3rd control signal, and the 23 path terminal electric property coupling hangs down reference potential, and the 20 four-way terminal, electric property coupling the 22 path terminal and its couple the output terminal of place as first controlling circuit of voltage regulation.
In preferred embodiment of the present invention, the 3rd above-mentioned control signal is corresponding drive pulse signal.
In preferred embodiment of the present invention, the first above-mentioned controlling circuit of voltage regulation further comprises the 13 transistor and the 14 transistor.The 13 transistor comprises the 13 control end, the 20 five-way terminal and the 26 path terminal.The 13 control end is used to receive the 4th control signal, the 20 five-way terminal electric property coupling Section Point, and the low reference potential of the 26 path terminal electric property coupling.The 14 transistor comprises the 14 control end, the 27 path terminal and the 28 path terminal.The 14 control end also is used to receive the 4th control signal, and the 27 path terminal electric property coupling hangs down reference potential, and the output terminal of the 28 path terminal electric property coupling first controlling circuit of voltage regulation.
In preferred embodiment of the present invention, the 4th above-mentioned control signal is the previous drive pulse signal that the previous stage shift register is exported.Perhaps the 4th control signal is corresponding starting impulse signal.
In preferred embodiment of the present invention, the 3rd above-mentioned control signal is the current potential on the first node.
Second driving circuit of shift register of the present invention is by fixing high reference potential its output terminal to be charged, and discharge circuit is before the output terminal to second driving circuit discharges, and first node is discharged drags down current potential on the first node earlier.Can prevent that so the high reference potential of fixing from docking earthy output, therefore can reduce the power consumption of shift register significantly.
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and cooperate appended accompanying drawing, be described in detail below.
Description of drawings
Fig. 1 illustrates the partial structurtes synoptic diagram into the disclosed shift register circuit of one embodiment of the invention;
Fig. 2 illustrates the block schematic diagram into the disclosed shift register of one embodiment of the invention;
Fig. 3 illustrates the physical circuit synoptic diagram into shift register shown in Figure 2;
Fig. 4 illustrates the sequential chart into various signals shown in Figure 3;
Fig. 5 illustrates the synoptic diagram into the disclosed pull-up circuit of another embodiment of the present invention;
Fig. 6 illustrates the synoptic diagram into the disclosed pull-up circuit of further embodiment of this invention;
Fig. 7 illustrates the synoptic diagram into the disclosed discharge circuit of another embodiment of the present invention;
Fig. 8 illustrates the synoptic diagram into the disclosed discharge circuit of further embodiment of this invention;
Fig. 9 illustrates the synoptic diagram into disclosed first controlling circuit of voltage regulation of another embodiment of the present invention;
Figure 10 illustrates the synoptic diagram into disclosed first controlling circuit of voltage regulation of further embodiment of this invention;
Figure 11 illustrates the synoptic diagram into disclosed first controlling circuit of voltage regulation of yet another embodiment of the invention.
Wherein, Reference numeral
100: shift register circuit SR (n-1), SR (n), SR (n+1): shift register
110: 120: the first driving circuits of pull-up circuit
160: the first mu balanced circuits of 150: the first controlling circuit of voltage regulation
180: the second mu balanced circuits of 170: the second controlling circuit of voltage regulation
VGH: high reference potential VSS: low reference potential
Q (n): first node
HC (m), HC (1), HC (2), HC (3), HC (4): clock pulse signal
A (n): Section Point P (n): the 3rd node
LC1: the first reference potential LC2: second reference potential
C2: electric capacity
T1、T2、T3、T41、T42、T45、T51、T52、T53、T54、T55、T56、T61、
T62: transistor
ST(n-2)、ST(n-1)、ST(n)、ST(n+1)、ST(n+2)、ST(1)、ST(2)、ST(3)、ST(4)：
The starting impulse signal
G (n-1), G (n), G (n+1), G (n+2), G (n+3), G (1), G (2), G (3), G (4): grid drives
Artery is towards signal
Embodiment
See also Fig. 1, it illustrates the partial structurtes synoptic diagram into the disclosed shift register circuit of one embodiment of the invention.As shown in Figure 1, shift register circuit 100 disclosed in this invention is applicable to the gate driver circuit of LCD, driving the gate line of LCD successively, but the present invention is not limited to this, and for example it also can be applicable to the source class driving circuit of LCD.Shift register circuit 100 comprises shift register that a plurality of cascades couple for example SR (n-1), SR (n) and SR (n+1) etc., wherein each shift register is in order to producing corresponding gate driving pulse signal such as G (n-1), G (n) or G (n+1) in order, and produces corresponding starting impulse signal such as ST (n-1), ST (n) and ST (n+1).And the starting impulse signal of the correspondence that each shift register produced transfers to the next stage shift register so that the next stage shift register is started working.
See also Fig. 2 and Fig. 3, wherein Fig. 2 illustrates the block schematic diagram into the disclosed shift register of one embodiment of the invention, and Fig. 3 illustrates the physical circuit synoptic diagram into shift register shown in Figure 2.As Fig. 2-shown in Figure 3, present embodiment is that example is introduced the present invention with shift register SR (n) shown in Figure 1.Particularly, shift register SR (n) comprises pull-up circuit 110, first driving circuit 120, second driving circuit 130 and discharge circuit 140.Wherein, first driving circuit 120 and second driving circuit 130 are parallel with one another, and pull-up circuit 110 difference electric property coupling first driving circuit 120 and second driving circuits 130, and its electric property coupling place is as first node Q (n).
Pull-up circuit 110 receives previous starting impulse signal ST (n-1) and reference signal such as the VGH that the previous stage shift register is exported, so that first node Q (n) is charged.Particularly, pull-up circuit 110 comprises transistor T 1, and its grid receives previous starting impulse signal ST (n-1), and its source electrode receives reference signal VGH, and its drain electrode electric property coupling first node Q (n).
First driving circuit, 120 electric property coupling first node Q (n), and receive corresponding clock pulse signal HC (m) produces correspondence with the current potential according to first node Q (n) starting impulse signal ST (n).Particularly, first driving circuit 120 comprises transistor T 2 and capacitor C 2, the grid electric property coupling first node Q (n) of transistor T 2, its source electrode receives corresponding clock pulse signal HC (n), and its drain electrode as the output terminal of first driving circuit 120 to export corresponding starting impulse signal ST (n).Capacitor C 2 is electrically coupled between the grid and drain electrode of transistor T 2.
The output terminal of the discharge circuit 140 electric property coupling first node Q (n) and second driving circuit 130, and receive first control signal, second control signal and low reference potential VSS in very first time section, first node Q (n) being discharged, and the output terminal to second driving circuit 130 discharges in second time period.In the present embodiment, the back one-level starting impulse signal ST (n+1) that first control signal is exported for back one-level shift register SR (n+1) (figure does not show), and the back secondary starting impulse signal ST (n+2) that second control signal is exported for back two-stage shift register SR (n+2) (figure does not show).Particularly, discharge circuit 140 comprises transistor T 41 and transistor T 42.The grid of transistor T 42 receives the first control signal ST (n+1), and its source electrode electric property coupling hangs down reference potential VSS, and its drain electrode electric property coupling first node Q (n).The grid of transistor T 41 receives the second control signal ST (n+2), and its source electrode electric property coupling hangs down reference potential VSS, and the output terminal of its drain electrode electric property coupling second driving circuit 130.
See also Fig. 4, it illustrates the sequential chart into above-mentioned various signals.See also Fig. 2 to Fig. 4, below will introduce the principle of work of shift register of the present invention particularly.To be that example is introduced the present invention with four clock pulse signal HC (1)～HC (4) below, the quantity that it will be appreciated by persons skilled in the art that clock pulse signal be determined that by the number of pixels of LCD the present invention is not limited thereto.After LCD received enabling signal ST, clock pulse signal HC (1)～HC (4) opened successively.
This sentences second level shift register SR (2) introduces present embodiment for example related content.As the starting impulse signal ST (1) of previous stage shift register SR (1) output when being in noble potential, transistor T 1 conducting in the pull-up circuit 110, reference signal is charged to first node Q (2), and in the present embodiment, reference signal can be high reference potential VGH.Therefore, transistor T 2 in first driving circuit 120 be subjected to first node Q (2) thus on the control conducting of current potential, but, the clock pulse signal HC (2) that transistor T 2 source electrodes are received still is in electronegative potential, therefore the corresponding starting impulse signal ST (2) that produced of first driving circuit 120 is in electronegative potential, but it can produce a slight fluctuation at this moment.In addition, transistor T 3 in second driving circuit 130 be subjected to node Q (2) thus on the control conducting of current potential, and because the fixing high reference potential VGH of its source electrode electric property coupling, therefore high reference potential VGH is to its drain charge, thereby draw high the gate driving pulse signal G (n) that its drain electrode is produced, make gate driving pulse signal G (n) be in noble potential.
As the starting impulse signal ST (1) of previous stage shift register SR (1) output when being in electronegative potential, transistor T 1 in the pull-up circuit 110 ends, first node Q this moment (2) is in floating (floating), transistor T 2 in first driving circuit 120 continues conducting, and the clock pulse signal HC (2) that transistor T 2 source electrodes are received is in noble potential, the corresponding starting impulse signal ST (2) that its drain electrode is produced draws high and is in noble potential, finishes until the clock pulse signal HC (2) of correspondence.And, because the existence of capacitor C 2, so the current potential on the first node Q (2) is raised corresponding starting impulse signal ST (2) further.In addition, the transistor T 3 in second driving circuit 130 be subjected to first node Q (2) thus on control of Electric potentials continue conducting, high reference potential VSS continues its drain charge, gate driving pulse signal G (n) that its drain electrode is produced keeps noble potential.
Further, because the grid of the transistor T 42 in the discharge circuit 140 is subjected to the first control signal ST (3) control, therefore the back one-level starting impulse signal ST (3) that one-level shift register SR (3) is exported after first control signal is is when being in noble potential, transistor T 42 conductings, this moment is because the low reference potential VSS of transistor T 42 source electrode electric property couplings, therefore discharge circuit 140 discharges by 42 couples of first node Q of transistor T (n) in very first time section, promptly drags down the current potential on the first node Q (n).In addition, because the grid of the transistor T 43 in the discharge circuit 140 is subjected to the second control signal ST (4) control, therefore the back secondary starting impulse signal ST (4) that two-stage shift register SR (4) is exported after second control signal is is when being in noble potential, transistor T 41 conductings, output terminal by 41 pairs second driving circuits 130 of transistor T in second time period discharges, and promptly drags down corresponding gate driving pulse signal G (2).
And, as shown in Figure 4, the startup of the first control signal ST (3) constantly constantly early than the startup of the second control signal ST (4), therefore, to the discharging action of first node Q (n) early than discharging action to the output terminal of second driving circuit 130.That is to say, current potential on the first node Q (n) is before the output terminal to second driving circuit 130 carries out discharging action, just be pulled down to electronegative potential, the transistor T 3 in second driving circuit 130 ends, and high reference potential VGH stops the output terminal of second driving circuit 130 is charged.Therefore, the present invention discharge circuit 140 can not occur and on one side the output terminal of second driving circuit 130 be discharged, the situation that high reference potential VGH charges to the output terminal of second driving circuit 130 on one side.Therefore, shift register of the present invention can reduce its dynamic power consumption significantly.
In addition, the discharge circuit of the embodiment of the invention also further comprises transistor T 45.The grid electric property coupling first contact Q (n) of transistor T 45 is to receive the current potential on the first node Q (n), its source electrode electric property coupling hangs down reference potential VSS, and the grid of its drain electrode electric property coupling transistor T 41 is adjusted with the second control signal ST (n+2) that grid was received to transistor T 41.Therefore, for second level shift register SR (2), when the current potential on its first node Q (2) is in noble potential, transistor T 45 conductings, low reference signal VSS can be to its drain electrode discharge, therefore the second control signal ST (4) can be dragged down at this moment, to eliminate second control signal ST (4) fluctuation herein.
Please continue to consult Fig. 2-Fig. 3, shift register SR (n) further comprises first controlling circuit of voltage regulation 150, first mu balanced circuit 160, second controlling circuit of voltage regulation 170 and second mu balanced circuit 180.First controlling circuit of voltage regulation, 150 electric property couplings, first mu balanced circuit 160 to be controlling the action of first mu balanced circuit 160, and the output terminal of first mu balanced circuit, the 160 electric property coupling first node Q (n) and second driving circuit 130 is to stablize the gate driving pulse signal G (n) that the current potential on the first node Q (n) and second driving circuit 130 are exported.Second controlling circuit of voltage regulation 170 is identical with the circuit structure of second mu balanced circuit 180 and first controlling circuit of voltage regulation 150 and first mu balanced circuit 160, and it also is to be used for stablizing further the gate driving pulse signal G (n) that current potential on the first node Q (n) and second driving circuit 130 are exported.
Particularly, first controlling circuit of voltage regulation 150 comprises transistor T 51, transistor T 52, transistor T 53, transistor T 54, transistor T 55 and transistor T 56.The grid electric property coupling first reference potential LC1 of transistor T 51, its source electrode is the electric property coupling first reference potential LC1 also, the drain electrode of its drain electrode electric property coupling transistor T 52, and its junction is defined as Section Point A (n).The grid of transistor T 52 receives the 3rd control signal, and as the grid impulse signal G (n) of correspondence, its source electrode electric property coupling hangs down reference potential VSS.The grid electric property coupling Section Point A (n) of transistor T 53, its source electrode electric property coupling first reference potential LC1, the drain electrode of its drain electrode electric property coupling transistor T 54, and its junction is defined as the 3rd node P (n), and the 3rd node P (n) is as the output terminal on first voltage stabilizing reference mark road 150.The grid of transistor T 54 also receives the 3rd control signal G (n), and its source electrode electric property coupling hangs down reference potential VSS.The grid of transistor T 55 receives the 4th control signal, and as the previous gate driving pulse signal G (n-1) that previous stage shift register SR (n-1) is exported, its source electrode electric property coupling hangs down reference potential VSS, and its drain also electric property coupling Section Point A (n).The grid of transistor T 56 also receives the 4th control signal G (n-1), and its source electrode electric property coupling hangs down reference potential VSS, and its also electric property coupling the 3rd node P (n) that drains.
That is to say, transistor T 55 is parallel with one another with the interlock circuit of transistor T 54 with the interlock circuit and the transistor T 52 of transistor T 56, and transistor T 52 is the control that is subjected to the 3rd control signal G (n) with transistor T 54, and transistor T 55 is the control that is subjected to the 4th control signal G (n-1) with transistor T 56.
First mu balanced circuit 160 comprises transistor T 61 and transistor T 62.The output terminal (Pn) of equal electric property coupling first controlling circuit of voltage regulation 150 of grid of transistor T 61 and transistor T 62, and the gate driving pulse signal G (n) of the source electrode electric property coupling correspondence of transistor T 61, and its drain electrode electric property coupling first node Q (n).The source electrode electric property coupling of transistor T 62 hangs down reference signal VSS, and the output terminal of its drain electrode electric property coupling second driving circuit 130.
In the present embodiment, first controlling circuit of voltage regulation 150 receives the 3rd control signal G (n), its control signal that can guarantee that the output terminal P (n) of first controlling circuit of voltage regulation 150 is exported makes first mu balanced circuit 160 when shift register SR at the corresponding levels (n) carries out work, stops the output terminal of the first node Q (n) and second driving circuit 130 is discharged.In addition, first controlling circuit of voltage regulation 150 receives the 4th control signal G (n-1), its control signal that can guarantee that the output terminal P (n) of first controlling circuit of voltage regulation 150 is exported makes first mu balanced circuit 160 when its previous stage shift register SR (n-1) carries out work, discharge with regard to the output terminal that begins to stop, thereby guarantee to stablize the gate driving pulse signal G (n) of the correspondence that the output terminal of the current potential on the first node Q (n) and second driving circuit 130 exports further the first node Q (n) and second driving circuit 130.
In addition, because second controlling circuit of voltage regulation 170 is identical with the circuit structure of second mu balanced circuit 180 and first controlling circuit of voltage regulation 150 and first mu balanced circuit 160, its difference only is second controlling circuit of voltage regulation, 170 electric property couplings, the second reference potential LC2, and remaining structure does not repeat them here.
See also Fig. 5, it illustrates the synoptic diagram into the disclosed pull-up circuit of another embodiment of the present invention.As shown in Figure 5, the disclosed pull-up circuit of present embodiment is similar to the disclosed pull-up circuit of Fig. 2-3, the reference signal that its difference only is pull-up circuit and is received not is to be the high reference potential VGH that fixes, but the previous gate driving pulse signal G (n-1) that previous stage shift register SR (n-1) is exported, it can be in the transistor T 1 of previous starting impulse signal ST (n-1) conducting shift register SR (n) pull-up circuit 110 at the corresponding levels that previous stage shift register SR (n-1) is exported, and previous gate driving pulse signal G (n-1) can charge to draw high the current potential on the first node Q (n) to first node Q (n).
See also Fig. 6, it illustrates the synoptic diagram into the disclosed pull-up circuit of further embodiment of this invention.As shown in Figure 6, the disclosed pull-up circuit of present embodiment is similar to the disclosed pull-up circuit of Fig. 2-3, the reference signal that its difference only is pull-up circuit and is received not is to be the high reference potential VGH that fixes, but the previous starting impulse signal ST (n-1) that previous stage shift register SR (n-1) is exported, it can be at previous starting impulse signal ST (n-1) that previous stage shift register SR (n-1) is exported in the transistor T 1 of conducting shift register SR (n) pull-up circuit 110 at the corresponding levels, and previous starting impulse signal ST (n-1) also can charge to draw high the current potential on the first node Q (n) to first node Q (n).Certainly, it will be understood by those skilled in the art that, the reference signal that pull-up circuit received can also be other signal, as long as the previous starting impulse signal ST (n-1) that previous stage shift register SR (n-1) is exported is in the transistor T 1 of conducting shift register SR (n) pull-up circuit 110 at the corresponding levels, above-mentioned reference signal can be charged to first node Q (n) and be got final product.
See also Fig. 7, it illustrates the synoptic diagram into the disclosed discharge circuit of another embodiment of the present invention.As shown in Figure 7, the discharge circuit of present embodiment is similar to the disclosed discharge circuit of Fig. 2 and Fig. 3, its difference only be first control signal for the back secondary gate driving pulse signal G (n+2) that exported of back two-stage shift register SR (n+2) in very first time section, first node Q (n) being discharged, and second control signal back three gate driving pulse signal G (n+3) that to be back three grades of shift register SR (n+3) exported discharge with the output terminal to second driving circuit 130 in second time period.Because the startup of back secondary gate driving pulse signal G (n+2) moment is early than the startup moment of back three gate driving pulse signal G (n+3), therefore it can guarantee that discharge circuit 140 at first discharges to first node Q (n), when preventing that output terminal to second driving circuit 130 from discharging, high reference potential VGH also charges to the output terminal of second driving circuit 130.
See also Fig. 8, it illustrates the synoptic diagram into the disclosed discharge circuit of further embodiment of this invention.As shown in Figure 8, the discharge circuit of present embodiment is similar to the disclosed discharge circuit of Fig. 2 and Fig. 3, its difference only be first control signal for the back secondary gate driving pulse signal G (n+2) that exported of back two-stage shift register SR (n+2) in very first time section, first node Q (n) being discharged, and second control signal is discharged with the output terminal to second driving circuit 130 in second time period for the back secondary starting impulse signal ST (n+2) that back two-stage shift register SR (n+2) is exported.Because the startup of back secondary gate driving pulse signal G (n+2) moment is early than the startup moment of back secondary starting impulse signal ST (n+2), so it also can guarantee that discharge circuit 140 at first discharges to first node Q (n).Certainly, it will be understood by those skilled in the art that, first control signal and second control signal can also be the combination of other signals, as long as its may command discharge circuit 140 is before the output terminal to second driving circuit 130 discharges, earlier first node Q (n) current potential that drags down on the first node Q (n) that discharges is got final product.
See also Fig. 9, it illustrates the synoptic diagram into disclosed first controlling circuit of voltage regulation of another embodiment of the present invention.As shown in Figure 9, first controlling circuit of voltage regulation of present embodiment is similar to disclosed first controlling circuit of voltage regulation of Fig. 2-3, and its difference only is that first controlling circuit of voltage regulation receives only the 3rd control signal G (n), and does not receive the 4th control signal G (n-1).Be that first controlling circuit of voltage regulation in the present embodiment does not have transistor T 55 and transistor T 56, it guarantees that first mu balanced circuit 160 when shift register SR at the corresponding levels (n) carries out work, stops the output terminal of the first node Q (n) and second driving circuit 130 is discharged.
See also Figure 10, it illustrates the synoptic diagram into disclosed first controlling circuit of voltage regulation of further embodiment of this invention.As shown in figure 10, first controlling circuit of voltage regulation of present embodiment is similar to disclosed first controlling circuit of voltage regulation of Fig. 9, its difference only is that the 3rd control signal is not is the gate driving pulse signal G (n) of the correspondence exported of shift register SR at the corresponding levels (n), but the current potential on the first node Q (n), it also can guarantee first mu balanced circuit 160 when shift register SR at the corresponding levels (n) carries out work, stops the output terminal of the first node Q (n) and second driving circuit 130 is discharged.
See also Figure 11, it illustrates the synoptic diagram into disclosed first controlling circuit of voltage regulation of yet another embodiment of the invention.As shown in figure 11, first controlling circuit of voltage regulation of present embodiment is similar to disclosed first controlling circuit of voltage regulation of Fig. 2 and Fig. 3, its difference only is that it is not the previous gate driving pulse signal G (n-1) that previous stage shift register SR (n-1) is exported that first controlling circuit of voltage regulation receives the 4th control signal, but the starting impulse signal ST (n) of the correspondence that shift register SR at the corresponding levels (n) is exported, it also can guarantee first mu balanced circuit 160 when shift register SR at the corresponding levels (n) carries out work, stops the output terminal of the first node Q (n) and second driving circuit 130 is discharged.Certainly, the 3rd control signal and the 4th control signal that are received of first controlling circuit of voltage regulation also can be done shifting gears of other.
In sum, second driving circuit of shift register of the present invention is by fixing high reference potential its output terminal to be charged, and discharge circuit is before the output terminal to second driving circuit discharges, earlier the first node current potential that drags down on the first node that discharges is got final product, prevent that the high reference potential of fixing from continuing the output terminal of second driving circuit is charged, so it can reduce the dynamic power consumption of shift register significantly.
Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection domain of the appended claim of the present invention.
Claims (19)
1. a shift register circuit is characterized in that, comprising:
Multi-stage shift register, these shift registers of each grade are in order to the starting impulse signal of exporting a correspondence and the drive pulse signal of a correspondence, and each these shift register comprises a pull-up circuit, one first driving circuit, one second driving circuit, a discharge circuit respectively, wherein:
This pull-up circuit receives previous starting impulse signal and reference signal that the previous stage shift register is exported, so that a first node is charged;
This first driving circuit is at this first node place this pull-up circuit of electric property coupling, and the clock pulse signal that receives a correspondence produces this corresponding starting impulse signal with the current potential according to this first node;
This second driving circuit is also at this first node place this pull-up circuit of electric property coupling, and receives a high reference potential to export this corresponding drive pulse signal at an output terminal; And
This discharge circuit comprises a first transistor and a transistor seconds; This first transistor comprises one first control end, one first path terminal and an alternate path end, this this first node of first path terminal electric property coupling, and this alternate path end electric property coupling one low reference potential, this first control end receives one first control signal in a very first time section this first node is discharged; And this transistor seconds comprises one second control end, one the 3rd path terminal and a four-way terminal, this output terminal of the 3rd this second driving circuit of path terminal electric property coupling, and this four-way terminal electric property coupling should hang down reference potential, and this second control end receives one second control signal and discharges with the output terminal to this second driving circuit in one second time period;
Wherein, the startup of this very first time section moment is early than the startup moment of this second time period.
2. shift register circuit according to claim 1, it is characterized in that, the back one-level starting impulse signal that this first control signal that this of this first transistor first control end is received is exported for back one-level shift register is to discharge to the current potential on this first node in this very first time section; And the back secondary starting impulse signal that this second control signal that this of this transistor seconds second control end is received is exported for back two-stage shift register discharges with the output terminal to this second driving circuit in this second time period.
3. shift register circuit according to claim 2 is characterized in that, this discharge circuit further comprises one the 3rd transistor, and it comprises:
One the 3rd control end;
One five-way terminal, this second control end of this transistor seconds of electric property coupling; And
One the 6th path terminal, electric property coupling should hang down reference potential;
Wherein, the 3rd control end receives this back secondary starting impulse signal that the current potential on this first node is received with this second control end of revising this transistor seconds.
4. shift register circuit according to claim 1, it is characterized in that, the back secondary drive pulse signal that this first control signal that this of this first transistor first control end is received is exported for back two-stage shift register is to discharge to this first node in this very first time section; And this second control signal that this of this transistor seconds second control end is received is back three drive pulse signals that back three grades of shift registers are exported, and discharges with the output terminal to this second driving circuit in this second time period.
5. shift register circuit according to claim 1, it is characterized in that, the back secondary drive pulse signal that this first control signal that this of this first transistor first control end is received is exported for back two-stage shift register is to discharge to this first node in this very first time section; And the back secondary starting impulse signal that this second control signal that this of this transistor seconds second control end is received is exported for this back two-stage shift register discharges with the output terminal to this second driving circuit in this second time period.
6. shift register circuit according to claim 1 is characterized in that, this pull-up circuit comprises one the 4th transistor, and the 4th transistor comprises:
One the 4th control end receives this previous starting impulse signal that this previous stage shift register is exported;
One the 7th path terminal receives this reference signal; And
One the 8th path terminal, this first node of electric property coupling.
7. shift register circuit according to claim 6 is characterized in that, this reference signal is this high reference potential.
8. shift register circuit according to claim 6 is characterized in that, the previous drive pulse signal that this reference signal is exported for this previous stage shift register.
9. shift register circuit according to claim 6 is characterized in that, this previous starting impulse signal that this reference signal is exported for this previous stage shift register.
10. shift register circuit according to claim 1 is characterized in that, this first driving circuit comprises:
One the 5th transistor, it comprises: one the 5th control end, this first node of electric property coupling; One the 9th path terminal is in order to receive this corresponding clock pulse signal; And 1 the tenth path terminal, in order to export this corresponding starting impulse signal; And
One electric capacity is electrically coupled between this first node and the tenth path terminal.
11. shift register circuit according to claim 1 is characterized in that, this second driving circuit comprises one the 6th transistor, and it comprises:
One the 6th control end, this first node of electric property coupling;
The 11 path terminal is in order to receive this high reference potential; And
The 12 path terminal is in order to export this corresponding drive pulse signal.
12. shift register circuit according to claim 1 is characterized in that, each these shift register of level further comprises:
One first mu balanced circuit, this output terminal of this first node of electric property coupling and this second driving circuit respectively;
One first controlling circuit of voltage regulation, whether this first mu balanced circuit of electric property coupling and the control that receives at least one control signal discharge to the output terminal of this first node and this second driving circuit to determine this first mu balanced circuit.
13. shift register circuit according to claim 12 is characterized in that, this first mu balanced circuit comprises:
One the 7th transistor, it comprises: one the 7th control end, an output terminal of this first controlling circuit of voltage regulation of electric property coupling; The 13 path terminal is used to receive this corresponding drive pulse signal; And 1 the tenth four-way terminal, this first node of electric property coupling; And
One the 8th transistor, it comprises: one the 8th control end, this output terminal of this first controlling circuit of voltage regulation of electric property coupling; The tenth a five-way terminal, electric property coupling should hang down reference potential; And 1 the 16 path terminal, this output terminal of this second driving circuit of electric property coupling.
14. shift register circuit according to claim 13 is characterized in that, this first controlling circuit of voltage regulation comprises:
One the 9th transistor, it comprises: one the 9th control end, electric property coupling one reference potential; The 17 path terminal, also this reference potential of electric property coupling; And 1 the 18 path terminal;
The tenth transistor, it comprises: 1 the tenth control end is used to receive one the 3rd control signal; The 19 path terminal, electric property coupling the 18 path terminal and its junction are as a Section Point; And one the 20 path terminal, electric property coupling should low reference potential;
The 11 transistor, it comprises: 1 the 11 control end, this Section Point of electric property coupling; One the 21 path terminal, this reference potential of electric property coupling; And one the 22 path terminal; And
The tenth two-transistor, it comprises: 1 the 12 control end also is used to receive the 3rd control signal; One the 23 path terminal, electric property coupling should hang down reference potential; And one the 20 four-way terminal, electric property coupling the 22 path terminal and its couple place's this output terminal as this first controlling circuit of voltage regulation.
15. shift register circuit according to claim 14 is characterized in that, the 3rd control signal is this corresponding drive pulse signal.
16. shift register circuit according to claim 15 is characterized in that, this first controlling circuit of voltage regulation further comprises:
The 13 transistor, it comprises: 1 the 13 control end is used to receive one the 4th control signal; One the 20 five-way terminal, this Section Point of electric property coupling; And one the 26 path terminal, electric property coupling should low reference potential; And
The 14 transistor, it comprises: 1 the 14 control end also is used to receive the 4th control signal; One the 27 path terminal, electric property coupling should hang down reference potential; And one the 28 path terminal, this output terminal of this first controlling circuit of voltage regulation of electric property coupling.
17. shift register circuit according to claim 16 is characterized in that, the 4th control signal is the previous drive pulse signal that the previous stage shift register is exported.
18. shift register circuit according to claim 16 is characterized in that, the 4th control signal is this corresponding starting impulse signal.
19. shift register circuit according to claim 14 is characterized in that, the 3rd control signal is the current potential on this first node.
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| CN201010289603XA CN101950522B (en) | 2010-09-19 | 2010-09-19 | Shift register circuit |
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| CN201010289603XA CN101950522B (en) | 2010-09-19 | 2010-09-19 | Shift register circuit |
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| CN101950522B CN101950522B (en) | 2012-07-04 |
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| WO2019161669A1 (en) * | 2018-02-26 | 2019-08-29 | 京东方科技集团股份有限公司 | Gate drive circuit, touch display device, and driving method |
| CN111627405A (en) * | 2020-06-10 | 2020-09-04 | 武汉华星光电技术有限公司 | Display driving circuit, driving method thereof and display device |
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| CN101950522B (en) | 2012-07-04 |
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