CN109559706B

CN109559706B - Display driving circuit and display device

Info

Publication number: CN109559706B
Application number: CN201910088286.6A
Authority: CN
Inventors: 田新斌; 徐向阳
Original assignee: Shenzhen China Star Optoelectronics Technology Co Ltd
Current assignee: TCL China Star Optoelectronics Technology Co Ltd
Priority date: 2019-01-29
Filing date: 2019-01-29
Publication date: 2020-08-11
Anticipated expiration: 2039-01-29
Also published as: WO2020155453A1; CN109559706A

Abstract

The invention provides a display driving circuit and a display device. The display driving circuit comprises a grid driving circuit and a plurality of rows of scanning lines which are electrically connected with the grid driving circuit and are arranged in parallel at intervals, the grid driving circuit comprises a plurality of stages of grid driving units, wherein each odd-numbered stage of grid driving units are cascaded, and the even-numbered stage of grid driving units are cascaded; through setting up each grade GOA unit and correspondingly scanning two rows of scanning lines, the GOA unit of odd level and the GOA unit of even level scan in turn, can make the operating time of each grade GOA unit halve to reduce the product consumption, prolong product life, promote the green energy-conserving level of product.

Description

Display driving circuit and display device

Technical Field

The invention relates to the technical field of display, in particular to a display driving circuit and a display device.

Background

Liquid Crystal Displays (LCDs) have many advantages such as thin body, power saving, no radiation, and the like, and are widely used. Such as: liquid crystal televisions, mobile phones, Personal Digital Assistants (PDAs), digital cameras, computer screens, notebook computer screens, or the like, are dominant in the field of flat panel displays.

Most of the existing liquid crystal displays in the market are backlight liquid crystal displays (lcds), which include a liquid crystal display panel and a backlight module (backlight module). The liquid crystal display panel operates on the principle that liquid crystal molecules are filled between a thin film Transistor Array Substrate (TFT Array Substrate) and a color filter Substrate (color filter, CF), and driving voltages are applied to the two substrates to control the rotation direction of the liquid crystal molecules, so that light of the backlight module is refracted out to generate a picture.

An Active Matrix Liquid Crystal Display (AMLCD) is currently the most commonly used Liquid Crystal Display device, and includes a plurality of pixels, each having a Thin Film Transistor (TFT) with a gate connected to a scan line extending in a horizontal direction, a drain connected to a data line extending in a vertical direction, and a source connected to a corresponding pixel electrode. If a positive voltage is applied to a scan line in the horizontal direction, all TFTs connected to the scan line are turned on, and a data signal voltage applied to the data line is written to the pixel electrode, thereby controlling the transmittance of different liquid crystals and further achieving the effect of controlling the color.

Currently, driving of horizontal scan lines (i.e., gate driving) of an active liquid crystal display panel is mainly performed by an external Integrated Circuit (IC), and the external IC can control the stage-by-stage charging and discharging of the horizontal scan lines. The GOA (Gate Driver on Array) technology, which is an Array substrate column driving technology, can use the original process of liquid crystal display panel to fabricate the driving circuit of the horizontal scanning line on the substrate around the display area, so that it can replace the external IC to complete the driving of the horizontal scanning line. The GOA technology can reduce the welding (bonding) process of an external IC, has the opportunity of improving the productivity and reducing the product cost, and can ensure that the liquid crystal display panel is more suitable for manufacturing narrow-frame or frameless display products.

The existing gate driving circuit usually comprises cascaded multi-stage gate driving units, the scanning mode is that a row of scanning lines are scanned by a first-stage gate driving unit, all the gate driving units need to participate in scanning in each frame of scanning time, the power consumption of the gate driving circuit of the scanning mode is large, the working time of each stage of gate driving unit is long, the loss is large, and the green and energy-saving product standards cannot be met.

Disclosure of Invention

The invention aims to provide a display driving circuit which can reduce the power consumption of a product, prolong the service life of the product and improve the green energy-saving level of the product.

The invention also provides a display device, which can reduce the power consumption of products, prolong the service life of the products and improve the green energy-saving level of the products.

In order to achieve the above object, the present invention provides a display driving circuit, which includes a gate driving circuit and a plurality of rows of scan lines electrically connected to the gate driving circuit and arranged in parallel at intervals, wherein the gate driving circuit includes a plurality of gate driving units, each odd-numbered gate driving unit is cascaded, and each even-numbered gate driving unit is cascaded;

each two adjacent stages of grid driving units are grid driving unit groups, each grid driving unit group corresponds to two rows of adjacent scanning lines, and the two stages of grid driving units in the same grid driving unit group are electrically connected with the two rows of scanning lines corresponding to the grid driving unit group;

during driving, the grid driving units of the odd-numbered stages and the grid driving units of the even-numbered stages alternately work according to a preset switching period; when the grid driving units of the odd-numbered stages work, the grid driving units of the odd-numbered stages receive the first group of high-frequency clock signals, and generate scanning signals by using the first group of high-frequency clock signals to scan each row of scanning lines; when the even-level gate driving units work, the even-level gate driving units receive the second group of high-frequency clock signals, and generate scanning signals by using the second group of high-frequency clock signals to scan each row of scanning lines.

The first group of high-frequency clock signals comprise a first high-frequency clock signal, a third high-frequency clock signal and a fifth high-frequency clock signal;

the second group of high-frequency clock signals comprises a second high-frequency clock signal, a fourth high-frequency clock signal and a sixth high-frequency clock signal;

the rising edge generation time of the first high-frequency clock signal, the third high-frequency clock signal and the fifth high-frequency clock signal are sequentially separated by a preset delay time; the waveforms of the second high-frequency clock signal, the fourth high-frequency clock signal and the sixth high-frequency clock signal are respectively the same as the waveforms of the first high-frequency clock signal, the third high-frequency clock signal and the fifth high-frequency clock signal;

and if n is a positive integer, the 6n-5 th-level gate driving unit, the 6n-4 th-level gate driving unit, the 6n-3 th-level gate driving unit, the 6n-2 th-level gate driving unit, the 6n-1 th-level gate driving unit and the 6n th-level gate driving unit respectively receive a first high-frequency clock signal, a second high-frequency clock signal, a third high-frequency clock signal, a fourth high-frequency clock signal, a fifth high-frequency clock signal and a sixth high-frequency clock signal.

The first group of high-frequency clock signals comprise a first high-frequency clock signal, a third high-frequency clock signal, a fifth high-frequency clock signal and a seventh high-frequency clock signal;

the second group of high-frequency clock signals comprise a second high-frequency clock signal, a fourth high-frequency clock signal, a sixth high-frequency clock signal and an eighth clock signal;

the rising edge generation time of the first high-frequency clock signal, the third high-frequency clock signal, the fifth high-frequency clock signal and the seventh high-frequency clock signal is sequentially separated by a preset delay time; the waveforms of the second high-frequency clock signal, the fourth high-frequency clock signal, the sixth high-frequency clock signal and the eighth high-frequency clock signal are respectively the same as the waveforms of the first high-frequency clock signal, the third high-frequency clock signal, the fifth high-frequency clock signal and the seventh high-frequency clock signal;

and if n is a positive integer, respectively receiving a first high-frequency clock signal, a second high-frequency clock signal, a third high-frequency clock signal, a fourth high-frequency clock signal, a fifth high-frequency clock signal, a sixth high-frequency clock signal, a seventh high-frequency clock signal and an eighth high-frequency clock signal by an 8n-7 th-stage gate driving unit, an 8n-6 th-stage gate driving unit, an 8n-5 th-stage gate driving unit, an 8n-4 th-stage gate driving unit, an 8n-3 rd-stage gate driving unit, an 8n-2 th-stage gate driving unit, an 8n-1 th-stage gate driving unit and an 8n th-stage gate driving unit.

When the grid driving units of the odd-numbered stages work, the grid driving unit of the first stage also receives a first starting signal for driving the grid driving units of the odd-numbered stages to start scanning;

when the even-level gate driving unit works, the second-level gate driving unit also receives a second starting signal for driving the even-level gate driving unit to start scanning.

Each stage of gate driving unit also receives a first low-frequency clock signal and a second low-frequency clock signal, and is used for maintaining the turn-off state of the stage of gate driving unit during the non-output period of the stage of gate driving unit.

The operation of the gate driving units of the odd-numbered stages and the operation of the gate driving units of the even-numbered stages are switched once every interval of 80 to 120 frame scanning times.

The operation of the gate driving units of the odd-numbered stages and the operation of the gate driving units of the even-numbered stages are switched once every 100 frame scanning times.

The display driving circuit further comprises a plurality of pixel units which are arranged in an array mode, and each row of scanning lines is electrically connected with one row of pixel units correspondingly.

The gate driving circuit is a GOA circuit.

The invention also provides a display device comprising the display driving circuit.

The invention has the beneficial effects that: the invention provides a display driving circuit, which comprises a grid driving circuit and a plurality of rows of scanning lines which are electrically connected with the grid driving circuit and are arranged in parallel at intervals, wherein the grid driving circuit comprises a plurality of levels of grid driving units, each odd level of grid driving units are cascaded, and even level of grid driving units are cascaded; through setting up each grade GOA unit and correspondingly scanning two rows of scanning lines, the GOA unit of odd level and the GOA unit of even level scan in turn, can make the operating time of each grade GOA unit halve to reduce the product consumption, prolong product life, promote the green energy-conserving level of product. The invention also provides a display device, which can reduce the power consumption of products, prolong the service life of the products and improve the green energy-saving level of the products.

Drawings

For a better understanding of the nature and technical aspects of the present invention, reference should be made to the following detailed description of the invention, taken in conjunction with the accompanying drawings, which are provided for purposes of illustration and description and are not intended to limit the invention.

In the drawings, there is shown in the drawings,

FIG. 1 is a diagram of a display driving circuit according to a first embodiment of the present invention;

FIG. 2 is a waveform diagram of a display driving circuit according to a first embodiment of the present invention;

FIG. 3 is a circuit diagram of a gate driving unit of the display driving circuit according to the present invention;

fig. 4 is a diagram of a display driving circuit according to a second embodiment of the invention.

Detailed Description

To further illustrate the technical means and effects of the present invention, the following detailed description is given with reference to the preferred embodiments of the present invention and the accompanying drawings.

Referring to fig. 1, the present invention provides a display driving circuit, which includes a gate driving circuit 1 and a plurality of rows of scan lines 2 electrically connected to the gate driving circuit 1 and arranged in parallel at intervals, wherein the gate driving circuit 2 includes a plurality of gate driving units 21, each odd-numbered gate driving unit 21 is cascaded, and each even-numbered gate driving unit 21 is cascaded;

each two adjacent gate driving units 21 are a gate driving unit group 210, each gate driving unit group 210 corresponds to two adjacent rows of scanning lines 2, and the two gate driving units 21 in the same gate driving unit group 210 are electrically connected to the two rows of scanning lines 2 corresponding to the gate driving unit group 210.

It should be noted that, when the display driving circuit of the present invention is driving, the odd-numbered gate driving units 21 and the even-numbered gate driving units 21 work alternately according to a preset switching period; when the odd-numbered gate driving units 21 work, the odd-numbered gate driving units 21 receive the first group of high-frequency clock signals, and generate scanning signals by using the first group of high-frequency clock signals to scan each row of scanning lines 2; when the even-numbered gate driving units 21 are operated, the even-numbered gate driving units 21 receive the second group of high-frequency clock signals, and generate scanning signals by using the second group of high-frequency clock signals to scan the scanning lines 2 of each row.

Further, when the gate driving units 21 of the odd-numbered stages operate, the gate driving unit 21 of the first stage also receives a first start signal STV1 for driving the gate driving units 21 of the odd-numbered stages to start scanning;

when the gate driving units 21 of the even-numbered stages operate, the gate driving units 21 of the second stage also receive a second start signal STV2 for driving the gate driving units 21 of the even-numbered stages to start scanning.

Further, each stage of the gate driving unit 21 also receives a first low frequency clock signal LC1 and a second low frequency clock signal LC2 for maintaining the off state of the stage of the gate driving unit 21 during the period when the stage of the gate driving unit 21 is not outputting.

Preferably, the operations of the gate driving units 21 of the odd-numbered stages and the gate driving units 21 of the even-numbered stages are switched once every interval of 80 to 120 frame scanning times. More preferably, the operations of the gate driving units 21 of the odd-numbered stages and the gate driving units 21 of the even-numbered stages are switched once every 100 frame scanning times.

Furthermore, the display driving circuit further includes a plurality of pixel units 3 arranged in an array, and each row of the scanning lines 2 is electrically connected to one row of the pixel units 3 correspondingly.

Preferably, the gate driving circuit 1 is a GOA circuit.

For example, as shown in fig. 1, in the first embodiment of the present invention, the first set of high frequency clock signals includes a first high frequency clock signal CK1, a third high frequency clock signal CK3, and a fifth high frequency clock signal CK 5; the second set of high frequency clock signals includes a second high frequency clock signal CK2, a fourth high frequency clock signal CK4, and a sixth high frequency clock signal CK 6; the rising edge generating time of the first high-frequency clock signal CK1, the third high-frequency clock signal CK3 and the fifth high-frequency clock signal CK5 are sequentially separated by a preset delay time; the waveforms of the second high-frequency clock signal CK2, the fourth high-frequency clock signal CK4 and the sixth high-frequency clock signal CK6 are respectively the same as the waveforms of the first high-frequency clock signal CK1, the third high-frequency clock signal CK3 and the fifth high-frequency clock signal CK 5;

assuming that n is a positive integer, the gate driving unit of the 6n-5 th stage, the gate driving unit of the 6n-4 th stage, the gate driving unit of the 6n-3 th stage, the gate driving unit of the 6n-2 th stage, the gate driving unit of the 6n-1 th stage and the gate driving unit of the 6n th stage respectively receive the first high frequency clock signal CK1, the second high frequency clock signal CK2, the third high frequency clock signal CK3, the fourth high frequency clock signal CK4, the fifth high frequency clock signal CK5 and the sixth high frequency clock signal CK 6.

Further, as shown in fig. 2 and fig. 1, the working process of the first embodiment is as follows: first, when the first start signal STV1 provides a high level pulse, the second start signal STV2 does not provide a high level pulse, the odd-level GOA unit 21 starts to operate, the even-level GOA unit 21 does not operate, and the odd-level GOA unit 21 operates, the first-level GOA unit 21 first receives the first high frequency clock signal CK1 to generate a first scan signal and outputs the first scan signal to the first scan line L1 and the second scan line L2 to scan the first scan line L1 and the second scan line L2, the third-level GOA unit 21 then receives the third high frequency clock signal CK3 to generate a second scan signal and outputs the second scan signal to the third scan line L3 and the fourth scan line L4 to scan the third scan line L3 and the fourth scan line L4, the fifth-level GOA unit 21 then receives the fifth high frequency clock signal CK5 to generate a third scan signal, and outputs the third scanning signal to the fifth scanning line L5 and the sixth scanning line L6 to scan the fifth scanning line L5 and the sixth scanning line L6, and so on until the last GOA unit 21 of the odd level completes scanning of one frame, after the GOA unit 21 of the odd level completes scanning of 100 frames, the second start signal STV2 provides a high level pulse from the 101 st frame, the first start signal STV1 does not provide a high level pulse, the GOA unit 21 of the even level starts to operate, the GOA unit 21 of the odd level does not operate, when the GOA unit 21 of the even level operates, the second GOA unit 21 of the second level receives the second high frequency clock signal L2 first to generate the first scanning signal, and outputs the first scanning signal to the first scanning line L1 and the second scanning line L2 to scan the first scanning line L1 and the second scanning line L2, and the fourth GOA unit 4 to receive the fourth high frequency clock signal L4, generating a second scanning signal, outputting the second scanning signal to a third scanning line L3 and a fourth scanning line L4 to scan the third scanning line L3 and the fourth scanning line L4, the sixth-level GOA unit 21 receiving the sixth high-frequency clock signal CK6 to generate a third scanning signal, outputting the third scanning signal to a fifth scanning line L5 and a sixth scanning line L6 to scan the fifth scanning line L5 and the sixth scanning line L6, repeating the above steps until the last odd-level GOA unit 21 completes scanning of one frame, starting from the 301 st frame after the even-level GOA unit 21 completes scanning of 100 frames, starting the operation of the odd-level GOA unit 21, stopping the operation of the even-level GOA unit 21, and continuously and cyclically and alternately operating, so that the present invention sets two-level GOA units to scan two rows of scanning lines, and alternately scans the odd-level GOA unit and the even-level GOA unit, the working time of each GOA unit is halved, so that the power consumption of the product is reduced, the service life of the product is prolonged, and the green energy-saving level of the product is improved

Further, as shown in fig. 4, in the second embodiment of the present invention, the first group of high frequency clock signals includes a first high frequency clock signal CK1, a third high frequency clock signal CK3, a fifth high frequency clock signal CK5, and a seventh high frequency clock signal CK 7; the second set of high frequency clock signals includes a second high frequency clock signal CK2, a fourth high frequency clock signal CK4, a sixth high frequency clock signal CK6, and an eighth clock signal CK 8;

rising edge generation times of the first high-frequency clock signal CK1, the third high-frequency clock signal CK3, the fifth high-frequency clock signal CK5 and the seventh high-frequency clock signal CK7 are sequentially separated by a preset delay time; the waveforms of the second high-frequency clock signal CK2, the fourth high-frequency clock signal CK4, the sixth high-frequency clock signal CK6 and the eighth high-frequency clock signal CK8 are respectively the same as the waveforms of the first high-frequency clock signal CK1, the third high-frequency clock signal CK3, the fifth high-frequency clock signal CK5 and the seventh high-frequency clock signal CK 7;

assuming that n is a positive integer, the 8n-7 th, 8n-6 th, 8n-5 th, 8n-4 th, 8n-3 th, 8n-2 th, 8n-1 th, and 8 n-th gate driving units receive the first, second, third, fourth, fifth, sixth, seventh, and eighth high-frequency clock signals CK1, CK2, CK3, CK4, CK5, CK6, CK7, and CK8, respectively.

Specifically, the working process of the second embodiment is the same as that of the first embodiment, and only the number of the high frequency clock signals is changed, which is not described herein again.

Further, in other embodiments of the present invention, the number of the high-frequency clock signals included in the first group of high-frequency clock signals and the second group of high-frequency clock signals may also be other numbers, for example, 2 or 6, and it is only required to ensure that the number of the high-frequency clock signals included in the first group of high-frequency clock signals and the second group of high-frequency clock signals are equal, and the waveforms are in one-to-one correspondence.

Specifically, in some embodiments of the present invention, assuming that M is a positive integer, the mth stage gate driving unit includes: a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, a fourth thin film transistor T4, a fifth thin film transistor T5, a sixth thin film transistor T6, a seventh thin film transistor T7, an eighth thin film transistor T8, a ninth thin film transistor T9, a tenth thin film transistor T10, an eleventh thin film transistor T11, a twelfth thin film transistor T12, a thirteenth thin film transistor T13, a fourteenth thin film transistor T14, a fifteenth thin film transistor T15, a sixteenth thin film transistor T16, and a capacitor C1;

the gate and the source of the first thin film transistor T1 both receive the scan signal G (M-2) of the M-2 th stage gate driving unit, and the drain is electrically connected to the first node q (M);

the grid electrode of the second thin film transistor T2 is electrically connected with a first node Q (M), the source electrode receives a high-frequency clock signal CK, and the drain electrode outputs a scanning signal G (M);

the gate of the third thin film transistor T3 receives a scan signal G (M +2) of the M +2 th stage gate driving unit, the source is electrically connected to the first node q (M), and the drain receives a low potential VSS;

the gate of the fourth thin film transistor T4 receives the scan signal G (M +2) of the M +2 th stage gate driving unit, the source thereof is electrically connected to the drain of the second thin film transistor T2, and the drain thereof receives the low potential VSS;

a gate of the fifth thin film transistor T5 is electrically connected to a drain of the tenth thin film transistor T10, a source thereof is electrically connected to the first node q (m), and the drain thereof receives a low potential VSS;

a gate of the sixth thin film transistor T6 is electrically connected to a drain of the tenth thin film transistor T10, a source thereof is electrically connected to a drain of the second thin film transistor T2, and the drain thereof receives a low potential VSS;

the gate and the source of the seventh thin film transistor T7 both receive the first low frequency clock signal LC1, and the drain is electrically connected to the gate of the tenth thin film transistor T10;

a gate of the eighth tft T8 is electrically connected to the first node q (m), a source thereof is electrically connected to a gate of the tenth tft T10, and a drain thereof receives a low potential VSS;

a gate of the ninth tft T9 is electrically connected to the first node q (m), a source thereof is electrically connected to a drain of the tenth tft T10, and the drain thereof receives a low voltage VSS;

a source of the tenth thin film transistor T10 receives a first low frequency clock signal LC 1;

a gate of the eleventh tft T11 is electrically connected to a drain of the sixteenth tft T16, a source of the eleventh tft T11 is electrically connected to the first node q (m), and the drain of the eleventh tft T11 receives a low voltage VSS;

a gate of the twelfth thin film transistor T12 is electrically connected to a drain of the sixteenth thin film transistor T16, a source thereof is electrically connected to a drain of the second thin film transistor T2, and the drain thereof receives a low potential VSS;

the gate and the source of the thirteenth thin film transistor T13 both receive the second low frequency clock signal LC2, and the drain is electrically connected to the gate of the sixteenth thin film transistor T16;

a gate of the fourteenth thin film transistor T14 is electrically connected to the first node q (m), a source thereof is electrically connected to a gate of the sixteenth thin film transistor T16, and a drain thereof receives a low potential VSS;

a gate of the fifteenth tft T15 is electrically connected to the first node q (m), a source thereof is electrically connected to a drain of the sixteenth tft T16, and the drain thereof receives a low voltage VSS;

the source of the sixteenth thin film transistor 16 receives a second low frequency clock signal LC 2;

a first end of the capacitor C1 is electrically connected to the first node q (m), and a second end is electrically connected to the drain of the second tft T2.

Specifically, in the first embodiment of the present invention, as shown in fig. 3, when M is an odd number, the high frequency clock signal CK in the gate driving unit 21 is one of the first high frequency clock signal CK1, the third high frequency clock signal CK3 and the fifth high frequency clock signal CK, and when M is an even number, the high frequency clock signal CK in the gate driving unit 21 is one of the second high frequency clock signal CK2, the fourth high frequency clock signal CK4 and the sixth high frequency clock signal CK 6.

Specifically, in the second embodiment of the present invention, as shown in fig. 3, when M is an odd number, the high frequency clock signal CK in the gate driving unit 21 is one of the first high frequency clock signal CK1, the third high frequency clock signal CK3, the fifth high frequency clock signal CK5 and the seventh high frequency clock signal CK7, and when M is an even number, the high frequency clock signal CK in the gate driving unit 21 is one of the second high frequency clock signal CK2, the fourth high frequency clock signal CK4, the sixth high frequency clock signal CK6 and the eighth high frequency clock signal CK 8.

Specifically, corresponding to the embodiment shown in fig. 3, in order to ensure the normal operation of the gate driving circuit, the source and the drain of the first thin film transistor T1 in the first stage gate driving unit 21 receive the first start signal STV1, the source and the drain of the first thin film transistor T1 in the second stage gate driving unit 21 receive the second start signal STV2, the gates of the third thin film transistor T3 and the fourth thin film transistor T4 of the last even-numbered stage GOA unit 21 receive the second start signal STV2, and the gates of the third thin film transistor T3 and the fourth thin film transistor T4 of the last odd-numbered stage GOA unit 21 receive the first start signal STV1, so that the gate driving unit 21 can be started and shut down smoothly.

Further, the operation process of the gate driving unit 21 shown in fig. 3 is: first, the scan signal G (M-2) of the M-2 th stage gate driving unit is at a high potential, the first tft T1 is turned on to charge the first node q (M), so that the second tft T2 is turned on, the high frequency clock signal CK outputs the scan signal G (M) through the drain of the second tft T2, then, the scan signal G (M +2) of the M +2 th stage gate driving unit is at a high potential, the third and fourth tfts T3, T4 are turned on, the first node q (M) and the scan signal G (M) are pulled down to a low potential VSS, and finally, the first low frequency clock signal LC1 and the second high frequency clock signal LC2 alternately operate to maintain the first node q (M) and the scan signal G (M) at the low potential VSS.

In addition, the invention also provides a display device which comprises the display driving circuit.

In summary, the present invention provides a display driving circuit, which includes a gate driving circuit and a plurality of rows of scan lines electrically connected to the gate driving circuit and arranged in parallel at intervals, wherein the gate driving circuit includes a plurality of gate driving units, each odd-numbered gate driving unit is cascaded, and each even-numbered gate driving unit is cascaded; through setting up each grade GOA unit and correspondingly scanning two rows of scanning lines, the GOA unit of odd level and the GOA unit of even level scan in turn, can make the operating time of each grade GOA unit halve to reduce the product consumption, prolong product life, promote the green energy-conserving level of product. The invention also provides a display device, which can reduce the power consumption of products, prolong the service life of the products and improve the green energy-saving level of the products.

As described above, it will be apparent to those skilled in the art that other various changes and modifications may be made based on the technical solution and concept of the present invention, and all such changes and modifications are intended to fall within the scope of the appended claims.

Claims

1. The display driving circuit is characterized by comprising a grid driving circuit (1) and a plurality of rows of scanning lines (2) which are electrically connected with the grid driving circuit (1) and are arranged in parallel at intervals, wherein the grid driving circuit (1) comprises a plurality of stages of grid driving units (21), each odd-numbered stage of grid driving units (21) are sequentially cascaded, and each even-numbered stage of grid driving units (21) are sequentially cascaded;

each two adjacent gate driving units (21) are a gate driving unit group (210), each gate driving unit group (210) corresponds to two rows of adjacent scanning lines (2), and the two gate driving units (21) in the same gate driving unit group (210) are electrically connected with the two rows of scanning lines (2) corresponding to the gate driving unit group (210);

during driving, the grid driving units (21) of the odd-numbered stages and the grid driving units (21) of the even-numbered stages alternately work according to a preset switching period; when the grid driving units (21) of the odd-numbered stages work, the grid driving units (21) of the odd-numbered stages receive the first group of high-frequency clock signals, and generate scanning signals by using the first group of high-frequency clock signals to scan each row of scanning lines (2); when the even-level gate driving units (21) work, the even-level gate driving units (21) receive the second group of high-frequency clock signals, generate scanning signals by utilizing the second group of high-frequency clock signals and scan each row of scanning lines (2);

the operation of the gate driving units (21) of the odd-numbered stages and the operation of the gate driving units (21) of the even-numbered stages are switched once every interval of 80 to 120 frame scanning times.

2. The display driving circuit of claim 1, wherein the first set of high frequency clock signals comprises a first high frequency clock signal (CK1), a third high frequency clock signal (CK3), and a fifth high frequency clock signal (CK 5);

the second set of high frequency clock signals includes a second high frequency clock signal (CK2), a fourth high frequency clock signal (CK4), and a sixth high frequency clock signal (CK 6);

the rising edge generating time of the first high-frequency clock signal (CK1), the third high-frequency clock signal (CK3) and the fifth high-frequency clock signal (CK5) are sequentially separated by a preset delay time; the waveforms of the second high-frequency clock signal (CK2), the fourth high-frequency clock signal (CK4) and the sixth high-frequency clock signal (CK6) are respectively the same as the waveforms of the first high-frequency clock signal (CK1), the third high-frequency clock signal (CK3) and the fifth high-frequency clock signal (CK 5);

assuming that n is a positive integer, the 6n-5 th, 6n-4 th, 6n-3 th, 6n-2 th, 6n-1 th and 6n th stage gate driving units respectively receive a first high frequency clock signal (CK1), a second high frequency clock signal (CK2), a third high frequency clock signal (CK3), a fourth high frequency clock signal (CK4), a fifth high frequency clock signal (CK5) and a sixth high frequency clock signal (CK 6).

3. The display driving circuit of claim 1, wherein the first set of high frequency clock signals comprises a first high frequency clock signal (CK1), a third high frequency clock signal (CK3), a fifth high frequency clock signal (CK5), and a seventh high frequency clock signal (CK 7);

the second set of high frequency clock signals includes a second high frequency clock signal (CK2), a fourth high frequency clock signal (CK4), a sixth high frequency clock signal (CK6), and an eighth clock signal (CK 8);

rising edge generation times of the first high-frequency clock signal (CK1), the third high-frequency clock signal (CK3), the fifth high-frequency clock signal (CK5) and the seventh high-frequency clock signal (CK7) are sequentially spaced by a preset delay time; the waveforms of the second high frequency clock signal (CK2), the fourth high frequency clock signal (CK4), the sixth high frequency clock signal (CK6), and the eighth high frequency clock signal (CK8) are respectively identical to the waveforms of the first high frequency clock signal (CK1), the third high frequency clock signal (CK3), the fifth high frequency clock signal (CK5), and the seventh high frequency clock signal (CK 7);

assuming that n is a positive integer, the 8n-7 th, 8n-6 th, 8n-5 th, 8n-4 th, 8n-3 th, 8n-2 th, 8n-1 th, and 8 n-th gate driving units receive a first high frequency clock signal (CK1), a second high frequency clock signal (CK2), a third high frequency clock signal (CK3), a fourth high frequency clock signal (CK4), a fifth high frequency clock signal (CK5), a sixth high frequency clock signal (CK6), a seventh high frequency clock signal (CK7), and an eighth high frequency clock signal (CK8), respectively.

4. A display driving circuit as claimed in claim 1, wherein the gate driving unit (21) of the odd-numbered stage is operated, and the gate driving unit (21) of the first stage further receives a first start signal (STV1) for driving the gate driving unit (21) of the odd-numbered stage to start scanning;

when the even-numbered gate drive units (21) are operated, the gate drive units (21) of the second stage also receive a second start signal (STV2) for driving the even-numbered gate drive units (21) to start scanning.

5. The display driving circuit according to claim 1, wherein each stage of the gate driving unit (21) further receives a first low frequency clock signal (LC1) and a second low frequency clock signal (LC2) for maintaining the off state of the stage of the gate driving unit (21) during the period when the stage of the gate driving unit (21) is not outputting.

6. A display drive circuit as claimed in claim 1, characterized in that the operation of the gate drive units (21) of the odd-numbered stages and the gate drive units (21) of the even-numbered stages is switched once every 100 frame scan times.

7. The display driving circuit according to claim 1, further comprising a plurality of pixel units (3) arranged in an array, wherein each row of the scanning lines (2) is electrically connected to a corresponding row of the pixel units (3).

8. The display driving circuit according to claim 1, wherein the gate driving circuit (1) is a GOA circuit.

9. A display device comprising the display drive circuit according to any one of claims 1 to 8.