CN114927113B - Scan driving circuit and display panel - Google Patents

Abstract

The embodiment of the application discloses scanning drive circuit, including n scanning drive units and M clock signal that arrange in proper order, every scanning drive unit includes two scanning signal output subunits, receives the clock signal respectively and outputs a scanning signal respectively under clock signal control, and in a frame image display period, the clock signal includes first intermediate clock potential and second clock potential in proper order, and first intermediate clock potential lasts for first default duration, and second clock potential lasts for second default duration, and the second clock potential is greater than first intermediate clock potential. In a frame image display period, the duration time of the voltage of the output control node in the scanning signal output subunit is longer than the duration time of the clock signal, so that the clock signal is ensured to have enough time to control the output of the corresponding scanning signal, the output stability of the scanning signal is improved, and the display panel comprising the scanning driving circuit is also disclosed.

Description

Scan driving circuit and display panel

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a scan driving circuit and a display panel.

Background

The Gate Driver Less technology (GDL) is to use the original array process of the liquid crystal display panel to manufacture the driving circuit of the horizontal scanning line on the substrate around the display area, so as to replace the external integrated circuit board (Integrated Circuit, IC) to complete the driving of the horizontal scanning line. The GDL technology can reduce the welding procedure of an external IC, and can make the liquid crystal display panel more suitable for manufacturing display products with narrow frames or without frames.

When the GDL technology is used for scan driving, since the output of the scan signal is controlled by the scan driving unit and the clock signal in cascade, the timing problem of the scan signal output is easily caused, so that the scan signal cannot be completely output, and the scan driving unit is disabled.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, the present application provides a scan driving circuit with stable output.

A scan driving circuit includes n scan driving units and M clock signals which are sequentially arranged and cascaded, n and M are integers greater than or equal to 1, each scan driving unit includes two scan signal output subunits, the two scan signal output subunits respectively receive the clock signals and respectively output a scan signal under the control of the clock signals, the scan signals are used for outputting to scan lines in a display area and controlling pixel units correspondingly connected to the scan lines to receive image display data so as to execute image display. In a frame of image display period, the clock signal sequentially comprises a first intermediate clock potential and a second clock potential, wherein the first intermediate clock potential lasts for a first preset duration, and the second clock potential lasts for a second preset duration, namely the clock signal sequentially comprises a first intermediate potential with the first preset duration and a second voltage with the second preset duration, and the second clock potential is larger than the first intermediate clock potential.

Optionally, the clock signal rises from the first clock potential to a first intermediate clock potential for a first preset period of time at a first time, and rises from the first intermediate clock potential to a second clock potential for a second preset period of time at a second time, the first intermediate clock potential being greater than the first clock potential.

Optionally, the first intermediate clock potential is one half of the second clock potential, and the second preset duration is seven times of the first preset duration.

Optionally, the clock signal is in duration of the first intermediate clock potential, and the scan signal output subunit is controlled to output the scan signal and the stage signal with the first intermediate scan potential for a first preset duration. The clock signal is in the duration of the second clock potential, controls the scanning signal output subunit to output the scanning signal with the second scanning potential and the level transmission signal, and lasts for a second preset duration, wherein the second scanning potential is larger than the first intermediate scanning potential.

Optionally, the jth scan driving unit includes a first scan signal output subunit and a second scan signal output subunit, where J is greater than or equal to 3 and less than or equal to n, the first scan signal output subunit outputs a jth stage transmission signal and a jth scan signal under control of an mth clock signal, and the second scan signal output subunit outputs a jth+1 stage transmission signal and a jth+1 scan signal under control of an mth+1 clock signal, where j=2j_1 is used for controlling output of corresponding scan signals and stage transmission signals in the cascaded scan driving unit.

Optionally, the first scan signal output subunit includes a first output control node and a first output module, where the first output control node is configured to control the first output module to receive an mth clock signal, and output a jth scan signal and a jth level pass signal according to the mth clock signal.

Optionally, in the first period, the first unit in the J-th scan driving unit receives the J-4 th level transmission signal output by the first scan signal output subunit in the J-2 th scan driving unit, so as to control the voltage of the first output control node in the first scan signal output subunit of the J-th scan driving unit to rise from the first node potential to the first intermediate node potential, and after a first preset period, the voltage of the first intermediate node potential rises to the second node potential, and continues for a second preset period, and when the voltage of the first output control node is greater than or equal to the second node potential, the first output control node controls the first output module to receive the m clock signal.

Optionally, in the second period, in the J-th scan driving unit, the m-th clock signal rises from the first clock potential to the second intermediate clock potential for a first preset period of time at the first time, the voltage of the first output control node rises from the second node potential to the second intermediate node potential for the first preset period of time under the control of the m-th clock signal,

The mth clock signal rises from the first intermediate clock potential to the second clock potential for a second preset time period at the second moment, and the voltage of the first output control node rises from the second intermediate node potential to the third node potential for the second preset time period under the control of the mth clock signal.

Optionally, in the third period, the voltage of the j+4-th level transmission signal rises from the first scanning potential to the first intermediate scanning potential for a first preset duration, and the voltage of the first output control node in the first scanning signal output subunit in the J-th scanning driving unit drops from the third node potential to the second intermediate node potential for the first preset duration under the control of the j+4-th level transmission signal;

the j+4 stage signal rises from the first intermediate scanning potential to the second scanning potential, and the voltage of the first output control node in the first scanning signal output subunit in the J-th scanning driving unit drops from the second intermediate node potential to the first node potential.

The embodiment of the application also discloses a display panel, which comprises the scanning driving circuit, the data driving circuit and the display control circuit, wherein the display control circuit receives an original data signal according to an external signal source and respectively outputs a source output control signal and a grid output control signal, and the data driving circuit controls the pixel unit to display images according to the source output control signal and the scanning driving circuit and the grid output control signal.

Compared with the prior art, the scan driving circuit provided by the application ensures that the maintenance time of the voltage of the output control node in the scan signal output subunit is longer than that of the clock signal in one frame of image display period, thereby ensuring that the clock signal has sufficient time to control the output of the corresponding scan signal, avoiding the problem of incomplete scan signal output caused by rapid pull-down of the node voltage, improving the output stability of the scan signal and enhancing the display effect.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of a display device according to a first embodiment of the present disclosure;

fig. 2 is a schematic side view of a display panel shown in fig. 1 according to a second embodiment of the present application;

FIG. 3 is a schematic plan layout of the display panel of FIG. 2;

Fig. 4 is a schematic structural diagram of a scan driving circuit shown in fig. 3 according to a third embodiment of the present application;

FIG. 5 is a schematic diagram of a cascade of GOA units of FIG. 4;

FIG. 6 is an equivalent circuit diagram of the GOA unit of FIG. 5;

FIG. 7 is a timing diagram of the output of the clock signal in the GOA unit shown in FIG. 4;

fig. 8 is a schematic diagram of a level change of an output control node in the GOA unit shown in fig. 6.

Reference numerals illustrate: display device-100, display panel-10, power supply module-20, support frame 30, data driving circuit-11, scan driving circuit-12, display control circuit-14, pixel unit-15 backlight module-17, array substrate-131, liquid crystal layer-132, color film substrate-133, first direction-F1, second direction-F2, data lines-S1 to Sm, scan lines-G1 to G2n, clock signal-CLK, GOA unit-140, j-th transmission signal-C (j), j-th scan signal-G (j), scan driving unit-GOA unit, scan signal output sub-unit-GDL unit, first GDL unit-GDL 1, second GDL unit-GDL 2, first pull-up control module-141, first output module-142, first pull-down control module-143A, second pull-down control module-143B, first pull-down module-144, first pull-down maintenance module 145, first node-Q (j), second node-Qb (j), second control module-j), second pull-up control module-151, second pull-down control module-j, second transistor (vss+q+3), second pull-down control module-q+fourth transistor (j), second pull-down control module-q+q 2, fourth pull-down control module 153, fourth pull-down control module-q+fourth voltage level, twenty-first transistor-T22, first capacitor-C1, thirty-first transistor-T31, thirty-first transistor-T32, thirty-third transistor-T33, thirty-fourth transistor-T34, thirty-fifth transistor-T35, thirty-sixth transistor-T36, thirty-seventh transistor-T37, forty-first transistor-T41, forty-first transistor-T42, forty-third transistor-T43, forty-fourth transistor-T44, fifty-first transistor-T51, fifty-first transistor-T52, fifty-third transistor-T53, sixty-first transistor-T61, seventy-first transistor-T71, seventy-first transistor-T72, second capacitor-C2, eighty-first transistor-T81, eighty-first transistor-T82, forty-first transistor-T42, fifty-first transistor-T52, seventy-first transistor-T71, seventy-first transistor-T72, seventy-first transistor-T81, seventy-first transistor-third transistor-T82, forty-first transistor-T eighty-third transistor-T83, eighty-fourth transistor-T84, eighty-fifth transistor-T85, eighty-sixth transistor-T86, eighty-seventh transistor-T87, ninety-first transistor-T91, ninety-fourth transistor-T92, ninety-third transistor-T93, ninety-fourth transistor-T94, ninety-fifth transistor-T95, ninety-sixth transistor-T96, ninety-seventh transistor-T97, first time Zhong Dianwei-Vk 1, first intermediate clock potential-Vka, second clock potential-Vk 2, first scan potential-Vg 1, first intermediate scan potential-Vga, second scan potential-Vg 2, first node potential-Vq 1, first intermediate node potential-Vqa, second node potential-Vq 2, second intermediate node potential-Vqb, third intermediate node potential-vqq 2, fourth intermediate node potential-Vq 2, third intermediate potential-Vq 2, fourth intermediate potential-Vq 2, third intermediate potential-Vq 2, fourth intermediate potential-Vg 2, third intermediate potential-v 2, and fourth intermediate potential-v 2, third node potential-Vq 3.

Detailed Description

In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. Preferred embodiments of the present application are shown in the accompanying drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

The following description of the embodiments refers to the accompanying drawings, which illustrate specific embodiments that can be used to practice the present application. The numbering of the components itself, e.g. "first", "second", etc., is used herein merely to distinguish between the described objects and does not have any sequential or technical meaning. The terms "coupled" and "connected," as used herein, are intended to encompass both direct and indirect coupling (coupling), unless otherwise indicated. Directional terms referred to in this application, such as "upper", "lower", "front", "rear", "left", "right", "inner", "outer", "side", etc., are merely directions referring to the attached drawings, and thus, directional terms are used for better, more clear description and understanding of the present application, rather than indicating or implying that the apparatus or element being referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present application.

In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; may be a mechanical connection; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context. It should be noted that the terms "first," "second," and the like in the description and claims of the present application and in the drawings are used for distinguishing between different objects and not for describing a particular sequential order.

Furthermore, the terms "comprises," "comprising," "includes," "including," "may be" or "including" as used in this application mean the presence of the corresponding function, operation, element, etc. disclosed, but not limited to other one or more additional functions, operations, elements, etc. Furthermore, the terms "comprises" or "comprising" mean that there is a corresponding feature, number, step, operation, element, component, or combination thereof disclosed in the specification, and that there is no intention to exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof. Furthermore, when describing embodiments of the present application, use of "may" means "one or more embodiments of the present application. Also, the term "exemplary" is intended to refer to an example or illustration.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a display device 100 according to a first embodiment of the present disclosure. The display device 100 includes a display panel 10, a power module 20 and a supporting frame 30, wherein the display panel 10 and the power module 20 are fixed on the supporting frame 30, and the power module 20 is disposed on a back surface of the display panel 10, i.e. a non-display surface of the display panel 10. The power module 20 is used for providing power voltage for the display panel 10 to display images, and the support frame 30 provides fixing and protecting functions for the display panel 10 and the power module 20.

Referring to fig. 2, fig. 2 is a schematic side view of a display panel 10 shown in fig. 1 according to a second embodiment of the present application. As shown in fig. 2, the display panel 10 includes a backlight module 17 (Back light Module, BM), the backlight module 17 is configured to provide display light to a display area of the display panel 10, and the display panel 10 emits corresponding light according to an image signal to be displayed to perform image display. The display panel 10 further includes other elements or components, such as a signal processor module and a signal sensing module.

In the exemplary embodiment, the display panel 10 may be a liquid crystal display panel, or may be another type of display panel, which is not limited in this application.

Taking the liquid crystal display panel AS an example, the display panel 10 further includes an Array Substrate (AS) 131, a color film substrate (Color film substrate, CF) 133, and a liquid crystal layer 132 interposed between the Array substrate 131 and the color film substrate 133. The driving elements disposed on the array substrate 131 and the color film substrate 133 generate corresponding electric fields according to the image signals, so as to drive the liquid crystal molecules in the liquid crystal layer 132 to rotate at an angle to emit light with corresponding brightness, so as to perform image display.

Referring to fig. 3, fig. 3 is a schematic plan layout structure of the display panel 10 in fig. 2.

As shown in fig. 3, the display panel 10 further includes a data driving circuit 11, a scan driving circuit 12, and a display control circuit 14, and the data driving circuit 11, the scan driving circuit 12, and the display control circuit 14 are disposed in a non-display area of the display panel 10.

The display area of the display panel 10 includes a plurality of scanning lines (Gate lines) G1 to Gn extending in the first direction F1 and a plurality of data lines (Source lines) S1 to Sm extending in the second direction F2, which are disposed in a grid-like manner with respect to each other. Wherein the first direction F1 and the second direction F2 are perpendicular to each other, and the plurality of scan lines G1 to G2n, the plurality of data lines S1 to Sm, and the plurality of scan lines G1 to G2n and the plurality of data lines S1 to Sm are insulated from each other.

The pixel units 15 are provided at intersections of the plurality of scanning lines G1 to G2n and the data lines S1 to Sm. In the present embodiment, the pixel units 15 may be represented as P11-P1 m, P21-P2 m, … …, pn 1-Pnm, respectively.

Each pixel unit 15 includes a driving element and a liquid crystal layer 132. The liquid crystal layer 132 emits light when driven by the driving element. In this embodiment, the driving element includes a semiconductor switch element and an energy storage element, the semiconductor switch may be a thin film transistor (Thin Film Transistor, TFT), and the energy storage element may be a capacitor formed by a pixel electrode (not identified) and a common electrode (not identified).

The scan lines G1 to G2n are connected to the scan driving circuit 12, receive scan signals from the scan driving circuit 12, and the Data lines S1 to Sm are connected to the Data driving circuit 11, for receiving Data signals Data stored and transmitted in the form of gray scale values supplied from the Data driving circuit 11.

The pixel unit 15 receives the Data voltages corresponding to the gray scale values in the image signals Data provided by the Data lines S1 to Sm in a predetermined period under the control of the scan lines G1 to G2n, and drives the liquid crystal layer 132 to deflect corresponding angles accordingly, so that the received backlight emits light rays with corresponding brightness according to the deflected corresponding angles, and the image display is performed by emitting the light rays with corresponding brightness according to the image signals.

The display control circuit 14 receives a raw Data signal representing image information, a clock signal CLK for synchronization, a horizontal synchronization signal Hsyn, and a vertical synchronization signal Vsyn from an external signal source, and outputs a gate output control signal Cg for controlling the scan driving circuit 12, a source output control signal Cs for controlling the Data driving circuit 11, and a Data signal Data representing image information. In this embodiment, the display control circuit 14 performs Data adjustment processing on the original Data signal to obtain a Data signal Data, and transmits the Data signal Data to the Data driving circuit 11.

The scan driving circuit 12 receives the gate output control signal Cg output from the display control circuit 14, and outputs scan signals to the respective scan lines G1 to G2 n. The Data driving circuit 11 receives the source output control signal Cs output from the display control circuit 14, and outputs a Data signal Data for performing image display to the driving element in each pixel unit 15 in the display panel 10 to each of the Data lines S1 to Sm. The Data signal Data provided to the display panel 10 is a gray scale voltage in analog form. The scan driving circuit 12 outputs a scan signal to control the pixel unit 15 to receive the Data signal Data output from the Data driving circuit 11, so as to control the pixel unit 15 to display a corresponding image.

Referring to fig. 4, fig. 4 is a schematic diagram illustrating a structure of the scan driving circuit 12 shown in fig. 3 according to a third embodiment of the present application. As shown in fig. 4, the scan driving circuit 12 includes a plurality of scan driving units 140 in cascade, M clock signals CLK1 to CLKM, a start signal STV, a reset signal R, a first low voltage level Vss1, and a second low voltage level Vss2. The scan driving unit 140 is hereinafter referred to as a GOA unit for convenience of description.

In the exemplary embodiment, the scan driving circuit 12 may also set the clock signal to any number for control according to specific needs, which is not limited in this application.

In the present embodiment, eight clock signals, that is, the first clock signal CLK1 to the eighth clock signal CLK8 are taken as an example. The scan driving circuit 12 includes n GOA units, each GOA unit correspondingly outputs two scan signals to two scan lines, and in a frame of image display process, the n GOA units correspondingly output 2n scan signals, which are G (1) to G (2 n) respectively.

In an exemplary embodiment, the number of scan lines may be set according to the actual resolution of the display panel, which is not limited in this application.

Eight clock signals CLK1-CLK8 are used to provide scan driving timing for the GOA unit output scan signals. The start signal STV is an initial start signal of the first GOA unit GOA1, and the other GOA units are used as start signals according to the stage signals output by the cascade GOA units. The first low voltage potential Vss1 and the second low voltage potential Vss2 are used to provide low voltages to nodes and signals in the scan driving unit.

Referring to fig. 5, fig. 5 is a schematic diagram of cascade connection of GOA units in fig. 4. As shown in FIG. 5, taking the Kth GOA unit as an example, wherein 2.ltoreq.K.ltoreq.n, the Kth GOA unit outputs a 2K-1 th level signal C (2K-1) and a 2K-th level signal C (2K) for pulling up the voltages of two nodes in the Kth+2GOA unit to control the output of two scanning signals in the Kth+2GOA unit, and simultaneously pulling down the voltages of two nodes in the Kth-2 GOA unit to control the two scanning signals in the Kth-2 GOA unit to stop outputting.

Taking the 4 th GOA unit GOA4 as an example, the 4 th GOA unit GOA4 outputs a 7 th level transmission signal and an 8 th level transmission signal, and the 7 th level transmission signal and the 8 th level transmission signal are used for pulling up node voltages in the 6 th GOA unit GOA6 to control the output of two scanning signals in the 6 th GOA unit GOA6 and are used for pulling down node voltages in the 2 nd GOA unit GOA2 to control the two scanning signals in the 2 nd GOA unit GOA2 to stop outputting.

Meanwhile, the 2K-5 th level transmission signal C (2K-5) and the 2K-4 th level transmission signal C (2K-4) output by the K-2 th GOA unit are used for pulling up two node voltages in the K-th GOA unit so as to control the 2K-1 st scanning signal and the 2K scanning signal output in the K-th GOA unit. The (K+2) th GOA unit outputs 2K+3 th level signal C (2K+3) and 2K+4 th level signal C (2K+4) for pulling down node voltages in the (K) th GOA unit to control the (2K-1) th scan signal and the (2K) th scan signal in the (K) th GOA unit to stop outputting.

For example, the 3 rd and 4 th pass signals C (3) and C (4) outputted from the 2 nd GOA unit are used to pull up the node voltage in the 4 th GOA unit GOA4 to control the outputs of the 7 th and 8 th scan signals in the 4 th GOA unit GOA 4. The 11 th and 12 th pass signals output from the 6 th GOA unit GOA6 are used to pull down the node voltage in the 4 th GOA unit GOA4 to control the 3 rd and 4 th scan signals in the 4 th GOA unit to stop outputting.

Referring to fig. 6, fig. 6 is an equivalent circuit diagram of the GOA unit of fig. 5. As shown in fig. 6, the GOA unit includes two scan signal output subunits, namely a first scan signal output subunit and a second scan signal output subunit, wherein the scan signal output subunit is replaced by a GDL unit for convenience of description, i.e. the first scan signal output subunit is a first GDL unit GDL1, and the second scan signal output subunit is a second GDL unit GDL2.

Taking the J-th GDL unit as an example, wherein 1.ltoreq.J.ltoreq.n. The J-th GOA unit includes a first GDL unit GDL1 outputting a J-th stage transmission signal C (J) and a J-th scan signal G (J) and a second GDL unit GDL2 outputting a j+1th stage transmission signal C (j+1) and a j+1th scan signal G (j+1), j=2j-1.

The first GDL unit GDL1 includes a first pull-up control module 141, a first output module 142, a first pull-down control module 143A, a second pull-down control module 143B, a first pull-down module 144, a first pull-down maintenance module 145, a first node Q (j), and a second node Qb (j), where the first node Q (j) is a first output control node.

The second GDL unit GDL2 includes a second pull-up control module 151, a second output module 152, a third pull-down control module 153A, a fourth pull-down control module 153B, a second pull-down module 154, a second pull-down maintenance module 155, a third node Q (j+1) and a fourth node Qb (j+1), wherein the third node Q (j+1) is a second output control node.

Specifically, in the first GDL unit GDL1, the first pull-up control module 141 connects the first node Q (J) while receiving the J-4 th level transmission signal C (J-4) output from the J-2 th GOA unit. The j-4 th level transmission signal C (j-4) is utilized to precharge the first node Q (j) and pull up the first node Q (j) from the first node potential to the second node potential, wherein the first node potential is greater than the second node potential.

The first output module 142 is connected to the ith clock signal CLK (i) (1+.i < M) and the first node Q (j), and is configured to output the jth level transmission signal C (j) and the jth scan signal G (j) when the potential of the first node Q (j) is the second node potential under the control of the ith clock signal CLKi. The J-th stage transmission signal C (J) is used for controlling the j+4-th stage transmission signal C (j+4) and the j+4-th stage scanning signal G (j+4) of the second scanning potential output by the first GDL unit GDL1 in the j+2-th GOA unit, and simultaneously controlling the J-4-th stage transmission signal C (J-4) and the J-4-th scanning signal G (J-4) of the first scanning potential output by the first GDL unit GDL1 in the J-2-th GOA unit.

The first pull-down control module 143A connects the first node Q (J), the second node Qb (J), and the first voltage level Vss1, and receives the j+4 th level transmission signal C (j+4) and the first reset signal R1 outputted from the j+2 th GOA unit. The potential of the first node Q (J) is pulled down to the first node potential by the j+4 th level transmission signal C (j+4) output by the j+2 th GOA unit. During each frame of image display, the first reset signal R1 is utilized to pull down the potentials of the first node Q (j) and the second node Qb (j) to the first node potential, namely the first low-voltage potential VSS, so as to avoid circuit leakage aggregation. Through the arrangement of the first node and the second node, the voltages of the first node and the second node can be controlled through the level transmission signal, so that the output and the stop of the scanning signal and the level transmission signal in the first GDL unit are effectively controlled.

The first pull-down module 144 is connected to an output terminal (not identified) of the jth stage of the transmission signal C (j), an output terminal (not identified) of the jth scan signal G (j), the second node Qb (j), the third node Q (j+1), the first low voltage level Vss1, and the second low voltage level Vss2. When the second node Qb (j) is at the second node potential, the j-th stage signal C (j) is pulled down to the first low voltage potential Vss1, the j-th stage signal C (j) having the first scan potential is output, and at the same time, the j-th scan signal is pulled down to the second low voltage potential Vss2, and the j-th scan signal G (j) is controlled to stop outputting.

The first pull-down maintaining module 145 connects the first node Q (J), the second node Qb (J), the third node Q (j+1), and the first voltage level Vss1 while receiving the J-4 th level transmission signal C (J-4) outputted from the first GDL unit among the J-2 nd GOA units. The first node Q (j) and the second node Qb (j) levels are maintained using the j-4 th level pass signal C (j-4). Wherein when the first node Q (j) is at the second node potential, the potential of the second node Qb (j) is pulled down to the first low voltage potential Vss1, that is, the first node potential, and the first node potential of the second node Qb (j) is maintained during a period in which the first node Q (j) is at the second node potential. When the third node Q (j+1) is at the second potential, the second node Qb (j) is controlled to stop receiving the power supply voltage VDD, and the potential of the second node Qb (j) is pulled down to the first low voltage potential Vss1 and the first node potential state of the second node is maintained during a period when the third node Q (j+1) is at the second potential. When the first node Q (j) and/or the third node Q (j+1) is at the first node potential, the second node Qb (j) receives the power supply voltage VDD and maintains the second node potential. The first node potential is low level, and the second node potential is high level.

In the second GDL unit GDL2, the second pull-up control module 151 is connected to the third node Q (j+1) and receives the J-3 rd level transmission signal C (J-3) outputted from the J-2 th GOA unit. Precharging the third node Q (j+1) with the j-3 rd pass signal C (j-3) pulls the potential of the third node Q (j+1) up from the first node potential to the second node potential.

The second output module 152 is connected to the i+1th clock signal CLK (i+1) and the third node Q (j+1). For outputting the j+1th-stage transmission signal C (j+1) and the j+1th scanning signal G (j+1) when the potential of the third node Q (j+1) is the second node potential under the control of the i+1th clock signal CLK (i+1). The j+1th stage transmission signal C (j+1) is used for controlling the j+5th stage transmission signal C (j+5) and the j+5th scanning signal G (j+5) of the second scanning potential output by the second GDL unit GDL2 in the j+2th stage GOA unit, and simultaneously controlling the J-5 th stage transmission signal C (J-5) and the J-5 th scanning signal G (J-5) of the first scanning potential output by the second GDL unit GDL2 in the J-3 th GOA unit.

The third pull-down control module 153A receives the second reset signal R2 and the j+5-th level signal C (j+5) output from the j+2th GOA unit at the same time, the third node Q (j+1), the fourth node Qb (j+1), and the first voltage level Vss1. The potential of the third node Q (j+1) is pulled down to the first node potential using the j+5 th stage signal C (j+5). The potentials of the third node Q (j+1) and the fourth node Qb (j+1) are pulled down by the second reset signal R2. The third node Q (j+1) is pulled down to the first low voltage level Vss1 by the third pull-down control module 153A.

The fourth pull-down control module 153B is electrically connected to the power voltage VDD, the third node Q (j+1) and the fourth node Qb (j+1). The fourth pull-down control module 153B controls the fourth node Qb (j+1) to be connected to the first voltage level Vss1 when the third node Q (j+1) is at the second node level, and controls the fourth node Qb (j+1) to be connected to the power supply voltage VDD when the third node Q (j+1) is at the first node level. Through the arrangement of the third node and the fourth node, the voltages of the third node and the fourth node can be controlled through the level transmission signal, so that the output and the stop of the scanning signal and the level transmission signal in the second GDL unit are effectively controlled.

The second pull-down module 154 is connected to an output terminal (not identified) of the j+1th stage of the signal C (j+1), an output terminal (not identified) of the j+1th scan signal G (j+1), the fourth node Qb (j+1), the first low voltage level Vss1, and the second low voltage level Vss2. When the fourth node Qb (j+1) is at the second node potential, the j+1th stage signal C (j+1) is pulled down to the first voltage potential Vss1, and the j+1th stage signal C (j+1) having the first scanning potential is output. The output terminal of the j+1th scan signal G (j+1) receives the second voltage level Vss2 and stops outputting the j+1th scan signal G (j+1).

The second pull-down maintenance module 155 connects the first node Q (J), the third node Q (j+1), the fourth node Qb (j+1), and the first voltage level Vss1, and receives the J-3 rd level transmission signal C (J-3) outputted from the second GDL unit GDL2 in the J-2 th GOA unit. The j-3 th level signal and the third node Q (j+1) at the second node potential are utilized to control the fourth node Qb (j+1) to access the first low voltage potential Vss1 and maintain the first low voltage potential Vss1 of the fourth node Qb (j+1) in the period. When the first node Q (j) is at the second node potential, the potential of the fourth node Qb (j+1) is pulled down to the first low voltage potential Vss1, and the first low voltage potential Vss1 of the fourth node Qb (j+1) is maintained for a period in which the first node Q (j) is at the second node potential. By setting the second pull-down maintaining module, when the first node and the third node are at the potential of the second node, the fourth node is controlled to be in a shutdown state, the scanning signals of the first GDL unit and/or the second GDL unit are maintained to be stably output, and the influence of the voltage fluctuation of the fourth node on the output of the current scanning signals is avoided.

More specifically, the first pull-up control module 141 includes an eleventh transistor T11. The gate and source of the eleventh transistor T11 are connected to the input terminal (not identified) of the j-4 th level signal C (j-4), and the drain is electrically connected to the first node Q (j).

The first output module 142 includes a twenty-first transistor T21, a twenty-second transistor T22, and a first capacitor C1. The source of the twenty-first transistor T21 is connected to the i-th clock signal CLK (i), the gate is electrically connected to the first node Q (j), and the drain is electrically connected to the output terminal (not identified) of the j-th stage signal C (j). The source electrode of the twenty-second transistor T22 is connected to the ith clock signal CLK (i), the gate electrode is electrically connected to the first node Q (j), the first capacitor C1 is connected between the gate electrode and the source electrode, and the drain electrode is electrically connected to the output end (not identified) of the jth scan signal G (j).

The first pull-down control module 143A includes a thirty-first transistor T31, a thirty-second transistor T32, a thirty-third transistor T33, and a thirty-fourth transistor T34. The thirty-first transistor T31 has a gate connected to the first reset signal R1, a source electrically connected to the first node Q (j), and a drain electrically connected to the first low voltage terminal for receiving the first low voltage level Vss1. The thirty-second transistor T32 has a gate electrically connected to the second node Qb (j), a source electrically connected to the first node Q (j), and a drain electrically connected to the first low voltage terminal to receive the first low voltage potential Vss1. The thirty-third transistor T33 has a gate connected to the j+4th stage of the transmission signal C (j+4), a source electrically connected to the first node Q (j), and a drain electrically connected to the first low voltage terminal for receiving the first low voltage level Vss1. The thirty-fourth transistor T34 has a gate electrically connected to the fourth node Qb (j+1), a source electrically connected to the first node Q (j), and a drain electrically connected to the first low voltage terminal for receiving the first low voltage potential Vss1.

The second pull-down control module 143B includes a thirty-fifth transistor T35, a thirty-sixth transistor T36, and a thirty-seventh transistor T37. The source and gate of the thirty-fifth transistor T35 are electrically connected to the power voltage VDD, and the drain is electrically connected to the gate of the thirty-sixth transistor T36 and the source of the thirty-seventh transistor T37. The thirty-sixth transistor T36 has a source electrically connected to the power voltage VDD and a drain electrically connected to the second node Qb (j). The thirty-seventh transistor T37 has a gate electrically connected to the first node Q (j), and a drain electrically connected to the first low voltage terminal for receiving the first low voltage potential Vss1.

The first pull-down module 144 includes a forty-first transistor T41, a forty-second transistor T42, a forty-third transistor T43, and a forty-fourth transistor T44. The gate of the forty-first transistor T41 is electrically connected to the second node Qb (j), the source is connected to the output terminal of the j-th level signal C (j), and the drain is electrically connected to the first low voltage terminal to receive the first low voltage potential Vss1. The gate of the forty-second transistor T42 is electrically connected to the second node Qb (j), the source is connected to the output terminal of the j-th scan signal G (j), and the drain is electrically connected to the second low voltage terminal to receive the second low voltage level Vss2. The forty-third transistor T43 has a gate electrically connected to the fourth node Qb (j+1), a source connected to the output terminal of the j-th scan signal G (j), and a drain electrically connected to the second low voltage terminal for receiving the second low voltage level Vss2. The gate of the forty-fourth transistor T44 is electrically connected to the fourth node Qb (j+1), the source is connected to the output terminal of the j-th stage signal C (j), and the drain is electrically connected to the second low voltage terminal to receive the second low voltage potential Vss2.

The first pull-down maintaining module 145 includes a fifty-first transistor T51, a fifty-second transistor T52, and a thirteenth transistor T53. The fifty-first transistor T51 has a gate connected to the first node Q (j), a source electrically connected to the second node Qb (j), and a drain electrically connected to the first low voltage terminal for receiving the first low voltage level Vss1. The fifty-th transistor T52 has a gate connected to the input terminal (not identified) of the j-4 th stage signal C (j-4), a drain electrically connected to the first low voltage terminal for receiving the first low voltage potential Vss1, and a source electrically connected to the second node Qb (j). The fifty-third transistor T53 has a gate electrically connected to the third node Q (j+1), a source electrically connected to the drain of the thirty-fifth transistor T35, and a drain electrically connected to the first low voltage terminal for receiving the first low voltage level Vss1.

The second pull-up control module 151 includes a sixty-one transistor T61. The gate and source of the sixty-first transistor T61 are connected to the input terminal (not identified) of the j-3 rd stage signaling C (j-3), and the drain is electrically connected to the third node Q (j+1).

The second output module 152 includes a seventy-first transistor T71, a seventy-second transistor T72, and a second capacitor C2. The source of the seventeenth transistor T71 is connected to the i+1th clock signal CLK (i+1), the gate is electrically connected to the third node Q (j+1), and the drain is electrically connected to the output terminal of the j+1th stage signal C (j+1). The source electrode of the seventy transistor T72 is connected to the i+1th clock signal CLK (i+1), the gate electrode is electrically connected to the third node Q (j+1), the second capacitor C2 is connected between the gate electrode and the source electrode, and the drain electrode is electrically connected to the output end of the j+2th scan signal G (j+2).

The third pull-down control module 153A includes an eighty-one transistor T81, an eighth twelve transistor T82, an eighty-thirteen transistor T83, and an eighty-four transistor T84. The eighth transistor T81 has a gate connected to the second reset signal R2, a source electrically connected to the third node Q (j+1), and a drain electrically connected to the first low voltage terminal for receiving the first low voltage potential Vss1. The eighth transistor T82 has a gate electrically connected to the fourth node Qb (j+1), a source electrically connected to the third node Q (j+1), and a drain electrically connected to the first low voltage terminal for receiving the first low voltage level Vss1. The eighth transistor T83 has a gate connected to the input terminal (not identified) of the j+5 th stage of signal C (j+5), a source electrically connected to the third node Q (j+1), and a drain electrically connected to the first low voltage terminal for receiving the first low voltage level Vss1. The eighty-fourth transistor T84 has a gate electrically connected to the fifth node Qb (j+2), a source electrically connected to the third node Q (j+1), and a drain electrically connected to the first low voltage terminal for receiving the first low voltage level Vss1.

The fourth pull-down control module 153B includes an eighty-five transistor T85, an eighty-six transistor T86, and an eighty-seven transistor T87. The source and gate of the eighty-fifth transistor T85 are electrically connected to the power voltage VDD, and the drain is electrically connected to the gate of the eighty-sixth transistor T86 and the source of the eighty-seventh transistor T87. The eighth transistor T86 has a source electrically connected to the power voltage VDD, and a drain electrically connected to the fourth node Qb (j+1). The eighth transistor T87 has a gate electrically connected to the third node Q (j+1), and a drain electrically connected to the first low voltage terminal for receiving the first low voltage level Vss1.

The second pull-down module 154 includes a nineteenth transistor T91, a nineteenth transistor T92, a nineteenth transistor T93, and a nineteenth transistor T94. The gate of the nineteenth transistor T91 is electrically connected to the fourth node Qb (j+1), the source is connected to the output terminal of the j+1th level signal C (j+1), and the drain is electrically connected to the first low voltage terminal to receive the first low voltage level Vss1. The gate of the ninety transistor T92 is electrically connected to the fourth node Qb (j+1), the source is connected to the output terminal of the j+2th scan signal G (j+2), and the drain is electrically connected to the second low voltage terminal to receive the second low voltage level Vss2. The nineteenth transistor T93 has a gate electrically connected to the fifth node Qb (j+2), a source electrically connected to the output terminal of the j+2th scan signal G (j+2), and a drain electrically connected to the second voltage level Vss2. The ninety-fourth transistor T94 has a gate electrically connected to the fifth node Qb (j+2), a source connected to the output terminal of the j+1st stage signal C (j+1), and a drain electrically connected to the second low voltage terminal for receiving the second low voltage level Vss2.

The second pull-down maintenance module 155 includes a ninety-fifth transistor T95, a ninety-sixth transistor T96, and a ninety-seventh transistor T97. The ninety-five transistor T95 has a gate electrically connected to the third node Q (j+1), a source electrically connected to the fourth node Qb (j+1), and a drain electrically connected to the first low voltage terminal for receiving the first low voltage level Vss1. The gate of the ninety-sixth transistor T96 is connected to the input terminal of the j-3 rd stage transmission signal C (j-3), the source is electrically connected to the fourth node Qb (j+1), and the drain is electrically connected to the first low voltage terminal to receive the first low voltage level Vss1. The ninety-seventh transistor T97 has a gate electrically connected to the first node Q (j), a source electrically connected to the drain of the eighty-fifth transistor T85, and a drain electrically connected to the first low voltage terminal for receiving the first low voltage level Vss1.

Referring to fig. 7, fig. 7 is a timing chart of the output of the clock signal in the GOA unit shown in fig. 4. As shown in fig. 7, eight clock signals CLK1-CLK8 are used to provide scan driving timing for the GDL cell output driving signals, each rising from a first clock Zhong Dianwei Vk1 to a second clock potential Vk2 at a first time t1, thereby controlling the output of the scan signals in the GDL cells. Wherein, each clock signal total duration is 4H, a first intermediate clock potential Vka is provided at the rising edge of the clock signal, and the first intermediate clock potential Vka is half of the second clock potential V2 for a duration of 0.5H. Taking a 60Hz 4K (3840×2160) lcd as an example, each frame of image needs to scan 2160 lines, i.e. 2160 times, and 60 frames of images can be scanned in one second, i.e. the refresh rate is 60Hz, so that the pixel time of each line is h=7.4um.

Referring to fig. 8, fig. 8 is a schematic diagram illustrating a level change of an output control node of the GOA unit of fig. 6. As shown in figure 8 of the drawings,

in the first GDL unit GDL1 of the J-th GOA unit, in the first period T1, the voltage of the first node Q (J) is pulled up by the J-4 th level transmission signal C (J-4) outputted by the first GDL unit GDL1 of the J-2 th GOA unit, and the voltage of the first node Q (J) is pulled up from the first node potential Vq1 to the second node potential Vq2. When the voltage of the j-4 th level signal C (j-4) rises from the first scan voltage Vg1 to the first intermediate scan voltage Vga and maintains the first preset time period of 0.5H, the voltage of the first node Q (j) rises from the first node voltage Vq1 to the first intermediate node voltage Vqa and maintains the first preset time period of 0.5H. When the voltage of the j-4 th stage transmission signal C (j-4) rises from the first intermediate scan voltage Vga to the second scan voltage Vg2 and is maintained for the second preset period of time 3.5H, the voltage of the first node Q (j) rises from the first node voltage Vq1 to the second node voltage Vq2 and is maintained for the second preset period of time 3.5H. The first intermediate node potential Vqa is half the second node potential Vq2. When the potential of the first node Q (j) is the second node potential Vq2, the first node Q (j), that is, the first output control node, controls the first output module 142 to receive the ith clock signal CLKi, and controls the jth scan signal G (j) and the jth stage signal C (j) to output at the ith clock signal CLKi.

In the second period T2, the voltage of the first node Q (J) is controlled by the i-th clock signal CLKi received by the first GDL unit GDL1 in the current J-th GOA unit to rise from the second node potential Vq2 to the third potential Vq3, wherein when the i-th clock signal rises from the first time Zhong Dianwei Vk1 to the first intermediate clock potential Vka for the first preset time period 0.5H at the first time T1, the voltage of the first output control node, i.e., the first node Q (J), rises from the second node potential Vq2 to the second intermediate node potential Vqb for the first preset time period 0.5H under the control of the i-th clock signal, the i-th clock signal rises from the first intermediate clock potential Vka to the second clock potential Vk2 for the second preset time period 3.5H, and the voltage of the first output control node rises from the second intermediate node potential qb to the third intermediate node potential Vq3 for the second preset time period 3.5H under the control of the i-th clock signal.

Meanwhile, the jth scan signal G (j) and the jth stage pass signal C (j) in the first GDL unit GDL1 are pulled up from the first scan potential Vg1 to the second scan potential Vg2 under the control of the ith clock signal CLKi, whose variation waveform is the same as the ith clock signal CLKi, and the total duration is 4H. When the ith clock signal rises from the first time Zhong Dianwei Vk1 to the first intermediate clock potential Vka and lasts for the first preset time period of 0.5H, the voltages of the jth scan signal and the jth stage transfer signal rise from the first scan potential Vg1 to the first intermediate scan potential Vga and last for the first preset time period of 0.5H under the control of the ith clock signal, the ith clock signal rises from the first intermediate clock potential Vka to the second clock potential Vk2 and last for the second preset time period of 3.5H at the second time t2, and the voltages of the jth scan signal and the jth stage transfer signal rise from the first intermediate scan potential Vqa to the second scan potential Vq2 and last for the second preset time period of 3.5H under the control of the ith clock signal.

When the i-th clock signal CLKi stops outputting, the j-th scan signal G (j) also immediately stops outputting following the i-th clock signal CLKi. In the second period T2, the first node Q (j) is higher in level than the second node potential Vq2, the first output control node, i.e., the first node Q (j), controls the reception of the ith clock signal in the first output module 142, and controls the output and stop of the jth scan signal G (j) and the jth stage transfer signal C (j) under the control of the ith clock signal.

In the third period T3, the level of the first node Q (J) is pulled down by the first GDL unit GDL1 in the j+2th GOA unit outputting the j+4th level transmission signal C (j+4), the level of the j+4th level transmission signal C (j+4) is raised from the first scanning potential Vg1 to the first intermediate scanning potential Vga for a first preset period of time 0.5H, the potential of the first node Q (J) is lowered from the third node potential Vq3 to the second intermediate node potential Vqb for a first preset period of time 0.5H, and the voltage of the first node Q (J) is lowered from the second intermediate node potential Vqb to the first node potential Vq1 when the j+4th level transmission signal C (j+4) is raised from the first intermediate scanning potential Vga to the second scanning potential Vg 2. When the voltage of the first node Q (j) is lower than the second node potential Vq2, the twenty-first transistor T21 and the twenty-second transistor T22 in the output module 142 are turned off, i.e., the output module 142 controls the j-th scan signal G (j) to stop outputting.

In the first GDL unit, the voltage pull-down time point of the first node Q (j) is later than the pull-down time point of the i-th clock signal CLKi by a first preset time period of 0.5H, that is, after the i-th clock signal is pulled down from the second clock potential Vk2 to the first time Zhong Dianwei Vk1 and the first preset time period of 0.5H, the voltage of the first node Q (j) is completely pulled down to the first node potential Vq1.

Similarly, the third node Q (j+1) in the second GDL unit GDL2 and the output control nodes in the other GDL units in the scan driving circuit 12 also have the above-mentioned changes, which are not described in detail in this application.

By controlling the output waveform of the clock signal, the duration of the voltage of the output control node in the scanning signal output unit is longer than the duration of the clock signal in a frame image display period, namely the pull-down time of the output control node is later than the pull-down time of the clock signal, so that the clock signal is ensured to have sufficient time to control the output of the corresponding scanning signal, the problem of incomplete scanning signal output caused by rapid pull-down of the node voltage is avoided, the output stability of the scanning signal is improved, and the display effect is enhanced.

It is to be understood that the invention is not limited in its application to the examples described above, but is capable of modification and variation in light of the above teachings by those skilled in the art, and that all such modifications and variations are intended to be included within the scope of the appended claims.

Claims (10)

1. The scanning driving circuit comprises n scanning driving units and M clock signals which are sequentially arranged and cascaded, wherein n and M are integers larger than or equal to 1, each scanning driving unit comprises two scanning signal output subunits, the two scanning signal output subunits respectively receive the clock signals and respectively output one scanning signal under the control of the clock signals, and the scanning signals are used for being output to scanning lines in a display area and controlling pixel units correspondingly connected to the scanning lines to receive image display data so as to execute image display;

the display method is characterized in that in a frame of image display time period, the clock signal sequentially comprises a first intermediate clock potential and a second clock potential, wherein the first intermediate clock potential lasts for a first preset duration, the second clock potential lasts for a second preset duration, and the second clock potential is larger than the first intermediate clock potential.

2. The scan driving circuit according to claim 1, wherein the clock signal rises from a first clock potential to the first intermediate clock potential for the first preset period of time at a first time, and rises from the first intermediate clock potential to the second clock potential for a second preset period of time at a second time, the first intermediate clock potential being greater than the first clock potential.

3. The scan driving circuit according to claim 2, wherein the first intermediate clock potential is one-half of the second clock potential, and the second preset duration is seven times the first preset duration.

4. The scan driving circuit according to claim 2, wherein,

the clock signal is in the duration of the first intermediate clock potential, controls the scanning signal output subunit to output the scanning signal and the hierarchical signal with the first intermediate scanning potential, and lasts for the first preset duration;

and the clock signal is in the duration of the second clock potential, controls the scanning signal output subunit to output the scanning signal and the hierarchical signal with a second scanning potential, and lasts for the second preset duration, wherein the second scanning potential is larger than the first intermediate scanning potential.

5. The scan driving circuit according to claim 4, wherein a J-th one of the scan driving units includes a first scan signal output subunit and a second scan signal output subunit, J being 3-n, the first scan signal output subunit outputting a J-th level transmission signal and a J-th scan signal under the control of an i-th clock signal, the second scan signal output subunit outputting a j+1th level transmission signal and a j+1th scan signal under the control of an i+1th clock signal, the J-th level transmission signal and the j+1th level transmission signal being used to control output of the corresponding scan signal and the level transmission signal in the scan driving unit in cascade, wherein J = 2J-1, 1-i being < M.

6. The scan driving circuit according to claim 5, wherein the first scan signal output sub-unit includes a first output control node and a first output module, the first output control node being configured to control the first output module to receive the i-th clock signal and output the j-th scan signal and the j-th pass signal according to the i-th clock signal.

7. The scan driving circuit according to claim 6, wherein a first scan signal output subunit of a J-th one of the scan driving units receives a J-4 th level of the transfer signal output by a first scan signal output subunit of a J-2 th one of the scan driving units to control a voltage of a first output control node of a first scan signal output subunit of the J-th one of the scan driving units to rise from a first node potential to a first intermediate node potential, and after the first preset period of time, to rise from the first intermediate node potential to a second node potential for the second preset period of time, the first output control node controls the first output module to receive the ith clock signal when the voltage of the first output control node is greater than or equal to the second node potential.

8. The scan driving circuit according to claim 7, wherein in the J-th one of the scan driving units, the i-th clock signal rises from the first clock potential to the second intermediate clock potential for the first preset period of time at the first time, the voltage of the first output control node rises from the second node potential to the second intermediate node potential for the first preset period of time under control of the i-th clock signal,

the ith clock signal rises from the first intermediate clock potential to the second clock potential for the second preset time period at a second moment, and the voltage of the first output control node rises from the second intermediate node potential to the third node potential for the second preset time period under the control of the ith clock signal.

9. The scan driving circuit according to claim 8, wherein in a third period, a voltage of the j+4th stage transmission signal rises from a first scan potential to the first intermediate scan potential for the first preset period, and a voltage of the first output control node in a first scan signal output subunit in the J-th one of the scan driving units falls from the third node potential to the second intermediate node potential for the first preset period under control of the j+4th stage transmission signal;

The j+4 stage transmission signal rises from the first intermediate scanning potential to the second scanning potential, and the voltage of the first output control node in the first scanning signal output subunit in the J-th scanning driving unit drops from the second intermediate node potential to the first node potential.

10. A display panel, comprising the scan driving circuit, the data driving circuit and the display control circuit according to any one of claims 1 to 9, wherein the display control circuit receives an original data signal according to an external signal source and outputs a source output control signal and a gate output control signal respectively, and the data driving circuit controls the pixel unit to display an image according to the source output control signal and the scan driving circuit according to the gate output control signal.