CN114299893B

CN114299893B - Scanning driving circuit, array substrate and display terminal

Info

Publication number: CN114299893B
Application number: CN202111679721.6A
Authority: CN
Inventors: 金秉勋; 卢昭阳; 曹尚操; 田尚益; 李荣荣
Original assignee: HKC Co Ltd; Changsha HKC Optoelectronics Co Ltd
Current assignee: HKC Co Ltd; Changsha HKC Optoelectronics Co Ltd
Priority date: 2021-12-31
Filing date: 2021-12-31
Publication date: 2023-06-23
Anticipated expiration: 2041-12-31
Also published as: CN114299893A

Abstract

The embodiment of the application discloses a scanning driving circuit with accurate scanning signal output, which comprises n scanning driving units which are sequentially arranged and cascaded, wherein each scanning driving unit is used for outputting two scanning signals at preset intervals. Each scan driving unit comprises two pull-down time adjusting modules for respectively adjusting the same time from outputting the scan signal to stopping outputting the scan signal at the scan signal output end. The voltage drop time of the two scanning signals output by each scanning driving unit is adjusted, so that the afterimage phenomenon during image display is reduced, and the image display effect is improved. The embodiment of the application also discloses an array substrate and a display terminal comprising the scanning driving circuit.

Description

Scanning driving circuit, array substrate and display terminal

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a scan driving circuit, an array substrate, and a display terminal applied in a display panel.

Background

Currently, the liquid crystal display panel mostly adopts an array substrate gate driving (Gate Driver on Array, GOA) technology, and the GOA technology utilizes a thin film transistor (Thin Film Transistor, TFT) liquid crystal display array process to manufacture a gate scanning driving circuit on a thin film transistor array substrate so as to realize a progressive scanning driving technology, and has the advantages of reducing production cost and realizing narrow frame of the panel.

Currently, in cascaded GOA units, one GOA unit may output two or more of the hierarchical signals and the scan signals under the control of a Clock signal (CLK). However, since the clock signal is performed at a certain timing, there is a certain time delay between the plurality of stage transmission signals and the scan signal outputted from one GOA unit, and thus the accuracy of the scan signal output is poor, resulting in poor image display effect.

Disclosure of Invention

In view of the above-mentioned shortcomings in the prior art, the present application provides a scan driving circuit, an array substrate and a display terminal with a better signal synchronization effect.

The application provides a scanning driving circuit, which comprises n scanning driving units which are sequentially arranged and cascaded, wherein each scanning driving unit is used for outputting two scanning signals with preset time intervals. Each scanning driving unit comprises two pull-down time adjusting modules which are respectively connected with two scanning signal output ends, and the two pull-down time adjusting modules are used for respectively adjusting the same time from outputting the scanning signal to stopping outputting the scanning signal by the scanning signal output ends.

Optionally, the J-th scan driving unit is any one of the first scan driving circuit and the second scan driving circuit, and the two GDL circuits included in any one scan driving unit are the first GDL circuit and the second GDL circuit respectively. The first GDL circuit is used for receiving the j-4 th level transmission signal, outputting the j-th level transmission signal and outputting the j-th level scanning signal from the scanning signal output end of the first GDL circuit, wherein j is more than or equal to 5 and less than or equal to 2n. The jth stage signal is used for controlling the first GDL circuit in the J+2 stage scanning driving unit to output the jth+4 stage signal and the jth+4 stage scanning signal of the first potential, and simultaneously controlling the first GDL circuit in the J-2 stage scanning driving unit to output the jth-4 stage signal and stopping outputting the jth-4 stage scanning signal of the second potential. The second GDL circuit is used for receiving the j-3 th level transmission signal, outputting the j+1 th level transmission signal and outputting the j+1 th level scanning signal from the scanning signal output end of the second GDL circuit. The j+1th stage signal is used for controlling the j+5th stage signal and the j+5th stage scanning signal of the first potential output by the second GDL circuit in the J+2th stage scanning driving unit, and simultaneously controlling the J-3 th stage signal and the J-3 th stage scanning signal of the second potential output by the second GDL circuit in the J-2 th stage scanning driving unit.

Optionally, the first GDL circuit includes a first pull-down time adjustment module, a first pull-up module, a first pull-down module, a first node, and a second node. The first pull-down time adjustment module is electrically connected to the first node and the output end of the j-th stage scanning signal, the first pull-up module is connected to the first node and the output end of the j-th stage scanning signal, and the first pull-down module is connected to the second node and the first pull-down time adjustment module. When the first node is at the first potential, the first pull-up module is controlled to output a scanning signal from the output end of the j-th stage scanning signal. When the first node receives a pull-down signal with a second potential at a first moment, the second node is controlled to have the first potential, and the first potential of the second node controls the first pull-down module to output the second potential to the scanning signal output end. The first pull-down time adjustment module is used for controlling the voltage of the first node to change from a first potential to a second potential in a first period after the first time begins, and the first pull-up module stops outputting the scanning signal when the first node is at the second potential.

Optionally, the second GDL circuit includes a second pull-down time adjustment module, a second pull-up module, a second pull-down module, a third node, and a fourth node. The second pull-down time adjusting module is electrically connected to the third node and the output end of the j+1th stage scanning signal, the second pull-up module is connected to the third node and the output end of the j+1th stage scanning signal, and the second pull-down module is connected to the fourth node and the second pull-down time adjusting module. When the third node is at the first potential, the second pull-up module is controlled to output a scanning signal from the output end of the j+1th stage scanning signal. When the third node receives the pull-down signal with the second potential at the third moment, the fourth node is controlled to have the first potential, and the first potential of the fourth node controls the second pull-down module to output the second potential to the scanning signal output end. The second pull-down time adjustment module is used for controlling the voltage of the third node to change from the first potential to the second potential in a second period from the third moment, and the second pull-up module stops outputting the scanning signal when the third node is at the second potential.

Optionally, the first GDL circuit further includes a second pull-down control module, and the second GDL circuit further includes a fourth pull-down control module. The second pull-down control module is electrically connected to the first node and the second node, and pulls up the voltage of the second node to the first potential when the first node receives a pull-down signal of the second potential at the first time. The fourth pull-down control module is electrically connected to the third node and the fourth node, and pulls up the voltage of the second node to the first potential when the third node receives a pull-down signal of the second potential at the second moment.

Optionally, the first pull-down time adjustment module includes a first capacitor, the second pull-down time adjustment module includes a second capacitor, and a ratio of a capacitance value of the first capacitor to a capacitance value of the second capacitor is in a range of 0.3-0.7.

Optionally, the first GDL circuit further includes a first pull-up control module, a first pull-down control module, and a first pull-down maintenance module. The first pull-up control module is used for pulling up the voltage of the first node to a first potential, and the first pull-down control module is used for pulling down the voltage of the first node to a second potential. The first pull-down maintaining module is electrically connected to the first node, the second node and the third node. When the first node is at the first potential, the second node voltage is pulled down to the second potential, and when the third node is at the first potential, the second node is controlled to stop receiving the power supply voltage.

Optionally, the second GDL circuit further includes a second pull-up control module, a third pull-down control module, and a second pull-down maintenance module. The second pull-up control module and the third pull-down control module are electrically connected to the third node, the second pull-up control module is used for pulling up the third node voltage to the first potential, and the third pull-down control module is used for pulling down the third node voltage to the second potential. The second pull-down maintaining module is electrically connected to the first node, the third node and the fourth node, and when the node voltage of the first node is the first potential, the fourth node is controlled to stop receiving the power supply voltage, and when the third node is the first potential, the fourth node is pulled down to the second potential.

Optionally, the application further provides an array substrate, including 2n scan lines, a plurality of pixel units arranged in an array, and a scan driving circuit according to any one of the foregoing, where the 2n scan lines are respectively connected to the n scan driving units, and respectively receive 2n scan signals from the n scan driving units in sequence, and the plurality of pixel units receive image data and display images under control of the 2n scan signals.

Optionally, the application further provides a display terminal, which comprises the array substrate.

Compared with the prior art, the scanning driving circuit provided by the application can effectively solve the afterimage phenomenon during image display by adjusting the voltage drop time of the two scanning signals output by each scanning driving unit, enhances the stability of the GDL circuit and improves the image display effect.

Drawings

In order to more clearly describe the technical scheme in the embodiments of the present application, the following will apply to the embodiments

The drawings that need to be used are briefly introduced, and it is apparent that the drawings in the following description are the present application

For one of ordinary skill in the art without undue burden

Further figures can be obtained from these figures.

FIG. 1 is a schematic side view of a display terminal according to an embodiment of the present application;

FIG. 2 is a schematic plan view of an array substrate in the display panel shown in FIG. 1;

fig. 3 is a schematic structural diagram of a scan driving circuit according to a first embodiment of the present application;

FIG. 4 is a schematic diagram of an equivalent circuit of the GOA unit in FIG. 3;

FIG. 5 is a schematic diagram showing a node voltage variation in the scan driving circuit shown in FIG. 4;

FIG. 6 is a schematic cross-sectional view of the first capacitor CB1 shown in FIG. 4;

fig. 7 is a top view of the first capacitor CB1 shown in fig. 6.

Detailed Description

In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. Preferred embodiments of the present application are shown in the accompanying drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

The following description of the embodiments refers to the accompanying drawings, which illustrate specific embodiments that can be used to practice the present application. The numbering of the components itself, e.g. "first", "second", etc., is used herein merely to distinguish between the described objects and does not have any sequential or technical meaning. The terms "coupled" and "connected," as used herein, are intended to encompass both direct and indirect coupling (coupling), unless otherwise indicated. Directional terms referred to in this application, such as "upper", "lower", "front", "rear", "left", "right", "inner", "outer", "side", etc., are merely directions referring to the attached drawings, and thus, directional terms are used for better, more clear description and understanding of the present application, rather than indicating or implying that the apparatus or element being referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present application.

In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; may be a mechanical connection; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context. It should be noted that the terms "first," "second," and the like in the description and claims of the present application and in the drawings are used for distinguishing between different objects and not for describing a particular sequential order.

Furthermore, the terms "comprises," "comprising," "includes," "including," "may be" or "including" as used in this application mean the presence of the corresponding function, operation, element, etc. disclosed, but not limited to other one or more additional functions, operations, elements, etc. Furthermore, the terms "comprises" or "comprising" mean that there is a corresponding feature, number, step, operation, element, component, or combination thereof disclosed in the specification, and that there is no intention to exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof. Furthermore, when describing embodiments of the present application, use of "may" means "one or more embodiments of the present application. Also, the term "exemplary" is intended to refer to an example or illustration.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

Referring to fig. 1, fig. 1 is a schematic side view of a display terminal 10 according to an embodiment of the present application. As shown in fig. 1, the display terminal 10 includes a display panel 11 and other components (not shown) including a power supply module, a signal processor module, a signal sensing module, and the like.

The display panel 11 includes a display area 11a for an image and a non-display area 11b. The display area 11a is used for performing image display, and the non-display area 11b is disposed around the display area 11a to provide other auxiliary components or modules. Specifically, the display panel 11 includes an array substrate 11c and an opposite substrate 11d, and a display medium layer 11e sandwiched between the array substrate 11c and the opposite substrate 11 d. In this embodiment, the display medium in the display medium layer is a Liquid Crystal (Liquid Crystal), that is, the display panel 11 in this embodiment is a Liquid Crystal display panel.

Fig. 2 is a schematic plan view of the array substrate 11c of the display panel 11 shown in fig. 1. As shown in fig. 2, the corresponding image display area 11a in the array substrate 11c includes a plurality of m×n Pixel units (pixels) P, m Data lines (Data lines) 120 and n Scan lines (Scan lines) 130 arranged in a matrix, where m and n are natural numbers greater than 1.

The display terminal 10 further includes a timing control circuit 101, a Data driving circuit (Data Driver) 102, and a Scan driving circuit (Scan Driver) 103 for driving the pixel units to display an image, corresponding to the non-display region 11b of the display panel 11, provided on the array substrate 11c.

The data driving circuit 102 is electrically connected to the plurality of data lines 120, and is configured to transmit the image data to be displayed to the plurality of pixel units P in the form of data voltages through the plurality of data lines 120.

The scan driving circuit 103 is electrically connected to the plurality of scan lines 130, and is configured to output a scan signal Gn through the plurality of scan lines 130 for controlling when the pixel unit P receives image data. The scan driving circuit 103 sequentially outputs scan signals G1, G2, … G3, …, gn from the plurality of scan lines 130 in the position arrangement order from the scan lines 130 in the scan period.

The timing control circuit 101 is electrically connected to the data driving circuit 102 and the scan driving circuit 103, and is used for controlling the operation timings of the data driving circuit 102 and the scan driving circuit 103, that is, outputting corresponding timing control signals to the scan driving circuit 103 and the data driving circuit 102, so as to control when to output corresponding scan signals Gn.

In this embodiment, the scan driving circuit 103 is disposed in the area corresponding to the array substrate 11c by using gate driving (GOA) technology and a process mode of the array substrate.

It will be appreciated that the display terminal 10 further includes other auxiliary circuits for jointly completing the display of the image, such as an image receiving processing circuit (Graphics Processing Unit, GPU), a power circuit, etc., which will not be described in detail in this embodiment.

Referring to fig. 3, fig. 3 is a schematic structural diagram of a scan driving circuit 103 according to a first embodiment of the present application, and for convenience of description, a scan driving unit is hereinafter denoted by a GOA unit. As shown in fig. 3, the scan driving circuit 103 includes a plurality of cascaded GOA units 140, eight clock signals CLKn (n=1, 2, …), a start signal STV, a reset signal R, a first low voltage level Vss1, and a second low voltage level Vss2.

In this embodiment, corresponding to 2160 scan lines, the plurality of cascaded GOA units 140 output corresponding scan signals, which may be denoted as G1-G2160, and the scan signals G1-G2160 are used to drive the scan lines of the pixels of the corresponding rows in the display array substrate. In other embodiments of the present application, the number of scan lines may be set according to the actual resolution, but is not limited thereto.

Specifically, each GOA unit 140 includes two stages of Gate Driver circuits (GDL), and each stage of GDL circuit outputs one scan signal, so that one GOA unit outputs two scan signals. For example, the first GOA unit GOA1 outputs the scan signals G1-G2, and the second GOA unit GOA2 outputs the scan signals G3-G4. In the present embodiment, the scan driving circuit 103 includes 1080 GOA units.

The cascaded GOA units 140 are specifically, any one GOA unit is cascaded with GOA units separated by 1 GOA unit, for example, a fourth GOA unit GOA4 is cascaded with a second GOA unit GOA2, and a third GOA unit GOA3 is cascaded with a first GOA unit GOA 1. The voltage of the node of the GOA cascaded thereto can be pulled down by the level signal output by each GOA unit, for example, the voltage of the node of the second GOA unit GOA2 can be pulled down by the level signal output by the fourth GOA unit GOA 4.

Eight clock signals CLKn (n=1, 2, …) are used to provide scan drive timing for the output drive signals of the GOA unit 140. In this embodiment, the timing control circuit 101 outputs the clock signal CLKn (n=1, 2, … 8) to provide the GOA unit 140 with the clock signal.

The start signal STV output by the timing control circuit 101 is an enable start signal of the first GOA unit GOA1, and the other GOA units 140 receive the enable start signal according to a cascade manner.

Please refer to fig. 4, which is an equivalent circuit diagram of the GOA unit 140 in fig. 3. As shown in FIG. 4, taking the J-th GOA unit as an example, 1.ltoreq.J.ltoreq.540. The J-th stage GOA unit includes two stages of GDL circuits, a first GDL circuit GDL1 and a second GDL circuit GDL2, respectively.

The first GDL circuit GDL1 includes a first pull-up control module 141, a first pull-up module 142, a first pull-down control module 143A, a second pull-down control module 143B, a first pull-down module 144, a first pull-down maintenance module 145, a first pull-down time adjustment module H1, a first node Q (j), and a second node Qb (j).

The second GDL circuit GDL2 includes a second pull-up control module 151, a second pull-up module 152, a third pull-down control module 153A, a fourth pull-down control module 153B, a second pull-down module 154, a second pull-down maintenance module 155, a second pull-down time adjustment module H2, a third node Q (j+1), a fourth node Qb (j+1), and a fifth node Qb (j+2).

In the first GDL circuit GDL1, the first pull-up control module 141 accesses the j-4 th level signal C (j-4) and the first node Q (j). The potential of the first node Q (j) is pulled up to the first potential by the j-4 th level of the pass signal C (j-4).

The first pull-up module 142 is connected to the mth clock signal CLK (m) (1+.m+. 8) and the first node Q (j), and is configured to output the jth level transmission signal C (j) and the jth scan signal G (j) when the potential of the first node Q (j) is the first potential under the control of the mth clock signal CLKm. The J-th stage transmission signal C (J) is used for controlling the j+4-th stage transmission signal C (j+4) and the j+4-th stage scanning signal G (j+4) of the first potential output by the first GDL circuit GDL1 in the j+2-th stage GOA unit, and simultaneously controlling the J-4-th stage transmission signal C (J-4) and the J-4-th stage scanning signal G (J-4) of the second potential output by the first GDL circuit GDL1 in the J-2-th stage GOA unit.

The first pull-down control module 143A accesses the j+4th stage transmission signal C (j+4), the first node Q (j), the second node Qb (j), the first reset signal R1, and the first voltage level Vss1. The potential of the first node Q (j) is pulled down to the second potential by the j+4-th level transmission signal C (j+4). The potentials of the first node Q (j) and the second node Qb (j) are pulled down by the first reset signal R1.

The second pull-down control module 143B is electrically connected to the power voltage VDD, the first node Q (j), and the second node Qb (j). The potential of the second node Qb (j) is pulled up to the first potential by the low level of the first node Q (j) and the power supply voltage VDD.

The first pull-down module 144 accesses an output terminal (not identified) of the j-th stage transmission signal C (j), an output terminal (not identified) of the j-th scan signal G (j), the second node Qb (j), the first low voltage level Vss1, and the second low voltage level Vss2. When the second node Qb (j) is at the first potential, the j-th stage signal C (j) is connected to the first low voltage terminal (not identified) to receive the first low voltage potential Vss1, output the j-th stage signal C (j) having the second potential, and stop outputting the j-th scan signal G (j). Wherein the first low voltage potential Vss1 is equivalent to the second potential.

The first pull-down maintenance module 145A accesses the j-4 th level transmission signal C (j-4), the first node Q (j), the second node Qb (j), the third node Q (j+1), and the first voltage level Vss1. The first node Q (j) and the second node Qb (j) levels are maintained using the j-4 th level pass signal C (j-4). Specifically, when the first node Q (j) is at the first potential, the potential of the second node Qb (j) is pulled down to the first low-voltage potential Vss1, and the second potential state of the second node Qb (j) is maintained for a period in which the first node Q (j) is at the first potential. When the third node Q (j+1) is at the first potential, the second node Qb (j) is controlled to stop receiving the power supply voltage VDD, and the first potential state of the second node is maintained during a period when the third node Q (j+1) is at the first potential.

One end of the first pull-down time adjusting module H1 is electrically connected to the first node Q (j), and the other end is electrically connected to the output end of the jth scan signal G (j). For adjusting the voltage drop time of the j-th scan signal G (j).

Wherein the first potential is high level and the second potential is low level.

In the second GDL circuit GDL2, the second pull-up control module 151 is connected to the j-3 rd stage of signal C (j-3) and electrically connected to the third node Q (j+1). The potential of the third node Q (j+1) is pulled up to the first potential by the j-3 rd level transmission signal C (j-3).

The second pull-up module 152 accesses the m+1th clock signal CLK (m+1) and the third node Q (j+1). For outputting the j+1th stage transmission signal C (j+1) and the j+1th scanning signal G (j+1) when the potential of the third node Q (j+1) is the first potential under the control of the m+1th clock signal CLK (m+1). The j+1th stage transmission signal C (j+1) is used for controlling the j+5th stage transmission signal C (j+5) and the j+5th stage scanning signal G (j+5) of the first potential output by the second GDL circuit GDL2 in the J+2th stage GOA unit, and simultaneously controlling the J-3 th stage transmission signal C (J-3) and the J-3 th stage scanning signal G (J-3) of the second potential output by the second GDL circuit GDL2 in the J-2 th stage GOA unit.

The third pull-down control module 153A accesses the j+5 th stage transmission signal C (j+5), the third node Q (j+1), the fourth node Qb (j+1), the fifth node Qb (j+2), the second reset signal R2, and the first voltage level Vss1. The potential of the third node Q (j+1) is pulled down to the second potential using the j+5-th stage signal C (j+5). The potentials of the third node Q (j+1) and the fourth node Qb (j+1) are pulled down by the second reset signal R2. The fifth node Qb (j+2) is connected to the second node Qb (j), and when the second node Qb (j) is at the first potential, the fifth node Qb (j+2) becomes the first potential, and the third node Q (j+1) is pulled down to the first low voltage potential Vss1 by the third pull-down module 153A.

The fourth pull-down control module 153B is electrically connected to the power voltage VDD, the third node Q (j+1) and the fourth node Qb (j+1). The potential of the fourth node Qb (j+1) is pulled up to the first potential using the low level of the third node Q (j+1) and the power supply voltage VDD. The potentials of the third node Q (j+1) and the fourth node Qb (j+1) are pulled down by the first reset signal R2.

The second pull-down module 154 is connected to an output terminal (not identified) of the j+1th stage of the signal C (j+1), an output terminal (not identified) of the j+1th scan signal G (j+1), the fourth node Qb (j+1), the fifth node Qb (j+2), the first low voltage level Vss1, and the second low voltage level Vss2. When the fourth node Qb (j+1) is at the first potential, the j+1th stage signal C (j+1) is connected to the first low voltage terminal to receive the first voltage potential Vss1, and the j+1th stage signal C (j+1) having the second potential is output. And stops outputting the j+1th scan signal G (j+1). The fifth node Qb (j+2) is connected to the second node Qb (j), and when the second node Qb (j) is at the first potential, the fifth node Qb (j+2) is at the first potential, the output terminal of the j+1th stage scan signal C (j+1) is maintained at the first low voltage potential Vss1 by the second pull-down module 154, the output terminal of the j+1th stage scan signal G (j+1) is maintained at the second low voltage potential Vss2, and the voltage stability of the output terminal of the j+1th stage scan signal C (j+1) and the output terminal of the j+1th stage scan signal G (j+1) is enhanced.

The second pull-down maintenance module 155 accesses the j-4 th level transmission signal C (j-4), the first node Q (j), the third node Q (j+1), the fourth node Qb (j+1), and the first voltage level Vss1. The levels of the third node Q (j+1) and the fourth node Qb (j+1) are maintained by the j-4 th level transmission signal C (j-4). Specifically, when the j-4 level signaling is accessed, the third node Q (j+1) and the fourth node Qb (j+1) access the first low voltage terminal and receive the first low voltage potential Vss1, and the third node Q (j+1) and the fourth node Qb (j+1) maintain the second potential state during this period. When the first node Q (j) is at the first potential, the potential of the fourth node Qb (j+1) is pulled down to the first low-voltage potential Vss1, and the second potential state of the fourth node Qb (j+1) is maintained for a period in which the first node is at the first potential.

One end of the second pull-down time adjustment module H2 is electrically connected to the third node Q (j+1), and the other end is electrically connected to an output end (not identified) of the j+1th scan signal G (j+1). For adjusting the voltage drop time of the j+1th scan signal G (j+1).

Specifically, the first pull-up control module 141 includes an eleventh transistor T11. The gate and source of the eleventh transistor T11 are connected to the input terminal (not identified) of the j-4 th level signal C (j-4), and the drain is electrically connected to the first node Q (j).

The first pull-up module 142 includes a twenty-first transistor T21 and a twenty-second transistor T22. The source of the twenty-first transistor T21 is connected to the mth clock signal CLK (m), the gate is electrically connected to the first node Q (j), and the drain is electrically connected to the output terminal (not identified) of the jth stage of signal C (j). The twenty-second transistor T22 has a source connected to the mth clock signal CLK (m), a gate electrically connected to the first node Q (j), and a drain electrically connected to an output terminal (not identified) of the jth scan signal G (j).

The first pull-down control module 143A includes a thirty-first transistor T31, a thirty-second transistor T32, a thirty-third transistor T33, and a thirty-fourth transistor T34. The thirty-first transistor T31 has a gate connected to the first reset signal R1, a source electrically connected to the first node Q (j), and a drain electrically connected to the first low voltage terminal for receiving the first low voltage level Vss1. The thirty-second transistor T32 has a gate electrically connected to the second node Qb (j), a source electrically connected to the first node Q (j), and a drain electrically connected to the first low voltage terminal to receive the first low voltage potential Vss1. The thirty-third transistor T33 has a gate connected to the j+4th stage of the transmission signal C (j+4), a source electrically connected to the first node Q (j), and a drain electrically connected to the first low voltage terminal for receiving the first low voltage level Vss1. The thirty-fourth transistor T34 has a gate electrically connected to the fourth node Qb (j+1), a source electrically connected to the first node Q (j), and a drain electrically connected to the first low voltage terminal for receiving the first low voltage potential Vss1.

The second pull-down control module 143B includes a thirty-fifth transistor T35, a thirty-sixth transistor T36, and a thirty-seventh transistor T37. The source and gate of the thirty-fifth transistor T35 are electrically connected to the power voltage VDD, and the drain is electrically connected to the gate of the thirty-sixth transistor T36 and the source of the thirty-seventh transistor T37. The thirty-sixth transistor T36 has a source electrically connected to the power voltage VDD and a drain electrically connected to the second node Qb (j). The thirty-seventh transistor T37 has a gate electrically connected to the first node Q (j), and a drain electrically connected to the first low voltage terminal for receiving the first low voltage potential Vss1.

The first pull-down module 144 includes a forty-first transistor T41, a forty-second transistor T42, a forty-third transistor T43, and a forty-fourth transistor T44. The gate of the forty-first transistor T41 is electrically connected to the second node Qb (j), the source is connected to the output terminal of the j-th level signal C (j), and the drain is electrically connected to the first low voltage terminal to receive the first low voltage potential Vss1. The gate of the forty-second transistor T42 is electrically connected to the second node Qb (j), the source is connected to the output terminal of the j-th scan signal G (j), and the drain is electrically connected to the second low voltage terminal to receive the second low voltage level Vss2. The forty-third transistor T43 has a gate electrically connected to the fourth node Qb (j+1), a source connected to the output terminal of the j-th scan signal G (j), and a drain electrically connected to the second low voltage terminal for receiving the second low voltage level Vss2. The gate of the forty-fourth transistor T44 is electrically connected to the fourth node Qb (j+1), the source is connected to the output terminal of the j-th stage signal C (j), and the drain is electrically connected to the first low voltage terminal to receive the first low voltage potential Vss1.

The first pull-down maintaining module 145 includes a fifty-first transistor T51, a fifty-second transistor T52, and a thirteenth transistor T53. The fifty-first transistor T51 has a gate connected to the first node Q (j), a source electrically connected to the second node Qb (j), and a drain electrically connected to the first low voltage terminal for receiving the first low voltage level Vss1. The fifty-th transistor T52 has a gate connected to the input terminal (not identified) of the j-4 th stage signal C (j-4), a drain electrically connected to the first low voltage terminal for receiving the first low voltage potential Vss1, and a source electrically connected to the second node Qb (j). The fifty-third transistor T53 has a gate electrically connected to the third node Q (j+1), a source electrically connected to the drain of the thirty-fifth transistor T35, and a drain electrically connected to the first low voltage terminal for receiving the first low voltage level Vss1.

The first pull-down time adjusting unit H1 includes a first capacitor CB1, one end of the first capacitor CB1 is electrically connected to the first node Q (j), and the other end is electrically connected to the output end of the jth scan signal G (j).

The second pull-up control module 151 includes a sixty-one transistor T61. The gate and source of the sixty-first transistor T61 are connected to the input terminal (not identified) of the j-3 rd stage signaling C (j-3), and the drain is electrically connected to the third node Q (j+1).

The second pull-up module 152 includes a seventy-first transistor T71 and a seventy-second transistor T72. The source of the seventeenth transistor T71 is connected to the m+1th clock signal CLK (m+1), the gate is electrically connected to the third node Q (j+1), and the drain is electrically connected to the output terminal of the j+1th stage signal C (j+1). The seventy-second transistor T72 has a source connected to the (m+1) th clock signal CLK (m+1), a gate electrically connected to the third node Q (j+1), and a drain electrically connected to the output of the (j+1) th scan signal G (j+1).

The third pull-down control module 153A includes an eighty-one transistor T81, an eighth twelve transistor T82, an eighty-thirteen transistor T83, and an eighty-four transistor T84. The eighth transistor T81 has a gate connected to the second reset signal R2, a source electrically connected to the third node Q (j+1), and a drain electrically connected to the first low voltage terminal for receiving the first low voltage potential Vss1. The eighth transistor T82 has a gate electrically connected to the fourth node Qb (j+1), a source electrically connected to the third node Q (j+1), and a drain electrically connected to the first low voltage terminal for receiving the first low voltage level Vss1. The eighth transistor T83 has a gate connected to the input terminal (not identified) of the j+5 th stage of signal C (j+5), a source electrically connected to the third node Q (j+1), and a drain electrically connected to the first low voltage terminal for receiving the first low voltage level Vss1. The eighty-fourth transistor T84 has a gate electrically connected to the fifth node Qb (j+2), a source electrically connected to the third node Q (j+1), and a drain electrically connected to the first low voltage terminal for receiving the first low voltage level Vss1.

The fourth pull-down control module 153B includes an eighty-five transistor T85, an eighty-six transistor T86, and an eighty-seven transistor T87. The source and gate of the eighty-fifth transistor T85 are electrically connected to the power voltage VDD, and the drain is electrically connected to the gate of the eighty-sixth transistor T86 and the source of the eighty-seventh transistor T87. The eighth transistor T86 has a source electrically connected to the power voltage VDD, and a drain electrically connected to the fourth node Qb (j+1). The eighth transistor T87 has a gate electrically connected to the third node Q (j+1), and a drain electrically connected to the first low voltage terminal for receiving the first low voltage level Vss1.

The second pull-down module 154 includes a nineteenth transistor T91, a nineteenth transistor T92, a nineteenth transistor T93, and a nineteenth transistor T94. The gate of the nineteenth transistor T91 is electrically connected to the fourth node Qb (j+1), the source is connected to the output terminal of the j+1th level signal C (j+1), and the drain is electrically connected to the first low voltage terminal to receive the first low voltage level Vss1. The gate of the ninety transistor T92 is electrically connected to the fourth node Qb (j+1), the source is connected to the output terminal of the j+1th scan signal G (j+1), and the drain is electrically connected to the second low voltage terminal to receive the second low voltage level Vss2. The nineteenth transistor T93 has a gate electrically connected to the fifth node Qb (j+2), a source electrically connected to the output terminal of the j+1th scan signal G (j+1), and a drain electrically connected to the second voltage level Vss2. The ninety-fourth transistor T94 has a gate electrically connected to the fifth node Qb (j+2), a source connected to the output terminal of the j+1st stage signal C (j+1), and a drain electrically connected to the first low voltage terminal for receiving the first low voltage level Vss2.

The second pull-down maintenance module 155 includes a ninety-seventh transistor T97, a ninety-eighth transistor T98, and a ninety-ninth transistor T99. The ninety-seventh transistor T97 has a gate electrically connected to the third node Q (j+1), a source electrically connected to the fourth node Qb (j+1), and a drain electrically connected to the first low voltage terminal for receiving the first low voltage level Vss1. The nineteenth transistor T98 has a gate connected to the input terminal of the j-4 th stage of the signal C (j-4), a source electrically connected to the drain of the fourth node Qb (j+1), and a gate electrically connected to the first low voltage terminal for receiving the first low voltage level Vss1. The nineteenth transistor T99 has a gate electrically connected to the first node Q (j), a source electrically connected to the drain of the eighty-fifth transistor T85, and a drain electrically connected to the first low voltage terminal for receiving the first low voltage level Vss1.

The second pull-down time adjusting unit H2 includes a second capacitor CB2, wherein one end of the second capacitor CB2 is electrically connected to the third node Q (j+1), and the other end is electrically connected to the output end of the j+1th scan signal G (j+1).

In this embodiment, the transistor in the GOA unit 140 is an N-type oxide thin film transistor, specifically, may be a zinc oxide (ZnO) TFT, a GaZnO TFT, an InZnO TFT, an AlZnO TFT, or an indium gallium zinc oxide TFT (InGaZnO TFT, IGZO TFT), which is not limited in this application.

Referring to fig. 4-5, fig. 5 is a schematic diagram of node voltage change in the GOA unit shown in fig. 4, and as shown in fig. 5, when the first node Q (j) receives a pull-down signal with a second potential at a first time t1, the voltage of the second node Qb (j) becomes a first potential, and the first potential of the second node Qb (j) controls the first pull-down module 144 to output the second potential to the scan signal output terminal. The pull-down signal is output by the j+4-th stage signaling control output by the cascade scanning driving unit J+2.

The first pull-down time adjustment module H1 controls the scan signal output terminal to control the voltage of the first node Q (j) to change from the first potential to the second potential in the first period T1 from the first time T1 to the second time T2, and the first pull-up module 142 stops outputting the scan signal when the first node Q (j) is at the second potential. Wherein, the voltage of the first node Q (j) is gradually, continuously and gently changed from the first potential to the second potential.

When the third node Q (j+1) is at the first potential, the second pull-up module 152 is controlled to output the j+1-th scan signal from the output terminal of the j+1-th scan signal.

When the third node Q (j+1) receives the pull-down signal of the second potential at the second time t2, the voltage of the fourth node Qb (j+1) becomes the first potential, and the first potential of the fourth node Qb (j+1) controls the second pull-down module 154 to output the second potential to the scan signal output terminal. The pull-down signal is output by the j+5-th stage signaling control output by the cascade scanning driving unit J+2.

The second pull-down time adjustment module H2 controls the scan signal output terminal to change the voltage of the third node Q (j+1) from the first potential to the second potential in the second period T2 from the third time T3 to the fourth time T4, and the second pull-up module 152 stops outputting the j+1-th stage scan signal when the third node Q (j+1) is at the second potential. Wherein, the voltage of the third node Q (j+1) is gradually, continuously and gently changed from the first potential to the second potential.

Referring to fig. 6, a schematic cross-sectional view of the first capacitor CB1 in fig. 4 is shown, where, as shown in fig. 6, the first capacitor CB1 includes a glass substrate GLS, a first metal layer M1, a gate insulation GI, and a second metal layer M2. The first metal layer M1 is deposited and patterned on the first surface GLS-1 of the glass substrate GLS, the gate insulating layer GI is deposited and patterned on the first surface M1-1 of the first metal layer M1, and the second metal layer M2 is deposited and patterned on the first surface GI-1 of the gate insulating layer GI. A capacitance is formed between the first metal layer M1 and the second metal layer M2.

Referring to fig. 6 to fig. 7, fig. 7 is a top view of the first capacitor CB 1. As shown in fig. 7, the area of the first surface M1-1 (fig. 6) of the first metal layer M1 is larger than the area of the second surface M2-2 (fig. 6) of the second metal layer M2. The capacitance of the first capacitor CB1 is related to the area of the first metal layer M1 and the second metal layer M2 covering the gate insulating layer GI.

Specifically, the capacitance of the first capacitor CB1 is determined by the common area of the first surface M1-1 of the first metal layer M1 and the second surface M2-2 of the second metal layer M2 covered on the gate insulating layer GI, that is, the area of the second metal layer M2 along the first direction F1 covered on the first metal layer M1, and the area of the first metal layer M1 is larger than the area of the second metal layer M2, so that the capacitance of the first capacitor CB1 is determined by the area of the second surface M2-2 of the second metal layer M2, in other words, the capacitance of the first capacitor CB1 can be controlled by controlling the area of the second surface M2-2 of the second metal layer M2. The second capacitor CB2 is fabricated in the same manner and the same principle as the first capacitor CB1, and thus will not be described again.

By using the charge-discharge principle of the capacitor, the voltage drop time of the output ends of the jth stage scan signal G (j) and the jth+1th stage scan signal G (j+1) can be adjusted for the first period T1 and the second period T2 by setting the capacitance values of the first capacitor CB1 in the first pull-down time adjustment unit H1 and the second capacitor CB2 in the second pull-down time adjustment unit H2.

Let the j-th stage scan signal G (j) be an odd-numbered stage scan signal, the j+1-th stage scan signal G (j+1) be an even-numbered stage scan signal. Because of the actual wiring, the wiring of the first node Q (j) in the odd-stage GDL circuit is longer than the wiring of the third node Q (j+1) in the even-stage GDL circuit, so the node voltage drop time of the first node Q (j) and the third node Q (j+1) is different.

The falling time of the scan signal G (j) and the scan signal G (j+1) are controlled by the node voltages of the first node Q (j) and the third node Q (j+1), so that the voltage falling time of the two-stage scan signals output by the two-stage GDL circuits in the same GOA unit is different, i.e., the first period T1 and the second period T2 are different.

In this embodiment, the capacitance values of the first capacitor CB1 and the second capacitor CB2 are adjusted, so as to adjust the voltage falling time after the j-th scan signal G (j) and the j+1-th scan signal G (j+1) are output, so that the falling time of the two-stage scan signals is the same, that is, the first period T1 and the second period T2 are the same. When the impedances RC1 and RC2 of the first capacitor CB1 and the second capacitor CB2 are equal, R _Q(j) ×CB1= R _Q(j+1) ×CB2，R _Q(j) Is the impedance of the first node Q (j), R _Q(j+1) Is the impedance of the third node Q (j+1). So when R is _Q(j) ＞R _Q(j+1) And when CB1 is smaller than CB2, performing simulation experiments based on the CB1 is smaller than CB 2.

Simulation experiments show that when the ratio of the capacitance value of the first capacitor CB1 to the capacitance value of the second capacitor CB2 is between 0.3 and 0.7, the phase difference between the first period T1 and the second period T2 is smaller. The capacitance value of the first capacitor CB1 is set to 3.36pf, the capacitance value of the second capacitor CB2 is set to 5.6pf, the capacitance ratio CB1/CB2 of the first capacitor CB1 and the second capacitor CB2 is 0.6, and at this time, the voltage drop time after the j-th level scan signal G (j) and the j+1th level scan signal G (j+1) are output is the same, and is 2.33us, that is, the capacitance ratio CB1/CB2 of the first capacitor CB1 and the second capacitor CB2 is optimal when 0.6. Of course, the capacitance value of the first capacitor CB1 and the second capacitor CB2 may be set to other values, which is not limited in this application.

In this embodiment, by setting the first pull-down time adjustment module H1 and the second pull-down time adjustment module H2 in the first GDL circuit GDL1 and the second GDL circuit GDL2, the output voltages of the jth stage scan signal G (j) and the jth+1st stage scan signal G (j+1) drop in the same time, so as to enhance the stability of the GDL circuits, enhance the display panel 11, reduce the ghost phenomenon during image display, and enhance the image display effect.

It is to be understood that the invention is not limited in its application to the examples described above, but is capable of modification and variation in light of the above teachings by those skilled in the art, and that all such modifications and variations are intended to be included within the scope of the appended claims.

Claims

1. A scan driving circuit includes n scan driving units sequentially arranged and cascaded, each of the scan driving units for outputting scan signals at intervals of two preset times, characterized in that,

each scanning driving unit comprises two pull-down time adjustment modules which are respectively connected with two scanning signal output ends, and the two pull-down time adjustment modules are used for respectively adjusting the same time from the output of the scanning signal output ends to the stop of the output of the scanning signals;

The J-th scanning driving unit comprises a first GDL circuit, wherein J is more than or equal to 1 and less than or equal to n, and the first GDL circuit comprises a first pull-down time adjusting module, a first pull-up module, a first pull-down module, a first node and a second node;

the first pull-down time adjustment module is electrically connected to the first node and the output end of the jth stage scanning signal, wherein j is more than or equal to 5 and less than or equal to 2n, the first pull-up module is connected to the first node and the output end of the jth stage scanning signal, and the first pull-down module is connected to the second node and the first pull-down time adjustment module;

when the first node is at a first potential, the first pull-up module is controlled to output the scanning signal from the output end of the j-th stage scanning signal,

when the first node receives a pull-down signal with a second potential at a first moment, controlling the second node to have the first potential, and controlling the first pull-down module to output the second potential to the scanning signal output end by the first potential of the second node;

the first pull-down time adjustment module is configured to control, in a first period from the first time, the voltage of the first node to change from the first potential to the second potential, and when the first node is the second potential, the first pull-up module stops outputting the scan signal.

2. The scan driving circuit according to claim 1, wherein,

the J-th scan driving unit further includes a second GDL circuit;

the first GDL circuit is used for receiving a J-4 th level transmission signal, outputting the J-4 th level transmission signal and outputting a J-th level scanning signal from a scanning signal output end of the first GDL circuit, wherein the J-th level transmission signal is used for controlling the j+4 th level transmission signal and the j+4 th level scanning signal of a first potential output by the first GDL circuit in a J+2-th level scanning driving unit, and simultaneously controlling the J-4 th level transmission signal and the J-4 th level scanning signal of a second potential output by the first GDL circuit in the J-2-th level scanning driving unit;

the second GDL circuit is used for receiving the J-3 th level transmission signal, outputting the j+1 th level transmission signal and outputting the j+1 th level scanning signal from the scanning signal output end of the second GDL circuit, wherein the j+1 th level transmission signal is used for controlling the j+5 th level transmission signal and the j+5 th level scanning signal of the first potential to be output by the second GDL circuit in the J+2 th level scanning driving unit, and simultaneously controlling the J-3 th level transmission signal of the second potential to be output by the second GDL circuit in the J-2 th level scanning driving unit and stopping outputting the J-3 th level scanning signal.

3. The scan drive circuit of claim 2, wherein the second GDL circuit comprises a second pull-down time adjustment module, a second pull-up module, a second pull-down module, a third node, and a fourth node;

the second pull-down time adjustment module is electrically connected to the third node and the output end of the j+1th stage scanning signal, the second pull-up module is connected to the third node and the output end of the j+1th stage scanning signal, and the second pull-down module is connected to the fourth node and the second pull-down time adjustment module;

when the third node is at the first potential, the second pull-up module is controlled to output the scanning signal from the output end of the j+1th stage scanning signal,

when the third node receives a pull-down signal with the second potential at a third moment, controlling the fourth node to have the first potential, and controlling the second pull-down module to output the second potential to the scanning signal output end by the first potential of the fourth node;

the second pull-down time adjustment module is configured to control, in a second period from the third time, the voltage of the third node to change from the first potential to the second potential, and the second pull-up module stops outputting the scan signal when the third node is at the second potential.

4. The scan driving circuit according to claim 3, wherein the first GDL circuit further comprises a second pull-down control module, the second GDL circuit further comprises a fourth pull-down control module,

the second pull-down control module is electrically connected to the first node and the second node, and pulls up the voltage of the second node to the first potential when the first node receives a pull-down signal of the second potential at the first moment;

the fourth pull-down control module is electrically connected to the third node and the fourth node, and pulls up the voltage of the second node to the first potential when the third node receives the pull-down signal of the second potential at the second moment.

5. The scan driving circuit according to claim 3, wherein,

the first pull-down time adjustment module comprises a first capacitor, the second pull-down time adjustment module comprises a second capacitor, and the ratio of the capacitance value of the first capacitor to the capacitance value of the second capacitor is in the range of 0.3-0.7.

6. The scan driving circuit according to claim 4, wherein,

The first GDL circuit further comprises a first pull-up control module, a first pull-down control module and a first pull-down maintenance module, wherein the first pull-up control module and the first pull-down control module are electrically connected to the first node, the first pull-up control module is used for pulling up the first node voltage to the first potential, and the first pull-down control module is used for pulling down the first node voltage to the second potential;

the first pull-down maintaining module is electrically connected to the first node, the second node and the third node, and is used for pulling down the voltage of the second node to the second potential when the first node is at the first potential and controlling the second node to stop receiving the power supply voltage when the third node is at the first potential.

7. The scan driving circuit according to claim 6, wherein,

the second GDL circuit further comprises a second pull-up control module, a third pull-down control module and a second pull-down maintenance module, wherein the second pull-up control module and the third pull-down control module are electrically connected to the third node, the second pull-up control module is used for pulling up the third node voltage to the first potential, and the third pull-down control module is used for pulling down the third node voltage to the second potential;

The second pull-down maintaining module is electrically connected to the first node, the third node and the fourth node, and is used for controlling the fourth node to stop receiving the power supply voltage when the node voltage of the first node is the first potential, and pulling down the fourth node to the second potential when the node voltage of the third node is the first potential.

8. An array substrate, characterized in that the array substrate comprises 2n scan lines, a plurality of pixel units arranged in an array, and the scan driving circuit according to any one of claims 1 to 7, the 2n scan lines are respectively connected to the n scan driving units, and respectively receive 2n scan signals from the n scan driving units in turn, and the plurality of pixel units receive image data and display images under the control of the 2n scan signals.

9. A display terminal, wherein the display terminal comprises the array substrate of claim 8.