KR102453948B1 - Thin film transistor and display divice having the same - Google Patents

Abstract

The thin film transistor substrate according to the present invention includes a first transistor and a second transistor. The first transistor includes a first source electrode and a first drain electrode disposed on the buffer layer. The first gate insulating layer covers the first source electrode and the first drain electrode. A gate electrode is disposed on the first gate insulating layer. The second transistor shares a gate electrode with the first transistor. The second gate insulating layer covers the gate electrode. A second source electrode and a second drain electrode are disposed on the second gate insulating layer.

Description

A thin film transistor substrate and a display device having the same

The present invention relates to a thin film transistor substrate, and more particularly, to a thin film transistor substrate capable of reducing the size while maintaining the characteristics of the thin film transistor and a display device having the same.

Thin film transistors are widely used in various semiconductor devices. The size and performance of the thin film transistor are closely related to the size and performance of the semiconductor device. The amount of current passing through the thin film transistor is proportional to the channel width and inversely proportional to the channel length. Therefore, in order to reduce the size of the thin film transistor, it is necessary to increase the channel width, decrease the channel length, or decrease the channel length while increasing the channel width under the same conditions.

Thin film transistors are typically widely used in flat panel display devices. The flat panel display includes a liquid crystal display device (LCD), a plasma display panel (PDP), an organic light emitting display device (OLED), and a field emission display device (Field Emission Display Device). : FED), and Electrophoretic Display Device (ED). In a flat panel display, data lines and gate lines are arranged to be perpendicular to each other, and pixels are arranged in a matrix form.

The thin film transistor is disposed at the intersection of the data line and the gate line in the pixel, is turned on by a gate pulse provided to the gate line, and supplies the data voltage provided to the data line to the pixels. Since the thin film transistor disposed in the pixel blocks light, it is also a factor of lowering the luminance of the display panel. Therefore, in order to improve luminance degradation, the size of the thin film transistor should be reduced while maintaining the same efficiency.

In addition, the thin film transistor is also used for the shift register of the display panel. The shift register for outputting the gate pulse provided to the gate line is sometimes implemented in the form of a gate in panel (GIP) formed of a combination of thin film transistors in a pixel area of the display panel and adjacent to the pixel area. Since the GIP-type shift register is disposed on the bezel of the display panel, it is necessary to reduce the size of the shift register in order to reduce the bezel. That is, as a part of reducing the bezel, a method for reducing the size of the thin film transistors may be sought.

SUMMARY OF THE INVENTION The present invention is to solve the above problems, and to provide a thin film transistor substrate capable of maintaining performance while reducing a planar area and a display device having the same.

The thin film transistor substrate according to the present invention includes a first transistor and a second transistor. The first transistor includes a first source electrode and a first drain electrode disposed on the buffer layer. The first gate insulating layer covers the first source electrode and the first drain electrode. A gate electrode is disposed on the first gate insulating layer. The second transistor shares a gate electrode with the first transistor. The second gate insulating layer covers the gate electrode. A second source electrode and a second drain electrode are disposed on the second gate insulating layer.

In the thin film transistor substrate of the present invention, since two transistors sharing a gate electrode are vertically disposed, an area in which the two transistors are disposed can be reduced.

Alternatively, the present invention can improve the performance without increasing the size of the thin film transistor.

1 is a plan view of the thin film transistor shown in FIG.
Fig. 2 is a cross-sectional view taken along line II' of Fig. 1;
3 is a view showing a display device including a thin film transistor substrate according to the present invention.
FIG. 4 is a view showing a shift register shown in FIG. 3;
FIG. 5 is a view showing the stage shown in FIG. 4;
6 is an equivalent circuit diagram illustrating another embodiment of the pull-up transistor shown in FIG. 5;
7 is a cross-sectional view illustrating a structure of a source electrode of each of the first and second transistors shown in FIG. 6 ;
8 is a view showing a display device according to another embodiment of the present invention.
9 is an equivalent circuit diagram of the display panel shown in FIG. 8;
FIG. 10 is a view showing the pixel area shown in FIG. 9;
11 is a cross-sectional view illustrating a cross-sectional view taken along line III-III' shown in FIG. 10;

Hereinafter, preferred embodiments according to the present invention will be described in detail with a focus on a liquid crystal display device with reference to the accompanying drawings. Like reference numerals refer to substantially identical elements throughout. In the following description, if it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted. Names of components used in the following description are selected in consideration of ease of writing the specification, and may be different from the names of actual products.

FIG. 1 is a plan view showing a thin film transistor substrate according to the present invention, and FIG. 2 is a cross-sectional view showing a cross-section taken along line I-I' of FIG. 1 .

1 and 2, the thin film transistor according to the present invention includes a first transistor (T1) and a second transistor (T2) disposed perpendicular to each other. The first transistor T1 and the second transistor T2 share a gate electrode G, and the region of the first transistor T1 and the region of the second transistor T2 at least partially overlap in plan view.

Each of the first drain electrode D1 and the first source electrode S1 of the first transistor T1 may have a finger structure. Similarly, the second drain electrode D2 and the second source electrode S2 of the second transistor T2 may each have a finger structure. Although FIG. 1 shows an embodiment in which the first drain electrode D1 has a width and a length greater than that of the second drain electrode D2, the second drain electrode D2 has a width and a length greater than that of the first drain electrode D1. may be formed to be large, and the width and length of the first drain electrode D1 and the second drain electrode D2 may be formed to be the same as each other. Similarly, the width and length of the first source electrode S1 and the second source electrode S2 are not limited to those shown in FIG. 1 .

The first transistor area TA1 and the second transistor area TA2 at least partially overlap. The first transistor area TA1 means a planar area occupied by the first transistor T1 on the substrate SUB, and the second transistor area TA2 is a planar area occupied by the second transistor T2 on the substrate SUB. means

The cross-sectional structures of the first transistor T1 and the second transistor T2 are as follows.

The first transistor T1 is positioned on the substrate SUB, and the second transistor T2 is positioned on the first transistor T1 . The first transistor T1 includes a first drain electrode D1 , a first source electrode S1 , and a gate electrode G . The second transistor T2 includes a second drain electrode D2 , a second source electrode S2 , and a gate electrode G .

A buffer layer BUF is positioned on the substrate SUB. The buffer layer (buffer) may use an oxide film (SiO2).

The first drain electrode D1 and the first source electrode S1 are positioned on the buffer layer BUF. The first drain electrode D1 and the first source electrode S1 are formed of aluminum (Al), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), gold (Au), and silver (Ag). , tungsten (W) or an alloy thereof may be formed of a conductive metal material selected from the group consisting of.

The first semiconductor layer ACT1 is disposed on the first drain electrode D1 and the first source electrode S1 . The first semiconductor layer ACT1 may be formed using amorphous silicon (a-Si), low temperature poly silicon (LTPS), an oxide semiconductor, or the like.

The first gate insulating layer GI1 is disposed to cover the first semiconductor layer ACT1 . The first gate insulating layer GI1 may be formed using a material such as silicon oxide (SiO2) or silicon nitride (SiNx).

A gate electrode G is disposed on the first gate insulating layer GI1. The gate electrode G may use any one metal or an alloy of two or more of aluminum (Al), aluminum neodium (AlNd), and molybdenum (Mo).

As described above, the first transistor T1 including the first drain electrode D1, the first source electrode S1, and the gate electrode G is formed in a top-gate structure.

The second gate insulating layer GI2 is formed to cover the gate electrode G. The second gate insulating layer GI2 may be formed using a material such as silicon oxide (SiO2) or silicon nitride (SiNx).

A second semiconductor layer ACT2 is disposed on the second gate insulating layer GI2 . The second semiconductor layer ACT2 is disposed on the second drain electrode D2 and the second source electrode S2 . The second semiconductor layer ACT2 may be formed using amorphous silicon (a-Si), low temperature polysilicon (LTPS), an oxide semiconductor, or the like.

A passivation layer PAS may be formed on the second semiconductor layer ACT2 .

As described above, the second transistor T2 including the second drain electrode D2 , the second source electrode S2 , and the gate electrode G has a bottom-gate structure.

As described above, the first transistor T1 and the second transistor T2 according to the present invention share the gate electrode G, and the first semiconductor layer ACT1 and the second semiconductor layer ACT2 have at least a portion in a plane view. overlap As a result, according to the present invention, the area of the array substrate for arranging the two transistors may be reduced by overlapping the first transistor area TA1 and the second transistor area TA2 .

Hereinafter, a display device to which the thin film transistor of the present invention is applied will be described.

3 is a view showing a display device to which the thin film transistor of the present invention is applied.

Referring to FIG. 3 , the display device of the present invention includes a display panel 100 , a timing controller 110 , a data driver 120 , a level shifter 130 , and a shift register 140 .

The display panel 100 includes data lines and scan lines that cross each other, and pixels arranged in a matrix form. The display panel 100 includes a display unit 100A in which pixels P are disposed and a non-display unit 100B in which various signal wires are disposed in an area adjacent to the display unit 100A.

The data driver 120 receives digital video data RGB from the timing controller 110 . The data driver 120 converts digital video data RGB into a gamma compensation voltage in response to a source timing control signal from the timing controller 110 to generate a data voltage, and displays the data voltage to be synchronized with the scan pulse It is supplied to the data lines of the panel 100 .

The level shifter 130 level-shifts a transistor-transistor-logic (TTL) logic level voltage of the gate clocks CLK input from the timing controller 110 to a gate high voltage VGH and a gate low voltage VGL. .

The shift register 140 is configured of stages that sequentially output a carry signal and a scan pulse Gout by shifting the gate start pulse VST to match the gate clock CLK. The shift register 130 may be formed through the same process as the switches SW disposed on the pixels P of the display unit 100A on the lower substrate of the display panel 100 .

The timing controller 110 receives timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a main clock MCLK. The timing controller 110 generates timing control signals for controlling the operation timing of the data driver 120 and the scan driver circuit based on the timing signal from the host computer.

The scan timing control signal includes a gate start pulse VST, a gate clock CLK, and the like. The gate start pulse VST is input to the shift register 140 to control the shift start timing.

The gate clock CLK is input to the shift register 140 after being level-shifted through the level shifter 130 .

FIG. 4 is a diagram showing the shift register 140, and FIG. 5 is a diagram showing an embodiment of the circuit configuration of the i-th stage (i is a natural number where 2<i<n) shown in FIG. 4 .

4 and 5 , the shift register 140 includes a plurality of stages (ST1 to STn, where n is a natural number equal to or greater than 2) that are connected to each other subordinately. In the following description, the term "front stage" refers to being located above the stage as a reference. For example, based on the kth stage (k is a natural number 1<k<n), the previous stage indicates the first stage STG1 to the k−1th stage STG[k−1]. The “rear stage” refers to being located below the stage as a reference. For example, based on the kth (1<k<n) stage STk, the rear stage indicates any one of the k+1th stage ST[k+1] to the nth stage.

The shift register 140 sequentially outputs the scan pulses Gout(1) to Gout(n). To this end, one gate clock among the sequentially delayed gate clocks is input to the first to nth stages STG1 to STGn. The first to nth stages STG1 to STGn output a gate pulse Gout corresponding to the timing of the input gate clock.

Each stage STGi includes a pull-up transistor (Tpu), a pull-down transistor (Tpd), and a node control circuit (NCON).

The pull-up transistor Tpu outputs the gate high voltage of the ith (a natural number less than or equal to n) clock signal CLKi according to the voltage of the Q node Q. The pull-down transistor Tpd discharges the output voltage to the low potential voltage VGL according to the QB node voltage.

The start controller Tst charges the Q node to a high potential voltage in response to the start pulse VST.

The first discharge control transistor Tc1 discharges the voltage of the Q node to the low potential voltage VGL according to the QB node. To this end, the first discharge control transistor Tc1 includes a gate electrode connected to the QB node, a drain electrode connected to the Q node, and a source electrode connected to the low potential voltage (VGL) input terminal.

The second discharge control transistor Tc2 discharges the voltage of the Q node to the low potential voltage VGL according to the downstream signal Next. To this end, the second discharge control transistor Tc2 includes a gate electrode connected to the next input terminal, a drain electrode connected to the Q node, and a source electrode connected to the low potential voltage VGL input terminal.

The node control circuit NCON stabilizes or controls the voltage of the Q node Q or the QB node QB.

As shown in FIG. 5 , the gate electrode of the first discharge control transistor Tc1 and the gate electrode of the pull-down transistor Tpd are connected to the QB node. That is, as shown in FIGS. 1 and 2 , the first discharge control transistor Tc1 and the pull-down transistor Tpd share a gate electrode and may be vertically disposed.

For example, the first discharge control transistor Tc1 may be formed on the substrate as a top gate structure, and the pull-down transistor Tpd may be disposed on the first discharge control transistor Tc1 as a bottom gate structure. That is, the first drain electrode D1 shown in FIGS. 1 and 2 is connected to the Q node, the first source electrode is connected to the low potential voltage VGL, and the gate electrode G is connected to the QB node. . The second drain electrode D2 is connected to the output terminal Nout, the second source electrode S2 is connected to the low potential voltage VGL, and the gate electrode G is connected to the QB node.

The node control circuit NCON shown in FIG. 5 is made of a combination of a plurality of transistors, and among the transistors, transistors having a gate electrode connected to the same node may exist. Transistors sharing the gate electrode in the stage STG may be vertically arranged as shown in FIGS. 1 and 2 to reduce the area of the stage STG.

In addition, according to an embodiment of the present invention, one transistor may be vertically disposed. For example, the pull-up transistor Tpu and the pull-down transistor Tpd of the stage STG are transistors requiring large capacitance.

6 is a diagram showing an equivalent circuit diagram of a pull-up transistor to which the transistor of the present invention is applied.

Referring to FIG. 6 , the pull-up transistor Tpu of the stage STG includes a first pull-up transistor Tpu1 and a second pull-up transistor Tpu2 . The drain electrode of the first pull-up transistor Tpu1 and the drain electrode of the second pull-up transistor Tpu2 are connected to the input terminal of the gate clock CLK. The source electrode of the first pull-up transistor Tpu1 and the source electrode of the second pull-up transistor Tpu2 are connected to the output terminal Nout of the stage. A gate electrode of the first pull-up transistor Tpu1 and a gate electrode of the second pull-up transistor Tpu2 are connected to the Q node.

The first pull-up transistor Tpu1 and the second pull-up transistor Tpu2 may be vertically disposed as shown in FIG. 2 . The first pull-up transistor Tpu1 may have a top gate structure like the first transistor T1 shown in FIG. 2 , and the second pull-up transistor Tpu2 may have a bottom gate structure like the second transistor T2 . can

Although FIG. 1 shows an embodiment in which the first transistor T1 and the second transistor T2 are formed with different areas, the first pull-up transistor Tpu1 and the second pull-up transistor Tpu2 may be formed with the same area. can That is, since the pull-up transistor Tpu according to the present invention includes the first pull-up transistor Tpu1 and the second pull-up transistor Tpu2 arranged vertically, the total area can be reduced to half.

7 is a diagram illustrating a connection relationship between the source electrode of the first pull-up transistor and the source electrode of the second pull-up transistor shown in FIG. 6 . The source electrode of the first pull-up transistor Tpu1 and the source electrode of the second pull-up transistor Tpu2 shown in FIG. 6 are both connected to the output terminal Nout. The contact hole CNT shown in FIG. 7 connects the source electrode S1 of the first pull-up transistor Tpu1 having a top gate structure and the source electrode S2 of the second pull-up transistor Tpu2 having a bottom gate structure to each other. make it

Similarly, although not shown in the drawings, the drain electrode of the first pull-up transistor Tpu1 and the drain electrode of the second pull-up transistor Tpu2 are connected to each other through a contact hole, and each may be connected to the input terminal of the gate clock CLK.

8 is a view showing a liquid crystal display device to which the thin film transistor according to the present invention is applied.

8 is a view showing a liquid crystal display according to an embodiment of the present invention.

Referring to FIG. 8 , the liquid crystal display device of the present invention includes a liquid crystal panel 100 , a timing controller 210 , a power module 220 , a gate driver 230 , and a data driver 240 .

The liquid crystal panel 100 includes a thin film transistor array substrate on which a thin film transistor array is formed and a color filter substrate on which a color filter is formed, and a liquid crystal layer is formed between the thin film transistor array substrate and the color filter substrate. Also, in the liquid crystal panel 100 , a region in which pixels P are arranged on the thin film transistor array substrate is defined as a pixel array region 100A.

The timing controller 210 receives digital video data (RGB) from an external host (not shown), a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a data enable signal (Data Enable, DE), and a main clock A timing signal such as (CLK) is received. The timing controller 210 transmits digital video data RGB to the source drive ICs 240 . The timing controller 210 includes a source timing control signal for controlling the operation timing of the data driver 240 using the timing signals Vsync, Hsync, DE, and CLK, and a source timing control signal for controlling the operation timing of the gate driver 230 . A gate timing control signal GCLK is generated.

The power module 220 receives the power supply voltage VCC and outputs a gate high voltage VGH, a gate low voltage VGL, a high potential voltage VDD, and a common voltage Vcom. The gate high voltage VGH is a high level voltage of the scan pulse supplied to the gate line GL, and the gate low voltage VGL is a low level voltage of the scan pulse supplied to the gate line GL.

The GIP-type gate driver 230 includes a level shifter 231 and a shift register 233 mounted on the PCB 200 .

The level shifter 231 receives driving voltages such as a gate high voltage VGH and a gate low voltage VGL, and receives a start signal ST and a gate clock signal GCLK from the timing controller 210 to receive a gate high voltage. A start pulse VST and a clock signal CLK swinging between the voltage VGH and the gate low voltage VGL are output. The shift register 233 is connected to the gate line GL of the display panel 100 . The shift register 233 includes a plurality of cascadingly connected stages. The shift register 233 shifts the start pulse VST input from the level shifter 231 according to the clock signal CLK and sequentially supplies the gate pulses to the gate lines GL.

The data driver 240 receives digital video data RGB from the timing controller 210 . The data driver 240 converts digital video data RGB into positive/negative analog data voltages in response to a source timing control signal from the timing controller 210 , and then synchronizes the data voltages with the gate pulses on the display panel It is supplied to the data lines DL1 to DLm of (100).

9 is an equivalent circuit diagram of a pixel array in a display panel.

8 and 9 , the pixel array according to the present invention includes pixel regions defined by intersections of gate lines GL_01 to GL_E[n] and data lines D1 to Dm. Two thin film transistors and two pixel electrodes are disposed in each pixel region. Two pixel electrodes disposed in each pixel region constitute a storage capacitor Cst. In FIG. 9 , each data line is expressed separately in order to represent an equivalent circuit, but a pair of adjacent data lines are overlapped on a plane as in FIG. 10 .

When the number of pixel rows HL is n (n is a natural number), the gate lines are odd gate lines (GL_O1, GLO2...GLO[n]) and even gate lines (GL_E1, GLE2...GLE[n]). includes The odd gate lines GL_O1, GLO2...GLO[n] are connected to the thin film transistors T11, T12, T31, T32... The gate lines GL_E1, GLE2...GLE[n] are connected to the thin film transistors T21, T22, T41, T42... of pixels disposed in an even-th column in each pixel row HL.

A pair of data lines DL adjacent to each other are supplied with voltages having opposite polarities. For example, if a positive voltage is applied to the odd-numbered data lines (DL1, DL3,...DL[n-1]), the even-numbered data lines (DL2, DL3,...DL[n-1]) are negatively voltage is applied. Accordingly, a voltage difference is generated between the first pixel electrode P11 and the second pixel electrode P12 in the same pixel region, thereby forming a horizontal electric field.

10 is a plan view illustrating a pixel region of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 11 is a cross-sectional view taken along line III-III′ of FIG. 10 . In FIG. 10 , the first and second data lines refer to data lines adjacent to each other, and are not limited to the first and second data lines illustrated in FIGS. 1 and 2 .

10 and 11 , the pixel area of the liquid crystal display according to the present invention includes an opening area OA and a capacitor area CA. The opening area OA is an area in which the liquid crystal is driven by an electric field generated by a voltage difference between the first and second pixel electrodes PXL1 and PXL2. In the capacitor area CA, the first pixel electrode P11 and the common electrode VCOM overlap to form a first capacitor, and the second pixel electrode P12 and the common electrode overlap to form a second capacitor.

The first and second data lines DL1 and DL2 of the liquid crystal display according to the embodiment of the present invention are disposed to overlap on a plane. The first and second data lines DL2 shown in FIG. 10 may be vertically disposed in cross-section in the same shape as the first drain electrode D1 and the second drain electrode D2 overlapping each other on the plane in FIG. 2 . have. For example, the first data line DL1 may be disposed on the substrate, and the second data line DL2 may be disposed on the first data line DL1 with an insulating layer interposed therebetween.

A partial region where the first data line DL1 and the gate line GL overlap becomes the first drain electrode D1 . The first source electrode S1 is formed in a region adjacent to the first data line DL1, and the gate line GL in the region where the first drain electrode D1 and the first source electrode S1 abut is a gate electrode. becomes this The gate electrode G, the first drain electrode D1, and the first source electrode S1 form a first transistor and operate in response to a gate pulse applied to the gate line GL.

Similarly, the second drain electrode D2 is branched from the second data line D2 , and forms a second transistor with the gate electrode and the second source electrode S2 . In addition, the second drain electrode D2 and the second source electrode S2 may be formed to overlap the first drain electrode D1 and the first source electrode S1, respectively.

The vertical common electrode VVCOM may be disposed on a side surface of the pixel area, but may be disposed between pixel areas where the data line DL is not disposed. The vertical common electrode VVCOM supplies a common voltage to the common electrode VCOM of the capacitor area CA. The vertical common electrode VVCOM may be connected to the common electrode VCOM of an adjacent pixel area. For example, the vertical common electrode VVCOM disposed in the second pixel area PA2 may be connected to the common electrode VCOM disposed in the first pixel area P11 .

The first pixel electrode P11 is disposed on the first insulating layer GI1 , and the second pixel electrode P12 is disposed on the second insulating layer GI2 covering the first pixel electrode P11 . The first pixel electrode P11 is connected to the first source electrode S1 through the first contact hole CNT1 to charge the data voltage supplied through the first data line DL1.

The second pixel electrode P12 is connected to the second source electrode S2 through the second contact hole CNT2 to charge the data voltage supplied through the second data line DL2 .

In the conventional liquid crystal display device, a horizontal electric field is generated by the voltage difference between the common electrode and the pixel electrode, and the common voltage supplied to the common electrode is set to the reference voltage level, so the voltage difference is not so great. However, in the liquid crystal display according to the exemplary embodiment of the present invention, the voltage applied between the first pixel electrode and the second pixel electrode is the difference between the positive data voltage and the negative data voltage, so a voltage difference twice as large as that of the related art occurs.

Therefore, in the liquid crystal display device according to the present invention, it is possible to obtain the effect of achieving high transmittance, which enables the liquid crystal to be driven at twice as high voltage as in the prior art. Alternatively, the liquid crystal display according to the present invention may exhibit transmittance at the same level as in the prior art while reducing power consumption by using a voltage corresponding to 1/2 of the conventional driving voltage.

In addition, since the liquid crystal display according to the present invention can be formed by overlapping the first and second data lines, the area in which any one of the data lines of the pair of data lines is disposed in comparison with the conventional liquid crystal display is reduced. margin is secured. As a result, the vertical common electrode vVOM for supplying the common voltage in the vertical direction may be disposed. In this way, the vertical common electrode VVCOM can improve the display quality by improving the delay difference of the common voltage.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the technical configuration of the present invention can be changed to other specific forms by those skilled in the art to which the present invention pertains without changing the technical spirit or essential features of the present invention. It will be appreciated that this may be practiced. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. In addition, the scope of the present invention is indicated by the claims to be described later rather than the above detailed description. In addition, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention.

100: display panel 110: timing controller
120: data driver 130, 140: gate driver

Claims (12)

A thin film transistor array substrate of a shift register that provides a gate pulse to the pixel array through the output unit according to the voltage of the Q node,
A first transistor and a second transistor comprising:
the first transistor
a first source electrode and a first drain electrode disposed on the buffer layer; and
and a top gate structure including a gate electrode disposed on a first gate insulating layer covering the first source electrode and the first drain electrode,
The second transistor is
and a bottom gate structure including a second source electrode and a second drain electrode which share the gate electrode and are disposed on a second gate insulating layer covering the gate electrode,
the first transistor is connected to the Q node,
The second transistor is a thin film transistor array substrate connected to the output unit. The method of claim 1,
The semiconductor layer of the first transistor covers the first source electrode and the first drain electrode, and is located under the first gate insulating layer. The method of claim 1,
The semiconductor layer of the second transistor is disposed below the second source electrode and the second drain electrode on the second gate insulating layer. The method of claim 1,
On the buffer layer, the thin film transistor array substrate in which at least a partial region of the first transistor and the second transistor overlap. a pixel array disposed in a region where the data line and the gate line intersect;
a shift register providing a gate pulse to each of the gate lines;
Each stage of the shift register is
a pull-up transistor for charging the high potential voltage of the gate clock input to the drain electrode to the output terminal according to the voltage of the Q node;
a pull-down transistor connecting the output terminal to a low potential voltage input terminal according to the voltage of the QB node;
a discharge control transistor connecting the Q node to the low potential voltage input terminal according to the voltage of the QB node,
The discharge control transistor has a top gate structure in which a gate electrode is located on a semiconductor layer,
and the pull-down transistor shares the gate electrode and has a bottom gate structure in which a semiconductor layer is disposed on the gate electrode. 6. The method of claim 5,
The discharge control transistor is
a first drain electrode disposed on the buffer layer and connected to the Q node;
a first source electrode disposed on the same array layer as the first drain electrode and connected to the low potential voltage input terminal; and
and the gate electrode disposed on a first gate insulating layer covering the first drain electrode and the first source electrode;
The pull-down transistor is
the gate electrode;
a second drain electrode disposed on a second gate insulating layer covering the gate electrode and connected to the output terminal; and
and a second source electrode disposed on the same array layer as the second drain electrode and connected to the low potential voltage input terminal. 7. The method of claim 6,
A display device in which an area of the pull-down transistor is larger than an area of the discharge control transistor in a plan view, and at least a portion of a region in which the discharge control transistor is disposed falls within a region in which the pull-down transistor is disposed. delete delete delete first and second data lines overlapping at least one region on the substrate and disposed on different layers;
first and second pixel electrodes respectively connected to the first and second data lines;
a common electrode forming the first pixel electrode and a first capacitor, and forming the second pixel electrode and a second capacitor;
a vertical common electrode disposed adjacent to the first data line and connected to the common electrode;
a gate line disposed along a horizontal line; and
and first and second transistors for respectively switching the first and second data lines and the first and second pixel electrodes;
The first and second transistors share a gate electrode that is a partial region of the gate line, and the semiconductor layer of the first transistor is disposed on different layers in a state in which at least a partial region overlaps with the semiconductor layer of the second transistor display device. 12. The method of claim 11,
The second data line is disposed on an insulating layer covering the first data line.

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