KR102651808B1 - Display Device Having the same - Google Patents

Abstract

The display device according to the present invention includes a display panel, a gate driver, and a gate distribution unit. First and second gate lines connected to the pixel array are disposed on the display panel. The gate driver outputs the first gate pulse through the first output terminal. The gate distributor drives the first and second gate lines using the first gate pulse. The gate distribution unit is connected between a first switch connected between the first output terminal and the first gate line and turned on in response to the first control signal, and between the output terminal and the second gate line, and turned on in response to the second control signal. It includes a second switch that is turned on. The first control signal maintains the gate-on voltage in synchronization with the rising edge and falling edge of the gate pulse. The second control signal maintains the gate-on voltage a predetermined period of time after the rising edge of the gate pulse, and maintains the gate-on voltage at a predetermined period of time after the falling edge of the gate pulse.

Description

Display Device Having the same}

The present invention relates to a display device that can reduce the bezel of a display panel.

In the display device, data lines and gate lines are arranged at right angles, and pixels are arranged in a matrix form. The video data voltage to be displayed is supplied to the data lines, and gate pulses are sequentially supplied to the gate lines. Video data voltage is supplied to the pixels of the display line to which the gate pulse is supplied, and all display lines are sequentially scanned by the gate pulse to display video data.

A gate driver for supplying gate pulses to gate lines of a display device usually includes a plurality of gate integrated circuits (hereinafter referred to as “ICs”). Since each gate drive IC must output gate pulses sequentially, it basically includes a shift register, and may include circuits and output buffers to adjust the output voltage of the shift register according to the driving characteristics of the display panel.

The gate driver that generates the gate pulse, which is a scan signal in the display device, is sometimes implemented in the form of a gate-in-panel (Gate Ii Paiel, hereinafter GIP) made up of a combination of thin film transistors in the bezel area, which is a non-display area of the display panel. The GIP-type gate driver has stages corresponding to the number of gate lines, and each stage outputs a gate pulse to the corresponding gate line on a one-to-one basis.

As resolution increases, the number of pixel lines in the display panel increases, and the number of gate lines for driving pixels arranged in each pixel line also increases. As a result, the number of stages of GIP-type shift registers for generating gate pulses is increasing. Ultimately, as the resolution increases, the size of the shift register increases, and as a result, the bezel of the display panel increases.

To solve these shortcomings, a technology has emerged that uses a multiplexer to supply one gate pulse to two or more gate lines. However, since known multiplexers divide the gate pulse into time division, each gate pulse does not overlap. In other words, when using a multiplexer, there is a disadvantage that overlap driving of gate pulses is not possible.

In order to solve the above-described problems, the present invention is intended to provide a display device capable of overlap driving while reducing the bezel of the display panel.

As a means of solving the above-described problem, a display device according to the present invention includes a display panel, a gate driver, and a gate distribution unit. First and second gate lines connected to the pixel array are disposed on the display panel. The gate driver outputs the first gate pulse through the first output terminal. The gate distributor drives the first and second gate lines using the first gate pulse. The gate distribution unit is connected between a first switch connected between the first output terminal and the first gate line and turned on in response to the first control signal, and between the output terminal and the second gate line, and turned on in response to the second control signal. It includes a second switch that is turned on. The first control signal maintains the gate-on voltage in synchronization with the rising edge and falling edge of the gate pulse. The second control signal maintains the gate-on voltage a predetermined period of time after the rising edge of the gate pulse, and maintains the gate-on voltage at a predetermined period of time after the falling edge of the gate pulse.

The present invention can drive two or more gate lines using a gate pulse output through one output terminal using a gate distribution unit.

In particular, the gate distribution unit of the present invention does not divide the gate pulse into time divisions, but outputs it by delaying it while maintaining the output period of the gate pulse, so overlap driving of the gate pulse is possible.

1 is a diagram showing a display device according to the present invention.
Figure 2 is a diagram showing a cross section of a display panel according to the present invention.
Figure 3 is a diagram showing a shift register according to the first embodiment.
Figure 4 is a diagram showing an embodiment of the stage.
Figure 5 is a diagram showing the timing of signals applied to the stage and output signals.
Figure 6 is a diagram showing a gate distribution unit according to the first embodiment.
Figure 7 is a diagram showing control signals driving the gate distribution unit and voltage changes in gate lines according to the first embodiment.
Figure 8 is a diagram showing a shift register according to the second embodiment.
Figure 9 is a diagram showing the timing of clock signals and output signals applied to the shift register according to the second embodiment.
Figure 10 is a diagram showing a gate distribution unit according to the second embodiment.
Figure 11 is a diagram showing control signals driving the gate distribution unit and voltage changes in gate lines according to the second embodiment.

Hereinafter, preferred embodiments according to the present invention will be described in detail, focusing on the liquid crystal display device, with reference to the attached drawings. Like reference numerals refer to substantially the same elements throughout the specification. In the following description, if it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description will be omitted. The names of the components used in the following description were selected in consideration of the ease of writing specifications, and may be different from the names of the actual product.

In the shift register of the present invention, the switch elements may be implemented as transistors with an n-type or p-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure. Although an n-type transistor is illustrated in the following examples, it should be noted that the present invention is not limited thereto. A transistor is a three-electrode device including a gate, source, and drain. The source is an electrode that supplies carriers to the transistor. Within the transistor, carriers begin to flow from the source. The drain is the electrode through which carriers exit the transistor. That is, the flow of carriers in the MOSFET flows from the source to the drain. In the case of an n-type MOSFET (NMOS), because the carriers are electrons, the source voltage has a lower voltage than the drain voltage so that electrons can flow from the source to the drain. In an n-type MOSFET, since electrons flow from the source to the drain, the direction of current flows from the drain to the source. In the case of a p-type MOSFET (PMOS), since the carrier is a hole, the source voltage is higher than the drain voltage to allow holes to flow from the source to the drain. In a p-type MOSFET, current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of the MOSFET are not fixed. For example, the source and drain of a MOSFET can change depending on the applied voltage. The invention should not be limited by the source and drain of the transistor in the following embodiments.

Additionally, in this specification, the gate-on voltage refers to the operating voltage of the transistor. Since this specification describes an n-type transistor as an example, a high potential voltage is defined as the gate-on voltage.

Although this specification is described with a focus on liquid crystal displays (LCDs), the present invention can also be applied to organic light-emitting diode displays (OLEDs), electrophoretic displays (EPDs), etc.

1 is a diagram showing a display device according to an embodiment of the present invention. Referring to FIG. 1, the display device of the present invention includes a display panel 100, a timing controller 110, a data driver 120, and gate drivers 130 and 140.

The display panel 100 includes a pixel array 100A in which data lines DL and gate lines GL are defined and pixels are arranged, and a non-display area in which various signal lines, pads, etc. are formed outside the pixel array 100A. Includes (100B). The pixel array 100A of the display panel 100 includes subpixels arranged in a matrix form by an intersection structure of data lines DL and gate lines GL1 to GLm.

The display panel 100 includes a TFT array substrate (TSUB) and a color filter substrate (CSUB). The color filter substrate (CSUB) includes a black matrix (BM), and the TFT array substrate (TSUB) includes an array portion (ARP) bonded to the color filter substrate (CSUB).

FIG. 2 shows a display panel including a coplanar type thin film transistor in which the gate electrode is located on top of the active layer.

Referring to FIG. 2, the light blocking pattern LS is located on the TFT array substrate TSUB. The light blocking pattern (LS) is made of a metal material. The light blocking pattern (LS) may be electrically floating or may be subject to a constant voltage. The voltage applied to the light blocking pattern (LS) may be the common voltage (VCOM). The light blocking pattern (LS) forms a capacitor with the gate line (GL) located between the gate insulating film (GI). As a result, when the gate line GL is in a floating state, it holds the previously charged voltage. A buffer layer (BUF) covering the light blocking pattern (LS) is located on the TFT array substrate (TSUB). The buffer layer (BUF) is formed to protect the thin film transistor formed in the subsequent process from impurities such as alkali ions leaking from the TFT array substrate (TSUB), and is made of silicon oxide (SiOx), silicon nitride (SiNx), or a multilayer thereof. It consists of The active layer (ACT) is located on the buffer layer (BUF). The active layer (ACT) is made of amorphous silicon, polycrystalline silicon, and oxide semiconductor. A gate insulating layer (GI) is located on the active layer (ACT). The gate insulating film (GI) is made of a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer thereof. A gate electrode (G) is located on the gate insulating film (GI). The gate electrode (G) is made of copper (Cu), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and tantalum (Ta). and tungsten (W), or an alloy thereof. The gate electrode (G) is located corresponding to the channel of the active layer (ACT).

An interlayer insulating layer (ILD) is located on the TFT array substrate (TSUB) on which the gate electrode (G) is formed. The interlayer insulating layer (ILD) is made of a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), or multiple layers thereof. A source electrode (S) and a drain electrode (D) are located on the interlayer insulating layer (ILD). The source electrode (S) and drain electrode (D) may be made of a single layer or multiple layers. In the case of a single layer, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), It may be made of any one selected from the group consisting of nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. In addition, when the source electrode (S) and drain electrode (D) are multilayered, they are a double layer of molybdenum/aluminum-neodymium, molybdenum/aluminum, or titanium/aluminum, or a double layer of molybdenum/aluminum-neodymium/molybdenum, molybdenum/aluminum/molybdenum, or titanium. It can be made of a triple layer of /aluminum/titanium. The source electrode (S) and the drain electrode (D) are each connected to the active layer (ACT) through contact holes formed in the interlayer dielectric (ILD).

A first passivation film (PAS1) is located on the source electrode (S) and the drain electrode (D). The first passivation film (PAS1) protects the thin film transistor and is made of silicon oxide (SiOx), silicon nitride (SiNx), or multiple layers thereof. An organic insulating layer (PAC) is located on the first passivation layer (PAS1). The organic insulating film (PAC) is used to flatten the lower step and can be made of organic materials such as photo acryl, polyimide, benzocyclobutene resin, and acrylate. there is. A common electrode (Vcom) is located on the organic insulating film (PAC). The common electrode (Vcom) is integrally formed on the entire surface of the array portion of the TFT array substrate (TSUB) to which a common voltage is applied, and may be made of a transparent conductive film. The transparent conductive film may be a transparent and conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide). A second passivation film (PAS2) is located on the common electrode (Vcom). The second passivation film (PAS2) is made of silicon oxide (SiOx), silicon nitride (SiNx), or a multilayer thereof. The pixel electrode (PXL) is located on the second passivation film (PAS2). The pixel electrode (PXL) is made of a transparent conductive film like the common electrode (Vcom). Additionally, the pixel electrode (PXL) contacts the drain electrode (D) through the via hole (VIA).

The color filter substrate (CSUB) is a color filter (CF) that converts the white light transmitted through the liquid crystal layer (LC) into R, G, and B, and a black matrix (BM) that divides the color filter (CF) into a plurality of pixels. ) includes. A protective layer (PL) covering the color filter (CF) and black matrix (BM) is located on the color filter (CF). The TFT array substrate (TSUB) and the color filter substrate (CSUB) are bonded through a sealant (SL) and a liquid crystal layer (LC) is injected to form the liquid crystal display device of the present invention.

The gate distribution unit GD may be disposed in the non-display area 100A of the display panel 100. The gate distributor (GD) drives two or more gate lines (GL) using a gate pulse output through one output terminal. In particular, the configuration and operation of the gate distribution unit (GD) will be described later.

The timing controller 110 receives timing signals such as a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a data enable signal (DE), and a dot clock (DLCK) through an LVDS or TMDS interface reception circuit connected to the video board. receives input. The timing controller 110 provides a data timing control signal (DDC) for controlling the operation timing of the data driver 120 based on the input timing signal and a gate timing control signal (DDC) for controlling the operation timing of the gate drivers 130 and 140 ( GDC) is created.

Data timing control signals include source start pulse (SSP), source sampling clock (SSC), polarity control signal (Polarity, POL), and source output enable signal (SOE). Includes. The source start pulse (SSP) controls the shift start timing of the data driver 120. The source sampling clock (SSC) is a clock signal that controls the sampling timing of data within the data driver 120 based on the rising or falling edge.

The scan timing control signal includes a start pulse (VST), a reset signal (VNEXT), and a gate clock (CLK). The start pulse (VST) is input to the first stage (STG1) of the shift register 140 to control the shift start timing. The reset signal VNEXT is a signal for discharging the Q node of the last stage of the shift register 140. The gate clock CLK is level shifted through the level shifter 130 and then input to the shift register 140.

The data driver 120 receives digital video data (RGB) and a source timing control signal (DDC) from the timing controller 110. The data driver 120 generates a data voltage by converting digital video data (RGB) into a gamma voltage in response to the source timing control signal (DDC), and transmits the data voltage to the data lines (DL) of the display panel 100. supplied through.

The gate drivers 130 and 140 include a level shifter 130 and a shift register 140. The level shifter 130 is formed on a printed circuit board (not shown) connected to the display panel 100 in the form of an IC. The level shifter 130 levels-shifts the start signal (VST), reset signal (VNEXT), and gate clock (CLK) and then supplies them to the shift register 140. Shift register 140 includes multiple stages that are dependently connected.

Figure 3 is a diagram showing a shift register according to the first embodiment. FIG. 4 is a diagram showing the configuration of the stage shown in FIG. 3.

Referring to Figures 3 and 4, the shift register 140 is a combination of a plurality of thin film transistors in the non-display area 100B of the display panel 100 by the gate-in-panel (GIP) method. It is formed and outputs gate pulses sequentially. For this purpose, the shift register 140 includes a plurality of stages (STG1 to STGn) that are dependently connected to each other. In the following description, “front stage” refers to something located above the standard stage. For example, based on the i-th stage (i is a natural number with 1<i<n), the previous stage indicates one of the first stage (STG1) to the (i-1)th stage (STG[i-1]). . “Rear stage” refers to something located below the standard stage. For example, based on the i-th stage (STGi), the rear stage indicates one of the [i+1]-th stage (STG[i+1]) to the n-th stage (STGn).

The first to nth stages (STG1 to STGn) sequentially output first to nth gate pulses (Gout[1] to Gout[n]), respectively.

The gate clock CLK applied to the stages of the first embodiment has four phases, and the period of each gate clock CLK is 8H. Additionally, each stage outputs a gate pulse (Gout) corresponding to the timing of the gate clock (CLK) received while the Q node is precharged.

The stages STG1 to STGn start operating by precharging the Q node when the first transistor T1 is turned on. And, the stages STG1 to STGn are initialized by discharging the Q node when the second transistor T2 is turned on.

Each stage (STG) includes a pull-up transistor (Tpu), a pull-down transistor (Tpd), a node control unit (NCON), and first to third transistors (T1, T2, T3). Includes.

The pull-up transistor (Tpu) includes a gate electrode connected to the Q node, a drain electrode connected to the gate clock (CLK) input terminal, and a source electrode connected to the output terminal (Nout).

The pull-down transistor (Tpd) includes a gate electrode connected to the QB node, a drain electrode connected to the output terminal (Nout), and a source electrode connected to the gate low voltage input terminal.

The node control unit (NCON) controls charging or discharging of the Q node and QB node. The node control unit (NCON) may be composed of a combination of one or more transistors, and any known configuration may be used.

The first transistor T1 includes a gate electrode that receives a start pulse (VST) or a carry signal, a drain electrode connected to the high potential voltage input line (VDDL), and a source electrode connected to the Q node. The first transistor T1 electrically connects the high potential voltage input line VDDL and the Q node in response to the start pulse VST or the carry signal. The high potential voltage input line (VDDL) supplies a high potential voltage (VDD) while the start signal (VST) is applied, and as a result, the Q node is charged with the high potential voltage (VDD). The carry signal corresponds to the gate pulse of the previous stage and may vary depending on the phase or period of the gate clock (CLK).

The second transistor T2 includes a gate electrode that receives a reset signal (Vnext) or a rear-end signal, a drain electrode connected to the Q node, and a source electrode connected to a low potential voltage (VSS) input terminal. The second transistor T2 discharges the Q node to a low potential voltage (VSS) in response to the reset signal (Vnext) or the rear end signal. The back-end signal refers to the gate pulse of the back-stage stage, and may vary depending on the phase or period of the gate clock (CLK).

The third transistor T3 includes a gate electrode connected to the QB node, a drain electrode connected to the Q node, and a source electrode connected to a low potential voltage (VSS) input terminal. When the QB node voltage is a high voltage, the third transistor T3 discharges the Q node to a low potential voltage (VSS).

Gate pulses (Gout1 to Gout[n]) output from each stage (STG1 to STGn) are applied to the gate distribution units (GD1 to GDn).

The first gate distributor (GD1) drives the first and second gate lines using the first gate pulse (Gout1). Likewise, the ith (i is a natural number less than or equal to n) gate distribution unit (GDi) uses the ith gate pulse (Gout[i]) to connect the (2i-1)th gate line (GL[2i-1]) and The 2i gate line (GL2i) is driven.

Figure 4 is a diagram showing the timing of the gate clock and gate pulse according to the first embodiment.

With reference to FIGS. 2 to 4, the operation of the shift register according to the present invention is as follows.

The first transistor T1 of the first stage STG1 pre-charges the Q node in response to the start signal VST.

When the gate clock (CLK) is input to the drain electrode of the pull-up transistor (Tpu) while the Q node is precharged, the Q node is bootstrapped as the voltage of the drain electrode of the pull-up transistor (Tpu) increases. As the Q node is bootstrapped, the potential difference between the gate and source of the pull-up transistor (Tpu) increases, and eventually, when the voltage difference between the gate and source reaches the threshold voltage, the pull-up transistor (Tpu) is turned on. The turned-on pull-up transistor (Tpu) charges the output terminal (Nout) using the gate clock (CLK). As a result, the output terminal (Nout) of the first stage (STG1) outputs the first gate pulse (Gout1).

Figure 5 is a diagram showing a gate distribution unit according to a first embodiment of the present invention. Figure 6 is a diagram showing the timing of first and second control signals.

Referring to Figures 5 and 6, the first gate distribution unit (GD1) according to the first embodiment includes a first switch (M1) and a second switch (M2), and the second gate distribution unit (GD2) It includes a third switch (M3) and a fourth switch (M4).

The first switch (M1) includes a gate electrode that receives the first control signal (CS1), a drain electrode connected to the first output terminal (Nout1) of the first stage (STG1), and a source connected to the first gate line (GL1). Contains electrodes.

The second switch (M2) includes a gate electrode that receives the second control signal (CS2), a drain electrode connected to the first output terminal (Nout1) of the first stage (STG1), and a source connected to the second gate line (GL2). Contains electrodes.

The third switch (M3) includes a gate electrode that receives the second control signal (CS2), a drain electrode connected to the second output terminal (Nout2) of the second stage (STG2), and a source connected to the third gate line (GL3). Contains electrodes.

The fourth switch (M4) includes a gate electrode that receives the first control signal (CS1), a drain electrode connected to the second output terminal (Nout2) of the second stage (STG2), and a source connected to the fourth gate line (GL4). Contains electrodes.

The first control signal CS1 has a gate-on voltage maintenance period and a gate-off voltage maintenance period repeated at equal intervals. The period of the first control signal CS1 is the same as the output period of the first gate pulse Gout1. That is, as in the first embodiment, when the output period of the first gate pulse (Gout1) is 4H, the period of the first control signal (CS1) is “4H”. At this time, “1H” refers to the scan period of pixels connected to one gate line.

The second control signal CS2 is opposite in phase to the first control signal CS1 and has the same period.

The first control signal CS1 maintains the turn-on voltage state when the first gate pulse Gout1 is applied and when the first gate pulse Gout1 ends.

The second control signal CS2 maintains the gate-on voltage state after the first gate pulse (Gout1) is applied and a predetermined period of time has elapsed, and the gate-on voltage state is maintained after the first gate pulse (Gout1) is terminated and a predetermined period of time has elapsed. maintain the status quo

The detailed operation of the first gate distribution unit GD1 is as follows.

The first gate pulse (Gout1) is output from the second period (t2) to the fifth period (t5).

The first control signal CS1 maintains the gate-on voltage during the first period t1 and the second period t2. During the second period t2, the first switch M1 is turned on, and as a result, the first gate pulse Gout1 is supplied to the first gate line GL1. The first gate line GL1 is charged by the first gate pulse Gout1 applied to the first gate line GL1, and the voltage level of the first gate line GL1 becomes the gate high voltage VGH. Since the first gate line GL1 forms a parasitic capacitance with adjacent metal layers, it can be charged by the first gate pulse Gout1. In particular, when the common voltage (VCOM) is applied to the light blocking pattern (LS), the first gate line (GL) can efficiently hold the charged voltage while reducing the coupling phenomenon.

The first control signal CS1 maintains the gate-off voltage during the third period t3 and the fourth period t4. During the third period t3 and the fourth period t4, the first switch M1 remains turned off, and the first gate line GL1 is in a floating state. As a result, the voltage level of the first gate line (GL1) is slightly reduced from the gate high voltage (VGH) to the kickback voltage and maintains the high level voltage during the third period (t3) and the fourth period (t4). .

The first control signal CS1 maintains the gate-on voltage during the fifth period t5 and the sixth period t6. During the fifth period t5, the first switch M1 is turned on, and as a result, the first gate pulse Gout1 is supplied to the first gate line GL1. The first gate line (GL1) is charged by the first gate pulse (Gout1) applied to the first gate line (GL1), and the voltage level of the first gate line (GL1) becomes the gate high voltage (VGH) again. .

At the end of the fifth period (t5), the first output terminal (Nout1) is inverted to the low potential voltage (VSS), so the first gate line (GL1) receives the low potential voltage (VSS). That is, the gate high voltage (VGH) maintained in the first gate line (GL1) is discharged to the low potential voltage (VSS).

The second control signal CS2 maintains the gate-on voltage during the third period t3 and the fourth period t4. At the start of the third period t3, the second switch M2 is turned on, and as a result, the first gate pulse Gout1 is supplied to the second gate line GL2. The second gate line GL2 is charged by receiving the first gate pulse Gout1, and the voltage level of the second gate line GL2 becomes the gate high voltage VGH. During the fourth period t4, the second switch M2 maintains the turn-on state, and the second gate line GL2 maintains the gate high voltage VGH.

The second control signal CS2 maintains the gate-off voltage during the fifth period t5 and the sixth period t6. During the fifth period t5 and the sixth period t6, the second switch M2 maintains the turned-off state, and the second gate line GL2 is in a floating state. As a result, the voltage level of the second gate line GL2 is slightly reduced from the gate high voltage VGH to the kickback voltage and maintains the high level voltage during the fifth period t5 and the sixth period t6. .

At the start of the sixth period t6, the second control signal CS2 becomes the gate-on voltage.

At the end of the sixth period (t6), since the first output terminal (Nout1) is in a low potential voltage (VSS) state, the second gate line (GL2) receives the low potential voltage (VSS). That is, the high voltage maintained in the second gate line GL2 is discharged to the low potential voltage VSS.

As seen, the section of the high voltage applied to the first gate line (GL1) and the second gate line (GL2) through the first gate distributor (GD1) is the same as the output period of the first gate pulse (Gout1). . That is, the first gate distributor GD1 can drive the first gate line GL1 and the second gate line GL2 without reducing the output timing of the signal output by the stage.

The third switch M3 of the second gate distribution unit GD2 operates by the second control signal CS2, and the fourth switch M4 operates by the first control signal CS1. Since the detailed operation of the second gate distribution unit GD2 is substantially the same as the operation of the above-described first gate distribution unit GD1, detailed description is omitted.

Figure 8 is a diagram showing a shift register according to the second embodiment and a gate distribution unit according to the second embodiment.

Referring to FIG. 8, the shift register 140 is formed by a combination of a plurality of thin film transistors by the gate-in-panel (GIP) method in the non-display area 100B of the display panel 100, Gate pulses are output sequentially. In the second embodiment, detailed description of the same configuration as the first embodiment described above will be omitted.

The shift register 140 includes a plurality of stages (STG1 to STGn) that are dependently connected to each other. The first to nth stages (STG1 to STGn) sequentially output first to nth gate pulses (Gout[1] to Gout[n]), respectively.

The first gate distribution unit GD1 drives the first to fourth gate lines GL4 using the first gate pulse Gout1. Likewise, the i-th gate distribution unit (GDi) uses the ith gate pulse (Gout[i]) to form the (4i-1)-th gate line (GL[4i-1]) to the 4i-th gate line (GL[4i]). ]).

Figure 9 is a diagram showing the timing of gate clocks and gate pulses according to the second embodiment.

The configuration and operation of the stages of the second embodiment are the same as those of the first embodiment described above. The gate clock CLK applied to the stages of the second embodiment has two phases, and the period of each gate clock CLK is 8H. Additionally, each stage outputs a gate pulse corresponding to the timing of the gate clock (CLK) received while the Q node is precharged.

Figure 10 is a diagram showing a gate distribution unit according to the second embodiment. Figure 11 is a diagram showing the timing of first and second control signals.

Referring to FIGS. 10 and 11 , the first gate distribution unit GD1 according to the second embodiment includes first to fourth switches M4.

The first switch (M1) includes a gate electrode that receives the first control signal (CS1), a drain electrode connected to the first output terminal (Nout1) of the first stage (STG1), and a source connected to the first gate line (GL1). Contains electrodes.

The second switch (M2) includes a gate electrode that receives the second control signal (CS2), a drain electrode connected to the first output terminal (Nout1) of the first stage (STG1), and a source connected to the second gate line (GL2). Contains electrodes.

The third switch (M3) includes a gate electrode that receives the third control signal (CS3), a drain electrode connected to the first output terminal (Nout1) of the first stage (STG1), and a source connected to the third gate line (GL3). Contains electrodes.

The fourth switch M4 includes a gate electrode receiving the fourth control signal CS4, a drain electrode connected to the first output terminal Nout1 of the first stage STG1, and a source connected to the fourth gate line GL4. Contains electrodes.

Each period of the first to fourth control signals CS1 to CS4 is the same as the output period of the gate pulse Gout. For example, when the output period of the gate pulse (Gout) is 4H, the period of the first to fourth control signals (CS4) is “4H”.

The output timing of each of the first to fourth control signals CS1 to CS4 determines the charging timing of the first to fourth gate lines GL4. And the output timing between the first to fourth control signals CS1 to CS4 is shifted by 1/4 of the output period of the gate pulse Gout. For example, when the output period of the gate pulse (Gout) is 4H, the output timing between the first to fourth control signals (CS4) has a difference of 1H period.

The output period of the first to fourth control signals CS1 to CS4 may be 1/2H to 1H.

The detailed operation of the first gate distribution unit GD1 is as follows.

The first gate pulse (Gout1) is output from the first period (t1) to the eighth period (t8). In FIG. 11, each of the first to fifteenth periods (t1 to t15) corresponds to 1/2H.

The first control signal CS1 maintains the gate-on voltage during the first period t1 and the ninth period t9. During the first period t1, the first switch M1 is turned on, and as a result, the first gate pulse Gout1 is supplied to the first gate line GL1. The first gate line GL1 is charged by the first gate pulse Gout1 applied to the first gate line GL1, and the voltage level of the first gate line GL1 becomes the gate high voltage VGH. Since the first gate line GL1 forms a parasitic capacitance with adjacent metal layers, it can be charged by the first gate pulse Gout1.

The first control signal CS1 maintains the gate-off voltage during the second period t2 and the eighth period t8. During the second period (t2) to the eighth period (t8), the first switch (M1) maintains the turned-off state, and the first gate line (GL1) is in a floating state. As a result, the voltage level of the first gate line GL1 maintains a high level voltage reduced by the kickback voltage from the gate high voltage VGH during the second period t2 to the eighth period t8.

The first control signal CS1 maintains the gate-on voltage during the ninth period t9. At the moment the eighth period (t8) ends, the first output terminal (Nout1) is inverted to the low potential voltage (VSS), and as a result, the first gate line (GL1) is inverted to the low potential voltage (VSS) during the ninth period (t9). ) is approved. That is, the gate high voltage (VGH) maintained in the first gate line (GL1) is discharged to the low potential voltage (VSS).

The second control signal CS2 maintains the gate-on voltage during the third period t3 and the eleventh period t11. During the third period t3, the first switch M1 is turned on, and as a result, the first gate pulse Gout1 is supplied to the second gate line GL2. The second gate line GL2 is charged by the first gate pulse Gout1 applied to the second gate line GL2, and the voltage level of the second gate line GL2 becomes the gate high voltage VGH.

The second control signal CS2 maintains the gate-off voltage during the fourth period t4 and the tenth period t10. During the fourth period t4 to the tenth period t10, the second switch M2 maintains the turned-off state, and the second gate line GL2 is in a floating state. As a result, the voltage level of the second gate line GL2 maintains a high level voltage reduced by the kickback voltage from the gate high voltage VGH during the fourth period t4 to the tenth period t10.

The first control signal CS1 maintains the gate-on voltage during the 11th period t11. During the 11th period (t11), the first output terminal (Nout1) maintains the low potential voltage (VSS), and as a result, the first gate line (GL1) receives the low potential voltage (VSS) during the 11th period (t11). . That is, the second gate line GL2 is discharged to the low potential voltage VSS.

The third control signal CS3 maintains the gate-on voltage during the fifth period t5 and the thirteenth period t13. During the fifth period t5, the third switch M3 is turned on, and as a result, the first gate pulse Gout1 is supplied to the third gate line GL3. The third gate line GL3 is charged by the first gate pulse Gout1 applied to the third gate line GL3, and the voltage level of the third gate line GL3 becomes the gate high voltage VGH.

The third control signal CS3 maintains the gate-off voltage during the sixth period t6 and the twelfth period t12. During the sixth period t6 to the twelfth period t12, the third switch M3 maintains the turned-off state, and the third gate line GL3 is in a floating state. As a result, the voltage level of the third gate line GL3 maintains a high level voltage reduced by the kickback voltage from the gate high voltage VGH during the sixth period t6 to the twelfth period t12.

The third control signal CS3 maintains the gate-on voltage during the thirteenth period t13. During the thirteenth period t13, the first output terminal Nout1 maintains the low potential voltage VSS, and as a result, the third gate line GL3 receives the low potential voltage VSS. That is, the third gate line GL3 is discharged to the low potential voltage VSS.

The fourth control signal CS4 maintains the gate-on voltage during the seventh period t7 and the fifteenth period t15. During the seventh period t7, the fourth switch M4 is turned on, and as a result, the first gate pulse Gout1 is supplied to the fourth gate line GL4. The fourth gate line GL4 is charged by the first gate pulse Gout1 applied to the fourth gate line GL4, and the voltage level of the fourth gate line GL4 becomes the gate high voltage VGH.

The fourth control signal CS4 maintains the gate-off voltage during the eighth period t8 and the fourteenth period t14. During the 8th period (t8) to the 14th period (t14), the fourth switch (M4) maintains the turned-off state, and the fourth gate line (GL4) is in a floating state. As a result, the voltage level of the fourth gate line GL4 maintains a high level voltage reduced by the kickback voltage from the gate high voltage VGH during the eighth period t8 to the fifteenth period t15.

The fourth control signal CS4 maintains the gate-on voltage during the fifteenth period t15. During the 15th period (t15), the first output terminal (Nout1) maintains the low potential voltage (VSS), and as a result, the fourth gate line (GL4) receives the low potential voltage (VSS). That is, the fourth gate line GL4 is discharged to the low potential voltage VSS.

As seen, the section of the high voltage applied to the first gate line (GL1) to the fourth gate line (GL4) through the first gate distribution unit (GD1) is the same as the output period of the first gate pulse (Gout1). . That is, the first gate distribution unit GD1 can drive the first gate line GL1 to the fourth gate line GL4 without reducing the output timing of the signal output from the stage STG.

Although embodiments of the present invention have been described with reference to the attached drawings, the technical configuration of the present invention described above can be modified by those skilled in the art in the technical field to which the present invention belongs in other specific forms without changing the technical idea or essential features of the present invention. You will understand that it can be done. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive. In addition, the scope of the present invention is indicated by the claims described later rather than the detailed description above. In addition, the meaning and scope of the patent claims and all changes or modified forms derived from the equivalent concept should be construed as being included in the scope of the present invention.

100: display panel 110: timing controller
120: data driver 130, 140: gate driver
GD: Gate distributor

Claims (14)

a display panel on which first and second gate lines connected to the pixel array are disposed;
A gate driver that outputs a gate pulse through a first output terminal; and
A gate distribution unit that drives the first and second gate lines using the gate pulse,
The gate distribution unit
a first switch connected between the first output terminal and the first gate line and turned on in response to a first control signal; and
A second switch connected between the first output terminal and the second gate line and turned on in response to a second control signal,
The first control signal maintains the gate-on voltage in synchronization with the rising edge and falling edge of the gate pulse,
The second control signal maintains the gate-on voltage after a predetermined period of time after the rising edge of the gate pulse, and maintains the gate-on voltage at a time delayed by the predetermined period after the falling edge of the gate pulse,
Within the gate driving period including the first to sixth periods,
The gate pulse is maintained for the second to fifth periods,
The first control signal maintains a first gate-on voltage during the first and second periods and a second gate-on voltage during the fifth and sixth periods,
The second control signal is in phase opposite to the first control signal. According to claim 1,
A display device wherein the period during which the gate-on voltage of the first and second control signals is maintained is 1/2 of the output period of the gate pulse. delete According to claim 1,
The gate driver further outputs a second gate pulse through the second output stage,
The gate distributor further includes a third switch and a fourth switch for driving third and fourth gate lines using the second gate pulse,
The third switch is connected between the second output terminal and the third gate line and is turned on in response to the second control signal,
The fourth switch is connected between the second output terminal and the fourth gate line and is turned on in response to the first control signal. delete delete delete According to claim 1,
The display panel further includes a metal layer facing the first and second gate lines with an insulating film therebetween, wherein the first and second gate lines form a capacitor with the metal layer,
The capacitor holds the voltage of the gate line in a floating state when the first and second switches are turned off. According to claim 8,
A display device in which the metal layer is a light blocking pattern. According to clause 9,
The light blocking pattern is a display device that receives a constant voltage. A method of driving a display device comprising a first switch selectively connecting a first output terminal outputting a gate pulse and a first gate line, and a second switch selectively connecting the first output terminal and a second gate line,
A first step of turning on the first switch in synchronization with the rising edge of the gate pulse to charge the first gate line;
a second step of turning on the first switch in synchronization with the falling edge of the gate pulse to discharge the first gate line to a low potential voltage of the first output terminal;
a third step of turning on the second switch after a predetermined delay after the rising edge of the gate pulse to charge the second gate line; and
A fourth step of discharging the second gate line by turning on the second switch after a predetermined delay after the falling edge of the gate pulse,
Within the gate driving period including the first to eighth periods,
The gate pulse maintains the gate-on voltage during the second to fifth periods,
The first step is performed during the first and second periods,
The second step is performed during the fifth and sixth periods. According to claim 11,
Between the first step and the second step, turning off the first switch to hold the voltage charged in the first gate line in the first step,
Between the third step and the fourth step, turning off the first switch to hold the voltage charged in the second gate line in the third step. delete delete

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