KR102593458B1 - Gate driving circuit and display device using the same - Google Patents

Abstract

The gate driving circuit of the present invention includes a plurality of stages that are dependently connected and output scan signals, and each of the stages provides a forward power supply voltage to the Q node according to the first and second carry signals input from each other stage. an input unit that supplies a reverse power voltage to the Q node; A node control unit that controls the voltage of the Q node and the voltage of the Qb node to be opposite to each other; and an output unit that outputs the scan signal and the carry signal according to the voltage of the Q node and the voltage of the Qb node, and the effective channel length of the TFTs included in the input unit is determined by the node control unit and the output unit. It is longer than the effective channel length of TFTs.

Description

Gate driving circuit and display device using the same {GATE DRIVING CIRCUIT AND DISPLAY DEVICE USING THE SAME}

The present invention relates to a gate driving circuit and a display device using the same.

The display device includes a data driving circuit that supplies data signals to the data lines of the pixel array, and a gate that sequentially supplies scan signals (or scan pulses) synchronized with the data signals to the gate lines (or scan lines) of the pixel array. It includes a timing controller that controls a driving circuit (or scan driving circuit), a data driving circuit, and a gate driving circuit.

Each of the pixels may include a thin film transistor (hereinafter referred to as a “TFT”) that supplies the voltage of the data line to the pixel electrode in response to the scan signal. The scan signal swings between gate-on and gate-off voltages. The gate-on voltage is set to a voltage higher than the threshold voltage of the pixel TFT, and the gate-off voltage is set to a voltage lower than the threshold voltage of the pixel TFT.

Recently, technology has been applied to embed a gate driving circuit in a display panel along with a pixel array. Hereinafter, the gate driving circuit built into the display panel will be referred to as a “GIP (Gate In Panel) circuit.” The GIP circuit includes a shift register. The shift register includes a plurality of dependently connected stages and shifts the output voltage according to the gate shift clock timing.

The scan signal is synchronized with the data voltage of the input image, that is, the pixel voltage, and sequentially selects pixels to be charged with the data voltage, one line at a time. The stage of the shift register receives a start pulse or a carry signal received from the previous stage as a start pulse and generates an output when a clock is input.

As shown in Figures 1 and 2, each stage of the shift register charges the output terminal (No) in response to the Q node voltage, rising the output voltage (SC(n)) to the gate-on voltage (VGH). A pull-up transistor (Tu), which discharges the output terminal (No) in response to the Qb node voltage, causes the output voltage (SC(n)) to fall to the gate-off voltage (VGL). It includes a pull-down transistor (Td), a switch circuit (1) that charges and discharges the Q node and the Qb node, and an input unit (2) connected to the Q node. The output terminal (No) of each stage is connected to the gate line of the display panel.

The pull-up transistor (Tu) operates at the gate-on voltage (VGH) of the gate shift clock (CLK) when the gate shift clock (CLK) is input to the drain while the Q node is pre-charged by the gate-on voltage (VGH). Charge the output terminal (No) until ). Specifically, when the gate shift clock (CLK) is input to the drain of the pull-up transistor (Tu), the voltage of the Q node floated through the capacitance between the drain and gate of the pull-up transistor (Tu) is switched to the gate by bootstrapping. It rises from the on voltage (VGH) to the boosting voltage (VBST). At this time, the pull-up transistor Tu is turned on by the boosting voltage VBST of the Q node, and the voltage SC(n) of the output terminal No increases to the gate-on voltage VGH. The pull-down transistor (Td) supplies the gate-off voltage (VGL) to the output terminal (No) when the voltage of the Qb node is charged by the gate-on voltage (VGH), thereby increasing the output voltage (SC(n)) to the gate-off voltage (VGL). ) until discharged.

The input unit 20 charges the Q node to the gate-on voltage (VGH) in response to the start pulse input through the start terminal or the carry signal (CR(n-x)) received from the previous stage, and gates the Qb node off. Discharge to voltage (VGL). Additionally, the input unit 20 discharges the Q node to the gate-off voltage (VGL) and charges the Qb node to the gate-on voltage (VGH) in response to a reset signal (not shown) input through the reset terminal.

The input unit 20 includes switches Ta, Tb, and Tc. Switch Ta has a control electrode and a first electrode (drain) connected to the input terminal of the carry signal (CR(n-x)), a second electrode (source) is connected to the first node (N1), and switch Tb connects a carry signal ( A control electrode is connected to the input terminal of CR(n-x)), a first electrode is connected to the first node (N1), and a second electrode is connected to the Q node. The switch Tc has a control electrode connected to the Q node, a first electrode connected to the input terminal of the high potential voltage (GVDD), and a second electrode connected to the first node (N1).

This conventional gate driving circuit has the following problems.

First, the threshold voltage of a TFT containing amorphous silicon (a-Si) (hereinafter referred to as “a-Si TFT”) is always greater than 0, but the threshold voltage of a TFT containing an oxide semiconductor (hereinafter referred to as “Oxide TFT”) is The threshold voltage may have a value less than 0. Oxide TFT is being applied to switch elements of GIP circuits, replacing a-Si TFT, which has low mobility, in the high-resolution requirements of display devices. However, if the initial threshold voltage characteristics of the oxide TFT shift in the (-) direction, the Q node may not be completely turned off during the period (Thd) during which the gate-off voltage (GVSS) is maintained, and may leak current.

During the period (Thd) during which the Q node is maintained at the gate-off voltage (VGL), the carry signal (CR(n-x)) is also maintained at the gate-off voltage (VGL). Therefore, during this period (Thd), the gate-source voltage (Vgs) of switch Tb becomes 0, and if the threshold voltage of switch Tb is less than 0, leakage current flows through switch Tb. Accordingly, the voltage of the Q node cannot be maintained at the gate-off voltage (VGL) due to leakage current and rises to a higher voltage, and as a result, the output voltage (SC(n)) may be distorted.

Second, the conventional gate driving circuit can only be operated as a unidirectional scan circuit because the switch Ta is connected to a diode. If the diode connection of switch Ta is disconnected to operate as a bidirectional scan circuit, there is no margin for the initial threshold voltage distribution, so even if the threshold voltage drops slightly below 0, the leakage current increases, so the output voltage (SC(n)) It is easily distorted and the stability of operation is greatly reduced.

The purpose of the present invention is to provide a gate driving circuit that improves leakage current characteristics of input switches controlled according to a carry signal to ensure driving stability and reliability, and a display device using the same.

Another object of the present invention is to provide a gate driving circuit capable of bidirectional scan driving by improving the leakage current characteristics of input switches controlled according to a carry signal and a display device using the same.

In order to achieve the above object, a gate driving circuit according to an embodiment of the present invention includes a plurality of stages that are dependently connected and output scan signals, each of the stages having first and second signals input from different stages. 2 An input unit that supplies a forward power voltage to the Q node and a reverse power supply voltage to the Q node according to the carry signal; A node control unit that controls the voltage of the Q node and the voltage of the Qb node to be opposite to each other; and an output unit that outputs the scan signal and the carry signal according to the voltage of the Q node and the voltage of the Qb node, and the effective channel length of the TFTs included in the input unit is determined by the node control unit and the output unit. It is longer than the effective channel length of TFTs.

The input unit includes a switch T1a and a switch T1b connected in series between the input terminal of the forward power voltage and the Q node to supply the forward power voltage to the Q node, and switched according to the first carry signal; and a switch connected in series between the input terminal of the reverse power voltage and the Q node to supply the reverse power voltage to the Q node, and includes a switch T2a and a switch T2b according to the second carry signal.

When driving a forward scan, the forward power supply voltage is input at an on level and the reverse power supply voltage is input at an off level. When driving a reverse scan, the forward power supply voltage is input at an off level and the reverse power supply voltage is input at an on level. The first carry signal becomes a start signal when driving the forward scan and a reset signal when driving the reverse scan, and the second carry signal becomes a reset signal when driving the forward scan and a start signal when driving the reverse scan. do.

The scan signal swings between a gate-on voltage and a first gate-off voltage, the carry signal swings between a gate-on voltage and a second gate-off voltage, and the first gate-off voltage is greater than the second gate-off voltage. higher and lower than the gate on voltage.

In addition, in order to achieve the above object, a gate driving circuit according to another embodiment of the present invention includes a plurality of stages that are dependently connected and output scan signals, and each of the stages receives a first signal input from a different stage. and an input unit that supplies a forward power voltage to the Q node and a reverse power supply voltage to the Q node according to the second carry signal; A node control unit that controls the voltage of the Q node and the voltage of the Qb node to be opposite to each other; and an output unit that outputs the scan signal and the carry signal according to the voltage of the Q node and the voltage of the Qb node, wherein the TFTs included in the input unit further include a light blocking layer, and the light blocking layer has a predetermined constant level. Negative bias is applied for a period of time.

The input unit includes a switch T1a and a switch T1b connected in series between the input terminal of the forward power voltage and the Q node to supply the forward power voltage to the Q node, and switched according to the first carry signal; and a switch T2a and a switch T2b connected in series between the input terminal of the reverse power voltage and the Q node to supply the reverse power voltage to the Q node, and switched according to the second carry signal.

The switch T1a includes a first light blocking layer, the switch T1b includes a second light blocking layer, the switch T2a includes a third light blocking layer, and the switch T2b includes a fourth light blocking layer. And the first to fourth light blocking layers are connected to the input terminal of the gate-off voltage.

The negative bias is applied to the first to fourth light blocking layers by the gate-off voltage.

The switch T1a includes a first light blocking layer, the switch T1b includes a second light blocking layer, the switch T2a includes a third light blocking layer, and the switch T2b includes a fourth light blocking layer. The first and second light blocking layers are connected to the input terminal of the first carry signal, and the third and fourth light blocking layers are connected to the input terminal of the second carry signal.

The negative bias is applied to the first and second light blocking layers while the first carry signal is maintained at an off level, and the third and fourth light blocking layers are applied while the second carry signal is maintained at an off level. The negative bias is applied to .

In addition, in order to achieve the above object, a gate driving circuit according to another embodiment of the present invention includes a plurality of stages that are dependently connected and output scan signals, and each of the stages is provided with a plurality of stages that are input from different stages. an input unit that supplies a forward power voltage to the Q node and a reverse power supply voltage to the Q node according to the first and second carry signals; A node control unit that controls the voltage of the Q node and the voltage of the Qb node to be opposite to each other; and an output unit that outputs the scan signal and the first and second carry signals according to the voltage of the Q node and the voltage of the Qb node, and the effective channel length of the TFTs included in the input unit is determined by the node control unit and the node control unit. It is longer than the effective channel length of the TFTs included in the output unit, and the TFTs included in the input unit further include a light blocking layer, and a negative bias is applied to the light blocking layer for a certain period of time.

A display device according to an embodiment of the present invention includes a display panel on which pixels connected to gate lines are arranged; and the gate driving circuit of any one of claims 1 to 13, which sequentially supplies scan signals to the gate lines.

The present invention designs the effective channel length of the input switch to be relatively long, and/or uses the light blocking layer of the input switch as a back gate to apply a negative bias to the light blocking layer for a certain period of time, thereby reducing the threshold voltage of the input switch. Leakage current characteristics can be improved by increasing .

The present invention improves the leakage current characteristics of the input switches controlled according to the carry signal, so that the input switches can be connected to the forward power voltage and reverse power supply voltage while ensuring driving stability, making it possible to easily implement bidirectional scan driving.

Figure 1 is a diagram schematically showing one stage that outputs a scan signal from a shift register of a conventional gate driving circuit.
FIG. 2 is a waveform diagram showing the operation of the stage shown in FIG. 1.
Figure 3 is a block diagram schematically showing a display device according to an embodiment of the present invention.
FIG. 4 is a diagram showing dependently connected stages in the GIP circuit of FIG. 3.
FIG. 5 is a circuit diagram showing the configuration of one stage of FIG. 4.
Figure 6 is a simulation result showing the relationship between the effective channel length and threshold voltage in the TFT constituting the GIP circuit.
Figure 7 is a cross-sectional view of a TFT constituting the GIP circuit.
Figures 8 and 9 are cross-sectional views showing example methods of varying the effective channel length of the TFT in the GIP circuit between the input part and other areas in order to minimize leakage current in the input part.
Figure 10 is another cross-sectional view of the TFT constituting the GIP circuit.
Figures 11 and 12 are circuit diagrams showing example methods of applying a negative bias to the light blocking layer to minimize leakage current of the input unit.
Figure 13 is a diagram for explaining forward scan driving.
Figure 14 is a diagram for explaining reverse scan driving.
FIG. 15 is a waveform diagram showing the operation of the stage shown in FIG. 5 during forward scan operation.
FIG. 16 is a waveform diagram showing the operation of the stage shown in FIG. 5 during reverse scan operation.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the attached drawings. Like reference numerals refer to substantially the same elements throughout the specification. In the following description, if it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description will be omitted.

The display device of the present invention can be implemented as a flat panel display device such as a liquid crystal display (LCD) or an organic light emitting diode display (OLED display). In the following embodiments, the description will focus on a liquid crystal display device as an example of a flat panel display device, but the present invention is not limited thereto. For example, the present invention can be applied to any display device including an in-cell touch sensor.

The switch elements in the gate driving circuit of the present invention may be implemented as transistors with an n-type or p-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure. Although an n-type transistor (NMOS) is illustrated in the following examples, it should be noted that the present invention is not limited thereto. A transistor is a three-electrode device including a gate, source, and drain. The source is an electrode that supplies carriers to the transistor. Within the transistor, carriers begin to flow from the source. The drain is the electrode through which carriers exit the transistor. That is, the flow of carriers in the MOSFET flows from the source to the drain. In the case of an n-type MOSFET (NMOS), because the carriers are electrons, the source voltage has a lower voltage than the drain voltage so that electrons can flow from the source to the drain. In an n-type MOSFET, since electrons flow from the source to the drain, the direction of current flows from the drain to the source. In the case of a p-type MOSFET (PMOS), since the carrier is a hole, the source voltage is higher than the drain voltage to allow holes to flow from the source to the drain. In a p-type MOSFET, current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of the MOSFET are not fixed. For example, the source and drain of a MOSFET can change depending on the applied voltage. In the following description of the embodiment, the source and drain of the transistor will be referred to as first and second electrodes. In the following description, it should be noted that the invention is not limited by the source and drain of the transistor.

The transistors constituting the GIP circuit of the present invention can be implemented with one or more of TFTs including Oxide TFT, a-Si TFT, and Low Temperature Poly Silicon (LTPS). In particular, when implemented with Oxide TFT, the effect is big.

3 and 4, the display device of the present invention includes a display panel 100 and a display for writing data of an input image into pixels of a pixel array 10 of the display panel 100. Includes a driving part.

The display panel 100 has data lines 12, gate lines 14 orthogonal to the data lines 12, and a matrix defined by the data lines 12 and the gate lines 14. It includes a pixel array 10 in which pixels are arranged. The pixel array 10 implements a screen on which an input image is displayed.

The pixels of the pixel array 10 may include red (R), green (G), and blue (B) subpixels to implement color. Each of the pixels may further include a white (W) subpixel in addition to the RGB subpixels.

The pixel array 10 of the display panel 100 can be divided into a TFT array and a color filter array. A TFT array may be formed on the lower panel of the display panel 100. The TFT array includes TFTs (Thin Film Transistors) formed at the intersections of the data lines 12 and the gate lines 14, a pixel electrode for charging the data voltage, and a storage capacitor connected to the pixel electrode to maintain the data voltage ( Displays the input image including Storage Capacitor, Cst), etc. An in-cell touch sensor may be disposed on the TFT array. In this case, the display device may further include a sensor driver for driving the in-cell touch sensor.

A color filter array may be formed on the upper or lower panel of the display panel 100. The color filter array includes a black matrix, a color filter, etc. In the case of the Color Filter on TFT (COT) or TFT on Color Filter (TOC) model, the color filter and black matrix along with the TFT array may be placed on one substrate.

The display driver includes a data driver 16 and gate drivers 18A, 18B, and 22, and writes data of the input image to pixels of the display panel 100.

The data driver 16 includes one or more source drive ICs. The source drive IC may be mounted on a chip on film (COF) and connected between the display panel 100 and a printed circuit board (PCB) 30. The source drive IC (SIC) may be directly attached to the substrate of the display panel 100 using a chip on glass (COG) process.

The data driver 16 converts the digital video data of the input image received from the timing controller (TCON) 20 into a gamma compensation voltage and outputs the data voltage. The data voltage output from the data driver 16 is supplied to the data lines 12. A multiplexer (not shown) may be placed between the data driver 16 and the data lines 12. The multiplexer distributes the data voltage input from the data driver 16 to the data lines 12 under the control of the timing controller 20. In the case of a 1:3 multiplexer, the multiplexer time-divides the data voltage input through one output channel of the data driver 16 and supplies it to two data lines. By using a 1:3 multiplexer, the number of channels in the data driver 16 can be reduced by 1/3.

The gate drivers 18A, 18B, and 22 include a level shifter (LS) 22 and GIP circuits 18A and 18B. The level shifter 22 is disposed between the timing controller 20 and the GIP circuits 18A and 18B. The GIP circuits 18A and 18B may be formed directly on the lower panel of the display panel 100 together with the TFT array.

GIP circuits 18A and 18B include shift registers. The GIP circuits 18A and 18B may be formed outside the pixel array on a bezel (BZ) at one edge of the display panel 100 or on bezels (BZ) at both edges. The level shifter 22 shifts the swing width of the gate timing control signal received from the timing controller 20 into a gate-on voltage and a gate-off voltage and outputs them to the GIP circuits 18A and 18B. In NMOS, the gate-on voltage is a gate-on voltage (VGH in FIG. 5) higher than the threshold voltage of NMOS, and the gate-off voltage is a gate-off voltage (VGL1 in FIG. 5) lower than the threshold voltage of NMOS. For PMOS, the gate-on voltage is the gate-off voltage (VGL1), and the gate-off voltage is the gate-on voltage (VGH). Hereinafter, the transistors of the GIP circuits 18A and 18B will be described focusing on NMOS, but the present invention is not limited thereto.

Each of the GIP circuits 18A and 18B shifts the scan signal (SC1 to SC(n+3)) according to the gate shift clock (CLK) and supplies the scan signal (SC1 to SC(n+3)) to the gate lines 14. ) are supplied sequentially. The gate shift clock (CLK) may be a 2-phase clock to an 8-phase clock, but is not limited thereto.

The scan signals (SC1 to SC(n+3)) output from the GIP circuits 18A and 18B swing between the gate-on voltage (VGH) and the first gate-off voltage (VGL1). The gate-on voltage (VGH) is higher than the pixel's TFT threshold voltage. The first gate-off voltage (VGL1) is lower than the gate-on voltage (VGH) and is also lower than the TFT threshold voltage of the pixel. The TFTs of the pixel are turned on according to the gate-on voltage (VGH) of the scan signals (SC1 to SC(n+3)) and supply the data voltage from the data line 12 to the pixel electrode.

The GIP circuits 18A and 18B may be disposed on the left and right sides of the display panel 100 with the pixel array 10 on the left and right. Left and right GIP circuits 18A, 18B are synchronized by timing controller 20. The left GIP circuit 18A is connected to the odd-numbered gate lines 14 of the pixel array 10 and can sequentially supply scan signals to the gate lines 14. The right GIP circuit 18B is connected to the even gate lines 14 of the pixel array 10 and can sequentially output scan signals to the gate lines 14. The left GIP circuit 18A and the right GIP circuit 18A may be connected to all gate lines and simultaneously supply scan signals to the same gate line.

The shift registers of the GIP circuits 18A and 18B are cascade connected through a carry signal wire through which the carry signal (CR) is transmitted, as shown in FIG. 4, and shift the scan signal according to the gate shift clock (CLK) timing. It includes stages (ST(1) to ST(n+3)). Each of the stages (ST(1) to ST(n+3)) sequentially supplies scan signals (SC1 to SC(n+3)) to the gate lines 14, and carries a carry signal (CR). ) is passed to another stage. The scan signal and carry signal can be the same signal output through one output terminal from each stage, or they can be separated through two output terminals from each stage. When the scan signal and the carry signal are separated through two output terminals, the gate shift clock (CLK) may include a scan shift clock for shifting the scan signal and a carry shift clock for shifting the carry signal. For stable operation, the gate-off voltages that constitute the scan shift clock and carry shift clock may be different. The gate-off voltage of the scan shift clock may be a first gate-off voltage (VGL1 in FIG. 5), and the gate-off voltage of the carry shift clock may be a second gate-off voltage (VGL1 in FIG. 5) lower than the first gate-off voltage (VGL1). It may be VGL2).

When the scan signal and the carry signal are separated through two output terminals, the carry signal is shifted according to the carry shift clock and may swing between the gate-on voltage (VGH) and the second gate-off voltage (VGL2). To ensure operational stability and reliability of the GIP circuits 18A and 18B, the second gate-off voltage VGL2 may be lower than the first gate-off voltage VGL1. Once the carry signal output from the stage is input to the start terminal of the other stage, it is used to activate the operation of the other stage. Meanwhile, the stage that transmits the carry signal (CR) is not limited to a specific stage. For example, the nth (n is a positive integer) stage can receive a carry signal output from the n-x (x is a positive integer) stage and a carry signal output from the n+xth stage, but is not limited to this. .

The shift registers of the GIP circuits 18A and 18B are configured so that the effective channel length of the TFTs included in the input section is longer than the effective channel length of the TFTs provided in other areas of each stage in order to prevent current leakage occurring in the input section of each stage. can be designed.

In addition, the shift registers of the GIP circuits 18A and 18B design the TFTs included in the input section to further include a light blocking layer to prevent current leakage occurring at the input section of each stage, and the light blocking layer has a negative effect for a certain period of time. It can be driven so that a bias (negative bias) is applied.

In addition, the shift registers of the GIP circuits 18A and 18B have the effective channel length of the TFTs included in the input section longer than the effective channel lengths of the TFTs provided in other areas of each stage in order to prevent current leakage occurring in the input section of each stage. In addition to being designed to be long, the TFTs included in the input unit are designed to include an additional light blocking layer, and the light blocking layer can be driven to apply a negative bias for a certain period of time.

The shift registers of the GIP circuits 18A and 18B may be designed to enable bidirectional scan operation. Bidirectional scan driving includes forward scan driving that sequentially supplies scan signals to the gate lines 14 from one side of the display panel 100 toward the other side, and supplying scan signals from the other side of the display panel 100 toward the one side. It includes reverse scan driving to sequentially supply gate lines 14.

The timing controller 20 transmits digital video data of an input image received from a host system (not shown) to the data driver 16. The timing controller 20 inputs timing signals such as a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a data enable signal (Data Enable, DE), and a main clock (MCLK) that are received in synchronization with the input image data. It outputs a data timing control signal for controlling the operation timing of the data driver 16 and a gate timing control signal for controlling the operation timing of the level shifter 22 and the GIP circuits 18A and 18B. The timing controller 20 and level shifter 22 may be mounted on the PCB 30.

The gate timing control signal includes a start pulse (VST), gate shift clock (Gate Shift Clock, CLK), and output enable signal (Gate Output Enable, GOE). The output enable signal (Gate Output Enable, GOE) can be omitted. The start pulse VST is input to the start terminal in the first stage of the GIP circuits 18A and 18B to control the output timing of the first scan signal that occurs first in one frame period. The gate shift clock CLK controls the shift timing of the scan signal by controlling the output timing of the scan signal in each of the stages of the GIP circuits 18A and 18B. Meanwhile, the gate shift clock CLK may control the shift timing of each scan signal and carry signal by controlling the output timing of each scan signal and carry signal at each stage of the GIP circuit 18A and 18B.

The host system may be implemented as any one of a television system, set-top box, navigation system, DVD player, Blu-ray player, personal computer (PC), home theater system, and phone system. The host system converts the digital video data of the input image into a format suitable for display on the display panel 100. The host system transmits timing signals (Vsync, Hsync, DE, MCLK) along with digital video data of the input image to the timing controller 20. The host system executes an application program linked to the coordinate information of the touch input received from the touch sensing unit.

FIG. 5 is a circuit diagram showing the configuration of one stage of FIG. 4.

Referring to FIG. 5, the nth stage (ST(n)) can be designed to enable bidirectional scan driving, and the scan signal (SC(n)) and carry signal (CR(n)) are connected to two output terminals ( It can be designed to be separated through No1, No2). If the scan signal (SC(n)) and the carry signal (CR(n)) are designed to be electrically separated, the carry signal (CR(n)) is not affected by the panel load, enabling more stable operation. That is, the rising and falling characteristics of the scan signal (SC(n)) and carry signal (CR(n)) are greatly improved.

Referring to FIG. 5, the nth stage (ST(n)) includes an input unit 110, a node control unit 120, and an output unit 130.

Referring to FIG. 5, the output unit 130 generates a scan signal (SC(n)) that swings between the gate-on voltage (VGH) and the first gate-off voltage (VGL1) according to the voltage of the Q node and the voltage of the Qb node. ) is output. For this purpose, the output unit 130 includes a switch To1, a switch To2, and a first capacitor C1.

Switch To1 is turned on when the voltage of the Q node increases to the boosting voltage and supplies the gate-on voltage (VGH) of the scan shift clock (SCCLK(n)) to the first output terminal (No1). The switch To1 includes a control electrode connected to the Q node, a first electrode connected to the input terminal of the scan shift clock SCCLK(n), and a second electrode connected to the first output terminal No1.

Switch To2 is turned on when the voltage of the Qb node becomes the gate-on voltage (VGH) and supplies the first gate-off voltage (VGL1) to the first output terminal (No1). The switch To2 includes a control electrode connected to the Qb node, a first electrode connected to the first output terminal No1, and a second electrode connected to the input terminal of the first gate-off voltage VGL1.

The first capacitor C1 is connected between the Q node and the first output terminal No1, and when the scan shift clock SCCLK(n) rises to the gate-on voltage VGH, the voltage of the Q node is converted to a boosting voltage. Raise it.

Meanwhile, the output unit 130 further outputs a carry signal (CR(n)) that swings between the gate-on voltage (VGH) and the second gate-off voltage (VGL2) depending on the voltage of the Q node and the voltage of the Qb node. can do. For this purpose, the output unit 130 includes a switch Tc1, a switch Tc2, and a second capacitor C2.

Switch Tc1 is turned on when the voltage of the Q node increases to the boosting voltage and supplies the gate-on voltage (VGH) of the carry shift clock (CRCLK(n)) to the second output terminal (No2). The switch Tc1 includes a control electrode connected to the Q node, a first electrode connected to the input terminal of the carry shift clock CRCLK(n), and a second electrode connected to the second output terminal No2.

Switch Tc2 is turned on when the voltage of the Qb node becomes the gate-on voltage (VGH) and supplies the second gate-off voltage (VGL2) to the second output terminal (No2). The switch Tc2 includes a control electrode connected to the Qb node, a first electrode connected to the second output terminal No2, and a second electrode connected to the input terminal of the second gate-off voltage VGL2.

The second capacitor C2 is connected between the Q node and the second output terminal No2, and when the carry shift clock CRCLK(n) rises to the gate-on voltage VGH, the voltage of the Q node is converted to a boosting voltage. Raise it.

When the voltage of the Q node is maintained above the gate-on voltage (VGH), the voltage of the Qb node is discharged to the second gate-off voltage (VGL2). During this period, switch To2 must be completely turned off so that the scan signal (SC(n)) can be output with the normal gate-on voltage (VGH). In order to prevent leakage current through switch To2, the gate-source voltage (Vgs) of switch To2 must be sufficiently lower than the threshold voltage (Vth) during this period. For this purpose, the second gate-off voltage (VGL2) is preferably set lower than the first gate-off voltage (VGL1).

Referring to FIG. 5, the node control unit 120 charges and discharges the Q node and Qb node in opposite directions between the gate-on voltage (VGH) and the second gate-off voltage (VGL2). The node control unit 120 includes a plurality of switches (T3, T4a, T4b, T5, T6, T7a, T7b, T8, T9a, and T9b).

Switch T3 is turned on according to the voltage of the Q node and supplies the gate-on voltage (VGH) to the first node (N1). Switch T3 includes a control electrode connected to the Q node, a first electrode connected to the input terminal of the gate-on voltage (VGH), and a second electrode connected to the first node (N1). Switch T4a and switch T4b are connected in series through the first node (N1), and are simultaneously turned on according to the voltage of the Qb node to discharge the Q node to the second gate-off voltage (VGL2). Switch T4a includes a control electrode connected to the Qb node, a first electrode connected to the Q node, and a second electrode connected to the first node N1. And, the switch T4b includes a control electrode connected to the Qb node, a first electrode connected to the first node N1, and a second electrode connected to the input terminal of the second gate-off voltage VGL2. Switch T5 is turned on according to the voltage of the Q node and discharges the Qb node to the second gate-off voltage (VGL2). Switch T5 includes a control electrode connected to the Q node, a first electrode connected to the Qb node, and a second electrode connected to the input terminal of the second gate-off voltage VGL2. Switch T6 is turned on according to the voltage of the second node (N2) and supplies the gate-on voltage (VGH) to the Qb node. Switch T6 includes a control electrode connected to the second node N2, a first electrode connected to the input terminal of the gate-on voltage VGH, and a second electrode connected to the Qb node. Switch T7a and switch T7b are connected in series through the second node (N2). Switch T7a is diode connected and supplies gate-on voltage (VGH) to the second node (N2). Switch T7b is turned on according to the voltage of the Q node and discharges the second node N2 to the second gate-off voltage VGL2. The switch T7b includes a control electrode connected to the Q node, a first electrode connected to the second node N2, and a second electrode connected to the input terminal of the second gate-off voltage VGL2. Switch T8 is turned on according to the voltage of the third node (N3) and discharges the Qb node to the second gate-off voltage (VGL2). Switch T8 includes a control electrode connected to the third node N3, a first electrode connected to the Qb node, and a second electrode connected to the input terminal of the second gate-off voltage VGL2. Switch T9a is turned on according to the other end carry signal (CR(n-x)) and supplies the forward power voltage (GVDD_F) to the third node (N3). Switch T9b is turned on according to the other end carry signal (CR(n+x)) and supplies the reverse power supply voltage (GVDD_R) to the third node (N3).

Referring to FIG. 5, the input unit 110 supplies the forward power voltage (GVDD_F) to the Q node according to the first and second carry signals (CR(n-x) and CR(n+x)) input from other stages. And, the reverse power supply voltage (GVDD_R) is supplied to the Q node. The input unit 110 includes switch T1a and switch T1b, and switch T2a and switch T2b.

Switch T1a and switch T1b are connected in series through the first node (N1), and are simultaneously turned on according to the first carry signal (CR(n-x)) input from the upper stage to apply the forward power voltage (GVDD_F) to the Q node. supply. Switch T1a includes a control electrode connected to the input terminal of the first carry signal (CR(n-x)), a first electrode connected to the input terminal of the forward power voltage (GVDD_F), and a second electrode connected to the first node (N1). Includes. The switch T1b includes a control electrode connected to the input terminal of the first carry signal CR(n-x), a first electrode connected to the first node N1, and a second electrode connected to the Q node.

Meanwhile, switch T2a and switch T2b are connected in series through the first node (N1) and are simultaneously turned on according to the second carry signal (CR(n+x)) input from the lower stage, thereby generating the reverse power supply voltage (GVDD_R). is supplied to the Q node. Switch T2a includes a control electrode connected to the input terminal of the second carry signal CR(n+x), a first electrode connected to the Q node, and a second electrode connected to the first node N1. Switch T2b includes a control electrode connected to the input terminal of the second carry signal CR(n+x), a first electrode connected to the first node N1, and a second electrode connected to the input terminal of the reverse power supply voltage GVDD_R. Contains electrodes.

The forward power supply voltage (GVDD_F) is input at an on level (high level) during forward scan driving, and is input at an off level (low level) during reverse scan driving. The reverse power supply voltage (GVDD_R) is input as an on level (high level) when driving a reverse scan, and input as an off level (low level) when driving a forward scan.

Therefore, the switch T1a and switch T1b charge the Q node by supplying the on-level forward power supply voltage (GVDD_F) to the Q node when driving the forward scan, and supply the forward power supply voltage (GVDD_F) at the off-level to the Q node when driving the reverse scan. to discharge the voltage at the Q node. In addition, switch T2a and switch T2b charge the Q node by supplying an on-level reverse power supply voltage (GVDD_R) to the Q node when driving the reverse scan, and supply an off-level reverse power supply voltage (GVDD_R) to the Q node when driving the forward scan. to discharge the voltage at the Q node.

Figure 6 is a simulation result showing the relationship between the effective channel length and threshold voltage in the TFT constituting the GIP circuit. Figure 7 is a cross-sectional view of a TFT constituting the GIP circuit.

Referring to FIG. 6, in the TFT constituting the GIP circuit, the effective channel length and threshold voltage are proportional to each other. In other words, as the effective channel length of the TFT increases, the threshold voltage of the TFT increases.

During the forward scan drive, the first carry signal CR(n-x) is also maintained at the second gate off level (VGL2) while the voltage of the Q node is maintained at the second gate off level (VGL2). During this period, switch T1a and switch T1b must be completely turned off to maintain the voltage of the Q node at the second gate-off level (VGL2). In order to prevent leakage current from occurring through switch T1a and switch T1b, the condition under which switch T1a and switch T1b can be completely turned off during this period is the threshold voltage (Vth) of switch T1a and switch T1b. It must satisfy conditions that are sufficiently higher than the gate-source voltage (Vgs).

To this end, the present invention designs the effective channel length of switches T1a and switch T1b, which are TFTs included in the input unit 110, to be longer than the effective channel length of the TFTs included in the node control unit 120 and the output unit 130, Relatively increase the threshold voltage (Vth) of T1a and switch T1b. If the leakage current is suppressed in switch T1a and switch T1b, the driving reliability margin for negative threshold voltage can be secured even if switch T1a is connected to the forward power supply voltage (GVDD_F) without connecting a diode. Through this, the present invention can easily implement bidirectional scan driving.

Additionally, during reverse scan driving, the second carry signal CR(n+x) is also maintained at the second gate-off level (VGL2) while the voltage of the Q node is maintained at the second gate-off level (VGL2). During this period, switch T2b must be completely turned off to maintain the voltage of the Q node at the second gate-off level (VGL2). In order to prevent leakage current from occurring through switch T2b, the condition is that switch T2b can be completely turned off during this period, that is, the threshold voltage (Vth) of switch T2b is sufficiently higher than the gate-source voltage (Vgs) of switch T2b. The conditions must be satisfied.

To this end, the present invention designs the effective channel length of switches T2a and switch T2b, which are the TFTs included in the input unit 110, to be longer than the effective channel length of the TFTs included in the node control unit 120 and the output unit 130, Relatively increase the threshold voltage (Vth) of T2a and switch T2b. If the leakage current is suppressed in switch T2a and switch T2b, the driving reliability margin for negative threshold voltage can be secured even if switch T2a is connected to the reverse power supply voltage (GVDD_R) without connecting a diode. Through this, the present invention can easily implement bidirectional scan driving.

Referring to FIG. 7, the TFT constituting the GIP circuit may be implemented with a top gate structure. TFTs with a top gate structure have the advantage of generating almost no parasitic capacitance between the gate electrode (G) and the source-drain electrodes (S-D). Therefore, the characteristics of the semiconductor channel layer (A) containing excellent metal oxide are not deteriorated and can be maintained for a long time.

The semiconductor layer includes a central channel layer (A), a source region (SA) disposed on the left side of the channel layer (A), and a drain region (DA) disposed on the right side of the channel layer (A).

A gate insulating film (GI) and a gate electrode (G) are formed on the channel layer (A) of the semiconductor layer. The gate insulating film (GI) and the gate electrode (G) have substantially the same size (L) as the channel layer (A) and have a structure that completely overlaps substantially vertically. An intermediate insulating film (IN) covers the semiconductor layer and the gate electrode (G). After the source region (SA) and drain region (DA) of the semiconductor layer undergo a conduction process, they penetrate the intermediate insulating film (IN) and contact the source electrode (S) and drain electrode (D), respectively. In this conductivity process, the effective channel length (Leff) is reduced by ΔL on each of the left and right sides of the channel layer (A) due to the introduction of impurities.

Figures 8 and 9 are cross-sectional views showing example methods of varying the effective channel length of the TFT in the GIP circuit between the input part and other areas in order to minimize leakage current in the input part.

As an example, the TFTs included in the input unit 110 use a different channel definition mask for the conduction process compared to the TFTs included in the node control unit 120 and the output unit 130 to determine the effective channel length relative to the TFTs included in the input unit 110. can be increased.

Specifically, as shown in (A) of FIG. 8, the TFTs included in the node control unit 120 and the output unit 130 perform a conduction process using the gate electrode (G) as a channel definition mask, thereby forming the first effective channel. It can have a length (Leff1). On the other hand, as shown in (B) of FIG. 8, the TFTs included in the input unit 110 perform a conduction process using a photo resistor (PR) larger than the gate electrode (G) as a channel definition mask, thereby reducing the first effective channel length. It may have a second effective channel length (Leff2) that is longer than (Leff1). The photo resistor (PR) is removed after the conductivity process. In Figure 8, a conductive process may be performed after the gate electrode (G) is formed.

Meanwhile, as shown in (A) of FIG. 9, the TFTs included in the node control unit 120 and the output unit 130 perform a conduction process using the first photo resistor (PR) as a channel definition mask, thereby forming the first effective It may have a channel length (Leff1). On the other hand, as shown in (B) of FIG. 9, the TFTs included in the input unit 110 perform a conduction process using the second photo resistor (PR2), which is larger than the first photo resistor (PR), as a channel definition mask. It may have a second effective channel length (Leff2) that is longer than the effective channel length (Leff1). The first and second photo resistors PR1 and PR2 are removed after the conduction process. In FIG. 9 , the conduction process may be performed first, followed by the formation process of the gate insulating film (GI) and the gate electrode (G).

Figure 10 is another cross-sectional view of the TFT constituting the GIP circuit.

Referring to FIG. 10, the TFTs included in the input unit 110 may be designed as a top gate structure further including a light blocking layer (LS). The light blocking layer (LS) can be formed longer than the length of the semiconductor layers (SA, A, DA) in consideration of light blocking efficiency, and can be insulated from the semiconductor layers (SA, A, DA) through the buffer layer (BUF). there is. Meanwhile, the TFTs included in the node control unit 120 and the output unit 130 may be designed with a top gate structure without a light blocking layer (LS).

If the TFTs included in the input unit 110 are designed with a top gate structure further equipped with a light blocking layer (LS), not only will almost no parasitic capacitance occur between the gate electrode (G) and the source-drain electrodes (S-D). , light coming from the bottom of the substrate (SUB) is blocked by the light blocking layer (LS). Therefore, the characteristics of the semiconductor channel layer (A) containing excellent metal oxide are not deteriorated and can be maintained for a long time. The remaining configuration is substantially the same as that described in FIG. 7.

By using this light blocking layer (LS) as a back gate and applying a negative bias to the light blocking layer (LS), the threshold voltage of the TFT can be increased, thereby eliminating leakage current through the TFT. .

Figures 11 and 12 are circuit diagrams showing example methods of applying a negative bias to the light blocking layer to minimize leakage current of the input unit.

As described in FIG. 5, the TFTs included in the input unit 110 include a switch T1a and a switch T1b that are switched according to the first carry signal (C(n-3)) and the second carry signal (C(n+3)). ) includes switch T2a and switch T2b, which are switched according to ).

Switch T1a includes a first light blocking layer (LS1), switch T1b includes a second light blocking layer (LS2), switch T2a includes a third light blocking layer (LS3), and switch T2b includes a fourth light blocking layer (LS3). Includes a light blocking layer (LS4).

Referring to FIG. 11, in order to apply a negative bias to the light blocking layer LS for a certain period of time, the first to fourth light blocking layers LS1 to LS4 may be connected to the input terminal of the gate-off voltage VGL2. there is. In this way, when the first to fourth light blocking layers (LS1 to LS4) are connected to the input terminal of the gate-off voltage (VGL2), the first to fourth light-blocking layers (LS1 to LS4) are affected by the gate-off voltage (VGL2) during forward scan driving and reverse scan driving, respectively. 4 A negative bias may be applied to the light blocking layers (LS1 to LS4). Due to this negative bias, the threshold voltage of the TFTs included in the input unit 110 increases, so leakage current through the TFTs can be prevented.

Meanwhile, the configuration of FIG. 11 can be applied together with the configuration described in FIGS. 6 to 9. If the configuration of FIG. 11 is applied together with the configuration of FIGS. 6 to 9, the threshold voltage of the TFTs included in the input unit 110 can be further increased, and thus leakage current through the TFTs can be more effectively prevented.

Referring to FIG. 12, in order to apply a negative bias to the light blocking layer LS for a certain period of time, the first and second light blocking layers LS1 and LS2 are connected to the first carry signal C(n-3). and the third and fourth light blocking layers LS3 and LS4 may be connected to the input terminal of the second carry signal C(n+3).

When the first and second light blocking layers LS1 and LS2 are connected to the input terminal of the first carry signal C(n-3), the first carry signal C( While n-3)) is maintained at the off level, a negative bias corresponding to the off level may be applied to the first and second light blocking layers LS1 and LS2.

And, when the third and fourth light blocking layers LS3 and LS4 are connected to the input terminal of the second carry signal C(n+3), the second carry signal ( While C(n+3)) is maintained at the off level, a negative bias corresponding to the off level may be applied to the third and fourth light blocking layers LS3 and LS4.

Due to this negative bias, the threshold voltage of the TFTs included in the input unit 110 increases, so leakage current through the TFTs can be prevented.

Meanwhile, the configuration of FIG. 12 can be applied together with the configuration described in FIGS. 6 to 9. If the configuration of FIG. 12 is applied together with the configuration of FIGS. 6 to 9, the threshold voltage of the TFTs included in the input unit 110 can be further increased, and thus leakage current through the TFTs can be more effectively prevented.

Figure 13 is a diagram for explaining forward scan driving.

Referring to FIG. 13, during forward scan driving, the forward power supply voltage (GVDD_F) is input at an on level (high level), and the reverse power supply voltage (GVDD_R) is input at an off level (low level).

When driving the forward scan, according to the first carry signal (CR(n-3)) input from the upper stage, switch T1a and switch T1b are turned on and supply the forward power voltage (GVDD_F) at the on level to the Q node, Charges the Q node of the stage (ST(n)).

When driving the forward scan, according to the second carry signal (CR(n+3)) input from the lower stage, switch T2a and switch T2b are turned on and supply the off-level reverse power supply voltage (GVDD_R) to the Q node, Discharges the Q node of the stage (ST(n)).

During this forward scan operation, scan signals are sequentially supplied from the top to the bottom of the display panel. That is, the scanning direction is from top to bottom.

Figure 14 is a diagram for explaining reverse scan driving.

Referring to FIG. 14, during reverse scan driving, the reverse power supply voltage (GVDD_R) is input at an on level (high level), and the forward power supply voltage (GVDD_R) is input at an off level (low level).

During reverse scan operation, according to the second carry signal (CR(n+3)) input from the lower stage, switch T2a and switch T2b are turned on and supply the reverse power supply voltage (GVDD_R) at the on level (high level) to the Q node. Thus, the Q node of the nth stage (ST(n)) is charged.

During reverse scan operation, switch T1a and switch T1b are turned on according to the first carry signal (CR(n-3)) input from the upper stage and supply the off-level (low level) forward power voltage (GVDD_F) to the Q node. Thus, the Q node of the nth stage (ST(n)) is discharged.

During this reverse scan operation, scan signals are sequentially supplied from the bottom to the top of the display panel. That is, the scanning direction is from bottom to top.

FIG. 15 is a waveform diagram showing the operation of the nth stage shown in FIG. 5 during forward scan driving.

Referring to FIG. 15, the forward scan drive includes a first precharging period (①), a bootstrapping period (②), a second precharging period (③), and a holding period (④).

During the first precharging period (①), the switches (T1a, T1b, T3, T7a, T7b, T5, T8, T9a, Tc1, To1) are turned on, and the switches (T2a, T2b, T4a, T4b, T6) are turned on. ,T9b,Tc2,Toe) are turned off. During the first precharging period (①), the Q node is precharged with the gate-on voltage (VGH), and the Qb node is discharged with the second gate-off voltage (VGL2). The switches T1a and T1b are turned off when the first carry signal CR(n-3) is polled to the second gate-off voltage VGL2 within the first precharging period ①.

During the bootstrapping period (②), the switches (T3, T7a, T7b, T5, T8, Tc1, To1) are turned on, and the switches (T1a, T1b, T2a, T2b, T4a, T4b, T6, T9a, T9b, Tc2, To2) are turned off. During the bootstrapping period (②), when the carry shift clock (CRCLK(n)) and scan shift clock (SCCLK(n)) of the gate-on voltage (VGH) are input, the first and second capacitors (C1, C2) ), the voltage of the Q node is bootstrapped to the boosting level (VBST). As a result, the gate-on voltage (VGH) of the scan sheet clock (SCCLK(n)) is supplied to the first output terminal (No1), and the scan signal (SC(n)) of the gate-on voltage (VGH) is output. Then, the gate-on voltage (VGH) of the carry shift clock (CRCLK(n)) is supplied to the second output terminal (No2), and the carry signal (CR(n)) of the gate-on voltage (VGH) is output.

During the second precharging period (③), the switches (T3, T7a, T7b, T5, T8, Tc1, To1) are turned on, and the switches (T1a, T1b, T2a, T2b, T4a, T4b, T6, T9a) are turned on. ,T9b,Tc2,To2) are turned off. During the second precharging period (③), the scan shift clock (SCCLK(n)) is polled to the first gate-off voltage (VGL1), and the carry shift clock (CRCLK(n)) is polled to the second gate-off voltage (VGL2). ), the voltage at the Q node is lowered to the gate-on voltage (VGH).

During the holding period (④), switches (T2a, T2b, T4a, T4b, T6, T7a, T9b, Tc2, To2) are turned on, and switches (T1a, T1b, T3, T5, T7b, T8, T9a, Tc1) are turned on. ,To1) is turned off. During the holding period (④), the Qb node is charged to the gate-on voltage (VGH) in synchronization with the second carry signal (CR(n+3)), and the Q node is discharged to the second gate-off voltage (VGL2). During the holding period (④), the first gate-off voltage (VGL1) is supplied to the first output terminal (No1), and the scan signal (SC(n)) of the first gate-off voltage (VGL1) is output. Then, during the holding period (④), the second gate-off voltage (VGL2) is supplied to the second output terminal (No2), and the carry signal (CR(n)) of the second gate-off voltage (VGL2) is output.

FIG. 16 is a waveform diagram showing the operation of the nth stage shown in FIG. 5 during reverse scan driving.

Referring to FIG. 16, reverse scan driving includes a first precharging period (①), a bootstrapping period (②), a second precharging period (③), and a holding period (④).

During the first precharging period (①), the switches (T2a, T2b, T3, T5, T7a, T7b, T8, T9b, Tc1, To1) are turned on, and the switches (T1a, T1b, T4a, T4b, T6) are turned on. ,T9a,Tc2,Toe) are turned off. During the first precharging period (①), the Q node is precharged with the gate-on voltage (VGH), and the Qb node is discharged with the second gate-off voltage (VGL2). The switches T2a and T2b are turned off when the second carry signal CR(n+3) is polled to the second gate-off voltage VGL2 within the first precharging period ①.

During the bootstrapping period (②), the switches (T3, T7a, T7b, T5, T8, Tc1, To1) are turned on, and the switches (T1a, T1b, T2a, T2b, T4a, T4b, T6, T9a, T9b, Tc2, To2) are turned off. During the bootstrapping period (②), when the carry shift clock (CRCLK(n)) and scan shift clock (SCCLK(n)) of the gate-on voltage (VGH) are input, the first and second capacitors (C1, C2) ), the voltage of the Q node is bootstrapped to the boosting level (VBST). As a result, the gate-on voltage (VGH) of the scan sheet clock (SCCLK(n)) is supplied to the first output terminal (No1), and the scan signal (SC(n)) of the gate-on voltage (VGH) is output. Then, the gate-on voltage (VGH) of the carry shift clock (CRCLK(n)) is supplied to the second output terminal (No2), and the carry signal (CR(n)) of the gate-on voltage (VGH) is output.

During the second precharging period (③), the switches (T3, T7a, T7b, T5, T8, Tc1, To1) are turned on, and the switches (T1a, T1b, T2a, T2b, T4a, T4b, T6, T9a) are turned on. ,T9b,Tc2,To2) are turned off. During the second precharging period (③), the scan shift clock (SCCLK(n)) is polled to the first gate-off voltage (VGL1), and the carry shift clock (CRCLK(n)) is polled to the second gate-off voltage (VGL2). ), the voltage at the Q node is lowered to the gate-on voltage (VGH).

During the holding period (④), switches (T1a, T1b, T4a, T4b, T6, T7a, T9a, Tc2, To2) are turned on, and switches (T2a, T2b, T3, T5, T7b, T8, T9b, Tc1) are turned on. ,To1) is turned off. During the holding period (④), the Qb node is charged to the gate-on voltage (VGH) in synchronization with the first carry signal (CR(n-3)), and the Q node is discharged to the second gate-off voltage (VGL2). During the holding period (④), the first gate-off voltage (VGL1) is supplied to the first output terminal (No1), and the scan signal (SC(n)) of the first gate-off voltage (VGL1) is output. Then, during the holding period (④), the second gate-off voltage (VGL2) is supplied to the second output terminal (No2), and the carry signal (CR(n)) of the second gate-off voltage (VGL2) is output.

As described above, the present invention designs the effective channel length of the input switches to be relatively long, and/or uses the light blocking layer of the input switch as a back gate to apply a negative bias to the light blocking layer for a certain period of time, Leakage current characteristics can be improved by increasing the threshold voltage of the input switches.

Furthermore, the present invention improves the leakage current characteristics of the input switches controlled according to the carry signal, so that the input switches can be connected to the forward power voltage and reverse power supply voltage while ensuring driving stability, making it possible to easily implement bidirectional scan driving. there is.

Through the above-described content, those skilled in the art will be able to see that various changes and modifications can be made without departing from the technical idea of the present invention. Therefore, the technical scope of the present invention should not be limited to what is described in the detailed description of the specification, but should be defined by the scope of the patent claims.

16: data driver 18A, 18B: GIP circuit (gate driver)
20: Timing controller 22: Level shifter (gate driver)
100: display panel 110: input unit
120: node control unit 130: output unit

Claims (14)

Equipped with a plurality of stages that are dependently connected and output scan signals,
Each of the above stages is
an input unit that supplies a forward power supply voltage to the Q node and a reverse power supply voltage to the Q node in accordance with first and second carry signals input from different stages;
A node control unit that controls the voltage of the Q node and the voltage of the Qb node to be opposite to each other; and
An output unit that outputs the scan signal and the carry signal according to the voltage of the Q node and the voltage of the Qb node,
The effective channel length of the TFTs included in the input unit is longer than the effective channel length of the TFTs included in the node control unit and the output unit,
The input unit,
Switches T1a and T1b connected in series between the input terminal of the forward power voltage and the Q node to supply the forward power voltage to the Q node, and switched according to the first carry signal; and
A gate driving circuit connected in series between the input terminal of the reverse power voltage and the Q node to supply the reverse power voltage to the Q node, and including a switch T2a and a switch T2b according to the second carry signal. delete According to claim 1,
When driving a forward scan, the forward power supply voltage is input at an on level and the reverse power supply voltage is input at an off level,
When driving a reverse scan, the forward power supply voltage is input at an off level and the reverse power supply voltage is input at an on level,
The first carry signal becomes a start signal when driving the forward scan and a reset signal when driving the reverse scan,
A gate driving circuit wherein the second carry signal becomes a reset signal when driving the forward scan and becomes a start signal when driving the reverse scan. According to claim 1,
the scan signal swings between a gate-on voltage and a first gate-off voltage,
the carry signal swings between a gate-on voltage and a second gate-off voltage,
A gate driving circuit wherein the first gate-off voltage is higher than the second gate-off voltage and lower than the gate-on voltage. Equipped with a plurality of stages that are dependently connected and output scan signals,
Each of the above stages is
an input unit that supplies a forward power supply voltage to the Q node and a reverse power supply voltage to the Q node in accordance with first and second carry signals input from different stages;
A node control unit that controls the voltage of the Q node and the voltage of the Qb node to be opposite to each other; and
An output unit that outputs the scan signal and the carry signal according to the voltage of the Q node and the voltage of the Qb node,
The TFTs included in the input unit further include a light blocking layer,
A gate driving circuit in which a negative bias is applied to the light blocking layer for a certain period of time. According to claim 5,
The input unit,
Switches T1a and T1b connected in series between the input terminal of the forward power voltage and the Q node to supply the forward power voltage to the Q node, and switched according to the first carry signal; and
A gate driving circuit comprising a switch T2a and a switch T2b connected in series between the input terminal of the reverse power voltage and the Q node to supply the reverse power voltage to the Q node, and switched according to the second carry signal. According to claim 6,
The switch T1a includes a first light blocking layer, the switch T1b includes a second light blocking layer, the switch T2a includes a third light blocking layer, and the switch T2b includes a fourth light blocking layer. And
A gate driving circuit in which the first to fourth light blocking layers are connected to an input terminal of a gate-off voltage. According to claim 7,
A gate driving circuit in which the negative bias is applied to the first to fourth light blocking layers by the gate-off voltage. According to claim 6,
The switch T1a includes a first light blocking layer, the switch T1b includes a second light blocking layer, the switch T2a includes a third light blocking layer, and the switch T2b includes a fourth light blocking layer. And
The first and second light blocking layers are connected to the input terminal of the first carry signal, and the third and fourth light blocking layers are connected to the input terminal of the second carry signal. According to clause 9,
The negative bias is applied to the first and second light blocking layers while the first carry signal is maintained at an off level,
A gate driving circuit in which the negative bias is applied to the third and fourth light blocking layers while the second carry signal is maintained at an off level. According to claim 6,
When driving a forward scan, the forward power supply voltage is input at an on level and the reverse power supply voltage is input at an off level,
When driving a reverse scan, the forward power supply voltage is input at an off level and the reverse power supply voltage is input at an on level,
The first carry signal becomes a start signal when driving the forward scan and a reset signal when driving the reverse scan,
A gate driving circuit wherein the second carry signal becomes a reset signal when driving the forward scan and becomes a start signal when driving the reverse scan. According to claim 5,
the scan signal swings between a gate-on voltage and a first gate-off voltage,
the carry signal swings between a gate-on voltage and a second gate-off voltage,
A gate driving circuit wherein the first gate-off voltage is higher than the second gate-off voltage and lower than the gate-on voltage. Equipped with a plurality of stages that are dependently connected and output scan signals,
Each of the above stages is
an input unit that supplies a forward power supply voltage to the Q node and a reverse power supply voltage to the Q node in accordance with first and second carry signals input from different stages;
A node control unit that controls the voltage of the Q node and the voltage of the Qb node to be opposite to each other; and
An output unit outputting the scan signal and the first and second carry signals according to the voltage of the Q node and the voltage of the Qb node,
The effective channel length of the TFTs included in the input unit is longer than the effective channel length of the TFTs included in the node control unit and the output unit,
A gate driving circuit wherein the TFTs included in the input unit further include a light blocking layer, and a negative bias is applied to the light blocking layer for a certain period of time. A display panel on which pixels connected to gate lines are arranged; and
A display device comprising the gate driving circuit of any one of claims 1 and 3 to 13, which sequentially supplies scan signals to the gate lines.