CN115244610B

CN115244610B - Shift register and driving method thereof, grid driving circuit and display device

Info

Publication number: CN115244610B
Application number: CN202080003719.4A
Authority: CN
Inventors: 冯雪欢; 李永谦
Original assignee: BOE Technology Group Co Ltd; Hefei BOE Zhuoyin Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei BOE Zhuoyin Technology Co Ltd
Priority date: 2020-12-26
Filing date: 2020-12-26
Publication date: 2023-11-28
Anticipated expiration: 2040-12-26
Also published as: CN117496894A; US11848064B2; US20230148117A1; US20240071541A1; WO2022134114A1; CN115244610A

Abstract

A shift register (100), comprising: the anti-creeping device comprises a first scanning unit (1), an anti-creeping unit (3) and an anti-creeping input unit (4). The first scanning unit (1) includes: a first input circuit (101) configured to transmit an input signal to a first pull-up node (Q1). The anti-leakage input unit (4) is electrically connected with the first voltage signal end (VDD_A), the second voltage signal end (VDD_B) and the anti-leakage input node (M); the anti-leakage input unit (4) is configured to transmit a first voltage signal to the anti-leakage input node (M) in response to the first voltage signal received at the first voltage signal terminal (vdd_a); or, in response to a second voltage signal received at a second voltage signal terminal (vdd_b), transmitting the second voltage signal to the anti-leakage input node (M). The first voltage signal and the second voltage signal are mutually opposite signals. The anti-leakage unit (3) is electrically connected with the first pull-up node (Q1), the first anti-leakage node (OFF 1) and the anti-leakage input node (M); the anti-leakage unit (3) is configured to transmit a first voltage signal or a second voltage signal from the anti-leakage input node (M) to the first anti-leakage node (OFF 1).

Description

Shift register and driving method thereof, grid driving circuit and display device

Technical Field

The disclosure relates to the technical field of display, and in particular relates to a shift register, a driving method thereof, a gate driving circuit and a display device.

Background

The gate driving circuit (also referred to as a scan driving circuit) is an important component in the display device. The gate driving circuit may include a multi-stage cascade of shift registers, each stage of shift registers being electrically connected to a row of gate lines in the display device, respectively. The gate driving circuit may input a scanning signal (may also be referred to as a gate signal) into a plurality of gate lines in the display device line by line, and respectively drive each row of sub-pixels in the display device to perform display scanning, so that the display device can perform image display.

The gate driving circuit is arranged in the display device, so that the cost can be effectively reduced, and the yield can be improved.

Disclosure of Invention

In one aspect, a shift register is provided. The shift register includes: the device comprises a first scanning unit, an anti-creeping unit and an anti-creeping input unit. The first scanning unit includes: the first input circuit is electrically connected with the input signal end, the first pull-up node and the first anti-leakage node; the first input circuit is configured to transmit an input signal received at the input signal terminal to the first pull-up node in response to the input signal. The anti-leakage input unit is electrically connected with the first voltage signal end, the second voltage signal end and the anti-leakage input node; the anti-leakage input unit is configured to transmit a first voltage signal received at the first voltage signal terminal to the anti-leakage input node in response to the first voltage signal; or, transmitting a second voltage signal received at the second voltage signal terminal to the anti-leakage input node in response to the second voltage signal; wherein the first voltage signal and the second voltage signal are mutually inverted signals. The anti-creeping unit is electrically connected with the first pull-up node, the first anti-creeping node and the anti-creeping input node; the anti-leakage unit is configured to transmit a first voltage signal or a second voltage signal from the anti-leakage input node to the first anti-leakage node under control of a voltage of the first pull-up node.

In some embodiments, the anti-creeping input unit includes: the first anti-creeping input circuit and the second anti-creeping input circuit. The first anti-leakage input circuit is electrically connected with the first voltage signal end and the anti-leakage input node; the first anti-leakage input circuit is configured to transmit a first voltage signal received at the first voltage signal terminal to the anti-leakage input node in response to the first voltage signal. The second anti-leakage input circuit is electrically connected with the second voltage signal end and the anti-leakage input node; the second anti-leakage input circuit is configured to transmit a second voltage signal received at the second voltage signal terminal to the anti-leakage input node in response to the second voltage signal.

In some embodiments, the first anti-leakage input circuit comprises: a first transistor. The control electrode of the first transistor is electrically connected with the first voltage signal end, the first electrode of the first transistor is electrically connected with the first voltage signal end, and the second electrode of the first transistor is electrically connected with the anti-leakage input node. The second anticreep input circuit includes: and a second transistor. The control electrode of the second transistor is electrically connected with the second voltage signal end, the first electrode of the second transistor is electrically connected with the second voltage signal end, and the second electrode of the second transistor is electrically connected with the anti-leakage input node.

In some embodiments, the anti-creeping unit includes: the first anticreep circuit. The first anti-leakage circuit is electrically connected with the first pull-up node, the anti-leakage input node and the first anti-leakage node; the first anti-leakage circuit is configured to transmit the first voltage signal or the second voltage signal from the anti-leakage input node to the first anti-leakage node under control of a voltage of the first pull-up node.

In some embodiments, the first anti-leakage circuit comprises: and a third transistor. The control electrode of the third transistor is electrically connected with the first pull-up node, the first electrode of the third transistor is electrically connected with the anti-leakage input node, and the second electrode of the third transistor is electrically connected with the first anti-leakage node.

In some embodiments, the shift register further comprises: and a second scanning unit. The second scanning unit includes: the second input circuit is electrically connected with the input signal end, the second pull-up node and the second anti-leakage node; the second input circuit is configured to transmit an input signal received at the input signal terminal to the second pull-up node in response to the input signal. The anti-creeping unit is also electrically connected with the second pull-up node and the second anti-creeping node; the anti-leakage unit is further configured to transmit a first voltage signal or a second voltage signal from the anti-leakage input node to the second anti-leakage node under control of the voltage of the second pull-up node.

In some embodiments, the anti-creeping unit further comprises: and a second anti-leakage circuit. The second anti-leakage circuit is electrically connected with the second pull-up node, the anti-leakage input node and the second anti-leakage node; the second anti-leakage circuit is configured to transmit the first voltage signal or the second voltage signal from the anti-leakage input node to the second anti-leakage node under control of a voltage of the second pull-up node.

In some embodiments, the second anti-leakage circuit includes: and a fourth transistor. The control electrode of the fourth transistor is electrically connected with the second pull-up node, the first electrode of the fourth transistor is electrically connected with the anti-leakage input node, and the second electrode of the fourth transistor is electrically connected with the second anti-leakage node.

In some embodiments, the first scanning unit further comprises: the first output circuit is electrically connected with the first pull-up node, the first clock signal end, the second clock signal end, the shift signal end and the first scanning signal end; the first output circuit is configured to transmit a first clock signal received at the first clock signal terminal to the shift signal terminal under control of a voltage of the first pull-up node; and transmitting the second clock signal received at the second clock signal terminal to the first scan signal terminal under control of the voltage of the first pull-up node. In the case where the shift register further includes a second scanning unit, the second scanning unit further includes: the second output circuit is electrically connected with the second pull-up node, the third clock signal end and the second scanning signal end; the second output circuit is configured to transmit a third clock signal received at the third clock signal terminal to the second scan signal terminal under control of a voltage of the second pull-up node.

In some embodiments, the first input circuit comprises: a fifth transistor and a sixth transistor. The control electrode of the fifth transistor is electrically connected with the input signal end, the first electrode of the fifth transistor is electrically connected with the input signal end, and the second electrode of the fifth transistor is electrically connected with the first electrode of the sixth transistor and the first anti-leakage node. The control electrode of the sixth transistor is electrically connected with the input signal end, and the second electrode of the sixth transistor is electrically connected with the first pull-up node. The first output circuit includes: a seventh transistor, an eighth transistor, and a first capacitor. The control electrode of the seventh transistor is electrically connected with the first pull-up node, the first electrode of the seventh transistor is electrically connected with the first clock signal end, and the second electrode of the seventh transistor is electrically connected with the shift signal end. The control electrode of the eighth transistor is electrically connected with the first pull-up node, the first electrode of the eighth transistor is electrically connected with the second clock signal end, and the second electrode of the eighth transistor is electrically connected with the first scanning signal end. The first end of the first capacitor is electrically connected with the first pull-up node, and the second end of the first capacitor is electrically connected with the first scanning signal end. The second input circuit includes: a ninth transistor and a tenth transistor. The control electrode of the ninth transistor is electrically connected with the input signal end, the first electrode of the ninth transistor is electrically connected with the input signal end, and the second electrode of the ninth transistor is electrically connected with the first electrode of the tenth transistor and the second anti-leakage node. The control electrode of the tenth transistor is electrically connected with the input signal end, and the second electrode of the tenth transistor is electrically connected with the second pull-up node. The second output circuit includes: an eleventh transistor and a second capacitor. The control electrode of the eleventh transistor is electrically connected with the second pull-up node, the first electrode of the eleventh transistor is electrically connected with the third clock signal end, and the second electrode of the eleventh transistor is electrically connected with the second scanning signal end. The first end of the second capacitor is electrically connected with the second pull-up node, and the second end of the second capacitor is electrically connected with the second scanning signal end.

In some embodiments, the first output circuit is further electrically connected to a fifth clock signal terminal and a first sense signal terminal; the first output circuit is further configured to transmit a fifth clock signal received at the fifth clock signal terminal to the first sense signal terminal under control of a voltage of the first pull-up node. The second output circuit is also electrically connected with a sixth clock signal end and a second sensing signal end; the second output circuit is further configured to transmit a sixth clock signal received at the sixth clock signal terminal to the second sense signal terminal under control of a voltage of the second pull-up node.

In some embodiments, the first output circuit further comprises: a fifth transistor and a fourth capacitor. The control electrode of the fifty-second transistor is electrically connected with the first pull-up node, the first electrode of the fifty-second transistor is electrically connected with the fifth clock signal terminal, and the second electrode of the fifty-second transistor is electrically connected with the first sensing signal terminal. The first end of the fourth capacitor is electrically connected with the first pull-up node, and the second end of the fourth capacitor is electrically connected with the first sensing signal end. The second output circuit further includes: a thirteenth transistor and a fifth capacitor. The control electrode of the fifty-third transistor is electrically connected to the second pull-up node, the first electrode of the fifty-third transistor is electrically connected to the sixth clock signal terminal, and the second electrode of the fifty-third transistor is electrically connected to the second sensing signal terminal. The first end of the fifth capacitor is electrically connected with the second pull-up node, and the second end of the fifth capacitor is electrically connected with the second sensing signal end.

In some embodiments, the first scanning unit further comprises: the first control circuit is electrically connected with the first pull-up node, the first voltage signal end, the first pull-down node and the third voltage signal end; the first control circuit is configured to control the voltage of the first pull-down node under the control of the voltage of the first pull-up node and the first voltage signal transmitted by the first voltage signal terminal. In the case where the shift register further includes a second scanning unit, the second scanning unit further includes: the second control circuit is electrically connected with the second pull-up node, the second voltage signal end, the second pull-down node and the third voltage signal end; the second control circuit is configured to control the voltage of the second pull-down node under the control of the voltage of the second pull-up node and the second voltage signal transmitted by the second voltage signal terminal.

In some embodiments, the first control circuit comprises: a twelfth transistor, a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor. The control electrode of the twelfth transistor is electrically connected with the first voltage signal end, the first electrode of the twelfth transistor is electrically connected with the first voltage signal end, and the second electrode of the twelfth transistor is electrically connected with the control electrode of the thirteenth transistor and the first electrode of the fourteenth transistor. The first pole of the thirteenth transistor is electrically connected to the first voltage signal terminal, and the second pole of the thirteenth transistor is electrically connected to the first pull-down node and the first pole of the fifteenth transistor. The control electrode of the fourteenth transistor is electrically connected with the first pull-up node, and the second electrode of the fourteenth transistor is electrically connected with the third voltage signal terminal. The control electrode of the fifteenth transistor is electrically connected with the first pull-up node, and the second electrode of the fifteenth transistor is electrically connected with the third voltage signal terminal. The second control circuit includes: a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, and a nineteenth transistor. The control electrode of the sixteenth transistor is electrically connected with the second voltage signal terminal, the first electrode of the sixteenth transistor is electrically connected with the second voltage signal terminal, and the second electrode of the sixteenth transistor is electrically connected with the control electrode of the seventeenth transistor and the first electrode of the eighteenth transistor. The first pole of the seventeenth transistor is electrically connected to the second voltage signal terminal, and the second pole of the seventeenth transistor is electrically connected to the second pull-down node and the first pole of the nineteenth transistor. The control electrode of the eighteenth transistor is electrically connected with the second pull-up node, and the second electrode of the eighteenth transistor is electrically connected with the third voltage signal terminal. The control electrode of the nineteenth transistor is electrically connected with the second pull-up node, and the second electrode of the nineteenth transistor is electrically connected with the third voltage signal terminal.

In some embodiments, the first scanning unit further comprises: the first reset circuit is electrically connected with the first pull-down node, the first pull-up node, the third voltage signal end and the first anti-leakage node; the first reset circuit is configured to reset the first pull-up node under control of a voltage of the first pull-down node. In the case that the shift register further includes a second scan cell, the first reset circuit is further electrically connected to the second pull-down node; the first reset circuit is further configured to reset the first pull-up node under control of a voltage of the second pull-down node. The second scanning unit further includes: the second reset circuit is electrically connected with the first pull-down node, the second pull-up node, the third voltage signal end and the second anti-leakage node; the second reset circuit is configured to reset the second pull-up node under control of a voltage of the first pull-down node or a voltage of the second pull-down node.

In some embodiments, the first reset circuit comprises: a twentieth transistor and a twenty-first transistor. The control electrode of the twentieth transistor is electrically connected with the first pull-down node, the first electrode of the twentieth transistor is electrically connected with the first pull-up node, and the second electrode of the twentieth transistor is electrically connected with the first electrode of the twenty-first transistor and the first anti-leakage node. The control electrode of the twenty-first transistor is electrically connected with the first pull-down node, and the second electrode of the twenty-first transistor is electrically connected with the third voltage signal terminal. In the case where the shift register further includes a second scan cell, the first reset circuit further includes: a twenty-second transistor and a twenty-third transistor. The control electrode of the twenty-second transistor is electrically connected with the second pull-down node, the first electrode of the twenty-second transistor is electrically connected with the first pull-up node, and the second electrode of the twenty-second transistor is electrically connected with the first electrode of the twenty-third transistor and the first anti-leakage node. The control electrode of the twenty-third transistor is electrically connected with the second pull-down node, and the second electrode of the twenty-third transistor is electrically connected with the third voltage signal end. The second reset circuit includes: a twenty-fourth transistor, a twenty-fifth transistor, a twenty-sixth transistor, and a twenty-seventh transistor. The control electrode of the twenty-fourth transistor is electrically connected with the first pull-down node, the first electrode of the twenty-fourth transistor is electrically connected with the second pull-up node, and the second electrode of the twenty-fourth transistor is electrically connected with the first electrode of the twenty-sixth transistor and the second anti-leakage node. The control electrode of the twenty-fifth transistor is electrically connected with the second pull-down node, the first electrode of the twenty-fifth transistor is electrically connected with the second pull-up node, and the second electrode of the twenty-fifth transistor is electrically connected with the first electrode of the twenty-seventh transistor and the second anti-leakage node. The control electrode of the twenty-sixth transistor is electrically connected with the first pull-down node, and the second electrode of the twenty-sixth transistor is electrically connected with the third voltage signal terminal. The control electrode of the twenty-seventh transistor is electrically connected with the second pull-down node, and the second electrode of the twenty-seventh transistor is electrically connected with the third voltage signal end.

In some embodiments, the first scanning unit further comprises: the third reset circuit is electrically connected with the display reset signal end, the first pull-up node, the third voltage signal end and the first anti-leakage node; the third reset circuit is configured to reset the first pull-up node under control of a display reset signal transmitted by the display reset signal terminal. The second scanning unit further includes: the fourth reset circuit is electrically connected with the display reset signal end, the second pull-up node, the third voltage signal end and the second anti-leakage node; the fourth reset circuit is configured to reset the second pull-up node under control of a display reset signal transmitted by the display reset signal terminal.

In some embodiments, the third reset circuit comprises: a twenty-eighth transistor and a twenty-ninth transistor. The control electrode of the twenty-eighth transistor is electrically connected with the display reset signal end, the first electrode of the twenty-eighth transistor is electrically connected with the first pull-up node, and the second electrode of the twenty-eighth transistor is electrically connected with the first electrode of the twenty-ninth transistor and the first anti-leakage node. The control electrode of the twenty-ninth transistor is electrically connected with the display reset signal end, and the second electrode of the twenty-ninth transistor is electrically connected with the third voltage signal end. The fourth reset circuit includes: a thirty-first transistor and a thirty-first transistor. The control electrode of the thirty-first transistor is electrically connected with the display reset signal end, the first electrode of the thirty-first transistor is electrically connected with the second pull-up node, and the second electrode of the thirty-first transistor is electrically connected with the first electrode of the thirty-first transistor and the second anti-leakage node. The control electrode of the thirty-first transistor is electrically connected with the display reset signal end, and the second electrode of the thirty-first transistor is electrically connected with the third voltage signal end.

In some embodiments, the first scanning unit further comprises: the fifth reset circuit is electrically connected with the global reset signal end, the first pull-up node, the third voltage signal end and the first anti-leakage node; the fifth reset circuit is configured to reset the first pull-up node under control of a global reset signal transmitted by the global reset signal terminal. The second scanning unit further includes: the sixth reset circuit is electrically connected with the global reset signal end, the second pull-up node, the third voltage signal end and the second anti-leakage node; the sixth reset circuit is configured to reset the second pull-up node under control of a global reset signal transmitted by the global reset signal terminal.

In some embodiments, the fifth reset circuit comprises: a thirty-third transistor and a thirty-third transistor. The control electrode of the thirty-third transistor is electrically connected with the global reset signal end, the first electrode of the thirty-third transistor is electrically connected with the first pull-up node, and the second electrode of the thirty-third transistor is electrically connected with the first electrode of the thirty-third transistor and the first anti-leakage node. A control electrode of the thirty-third transistor is electrically connected to the global reset signal terminal, and a second electrode of the thirty-third transistor is electrically connected to the third voltage signal terminal. The sixth reset circuit includes: a thirty-fourth transistor and a thirty-fifth transistor. The control electrode of the thirty-fourth transistor is electrically connected with the global reset signal end, the first electrode of the thirty-fourth transistor is electrically connected with the second pull-up node, and the second electrode of the thirty-fourth transistor is electrically connected with the first electrode of the thirty-fifth transistor and the second anti-leakage node. The control electrode of the thirty-fifth transistor is electrically connected with the global reset signal terminal, and the second electrode of the thirty-fifth transistor is electrically connected with the third voltage signal terminal.

In some embodiments, the first scanning unit further comprises: a seventh reset circuit and an eighth reset circuit. The seventh reset circuit is electrically connected with the first pull-down node, the shift signal end, the first scanning signal end, the third voltage signal end and the fourth voltage signal end; the seventh reset circuit is configured to reset the shift signal terminal and the first scan signal terminal under control of a voltage of the first pull-down node. In the case that the shift register further includes a second scan cell, the seventh reset circuit is further electrically connected to the second pull-down node; the seventh reset circuit is configured to reset the shift signal terminal and the first scan signal terminal under control of a voltage of the second pull-down node. The eighth reset circuit is electrically connected with the input signal end, the first pull-down node and the third voltage signal end; the eighth reset circuit is configured to reset the first pull-down node under control of an input signal transmitted by the input signal terminal. The second scanning unit further includes: a ninth reset circuit and a tenth reset circuit. The ninth reset circuit is electrically connected with the first pull-down node, the second scanning signal end and the fourth voltage signal end; the ninth reset circuit is configured to reset the second scan signal terminal under control of a voltage of the first pull-down node or a voltage of the second pull-down node. The tenth reset circuit is electrically connected with the input signal end, the second pull-down node and the third voltage signal end; the tenth reset circuit is configured to reset the second pull-down node under control of an input signal transmitted by the input signal terminal.

In some embodiments, the seventh reset circuit includes: a thirty-sixth transistor and a thirty-ninth transistor. The control electrode of the thirty-sixth transistor is electrically connected with the first pull-down node, the first electrode of the thirty-sixth transistor is electrically connected with the shift signal terminal, and the second electrode of the thirty-sixth transistor is electrically connected with the third voltage signal terminal. The control electrode of the thirty-ninth transistor is electrically connected with the first pull-down node, the first electrode of the thirty-ninth transistor is electrically connected with the first scanning signal end, and the second electrode of the thirty-ninth transistor is electrically connected with the fourth voltage signal end. In the case where the shift register further includes a second scan cell, the seventh reset circuit further includes: thirty-eighth transistor and thirty-seventh transistor. The control electrode of the thirty-eighth transistor is electrically connected with the second pull-down node, the first electrode of the thirty-eighth transistor is electrically connected with the shift signal terminal, and the second electrode of the thirty-eighth transistor is electrically connected with the third voltage signal terminal. The control electrode of the thirty-seventh transistor is electrically connected with the second pull-down node, the first electrode of the thirty-seventh transistor is electrically connected with the first scanning signal end, and the second electrode of the thirty-seventh transistor is electrically connected with the fourth voltage signal end. The eighth reset circuit includes: forty transistors. The control electrode of the forty transistor is electrically connected with the input signal end, the first electrode of the forty transistor is electrically connected with the first pull-down node, and the second electrode of the forty transistor is electrically connected with the third voltage signal end. The ninth reset circuit includes: a forty-first transistor and a forty-second transistor. The control electrode of the forty-first transistor is electrically connected with the second pull-down node, the first electrode of the forty-first transistor is electrically connected with the second scanning signal end, and the second electrode of the forty-first transistor is electrically connected with the fourth voltage signal end. The control electrode of the forty-second transistor is electrically connected with the first pull-down node, the first electrode of the forty-second transistor is electrically connected with the second scanning signal end, and the second electrode of the forty-second transistor is electrically connected with the fourth voltage signal end. The tenth reset circuit includes: and a forty-third transistor. The control electrode of the forty-third transistor is electrically connected with the input signal end, the first electrode of the forty-third transistor is electrically connected with the second pull-down node, and the second electrode of the forty-third transistor is electrically connected with the third voltage signal end.

In some embodiments, the seventh reset circuit is further electrically connected to the first sense signal terminal, with the first output circuit being further electrically connected to a first sense signal terminal, and the second output circuit being further electrically connected to a second sense signal terminal; the seventh reset circuit is further configured to reset the first sensing signal terminal under control of a voltage of the first pull-down node or a voltage of the second pull-down node. The ninth reset circuit is also electrically connected with the second sensing signal end; the ninth reset circuit is further configured to electrically reset the second sense signal terminal under control of a voltage of the first pull-down node or a voltage of the second pull-down node.

In some embodiments, the seventh reset circuit further comprises: a fifty-fourth transistor and a fifty-fifth transistor. The control electrode of the fifty-fourth transistor is electrically connected with the first pull-down node, the first electrode of the fifty-fourth transistor is electrically connected with the first sensing signal terminal, and the second electrode of the fifty-fourth transistor is electrically connected with the fourth voltage signal terminal. The control electrode of the fifty-fifth transistor is electrically connected with the second pull-down node, the first electrode of the fifty-fifth transistor is electrically connected with the first sensing signal terminal, and the second electrode of the fifty-fifth transistor is electrically connected with the fourth voltage signal terminal. The ninth reset circuit further includes: a fifty-sixth transistor and a fifty-seventh transistor. The control electrode of the fifty-sixth transistor is electrically connected with the second pull-down node, the first electrode of the fifty-sixth transistor is electrically connected with the second sensing signal terminal, and the second electrode of the fifty-sixth transistor is electrically connected with the fourth voltage signal terminal. The control electrode of the fifty-seventh transistor is electrically connected with the first pull-down node, the first electrode of the fifty-seventh transistor is electrically connected with the second sensing signal terminal, and the second electrode of the fifty-seventh transistor is electrically connected with the fourth voltage signal terminal.

In some embodiments, the shift register further comprises: the input unit is blanked. The blanking input unit is electrically connected with the selection control signal end, the input signal end, the third voltage signal end, the fourth clock signal end, the first pull-up node, the first anti-leakage node and the anti-leakage input node. The blanking input unit is configured to transmit a fourth clock signal received at the fourth clock signal terminal to the first pull-up node under control of a selection control signal transmitted by the selection control signal terminal. In the case that the shift register further includes a second scan unit, the blank input unit is further electrically connected to the second pull-up node and the second anti-leakage node. The blanking input unit is further configured to transmit a fourth clock signal received at the fourth clock signal terminal to the second pull-up node under control of the selection control signal transmitted at the selection control signal terminal.

In some embodiments, the blanking input unit includes: the first transmission circuit is connected with the first input circuit and the second input circuit. The selection control circuit is electrically connected with the selection control signal end, the input signal end, the third voltage signal end, the first blanking node and the third anti-leakage node; the selection control circuit is configured to transmit an input signal received at the input signal terminal to the first blanking node under control of the selection control signal. The third anti-creeping circuit is electrically connected with a third anti-creeping node, the first blanking node and the anti-creeping input node; the third anti-leakage circuit is configured to transmit a first voltage signal or a second voltage signal from the anti-leakage input node to the third anti-leakage node under control of a voltage of the first blanking node. The third input circuit is electrically connected with the first blanking node, the fourth clock signal end and the second blanking node; the third input circuit is configured to transmit a fourth clock signal received at the fourth clock signal terminal to the second blanking node under control of a voltage of the first blanking node. The first transmission circuit is electrically connected with the fourth clock signal end, the second blanking node, the first pull-up node and the first anti-leakage node; the first transmission circuit is configured to transmit the fourth clock signal received at the second blanking node to the first pull-up node under control of the fourth clock signal transmitted by the fourth clock signal terminal. In case the shift register further comprises a second scanning unit, the blanking input unit further comprises: and a second transmission circuit. The second transmission circuit is electrically connected with the fourth clock signal end, the second blanking node, the second pull-up node and the second anti-leakage node; the second transmission circuit is configured to transmit the fourth clock signal received at the second blanking node to the second pull-up node under control of the fourth clock signal transmitted at the fourth clock signal terminal.

In some embodiments, the selection control circuit includes: a forty-fourth transistor, a forty-fifth transistor, and a third capacitor. The control electrode of the forty-fourth transistor is electrically connected with the selection control signal end, the first electrode of the forty-fourth transistor is electrically connected with the input signal end, and the second electrode of the forty-fourth transistor is electrically connected with the first electrode of the forty-fifth transistor and the third anti-leakage node. The control electrode of the forty-fifth transistor is electrically connected with the selection control signal end, and the second electrode of the forty-fifth transistor is electrically connected with the first blanking node. The first end of the third capacitor is electrically connected with the first blanking node, and the second end of the third capacitor is electrically connected with the third voltage signal end. The third anticreep circuit includes: forty-sixth transistor. The control electrode of the forty-sixth transistor is electrically connected with the first blanking node, the first electrode of the forty-sixth transistor is electrically connected with the anti-leakage input node, and the second electrode of the forty-sixth transistor is electrically connected with the third anti-leakage node. The third input circuit includes: forty-seventh transistor. The control electrode of the forty-seventh transistor is electrically connected with the first blanking node, the first electrode of the forty-seventh transistor is electrically connected with the fourth clock signal end, and the second electrode of the forty-seventh transistor is electrically connected with the second blanking node. The first transmission circuit includes: forty-eight transistors and forty-nine transistors. The control electrode of the forty-eight transistor is electrically connected with the fourth clock signal end, the first electrode of the forty-eight transistor is electrically connected with the second blanking node, and the second electrode of the forty-eight transistor is electrically connected with the first electrode of the forty-nine transistor and the first anti-leakage node. The control electrode of the forty-ninth transistor is electrically connected with the fourth clock signal end, and the second electrode of the forty-ninth transistor is electrically connected with the first pull-up node. The second transmission circuit includes: a fifty-first transistor and a fifty-second transistor. The control electrode of the fifty-first transistor is electrically connected with the fourth clock signal end, the first electrode of the fifty-first transistor is electrically connected with the second blanking node, and the second electrode of the fifty-first transistor is electrically connected with the first electrode of the fifty-first transistor and the second anti-leakage node. The control electrode of the fifty-first transistor is electrically connected with the fourth clock signal terminal, and the second electrode of the fifty-first transistor is electrically connected with the second pull-up node.

In another aspect, there is provided a driving method of the shift register according to any one of the above. The driving method includes: in an input phase, a first input circuit is turned on in response to an input signal received at an input signal terminal, the input signal being transmitted to a first pull-up node. Responding to a first voltage signal received at a first voltage signal end, starting an anti-leakage input unit, and transmitting the first voltage signal to an anti-leakage input node; or, in response to a second voltage signal received at a second voltage signal terminal, the anti-leakage input unit is turned on, transmitting the second voltage signal to the anti-leakage input node. And under the control of the voltage of the first pull-up node, the anti-leakage unit is started to transmit a first voltage signal or a second voltage signal from the anti-leakage input node to the first anti-leakage node.

In yet another aspect, a gate driving circuit is provided. The gate driving circuit includes: a shift register as in any one of the above embodiments in a multistage cascade.

In yet another aspect, a display device is provided. The display device includes: the gate driving circuit as in any one of the above embodiments.

Drawings

In order to more clearly illustrate the technical solutions of the present disclosure, the drawings that need to be used in some embodiments of the present disclosure will be briefly described below, and it is apparent that the drawings in the following description are only drawings of some embodiments of the present disclosure, and other drawings may be obtained according to these drawings to those of ordinary skill in the art. Furthermore, the drawings in the following description may be regarded as schematic illustrations, and are not limiting of the actual size of the products, the actual flow of the methods, etc. according to the embodiments of the present disclosure.

FIG. 1 is a block diagram of a display panel according to some embodiments of the present disclosure;

FIG. 2 is a block diagram of a display device according to some embodiments of the present disclosure;

FIG. 3 is a block diagram of a shift register according to one implementation;

FIG. 4 is a block diagram of a shift register according to some embodiments of the present disclosure;

FIG. 5 is a timing diagram of a first voltage signal and a second voltage signal according to some embodiments of the present disclosure;

FIG. 6 is a timing diagram of another first voltage signal and a second voltage signal according to some embodiments of the present disclosure;

FIG. 7 is a block diagram of another shift register according to some embodiments of the present disclosure;

FIG. 8 is a block diagram of a shift register according to yet another embodiment of the present disclosure;

FIG. 9 is a block diagram of a shift register according to yet another embodiment of the present disclosure;

FIG. 10 is a block diagram of a shift register according to yet another embodiment of the present disclosure;

FIG. 11 is a circuit diagram of a shift register according to some embodiments of the present disclosure;

FIG. 12 is a block diagram of a shift register according to yet another embodiment of the present disclosure;

FIG. 13 is a circuit diagram of another shift register according to some embodiments of the present disclosure;

FIG. 14 is a block diagram of a shift register according to yet another embodiment of the present disclosure;

FIG. 15 is a circuit diagram of a shift register according to yet another embodiment of the present disclosure;

FIG. 16 is a block diagram of a shift register according to yet another embodiment of the present disclosure;

FIG. 17 is a circuit diagram of a shift register according to yet another embodiment of the present disclosure;

fig. 18 is a block diagram of a gate drive circuit according to some embodiments of the present disclosure;

FIG. 19 is a timing control diagram corresponding to the shift register shown in FIG. 15 according to one of some embodiments of the present disclosure;

Fig. 20 is a block diagram of another gate drive circuit according to some embodiments of the present disclosure.

Detailed Description

The following description of the embodiments of the present disclosure will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by one of ordinary skill in the art based on the embodiments provided by the present disclosure are within the scope of the present disclosure.

Throughout the specification and claims, unless the context requires otherwise, the word "comprise" and its other forms such as the third person referring to the singular form "comprise" and the present word "comprising" are to be construed as open, inclusive meaning, i.e. as "comprising, but not limited to. In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiment", "example", "specific example", "some examples", "and the like are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

The terms "first" and "second" are used below for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the embodiments of the present disclosure, unless otherwise indicated, the meaning of "a plurality" is two or more.

In describing some embodiments, the expression "connected" and its derivatives may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the disclosure herein.

"A and/or B" includes the following three combinations: only a, only B, and combinations of a and B.

As used herein, the term "if" is optionally interpreted to mean "when … …" or "at … …" or "in response to a determination" or "in response to detection" depending on the context. Similarly, the phrase "if determined … …" or "if detected [ stated condition or event ]" is optionally interpreted to mean "upon determining … …" or "in response to determining … …" or "upon detecting [ stated condition or event ]" or "in response to detecting [ stated condition or event ]" depending on the context.

The use of "adapted" or "configured to" herein is meant to be an open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

In addition, the use of "based on" is intended to be open and inclusive in that a process, step, calculation, or other action "based on" one or more of the stated conditions or values may be based on additional conditions or beyond the stated values in practice.

As used herein, "about" or "approximately" includes the stated values as well as average values within an acceptable deviation range of the particular values as determined by one of ordinary skill in the art in view of the measurement in question and the errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system).

Exemplary embodiments are described herein with reference to cross-sectional and/or plan views as idealized exemplary figures. In the drawings, the thickness of layers and regions are exaggerated for clarity. Thus, variations from the shape of the drawings due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.

The transistors used in the circuits provided in the embodiments of the present disclosure may be thin film transistors, field effect transistors (e.g., oxide thin film transistors), or other switching devices with the same characteristics, and the thin film transistors are all described in the embodiments of the present disclosure as examples.

In some embodiments, the control of each transistor employed by the shift register is the gate of the transistor, the first being one of the source and drain of the transistor and the second being the other of the source and drain of the transistor. Since the source and drain of a transistor may be symmetrical in structure, the source and drain thereof may be indistinguishable in structure, that is, the first and second poles of the transistor in embodiments of the present disclosure may be indistinguishable in structure. Illustratively, in the case where the transistor is a P-type transistor, the first pole of the transistor is the source and the second pole is the drain; illustratively, in the case where the transistor is an N-type transistor, the first pole of the transistor is the drain and the second pole is the source.

In the circuit provided by the embodiment of the present disclosure, the nodes such as the first pull-up node, the second pull-up node, the first pull-down node, and the second pull-down node do not represent actually existing components, but represent junction points of related electrical connections in the circuit diagram, that is, the nodes are equivalent nodes formed by junction points of the related electrical connections in the circuit diagram.

In embodiments of the present disclosure, the term "pull-up" means that one electrode of one node or one transistor is charged such that the absolute value of the level of the node or the electrode is raised, thereby enabling the operation (e.g., turning on) of the corresponding transistor. The term "pull down" means that one electrode of one node or one transistor is discharged such that the absolute value of the level of the node or the electrode is reduced, thereby enabling the operation (e.g., turning off) of the corresponding transistor.

In the following, in the circuit provided in the embodiment of the present disclosure, the transistors are all exemplified by N-type transistors.

Some embodiments of the present disclosure provide a shift register 100 and a driving method thereof, a gate driving circuit 1000, and a display device 2000, and the shift register 100, the driving method of the shift register 100, the gate driving circuit 1000, and the display device 2000 are described below.

Some embodiments of the present disclosure provide a display device 2000, as shown in fig. 2. The display device may be any device that displays images, whether in motion (e.g., video) or stationary (e.g., still image), and whether textual or pictorial. More particularly, it is contemplated that the embodiments may be implemented in or associated with a variety of electronic devices such as, but not limited to, mobile telephones, wireless devices, personal Data Assistants (PDAs), hand-held or portable computers, GPS receivers/navigators, cameras, MP4 video players, video cameras, game consoles, wrist watches, clocks, calculators, television monitors, flat panel displays, computer monitors, auto displays (e.g., odometer display, etc.), navigators, cabin controllers and/or displays, displays of camera views (e.g., display of a rear view camera in a vehicle), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., display of images on a piece of jewelry), and the like.

In some examples, the display device 2000 includes a frame, a display panel PNL provided in the frame, a circuit board, a display drive IC (Integrated Circuit ), and other electronic parts, and the like.

The display panel may be, for example: an organic light emitting diode (Organic Light Emitting Diode, abbreviated as OLED) display panel, a quantum dot light emitting diode (Quantum Dot Light Emitting Diodes, abbreviated as QLED) display panel, a Micro light emitting diode (Micro Light Emitting Diodes, abbreviated as Micro LED) display panel, and the like, which is not particularly limited in this disclosure.

Some embodiments of the present disclosure are schematically described below taking the above-mentioned display panel as an OLED display panel as an example.

In some embodiments, as shown in fig. 1, the display panel PNL has a display area a and a frame area B disposed beside the display area a. Here, "side" means one side, two sides, three sides, or a peripheral side of the display area a, etc., that is, the bezel area B may be located at one side, two sides, or three sides of the display area a, or the bezel area B may be disposed around the display area a.

In some examples, as shown in fig. 1, the display panel PNL may include a plurality of subpixels disposed within the display area a, a plurality of gate lines GL extending in the first direction X, and a plurality of data lines DL extending in the second direction Y.

For example, the subpixels aligned in a row along the first direction X may be referred to as the same row subpixels, and the subpixels aligned in a row along the second direction Y may be referred to as the same column subpixels. The same row of subpixels may be electrically connected to at least one gate line GL, and the same column of subpixels may be electrically connected to one data line DL.

In some examples, as shown in fig. 1, the gate driving circuit 1000 is disposed in the frame region B and located at one side of the extending direction of the plurality of gate lines GL. The gate driving circuit 1000 may be electrically connected to the plurality of gate lines GL and input a scan signal to the plurality of gate lines GL to drive the plurality of rows of sub-pixels to perform image display.

In some examples, the gate driving circuit 1000 described above may be a gate driving IC. Of course, the gate driving circuit 1000 may be a GOA (Gate Driver on Array) circuit, that is, the gate driving circuit 1000 may be directly integrated into the array substrate of the display panel PNL. In comparison with the gate driving IC, the gate driving circuit 1000 is a GOA circuit, which can reduce the manufacturing cost of the display panel PNL; on the other hand, the frame size of the display panel PNL can also be reduced, and a narrow frame design is realized. The following embodiments are described taking the gate driving circuit 1000 as a GOA circuit as an example.

Some embodiments of the present disclosure provide a shift register 100, as shown in fig. 3 and 4, including: a first scanning unit 1.

In some examples, as shown in fig. 3 and 4, the first scanning unit 1 includes a first input circuit 101, and a first output circuit 102 electrically connected to the first input circuit 101. The first output circuit 102 may be electrically connected to a corresponding gate line GL, for example, and input a first scan signal to the gate line GL to drive the sub-pixels of the corresponding row to perform display scanning.

The plurality of shift registers 100 may be cascaded to form a gate driving circuit 1000, where the gate driving circuit 1000 is capable of providing scanning signals to a plurality of rows of sub-pixels in the display panel PNL respectively. That is, the gate driving circuit 200 may be used for the display device 2000 to provide a scan signal during display of one frame image of the display device 2000.

In some examples, as shown in fig. 3 and 4, the first Input circuit 101 is electrically connected to an Input signal terminal Input (in the drawings and below, abbreviated as Iput), a first pull-up node Q1, and a first anti-leakage node OFF 1. Wherein the first input circuit 101 is configured to transmit an input signal to the first pull-up node Q1 in response to the input signal received at the input signal terminal Iput.

For example, in a case where the level of the input signal is high, the first input circuit 101 may be turned on by the input signal and transmit the input signal to the first pull-up node Q1, and charge the first pull-up node Q1 such that the voltage of the first pull-up node Q1 increases.

In some examples, as shown in fig. 3 and 4, the first Output circuit 102 is electrically connected to the first pull-up node Q1, the first clock signal terminal clkd_1, the second clock signal terminal clke_1, the shift signal terminal CR < N >, and the first scan signal terminal Output1< N > (the drawing and the following are abbreviated as "Oput 1< N >). Wherein the first output circuit 102 is configured to transmit the first clock signal received at the first clock signal terminal clkd_1 to the shift signal terminal CR < N >, under control of the voltage of the first pull-up node Q1; and, the second clock signal received at the second clock signal terminal clke_1 is transmitted to the first scan signal terminal Oput1< N > under the control of the voltage of the first pull-up node Q1.

Illustratively, in the case where the first input circuit 101 charges the first pull-up node Q1 such that the voltage of the first pull-up node Q1 increases, the first output circuit 102 may be turned on under the control of the voltage of the first pull-up node Q1, output the first clock signal received at the first clock signal terminal clkd_1 as a shift signal from the shift signal terminal CR < N >, and simultaneously output the second clock signal received at the second clock signal terminal clke_1 as a first scan signal from the first scan signal terminal Oput1< N >.

Here, in the display stage of one frame, the signal waveforms of the shift signal and the first scan signal output by the first output circuit 102 may be the same or different.

For example, in the display stage of one frame, the first scan signal output by the first output circuit 102 may drive the corresponding row of sub-pixels in the display panel PNL to perform display scanning.

After the plurality of shift registers 100 are cascaded to form the gate driving circuit 1000, the shift signal terminal CR < N > of the first scan cell 1 of the N-th shift register 100 may be electrically connected to the input signal terminal Iput of the first scan cell 1 of the n+1th shift register 100, and further, the shift signal output from the shift signal terminal CR < N > of the N-th shift register 100 may be used as the input signal of the first scan cell 1 of the n+1th shift register 100. Wherein N is an integer, and N is not less than 1.

In addition, the input signal terminal Iput of the partial shift register 100 may be electrically connected to the start signal terminal STV, so as to receive the start signal transmitted by the start signal terminal STV as an input signal. The partial shift register 100 may be, for example, the first stage shift register 100 in the gate driving circuit 1000, or may be, for example, the first stage shift register 100, the second stage shift register 100, or the like.

Here, the number of shift registers 100 electrically connected to the start signal terminal STV is not limited, and may be selected according to actual needs.

It should be noted that, when the level of the input signal transmitted by the input signal terminal Iput is low, so that the first input circuit 101 is turned off and the voltage of the first pull-up node Q1 is maintained at the high voltage, the voltage of the first pull-up node Q1 is higher than the voltage at the input signal terminal Iput, and a large voltage difference is formed between the first pull-up node Q1 and the input signal terminal Iput. In this way, the first pull-up node Q1 is easily leaked through the first input circuit 101, so that the first output circuit 102 is difficult to maintain at a higher and more stable potential in the process of outputting the shift signal and/or the first scan signal, and further, the shift signal and/or the first scan signal deviate, which affects the display effects of the display panel PNL and the display device 2000.

In one implementation, as shown in fig. 3, the shift register 100 further includes a first anti-leakage circuit 3'.

As shown in fig. 3, the first leakage preventing circuit 3' is electrically connected to the first pull-up node Q1, the constant high voltage signal terminal VDD, and the first leakage preventing node OFF1. Wherein the first leakage preventing circuit 3' is configured to transmit a constant high voltage signal received at the constant high voltage signal terminal VDD to the first leakage preventing node OFF1 under the control of the voltage of the first pull-up node Q1.

For example, in the case where the voltage of the first pull-up node Q1 is a high voltage, the first anti-leakage circuit 3' may be turned on under the control of the voltage of the first pull-up node Q1 and transmit a constant high voltage signal received at the constant high voltage signal terminal VDD to the first anti-leakage node OFF1 so that the voltage of the first anti-leakage node OFF1 increases (for example, the voltage of the first anti-leakage node OFF1 may be made equal or substantially equal to the voltage of the first pull-up node Q1). This can reduce the voltage difference between the first anti-leakage node OFF1 and the first pull-up node Q1, weaken the degree of leakage of the first pull-up node Q1 through the first input circuit 101, and even avoid leakage of the first pull-up node Q1 through the first input circuit 101.

After cascade-connecting the plurality of shift registers to form the gate driving circuit, the gate driving circuit may include a constant high voltage signal line electrically connected to the constant high voltage signal terminal VDD of each shift register and for transmitting a constant high voltage signal to the constant high voltage signal terminal VDD of each shift register. Because the electric signal transmitted by the constant high voltage signal line to the constant high voltage signal terminal VDD is a constant high voltage signal, and the constant high voltage signal line needs to continuously transmit the constant high voltage signal for a long time, in the process of using the gate driving circuit or performing reliability test (environment is high temperature and high humidity) on the gate driving circuit, the voltage difference between the constant high voltage signal line and other wires above the constant high voltage signal line can damage the insulating layer between the constant high voltage signal line and the other wires to form a leakage path, and then the constant high voltage signal line is subject to electrochemical corrosion to fail.

Based on this, as shown in fig. 4, the shift register 100 provided in some embodiments of the present disclosure further includes: an anti-creeping unit 3 and an anti-creeping input unit 4.

In some examples, as shown in fig. 4, the anti-leakage input unit 4 is electrically connected to the first voltage signal terminal vdd_a, the second voltage signal terminal vdd_b, and the anti-leakage input node M. Wherein the anti-leakage input unit 4 is configured to transmit a first voltage signal to the anti-leakage input node M in response to the first voltage signal received at the first voltage signal terminal vdd_a; or, in response to the second voltage signal received at the second voltage signal terminal vdd_b, the second voltage signal is transmitted to the anti-leakage input node M. The first voltage signal and the second voltage signal are opposite signals.

By way of example, the "inverted signal" herein refers to the first voltage signal and the second voltage signal being unchanged during a display period of one frame or a display period of a plurality of consecutive frames, and the level of the second voltage signal being low in the case where the level of the first voltage signal is high and high in the case where the level of the first voltage signal is low.

For example, as shown in fig. 5, in the display stage of one frame, the level of the second voltage signal is changed from low level to high level while the level of the first voltage signal is changed from high level to low level. The level of the second voltage signal changes from a high level to a low level while the level of the first voltage signal changes from a low level to a high level.

As another example, as shown in fig. 6, in the display stage of one frame, the level of the second voltage signal is changed from low level to high level while the level of the first voltage signal is changed from high level to low level. The level of the second voltage signal is changed from a high level to a low level before the level of the first voltage signal is changed from a low level to a high level.

Of course, there may be other arrangements of the level of the first voltage signal and the level of the second voltage signal, so long as the level of the first voltage signal and the level of the second voltage signal are different in the display stage of one frame.

The present disclosure is schematically illustrated with an example in which the level of the first voltage signal and the level of the second voltage signal are simultaneously changed.

The high level and the low level in the present disclosure are relative values, for example, the high level is 15V, the low level is 5V, and thus the low level is not limited to a level of 0V or less.

Based on this, for example, in the case where the level of the first voltage signal is a high level and the level of the second voltage signal is a low level, the anti-leakage input unit 4 may be turned on by the first voltage signal, transmitting the first voltage signal to the anti-leakage input node M such that the voltage of the anti-leakage input node M increases.

For example, in the case where the level of the first voltage signal is a low level and the level of the second voltage signal is a high level, the anti-leakage input unit 4 may be turned on by the second voltage signal to transmit the second voltage signal to the anti-leakage input node M, so that the voltage of the anti-leakage input node M increases.

In some examples, as shown in fig. 4, the anti-leakage unit 3 is electrically connected with the first pull-up node Q1, the first anti-leakage node OFF1, and the anti-leakage input node M. Wherein the anti-leakage unit 3 is configured to transmit the first voltage signal or the second voltage signal from the anti-leakage input node M to the first anti-leakage node OFF1 under the control of the voltage of the first pull-up node Q1.

For example, in case the first input circuit 101 charges the first pull-up node Q1 such that the voltage of the first pull-up node Q1 increases, the anti-leakage unit 3 may be turned on under the control of the voltage of the first pull-up node Q1, and transmit the first voltage signal or the second voltage signal received at the anti-leakage input node M to the first anti-leakage node OFF1 such that the voltage of the first anti-leakage node OFF1 increases.

In the case where the voltage of the first anti-leakage node OFF1 is raised by the anti-leakage unit 3, the voltage of the first anti-leakage node OFF1 may be smaller than the voltage of the first pull-up node Q1, for example, so that the degree of leakage of the first pull-up node Q1 through the first input circuit 101 may be weakened, so that the first pull-up node Q1 can maintain a higher, more stable voltage. Alternatively, the voltage of the first anti-leakage node OFF1 may be equal to the voltage of the first pull-up node Q1, so that the situation that the first pull-up node Q1 leaks electricity through the first input circuit 101 can be avoided, and the first pull-up node Q1 maintains a higher and more stable voltage.

Here, taking the example that the level of the first voltage signal is high and the level of the second voltage signal is low, the operations of the anti-leakage unit 3 and the anti-leakage input unit 4 may be: the anti-leakage input unit 4 is conducted under the action of the first voltage signal, and transmits the first voltage signal to the anti-leakage input node M, so that the voltage of the anti-leakage input node M is increased. In the case where the anti-leakage unit 3 is turned on under the control of the voltage of the first pull-up node Q1, the anti-leakage unit 3 transmits the first voltage signal received at the anti-leakage input node M to the first anti-leakage node OFF1, so that the voltage of the first anti-leakage node OFF1 increases.

Since the anti-leakage input unit 4 is electrically connected to the first voltage signal terminal vdd_a and the second voltage signal terminal vdd_b, after the plurality of shift registers 100 are cascaded to form the gate driving circuit 1000, the gate driving circuit 1000 may include a first voltage signal line electrically connected to the first voltage signal terminal vdd_a of each shift register 100 for transmitting a first voltage signal to the first voltage signal terminal vdd_a of each shift register 100 (i.e., the thirteenth clock signal line clk_13 shown in fig. 16 and 18), and a second voltage signal line electrically connected to the second voltage signal terminal vdd_b of each shift register 100 for transmitting a second voltage signal to the second voltage signal terminal vdd_b of each shift register 100 (i.e., the fourteenth clock signal line clk_14 shown in fig. 16 and 18). Because the first voltage signal and the second voltage signal are opposite-phase signals, the first voltage signal line and the second voltage signal line can be used to input high-level voltage signals to the anti-leakage input unit 4 alternately in the display stage of different frames in the process of using the gate driving circuit 1000 or performing reliability test on the gate driving circuit 1000, so that the situation that the first voltage signal line and the second voltage signal line fail due to electrochemical corrosion caused by continuous transmission of constant high-voltage signals for a long time is avoided, and the reliability of the gate driving circuit 1000 is improved.

Therefore, in the shift register 100 provided in some embodiments of the present disclosure, by providing the anti-leakage unit 3 and the anti-leakage input unit 4 and electrically connecting the anti-leakage unit 3 with the first anti-leakage node OFF1 and the anti-leakage input node M, electrically connecting the anti-leakage input unit 4 with the first voltage signal terminal vdd_a, the second voltage signal terminal vdd_b and the anti-leakage input node M, the first voltage signal or the second voltage signal can be transmitted to the anti-leakage input node M through the anti-leakage input unit 4, and the first voltage signal or the second voltage signal can be transmitted to the first anti-leakage node OFF1 through the anti-leakage unit 3. In the case that the voltage of the first pull-up node Q1 increases, the voltage difference between the first anti-leakage node OFF1 and the first pull-up node Q1 can be reduced by using the anti-leakage unit 3 and the anti-leakage input unit 4, so as to weaken the leakage degree of the first pull-up node Q1 through the first input circuit 101, and even avoid the leakage of the first pull-up node Q1 through the first input circuit 101, so that the first pull-up node Q1 can be kept at a higher and more stable voltage. Thus, the anti-leakage unit 3 and the anti-leakage input unit 4 can be used to realize the anti-leakage protection of the first pull-up node Q1, so that the display device 2000 applied with the shift register 100 can have a better display effect.

Further, the present disclosure sets the first voltage signal transmitted from the first voltage signal terminal vdd_a and the second voltage signal transmitted from the second voltage signal terminal vdd_b as the inverted signals, so that the first voltage signal is transmitted to the anti-leakage input node M and the first anti-leakage node OFF1 by the anti-leakage input unit 4 when the level of the first voltage signal is high and the second voltage signal is transmitted to the anti-leakage input node M and the first anti-leakage node OFF1 by the anti-leakage input unit 4 when the level of the second voltage signal is high in the display stage of one frame. In this way, after the plurality of shift registers 100 are cascaded to form the gate driving circuit 1000, the first voltage signal terminal vdd_a of each shift register 100 can be electrically connected to the first voltage signal line for transmitting the first voltage signal, so that the second voltage signal terminal vdd_b of each shift register 100 is electrically connected to the second voltage signal line for transmitting the second voltage signal, and further, the first voltage signal line and the second voltage signal line can be used to input the high-level voltage signal to the anti-leakage input unit 4 alternately in the display stage of different frames, thereby avoiding the failure caused by electrochemical corrosion of the first voltage signal line and the second voltage signal line due to continuous transmission of the constant high voltage signal for a long time, and improving the reliability of the gate driving circuit 1000.

Further, after the first voltage signal line and the second voltage signal line are provided, a constant high voltage signal line for transmitting a constant high voltage signal can be prevented from being provided, and thus a display failure phenomenon due to signal crosstalk generated between the constant high voltage signal line and a low voltage signal line (for example, a signal line for transmitting a third voltage signal or a fourth voltage signal, which will be described later) can be prevented from occurring.

In some embodiments, as shown in fig. 7, the anti-creeping input unit 4 may include: a first anti-creeping input circuit 401 and a second anti-creeping input circuit 402.

In some examples, as shown in fig. 7 and 9-17, the first anti-leakage input circuit 401 is electrically connected to the first voltage signal terminal vdd_a and the anti-leakage input node M. Wherein the first anti-leakage input circuit 401 is configured to transmit a first voltage signal to the anti-leakage input node M in response to the first voltage signal received at the first voltage signal terminal vdd_a.

For example, in the case that the level of the first voltage signal transmitted by the first voltage signal terminal vdd_a is a high level, the first anti-leakage input circuit 401 may be turned on under the control of the first voltage signal and transmit the first voltage signal to the anti-leakage input node M, so that the voltage of the anti-leakage input node M increases.

In some examples, as shown in fig. 7 and 9-17, the second anti-leakage input circuit 402 is electrically connected to the second voltage signal terminal vdd_b and the anti-leakage input node M. Wherein the second anti-leakage input circuit 402 is configured to transmit a second voltage signal to the anti-leakage input node M in response to the second voltage signal received at the second voltage signal terminal vdd_b.

For example, in the case that the level of the second voltage signal transmitted by the second voltage signal terminal vdd_b is a high level, the second anti-leakage input circuit 402 may be turned on under the control of the second voltage signal and transmit the second voltage signal to the anti-leakage input node M, so that the voltage of the anti-leakage input node M increases.

Thus, in the display stage of one frame, if the level of the first voltage signal is high and the level of the second voltage signal is low, the second anti-leakage input circuit 402 is turned off under the control of the second voltage signal, and the first anti-leakage input circuit 401 is turned on under the control of the first voltage signal and receives and transmits the first voltage signal to the anti-leakage input node M.

On the contrary, in the display stage of one frame, if the level of the first voltage signal is low and the level of the second voltage signal is high, the first anti-leakage input circuit 401 is turned off under the control of the first voltage signal, and the second anti-leakage input circuit 402 is turned on under the control of the second voltage signal, and receives and transmits the second voltage signal to the anti-leakage input node M.

The structures of the first and second anti-creeping input circuits 401 and 402 included in the anti-creeping input unit 4 are schematically described below.

In some examples, as shown in fig. 11, 13, 15, and 17, the first anti-leakage input circuit 401 may include: a first transistor M1.

As illustrated in fig. 11, 13, 15 and 17, the control electrode of the first transistor M1 is electrically connected to the first voltage signal terminal vdd_a, the first electrode of the first transistor M1 is electrically connected to the first voltage signal terminal vdd_a, and the second electrode of the first transistor M1 is electrically connected to the leakage preventing input node M.

For example, in the case that the level of the first voltage signal transmitted by the first voltage signal terminal vdd_a is high, the first transistor M1 may be turned on under the control of the first voltage signal, receive the first voltage signal, and transmit the received first voltage signal to the anti-leakage input node M.

In some examples, as shown in fig. 11, 13, 15, and 17, the second anti-leakage input circuit 402 may include: and a second transistor M2.

As illustrated in fig. 11, 13, 15 and 17, the control electrode of the second transistor M2 is electrically connected to the second voltage signal terminal vdd_b, the first electrode of the second transistor M2 is electrically connected to the second voltage signal terminal vdd_b, and the second electrode of the second transistor M2 is electrically connected to the leakage preventing input node M.

For example, in the case that the level of the second voltage signal transmitted by the second voltage signal terminal vdd_b is high, the second transistor M2 may be turned on under the control of the second voltage signal, receive the second voltage signal, and transmit the received second voltage signal to the anti-leakage input node M.

Therefore, in the display stage of one frame, when the level of the first voltage signal is high and the level of the second voltage signal is low, the second transistor M2 is turned off under the control of the second voltage signal, and the first transistor M1 is turned on under the control of the first voltage signal, and receives and transmits the first voltage signal to the anti-leakage input node M.

In contrast, in the display stage of one frame, under the condition that the level of the first voltage signal is low and the level of the second voltage signal is high, the first transistor M1 is turned off under the control of the first voltage signal, and the second transistor M2 is turned on under the control of the second voltage signal, and receives and transmits the second voltage signal to the anti-leakage input node M.

In some embodiments, as shown in fig. 7, the anti-creeping unit 3 may include: a first anti-leakage circuit 301.

In some examples, as shown in fig. 7 and 9 to 17, the first leakage preventing circuit 301 is electrically connected to the first pull-up node Q1, the leakage preventing input node M, and the first leakage preventing node OFF1. Wherein the first leakage prevention circuit 301 is configured to transmit the first voltage signal or the second voltage signal from the leakage prevention input node M to the first leakage prevention node OFF1 under the control of the voltage of the first pull-up node Q1.

For example, in the case where the first input circuit 101 charges the first pull-up node Q1 such that the voltage of the first pull-up node Q1 increases, the first anti-leakage circuit 301 may be turned on under the control of the voltage of the first pull-up node Q1, transmitting the first voltage signal or the second voltage signal received from the anti-leakage input node M to the first anti-leakage node OFF1.

Here, in the case where the level of the first voltage signal is high and the level of the second voltage signal is low, the first voltage signal may be transmitted to the anti-leakage input node M through the anti-leakage input unit 4. In the case that the first anti-leakage circuit 301 is turned on, the first anti-leakage circuit 301 may receive the first voltage signal at the anti-leakage input node M and transmit the first voltage signal to the first anti-leakage node OFF1, so that the voltage of the first anti-leakage node OFF1 increases, and the voltage difference between the first anti-leakage node OFF1 and the first pull-up node Q1 is reduced.

In the case where the level of the first voltage signal is low and the level of the second voltage signal is high, the second voltage signal may be transmitted to the anti-leakage input node M through the anti-leakage input unit 4. In the case that the first anti-leakage circuit 301 is turned on, the first anti-leakage circuit 301 may receive the second voltage signal at the anti-leakage input node M and transmit the second voltage signal to the first anti-leakage node OFF1, so that the voltage of the first anti-leakage node OFF1 increases, and the voltage difference between the first anti-leakage node OFF1 and the first pull-up node Q1 is reduced.

The structure of the first leakage preventing circuit 301 included in the leakage preventing unit 3 is schematically described below.

In some examples, as shown in fig. 11, 13, 15, and 17, the first anticreep circuit 301 includes: and a third transistor M3.

As illustrated in fig. 11, 13, and 15 and 17, the control electrode of the third transistor M3 is electrically connected to the first pull-up node Q1, the first electrode of the third transistor M3 is electrically connected to the anti-leakage input node M, and the second electrode of the third transistor M3 is electrically connected to the first anti-leakage node OFF1.

For example, in case the first input circuit 101 charges the first pull-up node Q1 such that the voltage of the first pull-up node Q1 increases, the third transistor M3 may be turned on under control of the voltage of the first pull-up node Q1, receive the first voltage signal or the second voltage signal from the anti-leakage input node M, and transmit the received first voltage signal or the second voltage signal to the first anti-leakage node OFF1.

It should be noted that, in some embodiments of the present disclosure, the number of scan cells included in the shift register 100 is not limited, and may be selected according to actual needs.

By way of example, the shift register 100 may include two, three, four, or more scan cells. The configuration of the remaining scan cells included in the shift register 100 may be the same as that of the first scan cell 1, or may be different from that of the first scan cell 1, for example. In the case where the configuration of the remaining scan cells included in the shift register 100 is different from that of the first scan cell 1, the differences may include, for example: the output circuits of the remaining scan cells included in the shift register 100 are not electrically connected to the shift signal terminal CR < N >.

In the following, taking an example that the shift register 100 provided in some embodiments of the present disclosure further includes the second scanning unit 2, a structure of the shift register 100 is schematically described.

In some examples, as shown in fig. 8 and 9, the second scanning unit 2 includes a second input circuit 201, and a second output circuit 202 electrically connected to the second input circuit 201.

Based on this, the first output circuit 102 of the first scanning unit 1 in the shift register 100 may be electrically connected to the plurality of sub-pixels of the odd-numbered row through the corresponding gate line GL, and input the first scanning signal to the plurality of sub-pixels of the odd-numbered row to drive the sub-pixels of the corresponding row to perform the display scanning, for example. The second output circuit 202 in the second scanning unit 2 may be electrically connected to the plurality of sub-pixels of the even-numbered row through the corresponding gate line GL, and input a second scanning signal to the plurality of sub-pixels of the even-numbered row to drive the sub-pixels of the corresponding row to perform the display scanning.

In some examples, as shown in fig. 8 and 9, the second input circuit 201 is electrically connected to the input signal terminal Iput, the second pull-up node Q2, and the second anti-leakage node OFF 2. Wherein the second input circuit 201 is configured to transmit an input signal to the second pull-up node Q2 in response to the input signal received at the input signal terminal Iput.

For example, in a case where the level of the input signal is high, the second input circuit 201 may be turned on by the input signal and transmit the input signal to the second pull-up node Q2, and charge the second pull-up node Q2 such that the voltage of the second pull-up node Q2 increases.

Here, the input signal terminal Iput electrically connected to the second input circuit 201 and the input signal terminal Iput electrically connected to the first input circuit 101 are the same input signal terminal Iput, and the input signals received by the two terminals are the same input signal. In the case that the level of the input signal transmitted by the input signal terminal Iput is high, the first input circuit 101 and the second input circuit 201 may simultaneously receive the input signal, so that the first input circuit 101 and the second input circuit 201 are simultaneously turned on, and further, the first pull-up node Q1 and the second pull-up node Q2 are simultaneously charged.

After the plurality of shift registers 100 are cascaded to form the gate driving circuit 1000, the shift signal terminal CR < N > of the first scan cell 1 of the N-th shift register 100 may be electrically connected to the input signal terminal Iput of the first scan cell 1 and the second scan cell 2 of the n+1th shift register 100, and further, the shift signal outputted from the shift signal terminal CR < N > of the N-th shift register 100 may be used as the input signal of the first scan cell 1 and the second scan cell 2 of the n+1th shift register 100.

In some examples, as shown in fig. 8 and 9, the second Output circuit 202 is electrically connected to the second pull-up node Q2, the third clock signal terminal clke_2, and the second scan signal terminal Output1< n+1> (shown in the drawings and abbreviated as "op ut 1" hereinafter). The second output circuit 202 is configured to transmit the third clock signal received at the third clock signal terminal clke_2 to the second scan signal terminal Oput1< n+1> under control of the voltage of the second pull-up node Q2.

Illustratively, in the case where the second input circuit 201 charges the second pull-up node Q2 such that the voltage of the second pull-up node Q2 increases, the second output circuit 202 may be turned on under the control of the voltage of the second pull-up node Q2, outputting the third clock signal received at the third clock signal terminal clke_2 as the second scan signal from the second scan signal terminal oput1< n+1>.

For example, in the display stage of one frame, the second scan signal output by the second output circuit 202 may drive the corresponding row of sub-pixels in the display panel PNL to perform display scanning.

It should be noted that, when the level of the input signal transmitted by the input signal terminal Iput is low, so that the second input circuit 201 is turned off and the voltage of the second pull-up node Q2 is maintained at the high voltage, the voltage of the second pull-up node Q2 is higher than the voltage at the input signal terminal Iput, and a large voltage difference is formed between the second pull-up node Q2 and the input signal terminal Iput. In this way, the second pull-up node Q2 is easy to leak electricity through the second input circuit 201, so that the second output circuit 202 is difficult to maintain at a higher and more stable potential in the process of outputting the second scan signal, and further the second scan signal is deviated, which affects the display effects of the display panel PNL and the display device 2000.

In some examples, as shown in fig. 8 and 9, the anti-leakage unit 3 is further electrically connected to the second pull-up node Q2 and the second anti-leakage node OFF2. Wherein the anti-leakage unit 3 is further configured to transmit the first voltage signal or the second voltage signal from the anti-leakage input node M to the second anti-leakage node OFF2 under the control of the voltage of the second pull-up node Q2.

For example, in case the second input circuit 201 charges the second pull-up node Q2 such that the voltage of the second pull-up node Q2 increases, the anti-leakage unit 3 may be turned on under the control of the voltage of the second pull-up node Q2, and transmit the first voltage signal or the second voltage signal received at the anti-leakage input node M to the second anti-leakage node OFF2 such that the voltage of the second anti-leakage node OFF2 increases.

In the case that the voltage of the second anti-leakage node OFF2 is raised by the anti-leakage unit 3, the voltage of the second anti-leakage node OFF2 may be smaller than the voltage of the second pull-up node Q2, for example, so that the degree of leakage of the second pull-up node Q2 through the second input circuit 201 may be weakened, so that the second pull-up node Q2 can maintain a higher, more stable voltage. Alternatively, the voltage of the second anti-leakage node OFF2 may be equal to the voltage of the second pull-up node Q2, so that the situation that the second pull-up node Q2 leaks electricity through the second input circuit 201 can be avoided, and the second pull-up node Q2 maintains a higher and more stable voltage.

Here, taking the example that the level of the first voltage signal is high and the level of the second voltage signal is low, the operations of the anti-leakage unit 3 and the anti-leakage input unit 4 may be: the anti-leakage input unit 4 is conducted under the action of the first voltage signal, and transmits the first voltage signal to the anti-leakage input node M, so that the voltage of the anti-leakage input node M is increased. In the case where the anti-leakage unit 3 is turned on under the control of the voltage of the second pull-up node Q2, the anti-leakage unit 3 transmits the first voltage signal received at the anti-leakage input node M to the second anti-leakage node OFF2, so that the voltage of the second anti-leakage node OFF2 increases.

The present disclosure can realize the anti-leakage protection of the second pull-up node Q2 by using the anti-leakage unit 3 and the anti-leakage input unit 4 by electrically connecting the second anti-leakage node OFF2 in the second scan unit 2 with the anti-leakage unit 3. In this way, the display device 2000 applied with the shift register 100 can have a better display effect, and avoid using a constant high voltage signal line for transmitting a constant high voltage signal, so as to avoid the situation that the first voltage signal line and the second voltage signal line are subject to electrochemical corrosion and fail due to continuous transmission of the constant high voltage signal for a long time, thereby improving the reliability of the gate driving circuit 1000.

In some embodiments, as shown in fig. 9, the anti-creeping unit 3 further includes: a second anti-leakage circuit 302.

In some examples, as shown in fig. 9 and 12-17, the second anti-leakage circuit 302 is electrically connected to the second pull-up node Q2, the anti-leakage input node M, and the second anti-leakage node OFF2. Wherein the second anti-leakage circuit 302 is configured to transmit the first voltage signal or the second voltage signal from the anti-leakage input node M to the second anti-leakage node OFF2 under control of the voltage of the second pull-up node Q2.

For example, in the case where the second input circuit 201 charges the second pull-up node Q2 such that the voltage of the second pull-up node Q2 increases, the second anti-leakage circuit 302 may be turned on under the control of the voltage of the second pull-up node Q2, transmitting the first voltage signal or the second voltage signal received from the anti-leakage input node M to the second anti-leakage node OFF2.

Here, in the case where the level of the first voltage signal is high and the level of the second voltage signal is low, the first voltage signal may be transmitted to the anti-leakage input node M through the anti-leakage input unit 4. In the case where the second anti-leakage circuit 302 is turned on, the second anti-leakage circuit 302 may receive the first voltage signal at the anti-leakage input node M and transmit the first voltage signal to the second anti-leakage node OFF2, so that the voltage of the second anti-leakage node OFF2 increases, and the voltage difference between the second anti-leakage node OFF2 and the second pull-up node Q2 is reduced.

In the case where the level of the first voltage signal is low and the level of the second voltage signal is high, the second voltage signal may be transmitted to the anti-leakage input node M through the anti-leakage input unit 4. In the case where the second anti-leakage circuit 302 is turned on, the second anti-leakage circuit 302 may receive the second voltage signal at the anti-leakage input node M and transmit the second voltage signal to the second anti-leakage node OFF2, so that the voltage of the second anti-leakage node OFF2 increases, and the voltage difference between the second anti-leakage node OFF2 and the second pull-up node Q2 is reduced.

The structure of the second anti-creeping circuit 302 included in the anti-creeping unit 3 is schematically described below.

In some examples, as shown in fig. 13, 15, and 17, the second anti-leakage circuit 302 includes: and a fourth transistor M4.

As illustrated in fig. 13, 15 and 17, the control electrode of the fourth transistor M4 is electrically connected to the second pull-up node Q2, the first electrode of the fourth transistor M4 is electrically connected to the anti-leakage input node M, and the second electrode of the fourth transistor M4 is electrically connected to the second anti-leakage node OFF2.

For example, in the case where the second input circuit 201 charges the second pull-up node Q2 such that the voltage of the second pull-up node Q2 increases, the fourth transistor M4 may be turned on under the control of the voltage of the second pull-up node Q2, receive the first voltage signal or the second voltage signal from the anti-leakage input node M, and transmit the received first voltage signal or second voltage signal to the second anti-leakage node OFF2.

The structures of the first input circuit 101 and the first output circuit 102 included in the first scanning unit 1, and the second input circuit 201 and the second output circuit 202 included in the second scanning unit 2 are schematically described below.

In some examples, as shown in fig. 11, 13, 15, and 17, the first input circuit 101 may include: a fifth transistor M5 and a sixth transistor M6.

As shown in fig. 11, 13, 15 and 17, the control electrode of the fifth transistor M5 is electrically connected to the input signal terminal Iput, the first electrode of the fifth transistor M5 is electrically connected to the input signal terminal Iput, and the second electrode of the fifth transistor M5 is electrically connected to the first electrode of the sixth transistor M6 and the first leakage preventing node OFF1. The fifth transistor M5 is configured to be turned on under the control of the input signal transmitted from the input signal terminal Iput, and transmits the input signal to the first electrode of the sixth transistor M6 and the first anti-leakage node OFF1.

As shown in fig. 11, 13, 15 and 17, the control electrode of the sixth transistor M6 is electrically connected to the input signal terminal Iput, and the second electrode of the sixth transistor M6 is electrically connected to the first pull-up node Q1. The sixth transistor M6 is configured to be turned on under the control of the input signal transmitted from the input signal terminal Iput, and to transmit the input signal to the first pull-up node Q1.

For example, in the case where the level of the input signal transmitted by the input signal terminal Iput is high, the fifth transistor M5 and the sixth transistor M6 may be simultaneously turned on by the input signal. The fifth transistor M5 may receive the input signal transmitted by the input signal terminal Iput, and transmit the received input signal to the first electrode of the sixth transistor M6 and the first anti-leakage node OFF1. The sixth transistor M6 may transmit the received input signal to the first pull-up node Q1, and charge the first pull-up node Q1 such that the voltage of the first pull-up node Q1 increases.

Here, after the input signal finishes charging the first pull-up node Q1, the level of the input signal may be changed from a high level to a low level (the low level may be, for example, the level of the third voltage signal), and the fifth transistor M5 and the sixth transistor M6 may be turned OFF under the action of the input signal (the level thereof is the low level), so that the voltages at the control electrode of the sixth transistor M6 and the first anti-leakage node OFF1 are low voltages (the low voltage is the level of the third voltage signal, which is lower than the voltage of the first pull-up node Q1). Since the voltage of the first pull-up node Q1 increases, the first anti-leakage circuit 301 may be turned on under the control of the voltage of the first pull-up node Q1, and transmit the first voltage signal or the second voltage signal to the first anti-leakage node OFF1, so that the voltage of the first anti-leakage node OFF1 increases, further reducing the voltage difference between the first anti-leakage node OFF1 and the first pull-up node Q1, and making the voltage difference between the control electrode and the first electrode of the sixth transistor M6 smaller than zero, so as to ensure that the sixth transistor M6 is completely or more completely turned OFF. This prevents the first pull-up node Q1 from leaking through the first input circuit 101, so that the first pull-up node Q1 can be maintained at a higher, more stable voltage.

In some examples, as shown in fig. 11, 13, 15, and 17, the first output circuit 102 may include: a seventh transistor M7, an eighth transistor M8, and a first capacitor C1.

As illustrated in fig. 11, 13, 15 and 17, the control electrode of the seventh transistor M7 is electrically connected to the first pull-up node Q1, the first electrode of the seventh transistor M7 is electrically connected to the first clock signal terminal clkd_1, and the second electrode of the seventh transistor M7 is electrically connected to the shift signal terminal CR < N >. The seventh transistor M7 is configured to be turned on under control of the voltage of the first pull-up node Q1, and to transmit the first clock signal received at the first clock signal terminal clkd_1 to the shift signal terminal CR < N >, such that the shift signal terminal CR < N > outputs the shift signal.

For example, in case the first input circuit 101 is turned on such that the voltage of the first pull-up node Q1 increases, the seventh transistor M7 may be turned on under the control of the high voltage of the first pull-up node Q1, transmit the first clock signal to the shift signal terminal CR < N >, and output the first clock signal as the shift signal from the shift signal terminal CR < N >.

After the first anti-leakage node OFF1 and the first anti-leakage circuit 301 electrically connected to the first anti-leakage node OFF1 are provided, the first pull-up node Q1 can be kept at a higher and more stable voltage, so that the seventh transistor M7 is more stably turned on, and further deviation of the shift signal output by the seventh transistor M7 can be avoided.

As shown in fig. 11, 13, 15 and 17, the control electrode of the eighth transistor M8 is electrically connected to the first pull-up node Q1, the first electrode of the eighth transistor M8 is electrically connected to the second clock signal terminal clke_1, and the second electrode of the eighth transistor M8 is electrically connected to the first scan signal terminal Oput1< N >. The eighth transistor M8 is configured to be turned on under control of the voltage of the first pull-up node Q1, and to transmit the second clock signal received at the second clock signal terminal clke_1 to the first scan signal terminal Oput1< N >, so that the first scan signal terminal Oput1< N > outputs the first scan signal.

For example, in case the first input circuit 101 is turned on such that the voltage of the first pull-up node Q1 increases, the eighth transistor M8 may be turned on under the control of the high voltage of the first pull-up node Q1, transmit the second clock signal to the first scan signal terminal op ut1< N >, and output the second clock signal as the first scan signal from the first scan signal terminal op ut1< N >.

As illustrated in fig. 11, 13, 15 and 17, a first terminal of the first capacitor C1 is electrically connected to the first pull-up node Q1, and a second terminal of the first capacitor C1 is electrically connected to the first scan signal terminal Oput1< N >.

For example, in the case where the first input circuit 101 is turned on, a high level may be transmitted to the first pull-up node Q1, so that the voltage of the first pull-up node Q1 increases, while the first capacitor C1 may also be charged. With the first input circuit 101 turned off, the first capacitor C1 may be discharged such that the first pull-up node Q1 maintains a high level, and thus the eighth transistor M8 maintains an on state.

After the first anti-leakage node OFF1 and the first anti-leakage circuit 301 electrically connected to the first anti-leakage node OFF1 are set, the first pull-up node Q1 can be kept at a higher and more stable voltage, so that the eighth transistor M8 is more stably turned on, and further, the first scan signal output by the eighth transistor M8 is prevented from being deviated.

In some examples, as shown in fig. 13, 15, and 17, the second input circuit 201 may include: a ninth transistor M9 and a tenth transistor M10.

As shown in fig. 13, 15 and 17, the control electrode of the ninth transistor M9 is electrically connected to the input signal terminal Iput, the first electrode of the ninth transistor M9 is electrically connected to the input signal terminal Iput, and the second electrode of the ninth transistor M9 is electrically connected to the first electrode of the tenth transistor M10 and the second anti-leakage node OFF2. The ninth transistor M9 is configured to be turned on under the control of the input signal transmitted from the input signal terminal Iput, and transmits the input signal to the first electrode of the tenth transistor M10 and the second anti-leakage node OFF2.

As shown in fig. 13, 15 and 17, the gate electrode of the tenth transistor M10 is electrically connected to the input signal terminal Iput, and the second electrode of the tenth transistor M10 is electrically connected to the second pull-up node Q2. The tenth transistor M10 is configured to be turned on under the control of the input signal transmitted from the input signal terminal Iput, and to transmit the input signal to the second pull-up node Q2.

For example, in the case where the level of the input signal transmitted by the input signal terminal Iput is high, the ninth transistor M9 and the tenth transistor M10 may be simultaneously turned on by the input signal. The ninth transistor M9 may receive the input signal transmitted by the input signal terminal Iput, and transmit the received input signal to the first electrode of the tenth transistor M10 and the second anti-leakage node OFF2. The tenth transistor M10 may transmit the received input signal to the second pull-up node Q2, and charge the second pull-up node Q2 such that the voltage of the second pull-up node Q2 increases.

Here, after the input signal finishes charging the second pull-up node Q2, the level of the input signal may be changed from a high level to a low level (the low level may be, for example, the level of the third voltage signal), and the ninth transistor M9 and the tenth transistor M10 may be turned OFF under the action of the input signal (the level thereof is the low level), so that the voltages at the control electrode of the tenth transistor M10 and the second anti-leakage node OFF2 are low voltages (the low voltage is the level of the third voltage signal, which is lower than the voltage of the second pull-up node Q2). Since the voltage of the second pull-up node Q2 increases, the second anti-leakage circuit 302 may be turned on under the control of the voltage of the second pull-up node Q2, and transmit the first voltage signal or the second voltage signal to the second anti-leakage node OFF2, so that the voltage of the second anti-leakage node OFF2 increases, further reducing the voltage difference between the second anti-leakage node OFF2 and the second pull-up node Q2, and ensuring that the voltage difference between the control electrode and the first electrode of the tenth transistor M10 is less than zero, so as to ensure that the tenth transistor M10 is completely or more completely turned OFF. This prevents the second pull-up node Q2 from leaking through the second input circuit 201, so that the second pull-up node Q2 can be maintained at a higher, more stable voltage.

In some examples, as shown in fig. 13, 15, and 17, the second output circuit 202 may include: an eleventh transistor M11 and a second capacitor C2.

As illustrated in fig. 13, 15 and 17, the control electrode of the eleventh transistor M11 is electrically connected to the second pull-up node Q2, the first electrode of the eleventh transistor M11 is electrically connected to the third clock signal terminal clke_2, and the second electrode of the eleventh transistor M11 is electrically connected to the second scan signal terminal Oput1< n+1 >. The eleventh transistor M11 is configured to be turned on under control of the voltage of the second pull-up node Q2, and to transmit the third clock signal received at the third clock signal terminal clke_2 to the second scan signal terminal Oput1< n+1>, such that the second scan signal terminal Oput1< n+1> outputs the second scan signal.

For example, in case the second input circuit 201 is turned on such that the voltage of the second pull-up node Q2 increases, the eleventh transistor M11 may be turned on under the control of the high voltage of the second pull-up node Q2, transmit the third clock signal to the second scan signal terminal op ut1< n+1>, and output the third clock signal as the second scan signal from the second scan signal terminal op ut1< n+1 >.

As illustrated in fig. 13, 15 and 17, the first terminal of the second capacitor C2 is electrically connected to the second pull-up node Q2, and the second terminal of the second capacitor C2 is electrically connected to the second scan signal terminal Oput1< n+1 >.

For example, in the case where the second input circuit 201 is turned on, a high level may be transmitted to the second pull-up node Q2, so that the voltage of the second pull-up node Q2 increases, and at the same time, the second capacitor C2 may be charged. With the second input circuit 201 turned off, the second capacitor C2 may be discharged such that the second pull-up node Q2 maintains a high level, and thus the eleventh transistor M11 maintains an on state.

After the second anti-leakage node OFF2 and the second anti-leakage circuit 302 electrically connected to the second anti-leakage node OFF2 are provided, the second pull-up node Q2 can be kept at a higher and more stable voltage, so that the eleventh transistor M11 is more stably turned on, and further, deviation of the second scanning signal output by the eleventh transistor M11 can be avoided.

In some embodiments, as shown in fig. 16 and 17, the first Output circuit 102 is further electrically connected to the fifth clock signal terminal clkf_1 and the first sensing signal terminal Output2< N > (abbreviated as "Oput 2< N >" in the drawings and below). The first output circuit 102 is further configured to transmit the fifth clock signal received at the fifth clock signal terminal clkf_1 to the first sensing signal terminal Oput2< N > under control of the voltage of the first pull-up node Q1.

For example, in the case where the voltage of the first pull-up node Q1 is at a high level, the first output circuit 102 may be turned on under the control of the voltage of the first pull-up node Q1, and output the fifth clock signal received at the fifth clock signal terminal clkf_1 as the first sensing signal from the first sensing signal terminal Oput2< N >.

In some embodiments, as shown in fig. 16 and 17, the second Output circuit 202 is further electrically connected to the sixth clock signal terminal clkf_2 and the second sensing signal terminal Output2< n+1> (abbreviated as "Oput 2< n+1> (in the drawings and below). The second output circuit 202 is further configured to transmit the sixth clock signal received at the sixth clock signal terminal clkf_2 to the second sensing signal terminal oput2< n+1>, under control of the voltage of the second pull-up node Q2.

For example, in the case where the voltage of the second pull-up node Q2 is at the high level, the second output circuit 202 may be turned on under the control of the voltage of the second pull-up node Q2, and output the sixth clock signal received at the sixth clock signal terminal clkf_2 as the second sensing signal from the second sensing signal terminal Oput2< n+1>.

The display phase of one frame includes a display period and a blanking period that are sequentially performed.

For example, in the display period in one frame display period, the voltage of the first pull-up node Q1 is raised by the first input circuit 101, and the voltage of the second pull-up node Q2 is raised by the second input circuit 201. The first scanning signal and the first sensing signal output by the first output circuit 102 may cooperate with each other to drive a corresponding row of sub-pixels in the display panel PNL to perform display scanning; the first scan signal and the second sense signal output by the second output circuit 202 may cooperate with each other to drive the corresponding row of sub-pixels in the display panel PNL to perform display scanning.

For example, in the blanking period in one frame display period, the voltage of the first pull-up node Q1 and the voltage of the second pull-up node Q2 are both raised by the blanking input unit 3. The first scan signal and the first sense signal output by the first output circuit 102 may cooperate with each other to drive a corresponding row of sub-pixels in the display panel PNL to perform external compensation; the second scan signal and the second sense signal output by the second output circuit 102 may cooperate with each other to drive the corresponding row of sub-pixels in the display panel PNL to perform external compensation.

In the case where the first output circuit 102 is not electrically connected to the first sensing signal terminal Oput2< N >, and the second output circuit 202 is not electrically connected to the second sensing signal terminal Oput2< n+1>, both the first scanning signal and the second scanning signal can drive the corresponding row of sub-pixels in the display panel PNL to perform display scanning in the display period in one frame display period, and drive the corresponding row of sub-pixels in the display panel PNL to perform external compensation in the blanking period in one frame display period.

The description of the blanking input unit 3 may refer to the following related description, and will not be repeated here.

Based on this, in some examples, as shown in fig. 17, the first output circuit 102 further includes: a fifth twelve transistor M52 and a fourth capacitor C4.

Illustratively, as shown in fig. 17, the control electrode of the fifty-second transistor M52 is electrically connected to the first pull-up node Q1, the first electrode of the fifty-second transistor M52 is electrically connected to the fifth clock signal terminal clkf_1, and the second electrode of the fifty-second transistor M52 is electrically connected to the first sensing signal terminal Oput2< N >. The fifth twelfth transistor M52 is configured to be turned on under the control of the voltage of the first pull-up node Q1, and to transmit the fifth clock signal received at the fifth clock signal terminal clkf_1 to the first sensing signal terminal Oput2< N >, so that the first sensing signal terminal Oput2< N > outputs the first sensing signal.

For example, in a display period in one frame display period, in case that the first input circuit 101 is turned on such that the voltage of the first pull-up node Q1 increases, the fifty-th transistor M52 may be turned on under the control of the high voltage of the first pull-up node Q1, transmit the fifth clock signal to the first sensing signal terminal op ut2< N >, and output the fifth clock signal as the first sensing signal from the first sensing signal terminal op ut2< N >. In the blanking period in the one-frame display period, in case the blanking input unit 3 causes the voltage of the first pull-up node Q1 to rise, the fifty-th transistor M52 may be turned on under the control of the high voltage of the first pull-up node Q1, transmit the fifth clock signal to the first sensing signal terminal op ut2< N >, and output the fifth clock signal as the first sensing signal from the first sensing signal terminal op ut2< N >.

Illustratively, as shown in fig. 17, a first terminal of the fourth capacitor C4 is electrically connected to the first pull-up node Q1, and a second terminal of the fourth capacitor C4 is electrically connected to the first sensing signal terminal Oput2< N >.

For example, in the display period in one frame display period, in the case where the first input circuit 101 is turned on, a high level may be transmitted to the first pull-up node Q1, so that the voltage of the first pull-up node Q1 increases, and at the same time, the fourth capacitor C4 may be charged. With the first input circuit 101 turned off, the fourth capacitor C4 may be discharged such that the first pull-up node Q1 maintains a high level, thereby maintaining the fifty-second transistor M52 in an on state. In the blanking period in the one-frame display period, in the case where the blanking input unit 3 causes the voltage of the first pull-up node Q1 to rise, the fourth capacitor C4 may also be charged at the same time. In this way, in the case where the blanking input unit 3 is turned off, the fourth capacitor C4 may be discharged so that the first pull-up node Q1 maintains a high level, and thus the fifty-second transistor M52 maintains a conductive state.

After the first anti-leakage node OFF1 and the first anti-leakage circuit 301 electrically connected to the first anti-leakage node OFF1 are set, the first pull-up node Q1 can be kept at a higher and more stable voltage, so that the fifty-second transistor M52 is more stably turned on, and further, deviation of the first sensing signal output by the fifty-second transistor M52 can be avoided.

In some examples, as shown in fig. 17, the second output circuit 202 further includes: a fifty-third transistor M53 and a fifth capacitor C5.

Illustratively, as shown in fig. 17, the control electrode of the fifty-third transistor M53 is electrically connected to the second pull-up node Q2, the first electrode of the thirteenth transistor M53 is electrically connected to the sixth clock signal terminal clkf_2, and the second electrode of the thirteenth transistor M53 is electrically connected to the second sensing signal terminal Oput2< n+1 >. The thirteenth transistor M53 is configured to be turned on under the control of the voltage of the second pull-up node Q2, and to transmit the sixth clock signal received at the sixth clock signal terminal clkf_2 to the second sensing signal terminal oput2< n+1>, so that the second sensing signal terminal oput2< n+1> outputs the second sensing signal.

For example, in a display period in one frame display period, in case the second input circuit 201 is turned on such that the voltage of the second pull-up node Q2 increases, the fifty-third transistor M53 may be turned on under control of the high voltage of the second pull-up node Q2, transmit the sixth clock signal to the second sensing signal terminal Oput2< n+1>, and output the sixth clock signal as the second sensing signal from the second sensing signal terminal Oput2< n+1 >. In the blanking period in the one-frame display period, in case the blanking input unit 3 causes the voltage of the second pull-up node Q2 to rise, the fifty-third transistor M53 may be turned on under the control of the high voltage of the second pull-up node Q2, transmit the sixth clock signal to the second sensing signal terminal Oput2< n+1>, and output the sixth clock signal as the second sensing signal from the second sensing signal terminal Oput2< n+1 >.

Illustratively, as shown in fig. 17, a first terminal of the fifth capacitor C5 is electrically connected to the second pull-up node Q2, and a second terminal of the fifth capacitor C5 is electrically connected to the second sensing signal terminal Oput2< n+1 >.

For example, in the display period in one frame display period, in the case where the second input circuit 201 is turned on, a high level may be transmitted to the second pull-up node Q2, so that the voltage of the second pull-up node Q2 increases, and at the same time, the fifth capacitor C5 may be charged. With the second input circuit 201 turned off, the fifth capacitor C5 may be discharged such that the second pull-up node Q2 maintains a high level, and thus the fifty-third transistor M53 maintains a conductive state. In the blanking period in the one-frame display period, in the case where the blanking input unit 3 causes the voltage of the second pull-up node Q2 to rise, the fifth capacitor C5 may also be charged at the same time. In this way, in the case where the blanking input unit 3 is turned off, the fifth capacitor C5 may be discharged such that the second pull-up node Q2 maintains a high level, and thus the fifty-third transistor M53 maintains an on state.

After the second anti-leakage node OFF2 and the second anti-leakage circuit 302 electrically connected to the second anti-leakage node OFF2 are provided, the second pull-up node Q2 can be kept at a higher and more stable voltage, so that the fifty-third transistor M53 is more stably turned on, and further, deviation of the second sensing signal output by the fifty-third transistor M53 can be avoided.

In some embodiments, as shown in fig. 10 to 17, the first scanning unit 1 may further include: a first control circuit 103. As shown in fig. 12 to 17, in the case where the shift register 100 further includes the second scanning unit 2, the second scanning unit 2 may further include: a second control circuit 203.

In some examples, as shown in fig. 10 to 17, the first control circuit 103 is electrically connected to the first pull-up node Q1, the first voltage signal terminal vdd_a, the first pull-down node qb_a, and the third voltage signal terminal VGL 1. The first control circuit 103 is configured to control the voltage of the first pull-down node qb_a under the control of the voltage of the first pull-up node Q1 and the first voltage signal transmitted by the first voltage signal terminal vdd_a.

Here, the third voltage signal terminal VGL1 may be configured to transmit a direct current low level signal (e.g., lower than or equal to a low level portion of the clock signal). Illustratively, the third voltage terminal VGL1 is grounded.

For example, in case that the first input circuit 101 is turned on such that the voltage of the first pull-up node Q1 increases, the first control circuit 103 may transmit the third voltage signal transmitted by the third voltage signal terminal VGL1 to the first pull-down node qb_a, and pull down the voltage of the first pull-down node qb_a to a low voltage. In the case where the first input circuit 101 is turned off such that the voltage of the first pull-up node Q1 is a low voltage, the first control circuit 103 may transmit the first voltage signal transmitted by the first voltage signal terminal vdd_a to the first pull-down node qb_a, pulling the voltage of the first pull-down node qb_a high.

In some examples, as shown in fig. 12 to 17, the second control circuit 203 is electrically connected to the second pull-up node Q2, the second voltage signal terminal vdd_b, the second pull-down node qb_b, and the third voltage signal terminal VGL 1. The second control circuit 203 is configured to control the voltage of the second pull-down node QB under the control of the voltage of the second pull-up node Q2 and the second voltage signal transmitted by the second voltage signal terminal vdd_b.

For example, in the case where the second input circuit 201 is turned on such that the voltage of the second pull-up node Q2 increases, the second control circuit 203 may transmit the third voltage signal transmitted by the third voltage signal terminal VGL1 to the second pull-down node qb_b, and pull down the voltage of the second pull-down node qb_b to a low voltage. In the case where the second input circuit 201 is turned off such that the voltage of the second pull-up node Q2 is low, the second control circuit 204 may transmit the second voltage signal transmitted by the second voltage signal terminal vdd_b to the second pull-down node qb_b, and pull the voltage of the second pull-down node qb_b high.

The configuration of the first control circuit 103 included in the first scanning unit 1 and the second control circuit 203 included in the second scanning unit 2 is schematically described below.

In some examples, as shown in fig. 11, 13, 15, and 17, the first control circuit includes: a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, and a fifteenth transistor M15.

As shown in fig. 11, 13, 15 and 17, the control electrode of the twelfth transistor M12 is electrically connected to the first voltage signal terminal vdd_a, the first electrode of the twelfth transistor M12 is electrically connected to the first voltage signal terminal vdd_a, and the second electrode of the twelfth transistor M12 is electrically connected to the control electrode of the thirteenth transistor M13 and the first electrode of the fourteenth transistor M14.

For example, in the case that the level of the first voltage signal transmitted by the first voltage signal terminal vdd_a is high, the twelfth transistor M12 may be turned on by the first voltage signal, receive the first voltage signal, and transmit the received first voltage signal to the control electrode of the thirteenth transistor M13 and the first electrode of the fourteenth transistor M14. The thirteenth transistor M13 may be turned on by the first voltage signal.

As shown in fig. 11, 13, 15 and 17, the first pole of the thirteenth transistor M13 is electrically connected to the first voltage signal terminal vdd_a, and the second pole of the thirteenth transistor M13 is electrically connected to the first pull-down node qb_a and the first pole of the fifteenth transistor M15.

For example, after the twelfth transistor M12 is turned on and transmits the first voltage signal to the control electrode of the thirteenth transistor M13, the thirteenth transistor M13 may be turned on by the first voltage signal, receive the first voltage signal, and transmit the received first voltage signal to the first pull-down node qb_a and the first electrode of the fifteenth transistor M15.

As shown in fig. 11, 13, 15 and 17, the control electrode of the fourteenth transistor M14 is electrically connected to the first pull-up node Q1, and the second electrode of the fourteenth transistor M14 is electrically connected to the third voltage signal terminal VGL 1. The control electrode of the fifteenth transistor M15 is electrically connected to the first pull-up node Q1, and the second electrode of the fifteenth transistor M15 is electrically connected to the third voltage signal terminal VGL 1.

For example, in case that the voltage of the first pull-up node Q1 is at a high level, the fourteenth transistor M14 and the fifteenth transistor M15 may be turned on under the control of the voltage of the first pull-up node Q1, the fourteenth transistor M14 may transmit the third voltage signal transmitted by the third voltage signal terminal VGL1 to the control electrode of the thirteenth transistor M13 such that the thirteenth transistor M13 is turned off, and the fifteenth transistor M15 may transmit the third voltage signal transmitted by the third voltage signal terminal VGL1 to the first pull-down node qb_a and pull down the voltage of the first pull-down node qb_a to a low level.

In case that the voltage of the first pull-up node Q1 is low level, the fourteenth transistor M14 and the fifteenth transistor M15 may be turned off under the control of the voltage of the first pull-up node Q1, and the thirteenth transistor M13 may transmit the received first voltage signal to the first pull-down node qb_a to pull up the voltage of the first pull-down node qb_a to high level.

In some examples, as shown in fig. 13, 15, and 17, the second control circuit 203 includes: a sixteenth transistor M16, a seventeenth transistor M17, an eighteenth transistor M18, and a nineteenth transistor M19.

As shown in fig. 13, 15 and 17, the control electrode of the sixteenth transistor M16 is electrically connected to the second voltage signal terminal vdd_b, the first electrode of the sixteenth transistor M16 is electrically connected to the second voltage signal terminal vdd_b, and the second electrode of the sixteenth transistor M16 is electrically connected to the control electrode of the seventeenth transistor M17 and the first electrode of the eighteenth transistor M18.

For example, in the case that the level of the second voltage signal transmitted by the second voltage signal terminal vdd_b is high, the sixteenth transistor M16 may be turned on by the second voltage signal, receive the second voltage signal, and transmit the received second voltage signal to the control electrode of the seventeenth transistor M17 and the first electrode of the eighteenth transistor M18. Wherein, seventeenth transistor M17 may be turned on by the second voltage signal.

As illustrated in fig. 13, 15 and 17, the first pole of the seventeenth transistor M17 is electrically connected to the second voltage signal terminal vdd_b, and the second pole of the seventeenth transistor M17 is electrically connected to the second pull-down node qb_b and the first pole of the nineteenth transistor M19.

For example, after the sixteenth transistor M16 is turned on and transmits the second voltage signal to the control electrode of the seventeenth transistor M17, the seventeenth transistor M17 may be turned on by the second voltage signal and receive the second voltage signal, and transmit the received second voltage signal to the second pull-down node qb_b and the first electrode of the nineteenth transistor M19.

As shown in fig. 13, 15 and 17, the control electrode of the eighteenth transistor M18 is electrically connected to the second pull-up node Q2, and the second electrode of the eighteenth transistor M18 is electrically connected to the third voltage signal terminal VGL 1. The control electrode of the nineteenth transistor M19 is electrically connected to the second pull-up node Q2, and the second electrode of the nineteenth transistor M19 is electrically connected to the third voltage signal terminal VGL 1.

For example, in case that the voltage of the second pull-up node Q2 is at a high level, the eighteenth transistor M18 and the nineteenth transistor M19 may be turned on under the control of the voltage of the second pull-up node Q2, the eighteenth transistor M18 may transmit the third voltage signal transmitted by the third voltage signal terminal VGL1 to the control electrode of the seventeenth transistor M17 so that the seventeenth transistor M17 is turned off, and the nineteenth transistor M19 may transmit the third voltage signal transmitted by the third voltage signal terminal VGL1 to the second pull-down node QB and pull down the voltage of the second pull-down node QB to a low level.

In case that the voltage of the second pull-up node Q2 is low level, the eighteenth transistor M18 and the nineteenth transistor M19 may be turned off under the control of the voltage of the second pull-up node Q2, and the seventeenth transistor M17 may transmit the received second voltage signal to the second pull-down node qb_b, pulling the voltage of the second pull-down node qb_b high level.

It should be noted that the first voltage signal transmitted by the first voltage signal terminal vdd_a and the second voltage signal transmitted by the second voltage signal terminal vdd_b are opposite signals. Therefore, in the display stage of one frame, if the level of the first voltage signal is high and the level of the second voltage signal is low, the twelfth transistor M12 is kept in a turned-on state, and the first pull-up node Q1 and the first pull-down node qb_a are set to be opposite to each other in potential by the plurality of transistors included in the first control circuit 103; while the sixteenth transistor M16 and the seventeenth transistor M17 remain in an off state, in the case where the voltage of the second pull-up node Q2 is high or low, the potential of the second pull-down node qb_b is low. In the display stage of one frame, if the level of the first voltage signal is low and the level of the second voltage signal is high, the twelfth transistor M12 and the thirteenth transistor M13 remain in an off state, and in the case that the voltage of the first pull-up node Q1 is high or low, the potential of the first pull-down node qb_a is low; while the sixteenth transistor M16 is kept on, the potential of the second pull-up node Q2 and the potential of the second pull-down node QB are set to be a set of opposite potentials by the plurality of transistors included in the second control circuit 203.

The first control circuit 103 and the second control circuit 203 alternately operate in the display phases of different frames.

In some embodiments, as shown in fig. 10 to 17, the first scanning unit 1 may further include: a first reset circuit 104. As shown in fig. 12 to 17, the second scanning unit 2 may further include: a second reset circuit 204.

In some examples, as shown in fig. 10 to 17, the first reset circuit 104 is electrically connected to the first pull-down node qb_a, the first pull-up node Q1, the third voltage signal terminal VGL1, and the first anti-leakage node OFF 1. Wherein the first reset circuit 104 is configured to reset the first pull-up node Q1 under control of the voltage of the first pull-down node qb_a.

In the case where the shift register 100 further includes the second scan cell 2, the first reset circuit 104 is further electrically connected to the second pull-down node qb_b. The first reset circuit 104 is further configured to reset the first pull-up node Q1 under control of the voltage of the second pull-down node qb_b.

For example, in the case that the voltage of the first pull-down node qb_a is at the high level, the first reset circuit 104 may be turned on by the voltage of the first pull-down node qb_a, and transmit the third voltage signal transmitted by the third voltage signal terminal VGL1 to the first pull-up node Q1 to perform the pull-down reset on the first pull-up node Q1. In the case that the voltage of the second pull-down node qb_b is at the high level, the first reset circuit 104 may be turned on under the voltage of the second pull-down node qb_b, and transmit the third voltage signal transmitted by the third voltage signal terminal VGL1 to the first pull-up node Q1 to perform the pull-down reset on the first pull-up node Q1.

Here, when the potential of the first pull-up node Q1 is high and the first reset circuit 104 is in an inactive state, a large voltage difference exists between the first pull-up node Q1 and the third voltage signal terminal VGL1, so that the first pull-up node Q1 is easy to leak through the first reset circuit 104, and the stability of the potential of the first pull-up node Q1 is affected.

By electrically connecting the first reset circuit 104 with the first anti-leakage node OFF1, the first voltage signal or the second voltage signal can be transmitted to the first anti-leakage node OFF1 under the condition that the potential of the first pull-up node Q1 is high, the potential of the first anti-leakage node OFF1 is raised, the voltage difference between the first pull-up node Q1 and the third voltage signal end VGL1 is reduced, the first pull-up node Q1 is prevented from leaking electricity through the first reset circuit 104, and the stability of the potential of the first pull-up node Q1 is ensured.

In some examples, as shown in fig. 12 to 17, the second reset circuit 204 is electrically connected to the first pull-down node qb_a, the second pull-down node QB, the second pull-up node Q2, the third voltage signal terminal VGL1, and the second anti-leakage node OFF 2. Wherein the second reset circuit 204 is configured to reset the second pull-up node Q2 under control of the voltage of the first pull-down node qb_a or the voltage of the second pull-down node qb_b.

For example, in the case that the voltage of the first pull-down node qb_a is at the high level, the second reset circuit 204 may be turned on by the voltage of the first pull-down node qb_a, and transmit the third voltage signal transmitted by the third voltage signal terminal VGL1 to the second pull-up node Q2 to perform the pull-down reset on the second pull-up node Q2. In the case that the voltage of the second pull-down node qb_b is at the high level, the second reset circuit 204 may be turned on under the voltage of the second pull-down node qb_b, and transmit the third voltage signal transmitted by the third voltage signal terminal VGL1 to the second pull-up node Q2 to perform the pull-down reset on the second pull-up node Q2.

Here, when the potential of the second pull-up node Q1 is high and the second reset circuit 204 is in an inactive state, a large voltage difference exists between the second pull-up node Q2 and the third voltage signal terminal VGL1, so that the second pull-up node Q2 is easy to leak through the second reset circuit 204, and the stability of the potential of the second pull-up node Q2 is affected.

By electrically connecting the second reset circuit 204 with the second anti-leakage node OFF2, the first voltage signal or the second voltage signal can be transmitted to the second anti-leakage node OFF2 under the condition that the potential of the second pull-up node Q2 is high, the potential of the second anti-leakage node OFF2 is raised, the voltage difference between the second pull-up node Q2 and the third voltage signal end VGL1 is reduced, the second pull-up node Q2 is prevented from leaking electricity through the second reset circuit 204, and the stability of the potential of the second pull-up node Q2 is ensured.

The configuration of the first reset circuit 104 included in the first scanning unit 1 and the second reset circuit 204 included in the second scanning unit 2 is schematically described below.

In some examples, as shown in fig. 11, 13, 15, and 17, the first reset circuit 104 includes: a twentieth transistor M20 and a twenty-first transistor M21.

As illustrated in fig. 11, 13, 15 and 17, the control electrode of the twentieth transistor M20 is electrically connected to the first pull-down node qb_a, the first electrode of the twentieth transistor M20 is electrically connected to the first pull-up node Q1, and the second electrode of the twentieth transistor M20 is electrically connected to the first electrode of the twenty-first transistor M21 and the first leakage prevention node OFF 1. The control electrode of the twenty-first transistor M21 is electrically connected to the first pull-down node qb_a, and the second electrode of the twenty-first transistor M21 is electrically connected to the third voltage signal terminal VGL 1.

For example, in case that the voltage of the first pull-down node qb_a is at a high level, the twentieth transistor M20 and the twenty-first transistor M21 may be simultaneously turned on by the voltage of the first pull-down node qb_a, the twenty-first transistor M21 may transmit the third voltage signal transmitted by the third voltage signal terminal VGL1 to the first anti-leakage node OFF1, and the twentieth transistor M20 may transmit the third voltage signal from the first anti-leakage node OFF1 to the first pull-up node Q1 to reset the first pull-up node Q1.

In some examples, as shown in fig. 13, 15, and 17, in the case where the shift register 100 further includes the second scanning unit 2, the first reset circuit 104 further includes: a twenty-second transistor M22 and a twenty-third transistor M23.

As shown in fig. 13, 15 and 17, the control electrode of the twenty-second transistor M22 is electrically connected to the second pull-down node QB, the first electrode of the twenty-second transistor M22 is electrically connected to the first pull-up node Q1, and the second electrode of the twenty-second transistor M22 is electrically connected to the first electrode of the twenty-third transistor M23 and the first leakage preventing node OFF 1. The control electrode of the twenty-third transistor M23 is electrically connected to the second pull-down node qb_b, and the second electrode of the twenty-third transistor M23 is electrically connected to the third voltage signal terminal VGL 1.

For example, in case that the voltage of the second pull-down node QB is at a high level, the twenty-third transistor M22 and the twenty-third transistor M23 may be simultaneously turned on by the voltage of the second pull-down node QB, the twenty-third transistor M23 may transmit the third voltage signal transmitted by the third voltage signal terminal VGL1 to the first anti-leakage node OFF1, and the second transistor M22 may transmit the third voltage signal from the first anti-leakage node OFF1 to the first pull-up node Q1, resetting the first pull-up node Q1.

Here, in the case where the potential of the first pull-up node Q1 is a high potential and the first reset circuit 104 is in an inactive state, the first anti-leakage circuit 301 may be turned on under the control of the voltage of the first pull-up node Q1, and transmit the first voltage signal or the second voltage signal to the first anti-leakage node OFF1, so that the voltage of the first anti-leakage node OFF1 is increased, and further, the voltage difference between the first anti-leakage node OFF1 and the first pull-up node Q1 is reduced, and the voltage difference between the control electrode and the second electrode of the twentieth transistor M20 is less than zero, so that the twentieth transistor M20 is completely or relatively completely turned OFF, and the voltage difference between the control electrode and the second electrode of the twentieth transistor M22 is less than zero, so that the twenty-second transistor M22 is completely or relatively completely turned OFF. This prevents the first pull-up node Q1 from leaking through the first reset circuit 104, so that the first pull-up node Q1 can be maintained at a higher, more stable voltage.

In some examples, as shown in fig. 13, 15, and 17, the second reset circuit 204 includes: a twenty-fourth transistor M24, a twenty-fifth transistor M25, a twenty-sixth transistor M26, and a twenty-seventh transistor M27.

As shown in fig. 13, 15 and 17, the control electrode of the twenty-fourth transistor M24 is electrically connected to the first pull-down node qb_a, the first electrode of the twenty-fourth transistor M24 is electrically connected to the second pull-up node Q2, and the second electrode of the twenty-fourth transistor M24 is electrically connected to the first electrode of the twenty-sixth transistor M26 and the second leakage prevention node OFF 2. The control electrode of the twenty-sixth transistor M26 is electrically connected to the first pull-down node qb_a, and the second electrode of the twenty-sixth transistor M26 is electrically connected to the third voltage signal terminal VGL 1.

For example, in case that the voltage of the first pull-down node qb_a is at a high level, the twenty-fourth transistor M24 and the twenty-sixth transistor M26 may be simultaneously turned on by the voltage of the first pull-down node qb_a, the twenty-sixth transistor M26 may transmit the third voltage signal transmitted from the third voltage signal terminal VGL1 to the second anti-leakage node OFF2, and the twenty-fourth transistor M24 may transmit the third voltage signal from the second anti-leakage node OFF2 to the second pull-up node Q2, and reset the second pull-up node Q2.

As shown in fig. 13, 15 and 17, the control electrode of the twenty-fifth transistor M25 is electrically connected to the second pull-down node QB, the first electrode of the twenty-fifth transistor M25 is electrically connected to the second pull-up node Q2, and the second electrode of the twenty-fifth transistor M25 is electrically connected to the first electrode of the twenty-seventh transistor M27 and the second anti-leakage node OFF 2. The control electrode of the twenty-seventh transistor M27 is electrically connected to the second pull-down node qb_b, and the second electrode of the twenty-seventh transistor M27 is electrically connected to the third voltage signal terminal VGL 1.

For example, in case that the voltage of the second pull-down node QB is at a high level, the twenty-fifth transistor M25 and the twenty-seventh transistor M27 may be simultaneously turned on by the voltage of the second pull-down node QB, the twenty-seventh transistor M27 may transmit the third voltage signal transmitted by the third voltage signal terminal VGL1 to the second anti-leakage node OFF2, and the twenty-fifth transistor M25 may transmit the third voltage signal from the second anti-leakage node OFF2 to the second pull-up node Q2, resetting the second pull-up node Q2.

Here, when the potential of the second pull-up node Q2 is high and the second reset circuit 204 is in an inactive state, the second anti-leakage circuit 302 may be turned on under the control of the voltage of the second pull-up node Q2, and transmit the first voltage signal or the second voltage signal to the second anti-leakage node OFF2, so that the voltage of the second anti-leakage node OFF2 is increased, and further, the voltage difference between the second anti-leakage node OFF2 and the second pull-up node Q2 is reduced, and the voltage difference between the control electrode and the second electrode of the twenty-fourth transistor M24 is less than zero, so that the twenty-fourth transistor M24 is completely or relatively completely turned OFF, and the voltage difference between the control electrode and the second electrode of the twenty-fifth transistor M25 is less than zero, so that the twenty-fifth transistor M25 is completely or relatively completely turned OFF. This prevents the second pull-up node Q2 from leaking through the second reset circuit 204, so that the second pull-up node Q2 can be maintained at a higher, more stable voltage.

In some embodiments, as shown in fig. 10 to 17, the first scanning unit 1 may further include: a third reset circuit 105. As shown in fig. 12 to 17, the second scanning unit 2 may further include: a fourth reset circuit 205.

In some examples, as shown in fig. 10 to 17, the third reset circuit 105 is electrically connected to the display reset signal terminal STD, the first pull-up node Q1, the third voltage signal terminal VGL1, and the first anti-leakage node OFF 1. The third reset circuit 105 is configured to reset the first pull-up node Q1 under the control of the display reset signal transmitted by the display reset signal terminal STD.

For example, in the case where the level of the display reset signal is high, the third reset circuit 105 may be turned on by the display reset signal, and transmit the third voltage signal transmitted by the third voltage signal terminal VGL1 to the first pull-up node Q1, and perform the pull-down reset on the first pull-up node Q1.

Here, when the potential of the first pull-up node Q1 is high and the third reset circuit 105 is in an inactive state, a large voltage difference exists between the first pull-up node Q1 and the third voltage signal terminal VGL1, so that the first pull-up node Q1 is easy to leak through the third reset circuit 105, and the stability of the potential of the first pull-up node Q1 is affected.

By electrically connecting the third reset circuit 105 with the first anti-leakage node OFF1, the first voltage signal or the second voltage signal can be transmitted to the first anti-leakage node OFF1 under the condition that the potential of the first pull-up node Q1 is high, the potential of the first anti-leakage node OFF1 is raised, the voltage difference between the first pull-up node Q1 and the third voltage signal end VGL1 is reduced, the first pull-up node Q1 is prevented from leaking electricity through the third reset circuit 105, and the stability of the potential of the first pull-up node Q1 is ensured.

In some examples, as shown in fig. 12 to 17, the fourth reset circuit 205 is electrically connected to the display reset signal terminal STD, the second pull-up node Q2, the third voltage signal terminal VGL1, and the second anti-leakage node OFF 2. The fourth reset circuit 205 is configured to reset the second pull-up node Q2 under the control of the display reset signal transmitted by the display reset signal terminal STD.

For example, in the case where the level of the display reset signal is high, the fourth reset circuit 205 may be turned on by the display reset signal, and transmit the third voltage signal transmitted by the third voltage signal terminal VGL1 to the second pull-up node Q2, and perform the pull-down reset on the second pull-up node Q2.

Here, when the potential of the second pull-up node Q2 is high and the fourth reset circuit 205 is in an inactive state, a large voltage difference exists between the second pull-up node Q2 and the third voltage signal terminal VGL1, so that the second pull-up node Q2 is easy to leak through the fourth reset circuit 205, and the stability of the potential of the second pull-up node Q2 is affected.

By electrically connecting the fourth reset circuit 205 with the second anti-leakage node OFF2, the first voltage signal or the second voltage signal can be transmitted to the second anti-leakage node OFF2 when the potential of the second pull-up node Q2 is high, so as to raise the potential of the second anti-leakage node OFF2, reduce the voltage difference between the second pull-up node Q2 and the third voltage signal terminal VGL1, avoid the second pull-up node Q2 from leaking electricity through the fourth reset circuit 205, and ensure the stability of the potential of the second pull-up node Q2.

Note that, in the case where the plurality of shift registers 100 are cascade-connected to form the gate driving circuit 1000, the display reset signal terminal STD of one stage of shift register 100 may be electrically connected to the shift signal terminal CR < N > of the other stage of shift register 100, so that the one stage of shift register 100 may receive the shift signal output from the other stage of shift register 100 and use the shift signal as the display reset signal. For example, the display reset signal terminal STD of the nth stage shift register 100 may be electrically connected to the shift signal terminal CR < N > of the n+4 th stage shift register 100.

The configuration of the third reset circuit 105 included in the first scanning unit 1 and the fourth reset circuit 205 included in the second scanning unit 2 is schematically described below.

In some examples, as shown in fig. 11, 13, 15, and 17, the third reset circuit 105 includes: a twenty eighth transistor M28 and a twenty ninth transistor M29.

As shown in fig. 11, 13, 15 and 17, the control electrode of the twenty-eighth transistor M28 is electrically connected to the display reset signal terminal STD, the first electrode of the twenty-eighth transistor M28 is electrically connected to the first pull-up node Q1, and the second electrode of the twenty-eighth transistor M28 is electrically connected to the first electrode of the twenty-ninth transistor M29 and the first leakage preventing node OFF 1. The control electrode of the twenty-ninth transistor M29 is electrically connected to the display reset signal terminal STD, and the second electrode of the twenty-ninth transistor M29 is electrically connected to the third voltage signal terminal VGL 1.

For example, in the case where the level of the display reset signal transmitted by the display reset signal terminal STD is high, the twenty-eighth transistor M28 and the twenty-ninth transistor M29 may be simultaneously turned on by the display reset signal, the twenty-ninth transistor M29 may transmit the third voltage signal transmitted by the third voltage signal terminal VGL1 to the first anti-leakage node OFF1, and the twenty-eighth transistor M28 may transmit the third voltage signal from the first anti-leakage node OFF1 to the first pull-up node Q1 to reset the first pull-up node Q1.

Here, in the case where the potential of the first pull-up node Q1 is a high potential and the third reset circuit 105 is in an inactive state, the first anti-leakage circuit 301 may be turned on under the control of the voltage of the first pull-up node Q1, and transmit the first voltage signal or the second voltage signal to the first anti-leakage node OFF1, so that the voltage of the first anti-leakage node OFF1 is increased, and further, the voltage difference between the first anti-leakage node OFF1 and the first pull-up node Q1 is reduced, and the voltage difference between the control electrode and the second electrode of the twenty-eighth transistor M28 is less than zero, so as to ensure that the twenty-eighth transistor M28 is completely or more completely turned OFF. This prevents the first pull-up node Q1 from leaking through the third reset circuit 105, so that the first pull-up node Q1 can be maintained at a higher, more stable voltage.

In some examples, as shown in fig. 13, 15, and 17, the fourth reset circuit 205 includes: a thirty-first transistor M30 and a thirty-first transistor M31.

As shown in fig. 13, 15 and 17, the control electrode of the thirty-first transistor M30 is electrically connected to the display reset signal terminal STD, the first electrode of the thirty-first transistor M30 is electrically connected to the second pull-up node Q2, and the second electrode of the thirty-first transistor M30 is electrically connected to the first electrode of the thirty-first transistor M31 and the second leakage prevention node OFF 2. The control electrode of the thirty-first transistor M31 is electrically connected to the display reset signal terminal STD, and the second electrode of the thirty-first transistor M31 is electrically connected to the third voltage signal terminal VGL 1.

For example, in the case where the level of the display reset signal transmitted by the display reset signal terminal STD is high, the thirty-first transistor M31 and the thirty-first transistor M30 may be simultaneously turned on by the display reset signal, the thirty-first transistor M31 may transmit the third voltage signal transmitted by the third voltage signal terminal VGL1 to the first anti-leakage node OFF1, and the thirty-first transistor M30 may transmit the third voltage signal from the first anti-leakage node OFF1 to the second pull-up node Q2 to reset the second pull-up node Q2.

Here, in the case where the potential of the second pull-up node Q2 is high and the fourth reset circuit 205 is in an inactive state, the second anti-leakage circuit 302 may be turned on under the control of the voltage of the second pull-up node Q2, and transmit the first voltage signal or the second voltage signal to the second anti-leakage node OFF2, so that the voltage of the second anti-leakage node OFF2 is increased, and further, the voltage difference between the second anti-leakage node OFF2 and the second pull-up node Q2 is reduced, and the voltage difference between the control electrode and the second electrode of the thirty-th transistor M30 is less than zero, so as to ensure that the thirty-th transistor M30 is completely or more completely turned OFF. This prevents the second pull-up node Q2 from leaking through the fourth reset circuit 205, so that the second pull-up node Q2 can be maintained at a higher, more stable voltage.

In some embodiments, as shown in fig. 10 to 17, the first scanning unit 1 may further include: a fifth reset circuit 106. As shown in fig. 13 to 17, the second scanning unit 2 may further include: a sixth reset circuit 206.

In some examples, as shown in fig. 10 to 17, the fifth reset circuit 106 is electrically connected to the global reset signal terminal TRST, the first pull-up node Q1, the third voltage signal terminal VGL1, and the first anti-leakage node OFF 1. The fifth reset circuit 106 is configured to reset the first pull-up node Q1 under the control of the global reset signal transmitted by the global reset signal terminal TRST.

For example, in the case that the level of the global reset signal is high, the fifth reset circuit 106 may be turned on under the action of the global reset signal, and transmit the third voltage signal transmitted by the third voltage signal terminal VGL1 to the first pull-up node Q1, and perform the pull-down reset on the first pull-up node Q1.

Here, when the potential of the first pull-up node Q1 is high and the fifth reset circuit 106 is in an inactive state, a large voltage difference exists between the first pull-up node Q1 and the third voltage signal terminal VGL1, so that the first pull-up node Q1 is easy to leak through the fifth reset circuit 106, and the stability of the potential of the first pull-up node Q1 is affected.

By electrically connecting the fifth reset circuit 106 with the first anti-leakage node OFF1, the first voltage signal or the second voltage signal can be transmitted to the first anti-leakage node OFF1 when the potential of the first pull-up node Q1 is high, so as to raise the potential of the first anti-leakage node OFF1, reduce the voltage difference between the first pull-up node Q1 and the third voltage signal terminal VGL1, avoid the first pull-up node Q1 from leaking electricity through the fifth reset circuit 106, and ensure the stability of the potential of the first pull-up node Q1.

In some examples, as shown in fig. 12 to 17, the sixth reset circuit 206 is electrically connected to the global reset signal terminal TRST, the second pull-up node Q2, the third voltage signal terminal VGL1, and the second anti-leakage node OFF 2. The sixth reset circuit 206 is configured to reset the second pull-up node Q2 under the control of the global reset signal transmitted by the global reset signal terminal TRST.

For example, in the case that the level of the global reset signal is high, the sixth reset circuit 206 may be turned on by the global reset signal, and transmit the third voltage signal transmitted by the third voltage signal terminal VGL1 to the second pull-up node Q2, and perform the pull-down reset on the second pull-up node Q2.

Here, when the potential of the second pull-up node Q2 is high and the sixth reset circuit 206 is in an inactive state, a large voltage difference exists between the second pull-up node Q2 and the third voltage signal terminal VGL1, so that the second pull-up node Q2 is easy to leak through the sixth reset circuit 206, and the stability of the potential of the second pull-up node Q2 is affected.

By electrically connecting the sixth reset circuit 206 with the first anti-leakage node OFF1, the first voltage signal or the second voltage signal can be transmitted to the second anti-leakage node OFF2 when the potential of the second pull-up node Q2 is high, so as to raise the potential of the second anti-leakage node OFF2, reduce the voltage difference between the second pull-up node Q2 and the third voltage signal terminal VGL1, avoid the second pull-up node Q2 from leaking electricity through the sixth reset circuit 206, and ensure the stability of the potential of the second pull-up node Q2.

The configuration of the fifth reset circuit 106 included in the first scanning unit 1 and the sixth reset circuit 206 included in the second scanning unit 2 is schematically described below.

In some examples, as shown in fig. 11, 13, 15, and 17, the fifth reset circuit 106 includes: a thirty-third transistor M32 and a thirteenth transistor M33.

As shown in fig. 11, 13, 15 and 17, the control electrode of the thirty-third transistor M32 is electrically connected to the global reset signal terminal TRST, the first electrode of the thirty-third transistor M32 is electrically connected to the first pull-up node Q1, and the second electrode of the thirty-third transistor M32 is electrically connected to the first electrode of the thirty-third transistor M33 and the first leakage-preventing node OFF 1. The control electrode of the thirty-third transistor M33 is electrically connected to the global reset signal terminal TRST, and the second electrode of the thirty-third transistor M33 is electrically connected to the third voltage signal terminal VGL 1.

For example, in case that the level of the global reset signal transmitted by the global reset signal terminal TRST is high, the thirty-third transistor M32 and the thirty-third transistor M33 may be simultaneously turned on by the global reset signal, the thirty-third transistor M33 may transmit the third voltage signal transmitted by the third voltage signal terminal VGL1 to the first anti-leakage node OFF1, and the thirty-third transistor M32 may transmit the third voltage signal from the first anti-leakage node OFF1 to the first pull-up node Q1 to reset the first pull-up node Q1.

Here, in the case where the potential of the first pull-up node Q1 is a high potential and the fifth reset circuit 106 is in an inactive state, the first anti-leakage circuit 301 may be turned on under the control of the voltage of the first pull-up node Q1, and transmit the first voltage signal or the second voltage signal to the first anti-leakage node OFF1, so that the voltage of the first anti-leakage node OFF1 is increased, and further, the voltage difference between the first anti-leakage node OFF1 and the first pull-up node Q1 is reduced, and the voltage difference between the control electrode and the second electrode of the thirty-second transistor M32 is less than zero, so as to ensure that the thirty-second transistor M32 is completely or more completely turned OFF. This prevents the first pull-up node Q1 from leaking through the fifth reset circuit 106, so that the first pull-up node Q1 can be maintained at a higher, more stable voltage.

In some examples, as shown in fig. 13, 15, and 17, the sixth reset circuit 206 includes: a thirty-fourth transistor M34 and a thirty-fifth transistor M35.

As shown in fig. 13, 15 and 17, the control electrode of the thirty-fourth transistor M34 is electrically connected to the global reset signal terminal TRST, the first electrode of the thirty-fourth transistor M34 is electrically connected to the second pull-up node Q2, and the second electrode of the thirty-fourth transistor M34 is electrically connected to the first electrode of the thirty-fifth transistor M35 and the second anti-leakage node OFF 2. The control electrode of the thirty-fifth transistor M35 is electrically connected to the global reset signal terminal TRST, and the second electrode of the thirty-fifth transistor M35 is electrically connected to the third voltage signal terminal VGL 1.

For example, in the case where the level of the global reset signal transmitted by the global reset signal terminal TRST is high, the thirty-fourth transistor M34 and the thirty-fifth transistor M35 may be simultaneously turned on by the global reset signal, the thirty-fifth transistor M35 may transmit the third voltage signal transmitted by the third voltage signal terminal VGL1 to the first anti-leakage node OFF1, and the thirty-fourth transistor M34 may transmit the third voltage signal from the first anti-leakage node OFF1 to the first pull-up node Q1 to reset the first pull-up node Q1.

Here, in the case where the potential of the second pull-up node Q2 is high and the sixth reset circuit 206 is in an inactive state, the second anti-leakage circuit 302 may be turned on under the control of the voltage of the second pull-up node Q2, and transmit the first voltage signal or the second voltage signal to the second anti-leakage node OFF2, so that the voltage of the second anti-leakage node OFF2 is increased, and further, the voltage difference between the second anti-leakage node OFF2 and the second pull-up node Q2 is reduced, and the voltage difference between the control electrode and the second electrode of the thirty-fourth transistor M34 is less than zero, so as to ensure that the thirty-fourth transistor M34 is completely or more completely turned OFF. This prevents the second pull-up node Q2 from leaking through the sixth reset circuit 206, so that the second pull-up node Q2 can be maintained at a higher, more stable voltage.

In some embodiments, as shown in fig. 10 to 17, the first scanning unit 1 may further include: a seventh reset circuit 107 and an eighth reset circuit 108. As shown in fig. 12 to 17, the second scanning unit 2 may further include: a ninth reset circuit 207 and a tenth reset circuit 208.

In some examples, as shown in fig. 10 to 17, the seventh reset circuit 107 is electrically connected to the first pull-down node qb_a, the shift signal terminal CR < N >, the first scan signal terminal Oput1< N >, the third voltage signal terminal VGL1 and the fourth voltage signal terminal VGL 2. Wherein the seventh reset circuit 107 is configured to reset the shift signal terminal CR < N > and the first scan signal terminal Oput1< N > under the control of the voltage of the first pull-down node qb_a.

For example, as shown in fig. 12 to 17, in the case where the shift register 100 further includes the second scan cell 2, the seventh reset circuit 107 is further electrically connected to the second pull-down node qb_b. The seventh reset circuit 107 is further configured to reset the shift signal terminal CR < N > and the first scan signal terminal Oput1< N > under the control of the voltage of the second pull-down node qb_b.

For example, in the case that the voltage of the first pull-down node qb_a is at the high level, the seventh reset circuit 107 may be turned on by the voltage of the first pull-down node qb_a, transmit the third voltage signal transmitted by the third voltage signal terminal VGL1 to the shift signal terminal CR < N >, perform the pull-down reset on the shift signal terminal CR < N >, and transmit the fourth voltage signal transmitted by the fourth voltage signal terminal VGL2 to the first scan signal terminal Oput1< N >, and perform the pull-down reset on the first scan signal terminal Oput1< N >. In the case that the voltage of the second pull-down node qb_b is at the high level, the seventh reset circuit 107 may be turned on by the voltage of the second pull-down node QB, transmit the third voltage signal transmitted by the third voltage signal terminal VGL1 to the shift signal terminal CR < N >, perform the pull-down reset on the shift signal terminal CR < N >, transmit the fourth voltage signal transmitted by the fourth voltage signal terminal VGL2 to the first scan signal terminal Oput1< N >, and perform the pull-down reset on the first scan signal terminal Oput1< N >.

Here, the fourth voltage signal terminal VGL2 is configured to transmit a dc low level signal (e.g., lower than or equal to a low level portion of the clock signal). Illustratively, the fourth voltage signal terminal VGL2 is grounded. The voltage values of the low level signals transmitted by the third voltage signal terminal VGL1 and the fourth voltage signal terminal VGL2 may be equal or unequal.

In some examples, as shown in fig. 16 and 17, in the case where the first output circuit 102 is also electrically connected to the first sensing signal terminal Oput2< N >, the seventh reset circuit 107 is also electrically connected to the first sensing signal terminal Oput2< N >. The seventh reset circuit 107 is further configured to reset the first sensing signal terminal Oput2< N > under the control of the voltage of the first pull-down node qb_a or the voltage of the second pull-down node qb_b.

For example, in the case that the voltage of the first pull-down node qb_a is at the high level, the seventh reset circuit 107 may be turned on by the voltage of the first pull-down node qb_a, and transmit the third voltage signal transmitted by the third voltage signal terminal VGL1 to the first sensing signal terminal Oput2< N >, and perform the pull-down reset on the first sensing signal terminal Oput2< N >. In the case that the voltage of the second pull-down node qb_b is at the high level, the seventh reset circuit 107 may be turned on by the voltage of the second pull-down node qb_b, and transmit the third voltage signal transmitted by the third voltage signal terminal VGL1 to the first sensing signal terminal Oput2< N >, and perform the pull-down reset on the first sensing signal terminal Oput2< N >.

In some examples, as shown in fig. 10 to 17, the eighth reset circuit 108 is electrically connected to the input signal terminal Iput, the first pull-down node qb_a, and the third voltage signal terminal VGL 1. The eighth reset circuit 108 is configured to reset the first pull-down node qb_a under the control of the input signal transmitted by the input signal terminal Iput.

For example, in the case that the level of the input signal is high, the eighth reset circuit 108 may be turned on by the input signal to transmit the third voltage signal transmitted by the third voltage signal terminal VGL1 to the first pull-down node qb_a, and perform the pull-down reset on the first pull-down node qb_a.

In some examples, as shown in fig. 12 to 17, the ninth reset circuit 207 is electrically connected to the first pull-down node qb_a, the second pull-down node QB, the second scan signal terminal Oput1< n+1> and the fourth voltage signal terminal VGL 2. The ninth reset circuit 207 is configured to reset the second scan signal terminal Oput1< n+1> under the control of the voltage of the first pull-down node qb_a or the second pull-down node qb_b.

For example, in the case that the voltage of the first pull-down node qb_a is at the high level, the ninth reset circuit 207 may be turned on by the voltage of the first pull-down node qb_a, and may transmit the fourth voltage signal transmitted by the fourth voltage signal terminal VGL2 to the second scan signal terminal Oput1< n+1>, and perform the pull-down reset on the second scan signal terminal Oput1< n+1 >. In the case that the voltage of the second pull-down node qb_b is at the high level, the ninth reset circuit 207 may be turned on by the voltage of the second pull-down node qb_b, and transmit the fourth voltage signal transmitted by the fourth voltage signal terminal VGL2 to the second scan signal terminal Oput1< n+1>, and perform the pull-down reset on the second scan signal terminal Oput1< n+1 >.

In some examples, as shown in fig. 16 and 17, in the case where the second output circuit 202 is also electrically connected to the second sensing signal terminal oput2< n+1>, the ninth reset circuit 207 is also electrically connected to the second sensing signal terminal oput2< n+1 >. The ninth reset circuit 207 is further configured to electrically reset the second sensing signal terminal Oput2< n+1> under the control of the voltage of the first pull-down node qb_a or the voltage of the second pull-down node qb_b.

For example, in the case that the voltage of the first pull-down node qb_a is at the high level, the ninth reset circuit 207 may be turned on by the voltage of the first pull-down node qb_a, and may transmit the fourth voltage signal transmitted by the fourth voltage signal terminal VGL2 to the second sensing signal terminal Oput2< n+1>, and perform the pull-down reset on the second sensing signal terminal Oput2< n+1 >. In the case that the voltage of the second pull-down node qb_b is at the high level, the ninth reset circuit 207 may be turned on by the voltage of the second pull-down node qb_b, and transmit the fourth voltage signal transmitted by the fourth voltage signal terminal VGL2 to the second sensing signal terminal oput2< n+1>, and perform the pull-down reset on the second sensing signal terminal oput2< n+1 >.

In some examples, as shown in fig. 12 to 17, the tenth reset circuit 208 is electrically connected to the input signal terminal Iput, the second pull-down node qb_b, and the third voltage signal terminal VGL 1. The tenth reset circuit 208 is configured to reset the second pull-down node QB under the control of the input signal transmitted by the input signal terminal Iput.

For example, in the case that the level of the input signal is high, the tenth reset circuit 208 may be turned on by the input signal, and transmit the third voltage signal transmitted by the third voltage signal terminal VGL1 to the second pull-down node qb_b, and perform the pull-down reset on the second pull-down node qb_b.

The structures of the seventh reset circuit 107 and the eighth reset circuit 108 included in the first scanning unit 1, and the ninth reset circuit 207 and the tenth reset circuit 208 included in the second scanning unit 2 are schematically described below.

In some examples, as shown in fig. 11, 13, 15, and 17, the seventh reset circuit 107 includes: a thirty-sixth transistor M36 and a thirty-ninth transistor M39.

As illustrated in fig. 11, 13, 15 and 17, the control electrode of the thirty-sixth transistor M36 is electrically connected to the first pull-down node qb_a, the first electrode of the thirty-sixth transistor M36 is electrically connected to the shift signal terminal CR < N >, and the second electrode of the thirty-sixth transistor M36 is electrically connected to the third voltage signal terminal VGL 1.

For example, in the case that the voltage of the first pull-down node qb_a is at the high level, the thirty-sixth transistor M36 may be turned on by the voltage of the first pull-down node qb_a, and the third voltage signal transmitted by the third voltage signal terminal VGL1 is transmitted to the shift signal terminal CR < N >, and the shift signal terminal CR < N > is subjected to the pull-down reset.

As illustrated in fig. 11, 13, 15 and 17, the control electrode of the thirty-ninth transistor M39 is electrically connected to the first pull-down node qb_a, the first electrode of the thirty-ninth transistor M39 is electrically connected to the first scan signal terminal Oput1< N >, and the second electrode of the thirty-ninth transistor M39 is electrically connected to the fourth voltage signal terminal VGL 2.

For example, in case that the voltage of the first pull-down node qb_a is at the high level, the thirty-ninth transistor M39 may be turned on by the voltage of the first pull-down node qb_a, transmit the fourth voltage signal transmitted by the fourth voltage signal terminal VGL2 to the first scan signal terminal op ut1< N >, and perform the pull-down reset on the first scan signal terminal op ut1< N >.

In some examples, as shown in fig. 13, 15, and 17, in the case where the shift register 100 further includes the second scanning unit 2, the seventh reset circuit 107 further includes: a thirty-eighth transistor M38 and a thirty-seventh transistor M37.

As illustrated in fig. 13, 15 and 17, the control electrode of the thirty-eighth transistor M38 is electrically connected to the second pull-down node QB, the first electrode of the thirty-eighth transistor M38 is electrically connected to the shift signal terminal CR < N >, and the second electrode of the thirty-eighth transistor M38 is electrically connected to the third voltage signal terminal VGL 1.

For example, in the case that the voltage of the second pull-down node qb_b is at the high level, the thirty-eighth transistor M38 may be turned on by the voltage of the second pull-down node qb_b, and the third voltage signal transmitted by the third voltage signal terminal VGL1 is transmitted to the shift signal terminal CR < N >, and the shift signal terminal CR < N > is subjected to the pull-down reset.

As illustrated in fig. 13, 15 and 17, the control electrode of the thirty-seventh transistor M37 is electrically connected to the second pull-down node QB, the first electrode of the thirty-seventh transistor M37 is electrically connected to the first scan signal terminal Oput1< N >, and the second electrode of the thirty-seventh transistor M37 is electrically connected to the fourth voltage signal terminal VGL 2.

For example, in case that the voltage of the second pull-down node qb_b is at a high level, the thirty-seventh transistor M37 may be turned on by the voltage of the second pull-down node QB, transmit the fourth voltage signal transmitted by the fourth voltage signal terminal VGL2 to the first scan signal terminal Oput1< N >, and perform a pull-down reset on the first scan signal terminal Oput1< N >.

In some examples, as shown in fig. 17, in a case where the first output circuit 102 is also electrically connected to the first sensing signal terminal Oput2< N >, the seventh reset circuit 107 further includes: a fifty-fourth transistor M54 and a fifty-fifth transistor M55.

Illustratively, as shown in fig. 17, the control electrode of the fifty-fourth transistor M54 is electrically connected to the first pull-down node qb_a, the first electrode of the fifty-fourth transistor M54 is electrically connected to the first sensing signal terminal Oput2< N >, and the second electrode of the fifty-fourth transistor M54 is electrically connected to the fourth voltage signal terminal VGL 2. The control electrode of the fifty-fifth transistor M55 is electrically connected to the second pull-down node qb_b, the first electrode of the fifty-fifth transistor M55 is electrically connected to the first sensing signal terminal Oput2< N >, and the second electrode of the fifty-fifth transistor M55 is electrically connected to the fourth voltage signal terminal VGL 2.

For example, in case that the voltage of the first pull-down node qb_a is at the high level, the fifty-fourth transistor M54 may be turned on by the voltage of the first pull-down node qb_a to transmit the fourth voltage signal transmitted by the fourth voltage signal terminal VGL2 to the first sensing signal terminal Oput2< N >. In the case that the voltage of the second pull-down node qb_b is at the high level, the fifty-fifth transistor M55 may be turned on by the voltage of the second pull-down node QB, and the fourth voltage signal transmitted by the fourth voltage signal terminal VGL2 is transmitted to the first sensing signal terminal Oput2< N >.

In some examples, as shown in fig. 11, 13, 15, and 17, the eighth reset circuit 108 includes: forty-first transistor M40.

As illustrated in fig. 11, 13, 15 and 17, the control electrode of the forty transistor M40 is electrically connected to the input signal terminal Iput, the first electrode of the forty transistor M40 is electrically connected to the first pull-down node qb_a, and the second electrode of the forty transistor M40 is electrically connected to the third voltage signal terminal VGL 1.

For example, in case that the level of the input signal is high, the fortieth transistor M40 may be turned on by the input signal, transmit the third voltage signal transmitted by the third voltage signal terminal VGL1 to the first pull-down node qb_a, and perform the pull-down reset on the first pull-down node qb_a.

In some examples, as shown in fig. 13, 15, and 17, the ninth reset circuit 207 includes: a forty-first transistor M41 and a forty-second transistor M42.

As shown in fig. 13, 15 and 17, the control electrode of the forty-first transistor M41 is electrically connected to the second pull-down node QB, the first electrode of the forty-first transistor M41 is electrically connected to the second scan signal terminal Oput1< n+1>, and the second electrode of the forty-first transistor M41 is electrically connected to the fourth voltage signal terminal VGL 2.

For example, in the case that the voltage of the second pull-down node QB is at the high level, the forty-first transistor M41 may be turned on by the voltage of the second pull-down node QB, and the fourth voltage signal transmitted by the fourth voltage signal terminal VGL2 is transmitted to the second scan signal terminal Oput1< n+1>, and the pull-down reset is performed on the second scan signal terminal Oput1< n+1 >.

As shown in fig. 13, 15 and 17, the control electrode of the forty-second transistor M42 is electrically connected to the first pull-down node qb_a, the first electrode of the forty-second transistor M42 is electrically connected to the second scan signal terminal Oput1< N >, and the second electrode of the forty-second transistor M42 is electrically connected to the fourth voltage signal terminal VGL 2.

For example, in case that the voltage of the first pull-down node qb_a is at a high level, the forty-second transistor M42 may be turned on by the voltage of the first pull-down node qb_a, transmit the fourth voltage signal transmitted by the fourth voltage signal terminal VGL2 to the second scan signal terminal Oput1< n+1>, and perform the pull-down reset on the second scan signal terminal Oput1< n+1 >.

In some examples, as shown in fig. 17, in a case where the second output circuit 202 is also electrically connected to the second sensing signal terminal Oput2< n+1>, the ninth reset circuit 207 further includes: a fifty-sixth transistor M56 and a fifty-seventh transistor M57.

Illustratively, as shown in fig. 17, the control electrode of the fifty-sixth transistor M56 is electrically connected to the second pull-down node qb_b, the first electrode of the fifty-sixth transistor M56 is electrically connected to the second sensing signal terminal Oput2< n+1>, and the second electrode of the fifty-sixth transistor M56 is electrically connected to the fourth voltage signal terminal VGL 2. The control electrode of the fifty-seventh transistor M57 is electrically connected to the first pull-down node qb_a, the first electrode of the fifty-seventh transistor M57 is electrically connected to the second sensing signal terminal Oput2< n+1>, and the second electrode of the fifty-seventh transistor M57 is electrically connected to the fourth voltage signal terminal VGL 2.

For example, in the case that the voltage of the second pull-down node qb_b is at the high level, the fifty-sixth transistor M56 may be turned on by the voltage of the second pull-down node qb_b to transmit the fourth voltage signal transmitted by the fourth voltage signal terminal VGL2 to the second sensing signal terminal Oput2< n+1>. In the case that the voltage of the first pull-down node qb_a is at the high level, the fifty-seventh transistor M57 may be turned on by the voltage of the first pull-down node qb_a to transmit the fourth voltage signal transmitted by the fourth voltage signal terminal VGL2 to the second sensing signal terminal Oput2< n+1>.

In some examples, as shown in fig. 13, 15, and 17, the tenth reset circuit 208 includes: forty-third transistor M43.

As shown in fig. 13, 15 and 17, the control electrode of the forty-third transistor M43 is electrically connected to the input signal terminal Iput, the first electrode of the thirteenth transistor M43 is electrically connected to the second pull-down node qb_b, and the second electrode of the thirteenth transistor M43 is electrically connected to the third voltage signal terminal VGL 1.

For example, in case that the level of the input signal is high, the forty-third transistor M43 may be turned on by the input signal, transmit the third voltage signal transmitted by the third voltage signal terminal VGL1 to the second pull-down node qb_b, and perform a pull-down reset on the second pull-down node qb_b.

In some embodiments, the manner of compensating the sub-pixels in the display panel PNL may include various manners, and may be selected according to actual needs.

For example, a pixel compensation circuit may be provided in a sub-pixel to internally compensate the sub-pixel with the pixel compensation circuit. For another example, a sensing transistor may be provided in the sub-pixel to externally compensate the sub-pixel using the sensing transistor.

The present disclosure exemplifies a manner of employing external compensation. For example, as shown in fig. 1, the structure of each subpixel in the display panel PNL may be, for example, a 3T1C structure ("T" is denoted as a transistor and "C" is denoted as a capacitor). The pixel driving circuit of the sub-pixel may include a switching transistor T1, a driving transistor T2, a sensing transistor T3, and a storage capacitor Cst.

Here, in the shift register 100, in case that the first output circuit 201 in the first scan cell 1 is not electrically connected to the first sensing signal terminal op ut2< N >, the first scan signal terminal op ut1< N > may be electrically connected to one gate line GL through which the first scan signal may be transmitted to the control electrode of the corresponding switching transistor T1, and at the same time, the first scan signal may be transmitted as the first sensing signal to the control electrode of the corresponding sensing transistor T3 through the gate line GL. In the case where the second output circuit 202 in the second scan cell 2 is not electrically connected to the second sensing signal terminal oput2< n+1>, the second scan signal terminal oput1< n+1> may be electrically connected to a gate line GL through which the first scan signal may be transmitted to the control electrode of the corresponding switching transistor T1, and at the same time, the second scan signal may be transmitted as the second sensing signal to the control electrode of the corresponding sensing transistor T3 through the gate line GL.

In the shift register 100, in case that the first output circuit 201 in the first scan cell 1 is electrically connected to the first sensing signal terminal Oput2< N >, the first scan signal terminal Oput1< N > may be electrically connected to one gate line GL and transmit the first scan signal to the control electrode of the corresponding switching transistor T1 through the gate line GL, and the first sensing signal terminal Oput2< N > may be electrically connected to the other gate line GL and transmit the first sensing signal to the control electrode of the corresponding sensing transistor T3 through the gate line GL. In the case that the second output circuit 202 in the second scan cell 2 is electrically connected to the second sensing signal terminal Oput2< n+1>, the second scan signal terminal Oput1< n+1> may be electrically connected to one gate line GL and transmit the second scan signal to the control electrode of the corresponding switching transistor T1 through the gate line GL, and the second sensing signal terminal Oput2< n+1> may be electrically connected to the other gate line GL and transmit the second sensing signal to the control electrode of the corresponding sensing transistor T3 through the gate line GL.

From the foregoing, the display stage of one frame may include, for example, a display period and a blanking period that are sequentially performed. In the display period, the shift register 100 may drive the corresponding sub-pixel in the display panel PNL to perform display scanning; in the blanking period, the shift register 100 may drive the corresponding pixel in the display panel PNL to perform external compensation.

Based on this, in some embodiments, as shown in fig. 14 to 17, the shift register 100 may further include: the input unit 5 is blanked.

In some examples, as shown in fig. 14 to 17, the blanking input unit 5 is electrically connected to the selection control signal terminal OE, the input signal terminal Iput, the third voltage signal terminal VGL1, the fourth clock signal terminal CLKA, the first pull-up node Q1, the first anti-leakage node OFF1, and the anti-leakage input node M. Wherein the blanking input unit 5 is configured to transmit the fourth clock signal received at the fourth clock signal terminal CLKA to the first pull-up node Q1 under the control of the selection control signal transmitted by the selection control signal terminal OE.

When the shift register 100 further includes the second scan cell 2, the blanking input cell 5 is electrically connected to the second pull-up node Q2 and the second anti-leakage node OFF 2. The blanking input unit 5 is further configured to transmit the fourth clock signal received at the fourth clock signal terminal CLKA to the second pull-up node Q2 under the control of the selection control signal transmitted at the selection control signal terminal OE.

For example, in the blanking period in the display stage of one frame, in the case where the level of the selection control signal transmitted by the selection control signal terminal OE is high, it is possible to cooperate with the input signal received at the input signal terminal Iput so that the blanking input unit 5 transmits the fourth clock signal received at the fourth clock signal terminal CLKA to the first and second pull-up nodes Q1 and Q2, charging the first and second pull-up nodes Q1 and Q2.

After the voltage of the first pull-up node Q1 increases, the first output circuit 102 may be turned on under the control of the voltage of the first pull-up node Q1. If the first output circuit 102 is not electrically connected to the first sensing signal terminal Oput2< N >, the first output circuit 102 may output the second clock signal received at the second clock signal terminal clke_1 from the first scanning signal terminal Oput1< N > as the first scanning signal and the first sensing driving signal at the same time. If the first output circuit 102 is electrically connected to the first sensing signal terminal Oput2< N >, the first output circuit 102 may output the fifth clock signal received at the fifth clock signal terminal clkf_1 from the first sensing signal terminal Oput2< N > as the first sensing signal.

After the voltage of the second pull-up node Q2 increases, the second output circuit 202 may be turned on under the control of the voltage of the second pull-up node Q2. If the second output circuit 202 is not electrically connected to the second sensing signal terminal oput2< n+1>, the second output circuit 202 may output the third clock signal received at the third clock signal terminal clke_2 from the second scanning signal terminal oput1< n+1> as the second scanning signal and the second sensing driving signal at the same time. If the second output circuit 202 is electrically connected to the second sensing signal terminal oput2< n+1>, the second output circuit 202 may output the sixth clock signal received at the sixth clock signal terminal clkf_2 from the second sensing signal terminal oput2< n+1> as the second sensing signal.

Here, in the case where the blanking input unit 5 is not operated, if the voltage of the first pull-up node Q1 is high, the first pull-up node Q1 is liable to leak electricity through the blanking input unit 5; if the voltage of the second pull-up node Q2 is high, the second pull-up node Q2 is easily leaked through the blanking input unit 5.

By electrically connecting the blanking input unit 5 with the first anti-leakage node OFF1, the first anti-leakage circuit 301 can be used to transmit the first voltage signal or the second voltage signal to the first anti-leakage node OFF1 when the voltage of the first pull-up node Q1 is at a high potential, so as to reduce the voltage difference between the first anti-leakage node OFF1 and the first pull-up node Q1 and avoid the first pull-up node Q1 from leaking electricity through the blanking input unit 5.

By electrically connecting the blanking input unit 5 with the second anti-leakage node OFF2, the second anti-leakage circuit 302 can be used to transmit the first voltage signal or the second voltage signal to the second anti-leakage node OFF2 when the voltage of the second pull-up node Q2 is at a high potential, so as to reduce the voltage difference between the second anti-leakage node OFF2 and the second pull-up node Q2 and avoid the second pull-up node Q2 from leaking electricity through the blanking input unit 5.

In some embodiments, as shown in fig. 14 to 17, the blanking input unit 5 may include: a selection control circuit 501, a third input circuit 502, a first transmission circuit 503, and a third leakage prevention circuit 505.

In some examples, as shown in fig. 14 to 17, the selection control circuit 501 is electrically connected to the selection control signal terminal OE, the input signal terminal Iput, the third voltage signal terminal VGL1, the first blanking node H, and the third anti-leakage node OFF 3. Wherein the selection control circuit 501 is configured to transmit an input signal received at the input signal terminal Iput to the first blanking node H under the control of the selection control signal transmitted by the selection control signal terminal OE.

For example, in the case where the level of the selection control signal is high, the selection control circuit 501 may be turned on under the control of the selection control signal and transmit the received input signal to the first blanking node H, and charge the first blanking node H such that the voltage of the first blanking node H increases.

For example, when the shift register 100 needs to output the sensing signal, the waveform timing of the selection control signal and the waveform timing of the input signal may be made the same, and the selection control circuit 501 may be turned on.

In some examples, as shown in fig. 14 to 17, the third input circuit 502 is electrically connected to the first blanking node H, the fourth clock signal terminal CLKA, and the second blanking node N. Wherein the third input circuit 502 is configured to transmit the fourth clock signal received at the fourth clock signal terminal CLKA to the second blanking node N under control of the voltage of the first blanking node H.

Illustratively, in the case where the selection control circuit 501 is turned on such that the voltage of the first blanking node H increases, the third input circuit 502 may be turned on under the control of the voltage of the first blanking node H, receive the fourth clock signal transmitted by the fourth clock signal terminal CLKA, and transmit the fourth clock signal to the second blanking node N.

In some examples, as shown in fig. 14 to 17, the first transmission circuit 503 is electrically connected to the fourth clock signal terminal CLKA, the second blanking node N, the first pull-up node Q1, and the first anti-leakage node OFF 1. The first transmission circuit 503 is configured to transmit the fourth clock signal received at the second blanking node N to the first pull-up node Q1 under the control of the fourth clock signal transmitted by the fourth clock signal terminal CLKA.

For example, in case that the level of the fourth clock signal transmitted by the fourth clock signal terminal CLKA is high, the first transmission circuit 503 may be turned on under the control of the fourth clock signal and receive the fourth clock signal from the second blanking node N, and transmit the received fourth clock signal to the first pull-up node Q1 so that the voltage of the first pull-up node Q1 increases.

Here, under the condition that the voltage of the first pull-up node Q1 increases, the first anti-leakage circuit 301 may transmit the first voltage signal or the second voltage signal to the first anti-leakage node OFF1, so that the voltage of the first anti-leakage node OFF1 increases, the voltage difference between the first anti-leakage node OFF1 and the first pull-up node Q1 is reduced, the first pull-up node Q1 is prevented from leaking electricity through the first transmission circuit 503, and further the first pull-up node Q1 may be kept at a higher and more stable voltage, so that the accuracy of the first sensing signal is prevented from being affected.

In some examples, as shown in fig. 14 to 17, in the case where the shift register 100 further includes the second scanning unit 2, the blanking input unit 5 further includes: a second transmission circuit 504. The second transmission circuit 504 is electrically connected to the fourth clock signal terminal CLKA, the second blanking node N, the second pull-up node Q2, and the second anti-leakage node OFF 2. The second transmission circuit 504 is configured to transmit the fourth clock signal received at the second blanking node N to the second pull-up node Q2 under the control of the fourth clock signal transmitted by the fourth clock signal terminal CLKA.

For example, in case that the level of the fourth clock signal transmitted by the fourth clock signal terminal CLKA is high, the second transmission circuit 504 may be turned on under the control of the fourth clock signal and receive the fourth clock signal from the second blanking node N, and transmit the received fourth clock signal to the second pull-up node Q2 so that the voltage of the second pull-up node Q2 increases.

Here, under the condition that the voltage of the second pull-up node Q2 increases, the second anti-leakage circuit 302 may transmit the first voltage signal or the second voltage signal to the second anti-leakage node OFF2, so that the voltage of the second anti-leakage node OFF2 increases, the voltage difference between the second anti-leakage node OFF2 and the second pull-up node Q2 is reduced, the second pull-up node Q2 is prevented from leaking electricity through the second transmission circuit 504, and further the second pull-up node Q2 can be kept at a higher and more stable voltage, and the influence on the accuracy of the second sensing signal is avoided.

In some examples, as shown in fig. 14 to 17, the third anti-leakage circuit 505 is electrically connected to the third anti-leakage node OFF3, the first blanking node H, and the anti-leakage input node M. Wherein the third anti-leakage circuit 505 is configured to transmit the first voltage signal or the second voltage signal from the anti-leakage input node M to the third anti-leakage node OFF3 under control of the voltage of the first blanking node H.

For example, in the case where the selection control circuit 501 is turned on so that the voltage of the first blanking node H increases, the third anti-leakage circuit 505 may be turned on under the control of the voltage of the first blanking node H, receive the first voltage signal or the second voltage signal from the anti-leakage input node M, and transmit it to the third anti-leakage node OFF3 so that the voltage of the third anti-leakage node OFF3 increases. Therefore, the voltage difference between the third anti-leakage node OFF3 and the first blanking node H can be reduced, the first blanking node H is prevented from leaking electricity through the selection control circuit 501, and the first blanking node H can be kept at a higher and more stable voltage, so that the conduction state of the third input circuit 502 is prevented from being influenced.

The structures of the selection control circuit 501, the third input circuit 502, the first transmission circuit 503, the second transmission circuit 504, and the third anticreep circuit 505 included in the blanking input unit 5 are schematically described below.

In some examples, as shown in fig. 15 and 17, the selection control circuit 501 includes: a forty-fourth transistor M44, a forty-fifth transistor M45, and a third capacitor C3.

As shown in fig. 15 and 17, the control electrode of the forty-fourth transistor M44 is electrically connected to the selection control signal terminal OE, the first electrode of the forty-fourth transistor M44 is electrically connected to the input signal terminal Iput, and the second electrode of the forty-fourth transistor M44 is electrically connected to the first electrode of the forty-fifth transistor M45 and the third anti-leakage node OFF 3. The control electrode of the forty-fifth transistor M45 is electrically connected to the selection control signal terminal OE, and the second electrode of the forty-fifth transistor M45 is electrically connected to the first blanking node H.

For example, in the case that the level of the selection control signal transmitted by the selection control signal terminal OE is high, the forty-fourth transistor M44 and the forty-fifth transistor M45 may be simultaneously turned on under the action of the selection control signal, the forty-fourth transistor M44 may transmit the input signal transmitted by the input signal terminal Iput to the third anti-leakage node OFF3, and the forty-fifth transistor M45 may receive and transmit the input signal to the first blanking node H to charge the first blanking node H.

As illustrated in fig. 15 and 17, a first terminal of the third capacitor C3 is electrically connected to the first blanking node H, and a second terminal of the third capacitor C3 is electrically connected to the third voltage signal terminal VGL 1.

For example, in the process of charging the first blanking node H by the selection control circuit 501, the third capacitor C3 is also charged. This makes it possible to discharge with the third capacitor C3 with the selection control circuit 501 turned off, so that the first blanking node H remains high.

In some examples, as shown in fig. 15 and 17, the third anti-leakage circuit 505 includes: forty-sixth transistor M46.

As illustrated in fig. 15 and 17, the control electrode of the forty-sixth transistor M46 is electrically connected to the first blanking node H, the first electrode of the forty-sixth transistor M46 is electrically connected to the anti-leakage input node M, and the second electrode of the forty-sixth transistor M46 is electrically connected to the third anti-leakage node OFF 3.

For example, in the case where the voltage of the first blanking node H is at a high level, the forty-sixth transistor M46 may be turned on under the control of the voltage of the first blanking node H, transmitting the first voltage signal or the second voltage signal from the anti-leakage input node M to the third anti-leakage node OFF3, causing the voltage of the third anti-leakage node OFF3 to rise, reducing the voltage difference between the third anti-leakage node OFF3 and the first blanking node H, and causing the voltage difference between the control electrode and the first electrode of the forty-fifth transistor M45 to be less than zero, ensuring that the forty-fifth transistor M45 is completely or more completely turned OFF. This prevents the first blanking node H from leaking through the selection control circuit 501, so that the first blanking node H can be kept at a higher, more stable voltage.

In some examples, as shown in fig. 15 and 17, the third input circuit 502 includes: forty-seventh transistor M47.

Illustratively, as shown in fig. 15 and 17, the control electrode of the forty-seventh transistor M47 is electrically connected to the first blanking node H, the first electrode of the forty-seventh transistor M47 is electrically connected to the fourth clock signal terminal CLKA, and the second electrode of the forty-seventh transistor M47 is electrically connected to the second blanking node N.

For example, in case the voltage of the first blank node H is at a high level, the forty-seventh transistor M47 may be turned on under the control of the voltage of the first blank node H, transmitting the fourth clock signal received at the fourth clock signal terminal CLKA to the second blank node N.

In some examples, as shown in fig. 15 and 17, the first transmission circuit 503 includes: forty-eight transistor M48 and forty-nine transistor M49.

As shown in fig. 15 and 17, the control electrode of the forty-eighth transistor M48 is electrically connected to the fourth clock signal terminal CLKA, the first electrode of the forty-eighth transistor M48 is electrically connected to the second blanking node N, and the second electrode of the forty-eighth transistor M48 is electrically connected to the first electrode of the forty-ninth transistor M49 and the first leakage preventing node OFF 1. The control electrode of the forty-nine transistor M49 is electrically connected to the fourth clock signal terminal CLKA, and the second electrode of the forty-nine transistor M49 is electrically connected to the first pull-up node Q1.

For example, in the case that the level of the fourth clock signal transmitted by the fourth clock signal terminal CLKA is high, the forty-eight transistor M48 and the forty-nine transistor M49 may be simultaneously turned on by the fourth clock signal, the forty-eight transistor M48 may transmit the fourth clock signal from the second blanking node N to the first anti-leakage node OFF1, and the forty-nine transistor M49 may receive and transmit the fourth clock signal to the first pull-up node Q1 to charge the first pull-up node Q1.

Here, in the case where the voltage of the first pull-up node Q1 is at a high level, the first anti-leakage circuit 301 may transmit the first voltage signal or the second voltage signal from the anti-leakage input node M to the first anti-leakage node OFF1, so that the voltage of the first anti-leakage node OFF1 increases, the voltage difference between the first anti-leakage node OFF1 and the first pull-up node Q1 is reduced, and the voltage difference between the control electrode and the first electrode of the forty-nine transistor M49 is made smaller than zero, ensuring that the forty-nine transistor M49 is completely or more completely turned OFF. This prevents the first pull-up node Q1 from leaking through the first transmission circuit 503, so that the first pull-up node Q1 can be maintained at a higher, more stable voltage.

In some examples, as shown in fig. 15 and 17, the second transmission circuit 504 includes: a fifty-first transistor M50 and a fifty-second transistor M51.

As shown in fig. 15 and 17, the control electrode of the fifty-first transistor M50 is electrically connected to the fourth clock signal terminal CLKA, the first electrode of the fifty-first transistor M50 is electrically connected to the second blanking node N, and the second electrode of the fifty-first transistor M50 is electrically connected to the first electrode of the fifty-first transistor M51 and the second leakage preventing node OFF 2. The control electrode of the fifty-first transistor M51 is electrically connected to the fourth clock signal terminal CLKA, and the second electrode of the fifty-first transistor M51 is electrically connected to the second pull-up node Q2.

For example, in the case that the level of the fourth clock signal transmitted by the fourth clock signal terminal CLKA is high, the fifty-first transistor M50 and the fifty-first transistor M51 may be simultaneously turned on by the fourth clock signal, the fifty-first transistor M50 may transmit the fourth clock signal from the second blanking node N to the second anti-leakage node OFF2, and the fifty-first transistor M51 may receive and transmit the fourth clock signal to the second pull-up node Q2 to charge the second pull-up node Q2.

Here, in the case where the voltage of the second pull-up node Q2 is at a high level, the second anti-leakage circuit 302 may transmit the first voltage signal or the second voltage signal from the anti-leakage input node M to the second anti-leakage node OFF2, so that the voltage of the second anti-leakage node OFF2 increases, the voltage difference between the second anti-leakage node OFF2 and the second pull-up node Q2 is reduced, and the voltage difference between the control electrode and the first electrode of the fifty-first transistor M51 is less than zero, ensuring that the fifty-first transistor M51 is completely or more completely turned OFF. This prevents the second pull-up node Q2 from leaking through the second transmission circuit 504, so that the second pull-up node Q2 can be maintained at a higher, more stable voltage.

Some embodiments of the present disclosure also provide a gate driving circuit 1000. As shown in fig. 18 and 20, the gate driving circuit 1000 includes a plurality of shift registers 100 connected in cascade.

Illustratively, the structure of the gate driving circuit 1000 is schematically described taking as an example a structure in which each shift register 100 includes the first scanning unit 1 and the second scanning unit 2 and the shift register 100 adopts the structure shown in fig. 15.

A1, A2, A3 … … A2N shown in fig. 18 and 20 respectively represent each scanning unit in the shift register 100, for example, A1, A3, A5 respectively represent the first scanning unit 1 in the three shift registers 100, and A2, A4, A6 respectively represent the second scanning unit 2 in the three shift registers 100. Where N is the number of rows and N is a positive integer.

In this case, each scanning unit in the gate driving circuit 1000 may be electrically connected to each gate line GL in the above-mentioned display panel PNL in one-to-one correspondence, respectively. For example, A1, A2, A3, A4, A5, and A6 may be electrically connected to the first, second, third, fourth, fifth, and sixth gate lines GL, respectively, to thereby drive the first, second, third, fourth, fifth, and sixth lines of the display panel PNL to display, respectively.

Next, a schematic description will be given of signal lines in the gate driver circuit 1000, taking a configuration of the gate driver circuit 1000 as shown in fig. 18 as an example.

As shown in fig. 18, the gate driving circuit 1000 includes: a first clock signal line clk_1, a second clock signal line clk_2, and a third clock signal line clk_3.

The first clock signal terminal clkd_1 of the first scan cell 1 in the shift register 100 of the 3N-2 stage is electrically connected to the first clock signal line clk_1 to receive the first clock signal. The first clock signal terminal clkd_1 of the first scan cell 1 in the shift register 100 of the 3N-1 stage is electrically connected to the second clock signal line clk_2 to receive the first clock signal. The first clock signal terminal clkd_1 of the first scan cell 1 in the 3N-th stage shift register 100 is electrically connected to the third clock signal line clk_3 to receive the first clock signal.

As shown in fig. 18, the gate driving circuit 1000 further includes: the fourth clock signal line clk_4, the fifth clock signal line clk_5, the sixth clock signal line clk_6, the seventh clock signal line clk_7, the eighth clock signal line clk_8, and the ninth clock signal line clk_9.

The second clock signal terminal clke_1 of the first scan cell 1 in the 3N-2 stage shift register 100 is electrically connected to the fourth clock signal line clk_4 to receive the second clock signal, and the third clock signal terminal clke_2 of the second scan cell 2 is electrically connected to the fifth clock signal line clk_5 to receive the third clock signal.

The second clock signal terminal clke_1 of the first scan cell 1 in the shift register 100 of the 3N-1 stage is electrically connected to the sixth clock signal line clk_6 to receive the second clock signal, and the third clock signal terminal clke_2 of the second scan cell 2 is electrically connected to the seventh clock signal line clk_7 to receive the third clock signal.

The second clock signal terminal clke_1 of the first scan cell 1 in the 3N-th stage shift register 100 is electrically connected to the eighth clock signal line clk_8 to receive the second clock signal, and the third clock signal terminal clke_2 of the second scan cell 2 is electrically connected to the ninth clock signal line clk_9 to receive the third clock signal.

As shown in fig. 18, the gate driving circuit 1000 further includes: tenth clock signal line clk_10.

The global reset signal terminal TRST of the first scan cell 1 and the global reset signal terminal TRST of the second scan cell 2 in each stage of the shift register 100 are electrically connected to the tenth clock signal line clk_10 to receive the global reset signal.

As shown in fig. 18, the gate driving circuit 1000 further includes: an eleventh clock signal line clk_11 and a twelfth clock signal line clk_12.

The selection control signal end OE of the blanking input unit 5 in each stage of the shift register 100 is electrically connected to the eleventh clock signal line clk_11 for receiving the selection control signal.

The fourth clock signal terminal CLKA of the blanking input unit 5 in each stage of the shift register 100 is electrically connected to the twelfth clock signal line clk_12 to receive the fourth clock signal.

As shown in fig. 18, the gate driving circuit 1000 further includes: a thirteenth clock signal line clk_13 and a fourteenth clock signal line clk_14.

The first voltage signal terminal vdd_a of each stage of the shift register 100 is electrically connected to the thirteenth clock signal line clk_13 for receiving the first voltage signal. The second voltage signal terminal vdd_b of each stage of the shift register 100 is electrically connected to the fourteenth clock signal line clk_14 for receiving the second voltage signal.

As shown in fig. 18, the gate driving circuit 1000 further includes: the fifteenth clock signal line clk_15.

The input signal terminal Iput of the first scan cell 1 and the input signal terminal Iput of the second scan cell 2 in the first stage shift register 100 are electrically connected to the fifteenth clock signal line clk_15 to receive the start signal as an input signal.

As shown in fig. 18, the input signal terminals Iput of the first scanning unit 1 and the second scanning unit 2 in the shift register 100 of the other stages are electrically connected to the shift signal terminal CR < N > of the first scanning unit 1 in the shift register 100 of the previous stage, in addition to the shift register 100 of the first stage. The display reset signal terminals STD of the first scan cell 1 and the second scan cell 2 in the shift register 100 of the other stages are electrically connected to the shift signal terminal CR < N > of the first sub-cell 1 in the shift register 100 of the next two stages except for the last two stages of shift registers 100.

It should be noted that the cascade relationship shown in fig. 18 is only an example, and other cascade methods may be adopted according to practical situations.

Illustratively, the cascade relationship may also be as shown in FIG. 20. The first stage shift register 100 and the second stage shift register 100 are not electrically connected to the gate lines GL, the first scan cell 1 (i.e., A5) of the third stage shift register 100 is electrically connected to the first row gate lines GL, and the second scan cell 2 (i.e., A6) is electrically connected to the second row gate lines GL.

Fig. 19 shows a timing diagram of the operation of the shift register 100 shown in fig. 15. In fig. 19, Q1<5> and Q2<6> are denoted as a first pull-up node Q1 and a second pull-up node Q2 in the third stage shift register 100, respectively, and numerals in brackets are denoted as the number of lines of subpixels in the display panel PNL (hereinafter, referred to as "lines of dots"). The first scan signal output from the first scan signal terminal op 1< N > and the second scan signal output from the second scan signal terminal op 1< n+1> in the third stage shift register 100 are denoted as op 1<5> and op 1<6>, respectively. CR <3> is represented as a shift signal output from the shift signal terminal CR < N > in the second stage shift register 100, which can be used as an input signal to the third stage shift register 100. H <5> represents the first blanking node H in the third stage shift register 100. N <5> represents the second blanking node N in the third stage shift register 100. 1F represents one frame, display represents a Display period in one frame Display period, and Blank represents a blanking period in one frame Display period.

Next, a method of driving the shift register 100 shown in fig. 15 in the display stage of one frame will be schematically described with reference to fig. 18 and 19.

Before the display stage of one frame, the level of the global reset signal supplied from the tenth clock signal line clk_10 may be high, which may cause the fifth reset circuit 106 (the thirty-fourth transistor M32 and the thirty-third transistor M33) and the sixth reset circuit 206 (the thirty-fourth transistor M34 and the thirty-fifth transistor M35) in each stage of the shift register 100 to be turned on, thereby resetting the first pull-up node Q1 and the second pull-up node Q2 in each stage of the shift register 100 to realize global reset before one frame display.

The operation of the third stage shift register 100 (i.e., the subpixels corresponding to the fifth and sixth rows of the display panel PNL) for the display period in the one-frame display stage is described as follows.

In the first stage 1 (including the input stage), the level of the shift signal CR <3> output by the first scanning unit 1 in the second stage shift register 100 is high. That is, the signal transmitted to the input signal terminal Iput of the third stage shift register 100 and the level of the input signal transmitted by the input signal terminal Iput are at high level, the fifth transistor M5 and the sixth transistor M6 in the first input circuit 101 and the ninth transistor M9 and the tenth transistor M10 in the second input circuit 201 are turned on by the input signal, and the first pull-up node Q1<5> is charged by the input signal at high level, the first pull-up node Q1<5> is pulled up to high level, the second pull-up node Q2<6> is charged, and the second pull-up node Q2<6> is pulled up to high level.

The seventh transistor M7 in the first output circuit 102 is turned on under the control of the voltage of the first pull-up node Q1<5>, but since the level of the first clock signal supplied from the third clock signal line clk_3 is low, the level of the shift signal outputted from the shift signal terminal CR < N > is low in the first scan cell 1 of the third stage shift register 100. The eighth transistor M8 in the first output circuit 102 is turned on under the control of the voltage of the first pull-up node Q1<5>, but since the level of the second clock signal supplied from the eighth clock signal line clk_8 is low, the level of the first scan signal Oput1<5> output from the first scan signal terminal Oput1< N > is low in the first scan cell 1 of the third stage shift register 100. The eleventh transistor M11 in the second output circuit 202 is turned on under the control of the voltage of the second pull-up node Q2<6>, but since the level of the third clock signal supplied from the ninth clock signal line clk_9 is low, the second scan signal Oput1<6> output from the second scan signal end Oput1< n+1> is low in the second scan cell 2 of the third stage shift register 100.

The selection control signal provided by the eleventh clock signal line clk_11 is the same as the input signal transmitted by the input signal terminal Iput, i.e. the level of the selection control signal is high, and the forty-fourth transistor M44 and the forty-fifth transistor M45 in the selection control circuit 501 are turned on under the control of the selection control signal, so that the first blanking node H <5> is charged by the high level selection control signal.

At this stage, precharge is completed simultaneously for the first pull-up node Q1<5>, the second pull-up node Q2<6> and the first blank node H <5> in the third stage shift register 100.

Here, the level of the first voltage signal supplied from the thirteenth clock signal line clk_13 is a low level, and the level of the second voltage signal supplied from the fourteenth clock signal line clk_14 is a high level. In the anti-leakage input unit 4, the first transistor M1 in the first anti-leakage input circuit 401 is turned off, the second transistor M2 in the second anti-leakage input circuit 402 is turned on under the control of the second voltage signal, and the second anti-leakage input circuit 402 can transmit the second voltage signal to the anti-leakage input node M.

In the anti-leakage unit 3, the third transistor M3 in the first anti-leakage circuit 301 may be turned on under the control of the voltage of the first pull-up node Q1<5>, and the second voltage signal from the anti-leakage input node M may be transmitted to the first anti-leakage node OFF1 to raise the voltage of the first anti-leakage node OFF 1. The fourth transistor M4 in the second anti-leakage circuit 302 may be turned on under the control of the voltage of the second pull-up node Q2<6>, transmitting the second voltage signal from the anti-leakage input node M to the second anti-leakage node OFF2, raising the voltage of the second anti-leakage node OFF 2.

In the second stage 2, the first clock signal supplied from the third clock signal line clk_3 becomes a high level, and the second clock signal supplied from the eighth clock signal line clk_8 becomes a high level. The voltage of the first pull-up node Q1<5> is further increased due to the bootstrap action of the seventh transistor M7 and the eighth transistor M8, so that the seventh transistor M7 and the eighth transistor M8 maintain the on state, and further the shift signal outputted from the shift signal terminal CR < N > in the third stage shift register 100 becomes a high level, so that the level of the first scan signal op ut1<5> outputted from the first scan signal terminal op ut1< N > becomes a high level. But since the third clock signal supplied from the ninth clock signal line clk_9 is still at the low level, the level of the second scan signal op ut1<6> outputted from the second scan signal terminal op ut1< n+1> of the third stage shift register 100 continues to be maintained at the low level.

In the third stage 3, the third clock signal supplied from the ninth clock signal line clk_9 becomes a high level, and the voltage of the second pull-up node Q2<6> is further increased due to the bootstrap action of the eleventh transistor M11, so that the eleventh transistor M11 maintains the on state, and thus the level of the second scan signal op ut1<6> outputted from the second scan signal terminal op ut1< n+1> in the third stage shift register 100 becomes a high level.

In the fourth stage 4, the first pull-up node Q1<5> remains high due to the holding action of the first capacitor C1, so that the eighth transistor M8 remains in an on state. But since the second clock signal supplied from the eighth clock signal line clk_8 becomes a low level, the level of the first scan signal op ut1<5> output from the first scan signal terminal op ut1< N > of the third stage shift register 100 becomes a low level. At the same time, the voltage of the first pull-up node Q1<5> also decreases due to the bootstrap action of the first capacitor C1.

In the fifth stage 5, the second pull-up node Q2<6> remains high due to the holding action of the second capacitor C2, so that the eleventh transistor M11 remains in an on state. But since the third clock signal supplied from the ninth clock signal line clk_9 becomes a low level, the level of the second scan signal op ut1<6> output from the second scan signal terminal op ut1< n+1> of the third stage shift register 100 becomes a low level. At the same time, the potential of the second pull-up node Q2<6> also decreases due to the bootstrap action of the second capacitor C2.

In the first to fifth stages 1 to 5, since the first pull-up node Q1<5> is always kept at a high level, the third transistor M3 continuously transmits the second voltage signal to the first anti-leakage node OFF1; since the second pull-up node Q2<6> remains high all the time, the fourth transistor M4 continuously transmits the second voltage signal to the second anti-leakage node OFF2.

In the sixth stage 6, the embodiment of the disclosure adopts the clock signal of 6CLK, the signal output by each stage of the shift register 100 (each stage sequentially outputs the first scan signal and the second scan signal) is one cycle, and at the same time, since the shift register 100 of the third stage receives the shift signal CR <9> output by the shift register 100 of the fifth stage as the display reset signal, the display reset signal received by the shift register 100 of the third stage is also at the high level when the second clock signal provided by the sixth clock signal line clk_6 becomes at the high level, so that the eighth transistor M28 and the twenty-ninth transistor M29 in the third reset circuit 105 and the thirty-first transistor M30 and the thirty-first transistor M31 in the fourth reset circuit 205 are turned on, and the third voltage signal transmitted by the third voltage signal terminal VGL1 is transmitted to the first pull-up node Q1<5> and the second pull-up node Q2<6>, and the pull-down reset of the first pull-up node Q1<5> and the second pull-up node Q2<6> is completed.

After the third stage shift register 100 drives the subpixels of the fifth row and the sixth row in the display panel PNL to complete display, the fourth stage shift register 100, the fifth stage shift register 100 and the like drive the subpixels in the display panel PNL row by row to complete display driving of one frame. Up to this point, the display period in one frame display stage ends.

The operation of the third stage shift register 100 (i.e., the sub-pixels corresponding to the fifth and sixth rows of the display panel PNL) during the blanking period in the one-frame display stage is described as follows.

Here, in the first stage 1, after the first blanking node H <5> is charged such that the voltage of the first blanking node H <5> increases, the third capacitor C3 may be discharged such that the display period of the first blanking node H <5> in one frame display stage is always kept at a high potential.

In the seventh stage 7, the level of the fourth clock signal supplied from the twelfth clock signal line clk_12 is high. Since the first blanking node H <5> remains high at this stage, the forty-seventh transistor M47 in the third input circuit 502 may be turned on under the control of the voltage of the first blanking node H <5>, transmitting a fourth clock signal of high level to the second blanking node N <5>, thereby causing the second blanking node N <5> to become high.

The forty-eighth transistor M48 and the forty-ninth transistor M49 in the first transmission circuit 503 and the fifty-first transistor M50 and the fifty-first transistor M51 in the second transmission circuit 504 are turned on under the control of a high-level fourth clock signal that charges the first pull-up node Q1<5> and the second pull-up node Q2<6>, respectively, and the voltages of the first pull-up node Q1<5> and the second pull-up node Q2<6> are pulled up.

Meanwhile, in the seventh stage 7, due to the bootstrap effect of the forty-seventh transistor M47, the second blanking node N <5> is coupled to pull up the first blanking node H <5> when the low level is changed to the high level, so that the first blanking node H <5> can be kept at a higher high level, and the forty-seventh transistor M47 is ensured to be fully turned on.

Then, the level of the fourth clock signal supplied from the twelfth clock signal line clk_12 changes from the high level to the low level, so that the level of the second blank node N <5> changes to the low level. The potential of the first blanking node H <5> also decreases due to the bootstrap action of the forty-seventh transistor M47.

At this stage, the third transistor M3 may be turned on under the control of the voltage of the first pull-up node Q1<5>, transmitting the second voltage signal from the anti-leakage input node M to the first anti-leakage node OFF1, raising the voltage of the first anti-leakage node OFF1, preventing the first pull-up node Q1<5> from leaking through the nineteenth transistor M49. The fourth transistor M4 may be turned on under the control of the voltage of the second pull-up node Q2<6>, transmit the second voltage signal from the anti-leakage input node M to the second anti-leakage node OFF2, raise the voltage of the second anti-leakage node OFF2, and prevent the second pull-up node Q2<6> from leaking through the eleventh transistor M51.

In the eighth stage 8, the level of the second clock signal supplied from the eighth clock signal line clk_8 becomes a high level, the potential of the first pull-up node Q1<5> is further raised due to the bootstrap action of the seventh transistor M7 and the eighth transistor M8, so that the eighth transistor M8 remains in the on state, and the level of the first scan signal op ut1<5> (i.e., the first sense signal) output from the first scan signal terminal op ut1< N > of the third stage shift register 100 becomes a high level.

Since the level of the third clock signal supplied from the ninth clock signal line clk_9 is still at the low level, the level of the second scan signal op ut1<6> (i.e., the second sense signal) output from the second scan signal terminal op ut1< n+1 >) of the third stage shift register 100 is at the low level.

Here, the first scan signal output in the eighth stage 8 may be used to drive the sense transistor T3 in the sub-pixel of the corresponding row in the display panel PNL to implement external compensation.

In the ninth stage 9, the first pull-up node Q1<5> remains high due to the holding action of the first capacitor C1, so that the eighth transistor M8 remains in an on state. Since the level of the second clock signal supplied from the eighth clock signal line clk_8 becomes a low level, the level of the first scan signal op ut1<5> (i.e., the first sense signal) output from the first scan signal terminal op ut1< N >) of the third stage shift register 100 becomes a low level.

Meanwhile, the potential of the first pull-up node Q1<5> also decreases due to the bootstrap action of the eighth transistor M8.

In the tenth stage 10, the level of the global reset signal supplied from the tenth clock signal line clk_10 is high, the thirty-third transistor M32 and the thirty-third transistor M33 of the fifth reset circuit 106 and the thirty-fourth transistor M34 and the thirty-fifth transistor M35 of the sixth reset circuit 206 in each stage of the shift register 100 are turned on, the third voltage signal transmitted from the third voltage signal terminal VGL1 is transmitted to the first pull-up node Q1 and the second pull-up node Q2, and the first pull-up node Q1 and the second pull-up node Q2 in each stage of the shift register 100 are reset.

The level of the selection control signal supplied from the eleventh clock signal line clk_11 is high, and the forty-fourth transistor M44 and the forty-fifth transistor M45 of the selection control circuit 501 are turned on in each stage of the shift register 100. Since the level of the shift signal output in each stage of the shift register 100 is a low level, the shift signal of a low level can be transmitted to the first blanking node H, and the first blanking node H in each stage of the shift register 100 is reset, thereby completing global reset.

To this end, the blanking period in one frame display stage ends.

In the subsequent display stage of other frames, the driving process of the gate driving circuit 100 may refer to the above description, and will not be repeated here.

In some embodiments, in the case of using the shift registers 100 cascade-connected as shown in fig. 17 to form the gate driving circuit 1000, the cascade-connected relationship between the shift registers 100 in the gate driving circuit 1000 may be the cascade-connected relationship shown in fig. 18.

Based on this, the configuration of forming the gate driving circuit 1000 by cascade-connecting the shift registers 100 shown in fig. 17 may be such that the shift registers 100 in the gate driving circuit 1000 shown in fig. 18 are replaced with the shift registers 100 shown in fig. 17. On the basis of this, a plurality of clock signal lines for transmitting the fifth clock signal are added so that the fifth clock signal terminal clkf_1 in each stage of the shift register 100 (the structure shown in fig. 17) can receive the fifth clock signal, and a plurality of clock signal lines for transmitting the sixth clock signal are added so that the sixth clock signal terminal clkf_2 in each stage of the shift register 100 (the structure shown in fig. 17) can receive the sixth clock signal.

Of course, in the gate driving circuit 1000 configured by cascading the shift registers 100 as shown in fig. 17, the cascade relationship between the shift registers 100 may also be configured in other manners, but is not limited to the example shown in the present disclosure.

For example, in the gate driving circuit 1000 configured by cascading the shift registers 100 as shown in fig. 17, the cascade relationship between the shift registers 100 may be such that the input signal terminal Iput in the first stage shift register 100 and the second stage shift register 100 is electrically connected to the corresponding clock signal line, the start signal is used as the input signal, and the display reset signal terminal STD in the last stage shift register 100 is electrically connected to the corresponding clock signal line, and the display reset signal is received from the clock signal line. In the shift register 100 except the first stage shift register 100 and the second stage shift register 100, the shift signal terminal CR < N > of the nth stage shift register 100 is electrically connected to the input signal terminal Iput in the next two stages shift register 100. In the shift registers 100 other than the last-stage shift register 100, the display reset signal terminal STD of the nth-stage shift register 100 is electrically connected to the shift signal terminal CR < N-6> in the previous-stage shift register 100.

The foregoing is merely a specific embodiment of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art who is skilled in the art will recognize that changes or substitutions are within the technical scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A shift register, the shift register comprising: the device comprises a first scanning unit, an anti-creeping unit and an anti-creeping input unit;

the first scanning unit includes:

the first input circuit is electrically connected with the input signal end, the first pull-up node and the first anti-leakage node; the first input circuit is configured to transmit an input signal received at the input signal terminal to the first pull-up node in response to the input signal;

the first output circuit is electrically connected with the first pull-up node, the first clock signal end, the second clock signal end, the shift signal end and the first scanning signal end; the first output circuit is configured to transmit a first clock signal received at the first clock signal terminal to the shift signal terminal under control of a voltage of the first pull-up node; and transmitting a second clock signal received at the second clock signal terminal to the first scan signal terminal under control of the voltage of the first pull-up node;

The anti-leakage input unit is electrically connected with the first voltage signal end, the second voltage signal end and the anti-leakage input node; the anti-leakage input unit is configured to transmit a first voltage signal received at the first voltage signal terminal to the anti-leakage input node in response to the first voltage signal; or, transmitting a second voltage signal received at the second voltage signal terminal to the anti-leakage input node in response to the second voltage signal; wherein the first voltage signal and the second voltage signal are mutually inverted signals;

the anti-creeping unit is electrically connected with the first pull-up node, the first anti-creeping node and the anti-creeping input node; the anti-leakage unit is configured to transmit a first voltage signal or a second voltage signal from the anti-leakage input node to the first anti-leakage node under the control of the voltage of the first pull-up node;

the anti-creeping input unit includes: the first anti-creeping input circuit and the second anti-creeping input circuit;

the first anti-leakage input circuit is electrically connected with the first voltage signal end and the anti-leakage input node; the first anti-leakage input circuit is configured to transmit a first voltage signal received at the first voltage signal terminal to the anti-leakage input node in response to the first voltage signal;

The second anti-leakage input circuit is electrically connected with the second voltage signal end and the anti-leakage input node; the second anti-leakage input circuit is configured to transmit a second voltage signal received at the second voltage signal terminal to the anti-leakage input node in response to the second voltage signal;

the first anticreep input circuit includes: a first transistor;

the control electrode of the first transistor is electrically connected with the first voltage signal end, the first electrode of the first transistor is electrically connected with the first voltage signal end, and the second electrode of the first transistor is electrically connected with the anti-leakage input node;

the second anticreep input circuit includes: a second transistor;

the control electrode of the second transistor is electrically connected with the second voltage signal end, the first electrode of the second transistor is electrically connected with the second voltage signal end, and the second electrode of the second transistor is electrically connected with the anti-leakage input node.

2. The shift register of claim 1, wherein the anti-leakage unit comprises: a first anticreep circuit;

the first anti-leakage circuit is electrically connected with the first pull-up node, the anti-leakage input node and the first anti-leakage node; the first anti-leakage circuit is configured to transmit the first voltage signal or the second voltage signal from the anti-leakage input node to the first anti-leakage node under control of a voltage of the first pull-up node.

3. The shift register as claimed in claim 2, wherein,

the first anticreep circuit includes: a third transistor;

the control electrode of the third transistor is electrically connected with the first pull-up node, the first electrode of the third transistor is electrically connected with the anti-leakage input node, and the second electrode of the third transistor is electrically connected with the first anti-leakage node.

4. The shift register of claim 1, wherein the shift register further comprises: a second scanning unit;

the second scanning unit includes:

the second input circuit is electrically connected with the input signal end, the second pull-up node and the second anti-leakage node; the second input circuit is configured to transmit an input signal received at the input signal terminal to the second pull-up node in response to the input signal;

the anti-creeping unit is also electrically connected with the second pull-up node and the second anti-creeping node; the anti-leakage unit is further configured to transmit a first voltage signal or a second voltage signal from the anti-leakage input node to the second anti-leakage node under control of the voltage of the second pull-up node.

5. The shift register of claim 4, wherein the anti-leakage unit further comprises: a second anti-leakage circuit;

the second anti-leakage circuit is electrically connected with the second pull-up node, the anti-leakage input node and the second anti-leakage node; the second anti-leakage circuit is configured to transmit the first voltage signal or the second voltage signal from the anti-leakage input node to the second anti-leakage node under control of a voltage of the second pull-up node.

6. The shift register as claimed in claim 5, wherein,

the second anticreep circuit includes: a fourth transistor;

the control electrode of the fourth transistor is electrically connected with the second pull-up node, the first electrode of the fourth transistor is electrically connected with the anti-leakage input node, and the second electrode of the fourth transistor is electrically connected with the second anti-leakage node.

7. The shift register according to any one of claims 1-6, wherein,

in the case where the shift register further includes a second scanning unit, the second scanning unit further includes:

the second output circuit is electrically connected with the second pull-up node, the third clock signal end and the second scanning signal end; the second output circuit is configured to transmit a third clock signal received at the third clock signal terminal to the second scan signal terminal under control of a voltage of the second pull-up node.

8. The shift register as claimed in claim 7, wherein,

the first input circuit includes: a fifth transistor and a sixth transistor;

the control electrode of the fifth transistor is electrically connected with the input signal end, the first electrode of the fifth transistor is electrically connected with the input signal end, and the second electrode of the fifth transistor is electrically connected with the first electrode of the sixth transistor and the first anti-leakage node;

the control electrode of the sixth transistor is electrically connected with the input signal end, and the second electrode of the sixth transistor is electrically connected with the first pull-up node;

the first output circuit includes: a seventh transistor, an eighth transistor, and a first capacitor;

the control electrode of the seventh transistor is electrically connected with the first pull-up node, the first electrode of the seventh transistor is electrically connected with the first clock signal end, and the second electrode of the seventh transistor is electrically connected with the shift signal end;

the control electrode of the eighth transistor is electrically connected with the first pull-up node, the first electrode of the eighth transistor is electrically connected with the second clock signal end, and the second electrode of the eighth transistor is electrically connected with the first scanning signal end;

A first end of the first capacitor is electrically connected with the first pull-up node, and a second end of the first capacitor is electrically connected with the first scanning signal end;

the second input circuit includes: a ninth transistor and a tenth transistor;

the control electrode of the ninth transistor is electrically connected with the input signal end, the first electrode of the ninth transistor is electrically connected with the input signal end, and the second electrode of the ninth transistor is electrically connected with the first electrode of the tenth transistor and the second anti-leakage node;

the control electrode of the tenth transistor is electrically connected with the input signal end, and the second electrode of the tenth transistor is electrically connected with the second pull-up node;

the second output circuit includes: an eleventh transistor and a second capacitor;

the control electrode of the eleventh transistor is electrically connected with the second pull-up node, the first electrode of the eleventh transistor is electrically connected with the third clock signal end, and the second electrode of the eleventh transistor is electrically connected with the second scanning signal end;

the first end of the second capacitor is electrically connected with the second pull-up node, and the second end of the second capacitor is electrically connected with the second scanning signal end.

9. The shift register as claimed in claim 7, wherein,

the first output circuit is also electrically connected with a fifth clock signal end and a first sensing signal end; the first output circuit is further configured to transmit a fifth clock signal received at the fifth clock signal terminal to the first sense signal terminal under control of a voltage of the first pull-up node;

the second output circuit is also electrically connected with a sixth clock signal end and a second sensing signal end; the second output circuit is further configured to transmit a sixth clock signal received at the sixth clock signal terminal to the second sense signal terminal under control of a voltage of the second pull-up node.

10. The shift register of claim 9, wherein the shift register comprises a plurality of registers,

the first output circuit further includes: a fifth transistor and a fourth capacitor;

the control electrode of the fifty-second transistor is electrically connected with the first pull-up node, the first electrode of the fifty-second transistor is electrically connected with the fifth clock signal end, and the second electrode of the fifty-second transistor is electrically connected with the first sensing signal end;

the first end of the fourth capacitor is electrically connected with the first pull-up node, and the second end of the fourth capacitor is electrically connected with the first sensing signal end;

The second output circuit further includes: a thirteenth transistor and a fifth capacitor;

a control electrode of the fifty-third transistor is electrically connected to the second pull-up node, a first electrode of the fifty-third transistor is electrically connected to the sixth clock signal terminal, and a second electrode of the fifty-third transistor is electrically connected to the second sensing signal terminal;

the first end of the fifth capacitor is electrically connected with the second pull-up node, and the second end of the fifth capacitor is electrically connected with the second sensing signal end.

11. The shift register as claimed in claim 7, wherein,

the first scanning unit further includes:

the first control circuit is electrically connected with the first pull-up node, the first voltage signal end, the first pull-down node and the third voltage signal end; the first control circuit is configured to control the voltage of the first pull-down node under the control of the voltage of the first pull-up node and the first voltage signal transmitted by the first voltage signal terminal;

the second control circuit is electrically connected with the second pull-up node, the second voltage signal end, the second pull-down node and the third voltage signal end; the second control circuit is configured to control the voltage of the second pull-down node under the control of the voltage of the second pull-up node and the second voltage signal transmitted by the second voltage signal terminal.

12. The shift register of claim 11, wherein the shift register comprises a plurality of registers,

the first control circuit includes: a twelfth transistor, a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor;

the control electrode of the twelfth transistor is electrically connected with the first voltage signal end, the first electrode of the twelfth transistor is electrically connected with the first voltage signal end, and the second electrode of the twelfth transistor is electrically connected with the control electrode of the thirteenth transistor and the first electrode of the fourteenth transistor;

a first pole of the thirteenth transistor is electrically connected to the first voltage signal terminal, and a second pole of the thirteenth transistor is electrically connected to the first pull-down node and the first pole of the fifteenth transistor;

the control electrode of the fourteenth transistor is electrically connected with the first pull-up node, and the second electrode of the fourteenth transistor is electrically connected with the third voltage signal end;

a control electrode of the fifteenth transistor is electrically connected with the first pull-up node, and a second electrode of the fifteenth transistor is electrically connected with the third voltage signal end;

the second control circuit includes: a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, and a nineteenth transistor;

A control electrode of the sixteenth transistor is electrically connected with the second voltage signal end, a first electrode of the sixteenth transistor is electrically connected with the second voltage signal end, and a second electrode of the sixteenth transistor is electrically connected with the control electrode of the seventeenth transistor and the first electrode of the eighteenth transistor;

a first pole of the seventeenth transistor is electrically connected to the second voltage signal terminal, and a second pole of the seventeenth transistor is electrically connected to the second pull-down node and the first pole of the nineteenth transistor;

the control electrode of the eighteenth transistor is electrically connected with the second pull-up node, and the second electrode of the eighteenth transistor is electrically connected with the third voltage signal end;

the control electrode of the nineteenth transistor is electrically connected with the second pull-up node, and the second electrode of the nineteenth transistor is electrically connected with the third voltage signal terminal.

13. The shift register of claim 11, wherein the shift register comprises a plurality of registers,

the first scanning unit further includes:

the first reset circuit is electrically connected with the first pull-down node, the first pull-up node, the third voltage signal end and the first anti-leakage node; the first reset circuit is configured to reset the first pull-up node under control of a voltage of the first pull-down node;

In case the shift register further comprises a second scanning unit,

the first reset circuit is also electrically connected with the second pull-down node; the first reset circuit is further configured to reset the first pull-up node under control of a voltage of the second pull-down node;

the second scanning unit further includes:

the second reset circuit is electrically connected with the first pull-down node, the second pull-up node, the third voltage signal end and the second anti-leakage node; the second reset circuit is configured to reset the second pull-up node under control of a voltage of the first pull-down node or a voltage of the second pull-down node.

14. The shift register of claim 13, wherein the shift register comprises a plurality of registers,

the first reset circuit includes: a twentieth transistor and a twenty-first transistor;

the control electrode of the twentieth transistor is electrically connected with the first pull-down node, the first electrode of the twentieth transistor is electrically connected with the first pull-up node, and the second electrode of the twentieth transistor is electrically connected with the first electrode of the twenty-first transistor and the first anti-leakage node;

The control electrode of the twenty-first transistor is electrically connected with the first pull-down node, and the second electrode of the twenty-first transistor is electrically connected with the third voltage signal end;

in the case where the shift register further includes a second scan cell, the first reset circuit further includes: a twenty-second transistor and a twenty-third transistor;

the control electrode of the twenty-second transistor is electrically connected with the second pull-down node, the first electrode of the twenty-second transistor is electrically connected with the first pull-up node, and the second electrode of the twenty-second transistor is electrically connected with the first electrode of the twenty-third transistor and the first anti-leakage node;

the control electrode of the twenty-third transistor is electrically connected with the second pull-down node, and the second electrode of the twenty-third transistor is electrically connected with the third voltage signal end;

the second reset circuit includes: a twenty-fourth transistor, a twenty-fifth transistor, a twenty-sixth transistor, and a twenty-seventh transistor;

a control electrode of the twenty-fourth transistor is electrically connected with the first pull-down node, a first electrode of the twenty-fourth transistor is electrically connected with the second pull-up node, and a second electrode of the twenty-fourth transistor is electrically connected with the first electrode of the twenty-sixth transistor and the second anti-leakage node;

A control electrode of the twenty-fifth transistor is electrically connected with the second pull-down node, a first electrode of the twenty-fifth transistor is electrically connected with the second pull-up node, and a second electrode of the twenty-fifth transistor is electrically connected with the first electrode of the twenty-seventh transistor and the second anti-leakage node;

the control electrode of the twenty-sixth transistor is electrically connected with the first pull-down node, and the second electrode of the twenty-sixth transistor is electrically connected with the third voltage signal end;

the control electrode of the twenty-seventh transistor is electrically connected with the second pull-down node, and the second electrode of the twenty-seventh transistor is electrically connected with the third voltage signal end.

15. The shift register of claim 11, wherein the shift register comprises a plurality of registers,

the first scanning unit further includes:

the third reset circuit is electrically connected with the display reset signal end, the first pull-up node, the third voltage signal end and the first anti-leakage node; the third reset circuit is configured to reset the first pull-up node under the control of a display reset signal transmitted by the display reset signal end;

the second scanning unit further includes:

The fourth reset circuit is electrically connected with the display reset signal end, the second pull-up node, the third voltage signal end and the second anti-leakage node; the fourth reset circuit is configured to reset the second pull-up node under control of a display reset signal transmitted by the display reset signal terminal.

16. The shift register of claim 15, wherein the shift register comprises a plurality of registers,

the third reset circuit includes: a twenty-eighth transistor and a twenty-ninth transistor;

the control electrode of the twenty-eighth transistor is electrically connected with the display reset signal end, the first electrode of the twenty-eighth transistor is electrically connected with the first pull-up node, and the second electrode of the twenty-eighth transistor is electrically connected with the first electrode of the twenty-ninth transistor and the first anti-leakage node;

the control electrode of the twenty-ninth transistor is electrically connected with the display reset signal end, and the second electrode of the twenty-ninth transistor is electrically connected with the third voltage signal end;

the fourth reset circuit includes: a thirty-first transistor and a thirty-first transistor;

the control electrode of the thirty-first transistor is electrically connected with the display reset signal end, the first electrode of the thirty-first transistor is electrically connected with the second pull-up node, and the second electrode of the thirty-first transistor is electrically connected with the first electrode of the thirty-first transistor and the second anti-leakage node;

The control electrode of the thirty-first transistor is electrically connected with the display reset signal end, and the second electrode of the thirty-first transistor is electrically connected with the third voltage signal end.

17. The shift register of claim 11, wherein the shift register comprises a plurality of registers,

the first scanning unit further includes:

the fifth reset circuit is electrically connected with the global reset signal end, the first pull-up node, the third voltage signal end and the first anti-leakage node; the fifth reset circuit is configured to reset the first pull-up node under the control of the global reset signal transmitted by the global reset signal terminal;

the second scanning unit further includes:

the sixth reset circuit is electrically connected with the global reset signal end, the second pull-up node, the third voltage signal end and the second anti-leakage node; the sixth reset circuit is configured to reset the second pull-up node under control of a global reset signal transmitted by the global reset signal terminal.

18. The shift register of claim 17, wherein the shift register comprises a plurality of registers,

the fifth reset circuit includes: a thirty-third transistor and a thirty-third transistor;

The control electrode of the thirty-third transistor is electrically connected with the global reset signal end, the first electrode of the thirty-third transistor is electrically connected with the first pull-up node, and the second electrode of the thirty-third transistor is electrically connected with the first electrode of the thirty-third transistor and the first anti-leakage node;

a control electrode of the thirty-third transistor is electrically connected with the global reset signal end, and a second electrode of the thirty-third transistor is electrically connected with the third voltage signal end;

the sixth reset circuit includes: a thirty-fourth transistor and a thirty-fifth transistor;

a control electrode of the thirty-fourth transistor is electrically connected with the global reset signal end, a first electrode of the thirty-fourth transistor is electrically connected with the second pull-up node, and a second electrode of the thirty-fourth transistor is electrically connected with the first electrode of the thirty-fifth transistor and the second anti-leakage node;

the control electrode of the thirty-fifth transistor is electrically connected with the global reset signal terminal, and the second electrode of the thirty-fifth transistor is electrically connected with the third voltage signal terminal.

19. The shift register of claim 11, wherein the first scan cell further comprises: a seventh reset circuit and an eighth reset circuit;

The seventh reset circuit is electrically connected with the first pull-down node, the shift signal end, the first scanning signal end, the third voltage signal end and the fourth voltage signal end; the seventh reset circuit is configured to reset the shift signal terminal and the first scan signal terminal under control of the voltage of the first pull-down node;

in case the shift register further comprises a second scanning unit,

the seventh reset circuit is also electrically connected with the second pull-down node; the seventh reset circuit is configured to reset the shift signal terminal and the first scan signal terminal under control of the voltage of the second pull-down node;

the eighth reset circuit is electrically connected with the input signal end, the first pull-down node and the third voltage signal end; the eighth reset circuit is configured to reset the first pull-down node under the control of an input signal transmitted by the input signal terminal;

the second scanning unit further includes: a ninth reset circuit and a tenth reset circuit;

the ninth reset circuit is electrically connected with the first pull-down node, the second scanning signal end and the fourth voltage signal end; the ninth reset circuit is configured to reset the second scanning signal terminal under the control of the voltage of the first pull-down node or the voltage of the second pull-down node;

The tenth reset circuit is electrically connected with the input signal end, the second pull-down node and the third voltage signal end; the tenth reset circuit is configured to reset the second pull-down node under control of an input signal transmitted by the input signal terminal.

20. The shift register of claim 19, wherein the shift register comprises a plurality of registers,

the seventh reset circuit includes: a thirty-sixth transistor and a thirty-ninth transistor;

a control electrode of the thirty-sixth transistor is electrically connected with the first pull-down node, a first electrode of the thirty-sixth transistor is electrically connected with the shift signal terminal, and a second electrode of the thirty-sixth transistor is electrically connected with the third voltage signal terminal;

a control electrode of the thirty-ninth transistor is electrically connected with the first pull-down node, a first electrode of the thirty-ninth transistor is electrically connected with the first scanning signal end, and a second electrode of the thirty-ninth transistor is electrically connected with the fourth voltage signal end;

in the case where the shift register further includes a second scan cell, the seventh reset circuit further includes: a thirty-eighth transistor and a thirty-seventh transistor;

A control electrode of the thirty-eighth transistor is electrically connected with the second pull-down node, a first electrode of the thirty-eighth transistor is electrically connected with the shift signal terminal, and a second electrode of the thirty-eighth transistor is electrically connected with the third voltage signal terminal;

a control electrode of the thirty-seventh transistor is electrically connected with the second pull-down node, a first electrode of the thirty-seventh transistor is electrically connected with the first scanning signal end, and a second electrode of the thirty-seventh transistor is electrically connected with the fourth voltage signal end;

the eighth reset circuit includes: a forty-first transistor;

a control electrode of the forty transistor is electrically connected with the input signal end, a first electrode of the forty transistor is electrically connected with the first pull-down node, and a second electrode of the forty transistor is electrically connected with the third voltage signal end;

the ninth reset circuit includes: a forty-first transistor and a forty-second transistor;

the control electrode of the forty-first transistor is electrically connected with the second pull-down node, the first electrode of the forty-first transistor is electrically connected with the second scanning signal end, and the second electrode of the forty-first transistor is electrically connected with the fourth voltage signal end;

The control electrode of the forty transistor is electrically connected with the first pull-down node, the first electrode of the forty transistor is electrically connected with the second scanning signal end, and the second electrode of the forty transistor is electrically connected with the fourth voltage signal end;

the tenth reset circuit includes: a forty-third transistor;

the control electrode of the forty-third transistor is electrically connected with the input signal end, the first electrode of the forty-third transistor is electrically connected with the second pull-down node, and the second electrode of the forty-third transistor is electrically connected with the third voltage signal end.

21. The shift register of claim 19, wherein, in the case where the first output circuit is further electrically connected to the first sense signal terminal and the second output circuit is further electrically connected to the second sense signal terminal,

the seventh reset circuit is also electrically connected with the first sensing signal end; the seventh reset circuit is further configured to reset the first sensing signal terminal under the control of the voltage of the first pull-down node or the voltage of the second pull-down node;

the ninth reset circuit is also electrically connected with the second sensing signal end; the ninth reset circuit is further configured to electrically reset the second sense signal terminal under control of a voltage of the first pull-down node or a voltage of the second pull-down node.

22. The shift register of claim 21, wherein the seventh reset circuit further comprises: a fifty-fourth transistor and a fifty-fifth transistor;

a control electrode of the fifty-fourth transistor is electrically connected with the first pull-down node, a first electrode of the fifty-fourth transistor is electrically connected with the first sensing signal terminal, and a second electrode of the fifty-fourth transistor is electrically connected with the fourth voltage signal terminal;

a control electrode of the fifty-fifth transistor is electrically connected with the second pull-down node, a first electrode of the fifty-fifth transistor is electrically connected with the first sensing signal terminal, and a second electrode of the fifty-fifth transistor is electrically connected with the fourth voltage signal terminal;

the ninth reset circuit further includes: a fifty-sixth transistor and a fifty-seventh transistor;

a control electrode of the fifty-sixth transistor is electrically connected with the second pull-down node, a first electrode of the fifty-sixth transistor is electrically connected with the second sensing signal terminal, and a second electrode of the fifty-sixth transistor is electrically connected with the fourth voltage signal terminal;

the control electrode of the fifty-seventh transistor is electrically connected with the first pull-down node, the first electrode of the fifty-seventh transistor is electrically connected with the second sensing signal terminal, and the second electrode of the fifty-seventh transistor is electrically connected with the fourth voltage signal terminal.

23. The shift register according to any one of claims 1 to 6, further comprising: a blanking input unit;

the blanking input unit is electrically connected with a selection control signal end, the input signal end, a third voltage signal end, a fourth clock signal end, the first pull-up node, the first anti-leakage node and the anti-leakage input node;

the blanking input unit is configured to transmit a fourth clock signal received at the fourth clock signal terminal to the first pull-up node under control of the selection control signal transmitted by the selection control signal terminal;

in the case that the shift register further includes a second scanning unit, the blanking input unit is further electrically connected to a second pull-up node and a second anti-leakage node;

the blanking input unit is further configured to transmit a fourth clock signal received at the fourth clock signal terminal to the second pull-up node under control of the selection control signal transmitted at the selection control signal terminal.

24. The shift register of claim 23, wherein the shift register comprises a plurality of registers,

the blanking input unit includes: the first transmission circuit is connected with the first input circuit;

The selection control circuit is electrically connected with the selection control signal end, the input signal end, the third voltage signal end, the first blanking node and the third anti-leakage node; the selection control circuit is configured to transmit an input signal received at the input signal terminal to the first blanking node under control of the selection control signal;

the third anti-creeping circuit is electrically connected with a third anti-creeping node, the first blanking node and the anti-creeping input node; the third anti-leakage circuit is configured to transmit a first voltage signal or a second voltage signal from the anti-leakage input node to the third anti-leakage node under control of the voltage of the first blanking node;

the third input circuit is electrically connected with the first blanking node, the fourth clock signal end and the second blanking node; the third input circuit is configured to transmit a fourth clock signal received at the fourth clock signal terminal to the second blanking node under control of a voltage of the first blanking node;

the first transmission circuit is electrically connected with the fourth clock signal end, the second blanking node, the first pull-up node and the first anti-leakage node; the first transmission circuit is configured to transmit the fourth clock signal received at the second blanking node to the first pull-up node under control of the fourth clock signal transmitted by the fourth clock signal terminal;

In case the shift register further comprises a second scanning unit, the blanking input unit further comprises: a second transmission circuit;

the second transmission circuit is electrically connected with the fourth clock signal end, the second blanking node, the second pull-up node and the second anti-leakage node; the second transmission circuit is configured to transmit the fourth clock signal received at the second blanking node to the second pull-up node under control of the fourth clock signal transmitted at the fourth clock signal terminal.

25. The shift register of claim 24, wherein the shift register comprises a plurality of registers,

the selection control circuit includes: a forty-fourth transistor, a forty-fifth transistor, and a third capacitor;

a control electrode of the forty-fourth transistor is electrically connected with the selection control signal end, a first electrode of the forty-fourth transistor is electrically connected with the input signal end, and a second electrode of the forty-fourth transistor is electrically connected with the first electrode of the forty-fifth transistor and the third anti-leakage node;

the control electrode of the forty-fifth transistor is electrically connected with the selection control signal end, and the second electrode of the forty-fifth transistor is electrically connected with the first blanking node;

The first end of the third capacitor is electrically connected with the first blanking node, and the second end of the third capacitor is electrically connected with the third voltage signal end;

the third anticreep circuit includes: a forty-sixth transistor;

a control electrode of the forty-sixth transistor is electrically connected with the first blanking node, a first electrode of the forty-sixth transistor is electrically connected with the anti-leakage input node, and a second electrode of the forty-sixth transistor is electrically connected with the third anti-leakage node;

the third input circuit includes: a forty-seventh transistor;

the control electrode of the forty-seventh transistor is electrically connected with the first blanking node, the first electrode of the forty-seventh transistor is electrically connected with the fourth clock signal end, and the second electrode of the forty-seventh transistor is electrically connected with the second blanking node;

the first transmission circuit includes: forty-eighth and forty-ninth transistors;

a control electrode of the forty-eighth transistor is electrically connected with the fourth clock signal end, a first electrode of the forty-eighth transistor is electrically connected with the second blanking node, and a second electrode of the forty-eighth transistor is electrically connected with the first electrode of the forty-ninth transistor and the first anti-leakage node;

The control electrode of the forty-ninth transistor is electrically connected with the fourth clock signal end, and the second electrode of the forty-ninth transistor is electrically connected with the first pull-up node;

the second transmission circuit includes: a fiftieth transistor and a fiftieth transistor;

a control electrode of the fifty-first transistor is electrically connected with the fourth clock signal end, a first electrode of the fifty-first transistor is electrically connected with the second blanking node, and a second electrode of the fifty-first transistor is electrically connected with the first electrode of the fifty-first transistor and the second anti-leakage node;

the control electrode of the fifty-first transistor is electrically connected with the fourth clock signal terminal, and the second electrode of the fifty-first transistor is electrically connected with the second pull-up node.

26. A driving method of a shift register according to any one of claims 1 to 25, characterized in that the driving method comprises:

in an input phase, in response to an input signal received at an input signal terminal, a first input circuit is turned on, transmitting the input signal to a first pull-up node;

responding to a first voltage signal received at a first voltage signal end, starting an anti-leakage input unit, and transmitting the first voltage signal to an anti-leakage input node; or, in response to a second voltage signal received at a second voltage signal terminal, the anti-leakage input unit is turned on, transmitting the second voltage signal to the anti-leakage input node;

And under the control of the voltage of the first pull-up node, the anti-leakage unit is started to transmit a first voltage signal or a second voltage signal from the anti-leakage input node to the first anti-leakage node.

27. A gate drive circuit, the gate drive circuit comprising: a shift register as claimed in any one of claims 1 to 25 in a multistage cascade.

28. A display device, characterized in that the display device comprises: the gate drive circuit of claim 27.