CN113781967A

CN113781967A - Shifting register unit and driving method thereof, grid driving circuit and display device

Info

Publication number: CN113781967A
Application number: CN202111134895.4A
Authority: CN
Inventors: 冯雪欢; 程雪连
Original assignee: BOE Technology Group Co Ltd; Hefei BOE Zhuoyin Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei BOE Zhuoyin Technology Co Ltd
Priority date: 2021-09-27
Filing date: 2021-09-27
Publication date: 2021-12-10
Anticipated expiration: 2041-09-27
Also published as: CN113781967B

Abstract

The present disclosure provides a shift register unit including: a first display input sub-circuit configured to write an active level signal to the first aggregation node under control of the display cascade signal; a first black insertion input sub-circuit configured to write a black insertion cascade signal provided from the black insertion cascade signal input terminal to the black insertion control node under control of a first control clock signal, and to write an active level signal to the first aggregation node under control of a voltage at the black insertion control node and a second control clock signal; a voltage control circuit configured to write a first operating voltage provided by a first operating voltage terminal to a voltage control node under control of a voltage at a first pull-up node, the first aggregation node being coupled to the voltage control node; and a first leakage prevention circuit coupled to the first aggregation node and the first pull-up node and configured to write the voltage at the first aggregation node to the first pull-up node under the control of the voltage at the first aggregation node.

Description

Shifting register unit and driving method thereof, grid driving circuit and display device

Technical Field

The present invention relates to the field of display, and in particular, to a shift register unit, a driving method thereof, a gate driving circuit, and a display device.

Background

In the display field, especially in the organic light emitting diode display device, the dynamic image smear phenomenon is easily generated in the switching process of the dynamic display picture, that is, when the previous frame of display picture is switched to the next frame of display picture, the smear of the previous frame of picture is sensed. In order to overcome the smear phenomenon of the dynamic image, the related art adds a picture black cutting process during the pixel luminescence period, and reduces the normal display time of the pixel by adding the picture black cutting process, thereby effectively improving the smear phenomenon of the dynamic image.

Disclosure of Invention

In a first aspect, an embodiment of the present disclosure provides a shift register unit, including:

a display input circuit comprising: a first display input sub-circuit coupled to a display cascade signal input and a first aggregation node, the first display input sub-circuit configured to write an active level signal to the first aggregation node under control of a display cascade signal provided at the display cascade signal input;

a black insertion input circuit comprising: a first black insertion input sub-circuit coupled to a black insertion cascade signal input terminal, the first aggregation node, a first control clock signal terminal, and a second control clock signal terminal, the first black insertion input sub-circuit configured to write a black insertion cascade signal provided by the black insertion cascade signal input terminal to a black insertion control node under control of a first control clock signal provided by the first control clock signal terminal, and to write an active level signal to the first aggregation node under control of a voltage at the black insertion control node and a second control clock signal provided by the second control clock signal terminal;

a voltage control circuit coupled to a voltage control node, a first pull-up node, and a first operating voltage terminal, and configured to write a first operating voltage provided by the first operating voltage terminal to the voltage control node under control of a voltage at the first pull-up node, wherein the first aggregation node is coupled to the voltage control node;

a first leakage prevention circuit coupled to the first aggregation node and the first pull-up node and configured to write a voltage at the first aggregation node to the first pull-up node under control of a voltage at the first aggregation node.

In some embodiments, the first leakage prevention circuit includes: a first anticreeping transistor;

a control electrode of the first anti-leakage transistor is coupled to the first collection node, a first electrode of the first anti-leakage transistor is coupled to the first collection node, and a second electrode of the second anti-leakage transistor is coupled to the first pull-up node.

In some embodiments, the shift register cell further comprises:

a sense input circuit comprising: a first sense input sub-circuit coupled to the first aggregation node, the sense cascade signal input, the random sense signal terminal, and the sense control signal terminal, the first sense input sub-circuit configured to write the sense cascade signal provided by the sense cascade signal input to the sense control node under control of the random sense signal provided by the random sense signal terminal, and to write an active level signal to the first aggregation node under control of a voltage at the sense control node and the sense control signal provided by the sense control signal terminal.

In some embodiments, the shift register cell further comprises:

a display auxiliary input circuit coupled to the display cascade signal input, the first aggregation node, and the first pull-up node, and configured to write a voltage at the first aggregation node to the first pull-up node under control of a display cascade signal provided by the display cascade signal input.

In some embodiments, the display auxiliary input circuit comprises: an auxiliary input transistor;

a control electrode of the auxiliary input transistor is coupled to the display cascade signal input, a first electrode of the auxiliary input transistor is coupled to the first collection node, and a second electrode of the auxiliary input transistor is coupled to the first pull-up node.

In some embodiments, the shift register cell further comprises: display reset circuit and black insertion reset circuit, display reset circuit includes: a first display reset sub-circuit and a second display reset sub-circuit, the black insertion reset circuit comprising: a first black insertion reset sub-circuit and a second black insertion reset sub-circuit;

the first display reset sub-circuit is coupled with a display reset signal input end and the first pull-up node, and is configured to write an inactive level signal into the first pull-up node under the control of a display reset signal provided by the display reset signal input end;

the second display reset sub-circuit is coupled with the display reset signal input end and a second pull-up node, and is configured to write a non-active level signal into the second pull-up node under the control of a display reset signal provided by the display reset signal input end;

the first black insertion reset sub-circuit is coupled with a black insertion global reset input end, the first pull-up node and the black insertion control node, and is configured to write an inactive level signal into the first pull-up node under the control of a black insertion global reset signal provided by the black insertion global reset input end and a voltage at the black insertion control node;

the second black insertion reset sub-circuit is coupled with the black insertion global reset input end, the second pull-up node and the black insertion control node, and is configured to write an inactive level signal into the second pull-up node under the control of a black insertion global reset signal provided by the black insertion global reset input end and the voltage at the black insertion control node.

In some embodiments, the first display reset subcircuit is further coupled to a second aggregation node, the first display reset subcircuit being specifically configured to write an inactive level signal at the second aggregation node to the first pull-up node under control of a display reset signal provided at the display reset signal input;

the first black insertion reset sub-circuit is further coupled to the second aggregation node, and the first black insertion reset sub-circuit is specifically configured to write an inactive level signal at the second aggregation node to the first pull-up node under the control of a black insertion global reset signal provided by the black insertion global reset input terminal and a voltage at the black insertion control node;

the second aggregation node is coupled with the pressure control node;

the shift register unit further includes:

a second anti-leakage circuit coupled to the second aggregation node, the voltage control circuit, and a second working voltage terminal, and configured to write a second working voltage in a non-active level state provided by the second working voltage terminal to the second aggregation node when the first working voltage is not written to the voltage control node by the voltage control circuit;

and/or the presence of a gas in the gas,

the second display reset sub-circuit is further coupled to a third aggregation node, and the second display reset circuit is specifically configured to write an inactive level signal at the third aggregation node to the second pull-up node under the control of a display reset signal provided by the display reset signal input terminal;

the second black insertion reset sub-circuit is further coupled to the third aggregation node, and the second black insertion reset sub-circuit is specifically configured to write the inactive level signal at the third aggregation node to the second pull-up node under the control of a black insertion global reset signal provided by the black insertion global reset input terminal and the voltage at the black insertion control node;

the third aggregation node is coupled with the voltage control node;

the shift register unit further includes:

and the third leakage prevention circuit is coupled with the third aggregation node, the voltage control circuit and the second working voltage end and is configured to write the second working voltage which is provided by the second working voltage end and is in a non-effective level state into the third aggregation node when the first working voltage is not written into the voltage control node by the voltage control circuit.

In some embodiments, the shift register cell further comprises:

a sense reset circuit comprising: a first sensing reset sub-circuit and a second display reset sub-circuit;

the first sensing reset sub-circuit is coupled with a first pull-up node, a preset sensing reset control signal input end and a second aggregation node, and is configured to write an inactive level signal at the second aggregation node into the first pull-up node under the control of a preset sensing reset control signal provided by a preset sensing reset control signal input end;

the second sensing reset sub-circuit is coupled to the second pull-up node, the preset sensing reset control signal input terminal, and the third aggregation node, and the second sensing reset sub-circuit is configured to write the inactive level signal at the third aggregation node into the second pull-up node under the control of a preset sensing reset control signal provided by the preset sensing reset control signal input terminal.

In some embodiments, the second leakage prevention circuit includes: a second anti-leakage transistor, a control electrode of the second anti-leakage transistor being coupled to the second aggregation node, a first electrode of the second anti-leakage transistor being coupled to the second aggregation node, and a second electrode of the second anti-leakage transistor being coupled to the second operating voltage terminal;

the third leakage prevention circuit includes: and a third leakage prevention transistor, wherein a control electrode of the third leakage prevention transistor is coupled with the third aggregation node, a first electrode of the third leakage prevention transistor is coupled with the third aggregation node, and a second electrode of the third leakage prevention transistor is coupled with the second working voltage end.

In some embodiments, the shift register cell further comprises:

a sense reset circuit comprising: a first sensing reset sub-circuit and a second sensing reset sub-circuit;

the first sensing reset sub-circuit is coupled with a first pull-up node and a preset sensing reset control signal input end, and is configured to write an inactive level signal into the first pull-up node under the control of a preset sensing reset control signal provided by the preset sensing reset control signal input end;

the second sensing reset sub-circuit is coupled with a second pull-up node and a preset sensing reset control signal input end, and is configured to write an inactive level signal into the second pull-up node under the control of a preset sensing reset control signal provided by the preset sensing reset control signal input end;

the preset sensing reset control signal input end is a sensing global reset signal input end, and the preset sensing reset control signal is a sensing global reset signal; or, the preset sensing reset control signal input terminal is the random sensing signal terminal and the sensing control signal terminal, and the preset sensing reset control signal is the random sensing signal and the sensing control signal.

In some embodiments, the preset sensing reset control signal input terminal is the random sensing signal terminal and the sensing control signal terminal, and the preset sensing reset control signal is the random sensing signal and the sensing control signal;

the first sensing reset sub-circuit includes: a first sensing reset transistor and a second sensing reset transistor, the second sensing reset sub-circuit comprising: a third sensing reset transistor and a fourth sensing reset transistor;

a control electrode of the first sensing reset transistor is coupled with the random sensing signal terminal, a first electrode of the first sensing reset transistor is coupled with the first pull-up node, and a second electrode of the first sensing reset transistor is coupled with a first electrode of the second sensing reset transistor;

a control electrode of the second sensing reset transistor is coupled with the sensing control signal end, and a second electrode of the second sensing reset transistor is coupled with a second working voltage end or the voltage control node;

a control electrode of the third sensing reset transistor is coupled with the random sensing signal terminal, a first electrode of the third sensing reset transistor is coupled with the second pull-up node, and a second electrode of the third sensing reset transistor is coupled with a first electrode of the fourth sensing reset transistor;

a control electrode of the fourth sensing reset transistor is coupled to the sensing control signal terminal, and a second electrode of the fourth sensing reset transistor is coupled to the second working voltage terminal or the voltage control node.

In some embodiments, the display input circuit further comprises: a second display input sub-circuit coupled to the display cascade signal input, the voltage control node, and a second pull-up node, the second display input sub-circuit configured to write a voltage at the voltage control node to the second pull-up node under control of a display cascade signal provided at the display cascade signal input;

the black insertion input circuit further includes: a second black insertion input sub-circuit coupled to the second control clock signal terminal, the voltage control node, and the second pull-up node, the second black insertion input sub-circuit configured to write a voltage at the voltage control node to the second pull-up node under control of a second control clock signal provided by the second control clock signal terminal;

the shift register unit further includes:

and a first output circuit coupled to the first pull-up node, the second pull-up node, the two cascade clock signal terminals, the two first scan clock signal terminals, the two cascade signal output terminals, and the two first composite signal output terminals, and configured to write the cascade clock signal provided by one of the cascade clock signal terminals to one of the cascade signal output terminals and write the first scan clock signal provided by one of the first scan clock signal terminals to one of the first composite signal output terminals under control of a voltage at the first pull-up node, and write the cascade clock signal provided by the other of the cascade clock signal terminals to the other of the cascade signal output terminals and write the first scan clock signal provided by the other of the first scan clock signal terminals to the other of the first composite signal output terminals under control of a voltage at the second pull-up node.

In some embodiments, further comprising:

an inverting circuit coupled to the first pull-up node, the second pull-up node, the first pull-down node, the second pull-down node, configured to write to the first pull-down node a voltage that is inverted from a voltage at the first pull-up node, and to write to the second pull-down node a voltage that is inverted from a voltage at the second pull-up node;

the first output circuit is further coupled to the first and second pull-down nodes, and is further configured to write an inactive level signal to two cascaded signal outputs and two first composite signal outputs under control of a voltage at the first and second pull-down nodes.

In some embodiments, the shift register cell further comprises:

a first pull-down control circuit coupled to the display cascade signal input terminal, the first pull-down node, the second pull-down node, and a second operating voltage terminal, and configured to write a second operating voltage provided by the second operating voltage terminal to the first pull-down node under control of a display cascade signal provided by the display cascade signal input terminal;

and/or, the shift register unit further comprises: a second pull-down control circuit, coupled to the black insertion control node, the second control clock signal terminal, the first pull-down node, and a second operating voltage terminal, configured to write a second operating voltage provided by the second operating voltage terminal to the first pull-down node under control of a voltage at the black insertion control node and a second control clock signal provided by the second control clock signal terminal;

and/or, when the shift register unit comprises a sensing input circuit, the shift register unit further comprises: a third pull-down control circuit coupled to a sensing control signal terminal, a sensing control node, the first pull-down node, and the second operating voltage terminal, and configured to write a second operating voltage provided by the second operating voltage terminal to the first pull-down node under control of a voltage at the sensing control node and a sensing control signal provided by the sensing control signal terminal.

In a second aspect, an embodiment of the present disclosure further provides a gate driving circuit, including: a plurality of cascaded shift register units, the shift register units being the shift register units provided in the first aspect.

In some embodiments, the gate driving circuit includes M stages of shift register units, one of the two cascade signal output ends of each shift register unit is a display cascade signal output end, and the other is a black insertion cascade signal output end;

the display cascade signal input end of the M-th stage shift register unit is coupled with the display cascade signal output end of the M-a stage shift register unit, the display reset signal input end of the M-th stage shift register unit is coupled with the display cascade signal output end of the M + b stage shift register unit, the black insertion cascade signal input end of the M-th stage shift register unit is coupled with the black insertion cascade signal output end of the M-c stage shift register unit, a, b and c are respectively preset positive integers, a + b is less than or equal to c, M is a positive integer and satisfies a is less than M, c is less than M, and M + b is less than or equal to M.

In some embodiments, the M shift register units are divided into a plurality of first shift register unit groups and a plurality of second shift register unit groups, and the number of shift register units in the first shift register unit groups and the number of shift registers in the second shift register unit groups are both c;

the gate driving circuit is provided with 4c first scanning clock signal lines, the 4c first scanning clock signal lines are divided into a first signal line group and a second signal line group, and the number of the first scanning clock signal lines in the first signal line group and the number of the first scanning clock signal lines in the second signal line group are both 2 c; two first scanning clock signal ends of an ith shift register unit in the first shift register unit group are respectively coupled with a 2i-1 st first scanning clock signal line and a 2i first scanning clock signal line in the first signal line group, and two first scanning clock signal ends of an ith shift register unit in the second shift register unit group are respectively coupled with a 2i-1 st first scanning clock signal line and a 2i first scanning clock signal line in the second signal line group;

the gate driving circuit is provided with 4c cascaded clock signal lines, the 4c cascaded clock signal lines are divided into a fourth signal line group and a fifth signal line group, and the number of the cascaded clock signal lines in the fourth signal line group and the number of the cascaded clock signal lines in the fifth signal line group are both 2 c; two cascade clock signal ends of the ith shift register unit in the first shift register unit group are respectively coupled with the 2i-1 cascade clock signal line and the 2i cascade clock signal line in the fourth signal line group; two cascade clock signal ends of the ith shift register unit in the second shift register unit group are respectively coupled with the 2i-1 cascade clock signal line and the 2i cascade clock signal line in the fifth signal line group;

i is a positive integer and i is not more than c;

in the plurality of first shift register unit groups and the plurality of second shift register unit groups, one first shift register unit group and one second shift register unit group are sequentially and alternately arranged, or two first shift register unit groups and two second shift register unit groups are sequentially and alternately arranged.

In some embodiments, the first black insertion input sub-circuit comprises: a common part circuit and a non-common part circuit, the common part circuit and the non-common part circuit being coupled to a black insertion pull-up node;

the first black insertion input sub-circuits in the shift register units of the same first shift register unit group include the same shared part circuit part, and the first black insertion input sub-circuits in the shift register units of the same first shift register unit group include different non-shared part circuit parts;

the first black insertion sub-circuits in the shift register units of the same second shift register unit group include the same shared part circuit part, and the first black insertion sub-circuits in the shift register units of the same second shift register unit group include different non-shared part circuit parts;

the common part circuit is coupled with the black insertion cascade signal input end and a first control clock signal end, and is configured to write a black insertion cascade signal provided by the black insertion cascade signal input end into a black insertion control node under the control of a first control clock signal provided by the first control clock signal end, and write an effective level signal into the black insertion pull-up node under the control of a voltage at the black insertion control node;

the unshared part circuit is coupled with the second control clock signal terminal and the first aggregation node in the shift register unit, and is configured to write the voltage at the black insertion pull-up node into the corresponding first aggregation node under the control of a second control clock signal provided by the second control clock signal terminal.

In some embodiments, c has a value of 4.

In a third aspect, an embodiment of the present disclosure further provides a display device, including: the gate driving circuit as provided in the second aspect above.

In a fourth aspect, an embodiment of the present disclosure further provides a driving method applied to a shift register unit, where the shift register unit employs the shift register unit provided in the first aspect, and the driving method includes:

a display driving process comprising:

a display pre-charge stage, wherein the first display input sub-circuit writes an active level signal to the first collection node under the control of the display cascade signal, and the first anti-leakage circuit writes a voltage at the first collection node to the first pull-up node under the control of a voltage at the first collection node;

a black insertion driving process comprising:

a black insertion pre-charging stage, in which the first black insertion input sub-circuit writes the black insertion cascade signal into a black insertion control node under the control of the first control clock signal;

a black insertion writing phase, wherein the first black insertion input sub-circuit writes an active level signal to the first aggregation node under the control of the voltage at the black insertion control node and the second control clock signal, and the first anti-leakage circuit writes the voltage at the first aggregation node to the first pull-up node under the control of the voltage at the first aggregation node.

Drawings

FIG. 1 is a schematic top view of a display device in the practice of the present disclosure;

FIG. 2 is a schematic circuit diagram of a pixel unit in a display substrate according to the present disclosure;

FIG. 3A is a timing diagram illustrating operation of the pixel unit shown in FIG. 2;

FIG. 3B is a timing diagram illustrating another operation of the pixel unit shown in FIG. 2;

fig. 4A is a schematic circuit structure diagram of a shift register unit according to an embodiment of the present disclosure;

fig. 4B is a schematic circuit structure diagram of another shift register unit according to an embodiment of the present disclosure;

fig. 5 is a schematic circuit structure diagram of another shift register unit according to an embodiment of the present disclosure;

fig. 6 is a schematic circuit structure diagram of another shift register unit according to an embodiment of the present disclosure;

FIG. 7 is a timing diagram illustrating operation of the shift register unit shown in FIG. 6 during display driving and black insertion driving;

FIG. 8 is a timing diagram illustrating another operation of the shift register unit shown in FIG. 6 during display driving and black insertion driving;

FIG. 9 is a circuit diagram illustrating a shift register according to another embodiment of the present disclosure;

fig. 10 is a schematic circuit diagram of another shift register unit according to an embodiment of the present disclosure;

fig. 11 is a schematic circuit diagram of another shift register unit according to an embodiment of the present disclosure;

fig. 12 is a schematic circuit diagram of another shift register unit according to an embodiment of the present disclosure;

fig. 13 is a schematic circuit diagram of another shift register unit according to an embodiment of the present disclosure;

fig. 14 is a schematic circuit diagram of another shift register unit according to an embodiment of the present disclosure;

fig. 15 is a schematic circuit diagram of another shift register unit according to an embodiment of the present disclosure;

fig. 16 is a schematic circuit structure diagram of a gate driving circuit according to an embodiment of the disclosure;

FIG. 17 is a schematic diagram of a circuit configuration of a first shift register cell group according to an embodiment of the present disclosure;

FIG. 18 is a schematic diagram of a circuit configuration of a second shift register cell group according to an embodiment of the present disclosure;

fig. 19 is a schematic circuit diagram of another circuit structure of the gate driving circuit according to the embodiment of the disclosure;

FIG. 20 is a timing diagram illustrating the operation of the gate driving circuit shown in FIG. 16;

FIG. 21 is a timing diagram illustrating the operation of the gate driving circuit shown in FIG. 19;

FIG. 22 is a schematic diagram of a circuit structure of shift register units in the same shift register unit group sharing the first black insertion input sub-circuit according to an embodiment of the present disclosure;

fig. 23 is a flowchart of a driving method of a shift register unit according to an embodiment of the present disclosure.

Detailed Description

In order to make those skilled in the art better understand the technical solution of the present invention, a shift register unit, a driving method thereof, a gate driving circuit and a display device provided by the present invention are described in detail below with reference to the accompanying drawings.

The use of "first," "second," and similar terms in the embodiments of the disclosure is not intended to indicate any order, quantity, or importance, but rather to distinguish one element from another. Likewise, the word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "coupled" or "connected," and the like, are not restricted to physical or mechanical couplings, but may include electrical couplings, whether direct or indirect.

The transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics. In this embodiment, the drain and source of each transistor may be coupled in an interchangeable manner, and thus, the drain and source of each transistor in the embodiment of the present disclosure are not different. Here, only in order to distinguish two poles of the transistor except for the control electrode (i.e., the gate), one of the poles is referred to as a drain and the other pole is referred to as a source. The thin film transistor used in the embodiment of the present disclosure may be an N-type transistor or a P-type transistor. In the embodiment of the present disclosure, when an N-type thin film transistor is used, the first electrode thereof may be a source electrode, and the second electrode thereof may be a drain electrode. In the following embodiments, the thin film transistor is described as an N-type transistor.

In the present disclosure, an "active level signal" refers to a signal that can control the transistor to be turned on when the signal is input to the control electrode of the transistor, and an "inactive level signal" refers to a signal that can control the transistor to be turned off when the signal is input to the control electrode of the transistor. For an N-type transistor, a high level signal is an active level signal, and a low level signal is a non-active level signal; for a P-type transistor, the low level signal is an active level signal and the high level signal is an inactive level signal.

In the following description, the transistors will be described as N-type transistors as an example, and at this time, the active level signal refers to a high level signal and the inactive level signal refers to a low level signal. It is conceivable that when a P-type transistor is employed, the timing of the control signal needs to be adjusted accordingly. Specific details are not set forth herein but are intended to be within the scope of the present disclosure.

Fig. 1 is a schematic top view of a display device in the practice of the present disclosure. As shown in fig. 1, the display device 100 includes: a display area 101 and a peripheral area 102, a plurality of pixel units 300 arranged in an array are disposed in the display area 101, a gate driving circuit 200 is disposed in the peripheral area 102, and the gate driving circuit 200 includes: a plurality of shift register units SRU are cascaded.

Fig. 2 is a schematic circuit diagram of a pixel unit in a display substrate according to the disclosure, fig. 3A is a timing diagram of an operation of the pixel unit shown in fig. 2, and fig. 3B is a timing diagram of another operation of the pixel unit shown in fig. 2. As shown in fig. 2 to 3B, the pixel unit 300 includes: a pixel circuit and a light emitting element. In which the light emitting element is an Organic Light Emitting Diode (OLED) as an example.

The pixel circuit includes a data writing transistor QTFT (a control electrode connected to the first gate line G1), a driving transistor DTFT, a sensing transistor STFT (a control electrode connected to the second gate line G2, a first electrode connected to the sensing signal line sequence), and a storage capacitor Cst. Referring to fig. 2, when only the pixel unit 300 needs to perform light emitting display, the working process of the pixel unit 300 includes a display data writing phase and a light emitting phase; during the stage of writing display Data, the first gate line G1 controls the Data writing transistor QTFT to be turned on, and the Data line Data writes the Data voltage Vdata to the control electrode of the driving transistor DTFT; in the light emitting stage, the driving transistor DTFT outputs a corresponding driving current according to the voltage at the control electrode thereof, so as to drive the light emitting element OLED to emit light.

It should be noted that after one frame is finished, the electrical characteristics of the driving transistor DTFT and/or the light emitting element OLED in the pixel circuit may be sensed by the sensing transistor STFT, and the sensing result may be used to externally compensate the pixel circuit. The specific external compensation process belongs to the conventional technology in the field, and is not described in detail herein.

The pixel unit 300 may generate a moving image smear during operation, that is, when the display device switches from one frame to another frame, a user may feel the smear of the previous frame. One solution is: as shown in fig. 3, a black data writing process and a black data holding process, i.e., a process of one Picture black insertion, are set during the lighting of the pixel circuit, which reduces the lighting Time and enhances the Moving Picture Response Time (MPRT), the larger the MPRT, the lighter the smear.

In the related art, the display driving and the black insertion driving are integrated in the same gate driving circuit, that is, each stage of shift register unit in the gate driving circuit can be used for performing the display driving and the black insertion driving. Since the display driving process and the black insertion driving process are not synchronized, the cascade relationship in the display driving process and the cascade relationship in the black insertion driving process need to be set respectively.

Currently, a shift register unit SRU generally includes two shift register circuits, where the two shift register circuits respectively correspond to two rows of pixel units located in a display area, that is, one shift register unit corresponds to two rows of pixel units. At this time, the output of one shift register circuit in the shift register unit can be used for performing display driving cascade, and the output of the other shift register circuit in the shift register unit can be used for performing black insertion driving cascade.

The operation process of the gate driving circuit includes a display driving stage and a black insertion driving stage, which are alternately performed, during one display driving stage, the first composite signal output terminal of some stage of the shift register unit SRU in the gate driving circuit sequentially outputs a display driving signal (for example, pulse 1 in fig. 3) for performing display driving, and during one black insertion driving stage, the first composite signal output terminal of some stage of the shift register unit SRU in the gate driving circuit outputs a black insertion driving signal (for example, pulse 2 in fig. 3) for performing black insertion driving. Generally, a plurality of display driving stages are required to completely write a complete frame of display data into each corresponding pixel unit. The specific procedure will be described in detail later with reference to specific examples.

In the related art, in order to realize that the shift register unit has the functions of outputting the display driving signal and the black insertion driving signal, the circuit structure of the shift register unit is generally designed to be relatively complex; meanwhile, in order to ensure the working stability of the shift register unit, a voltage control circuit and a plurality of anti-creeping circuits matched with the voltage control circuit are arranged in the shift register unit; for example, in order to prevent the pull-up node in the shift register unit from leaking electricity through the display input circuit and the black insertion input circuit, an anti-leakage circuit is provided between the display input circuit and the pull-up node, and another anti-leakage circuit is also provided between the black insertion input circuit and the pull-up node; however, although the addition of the two anti-leakage circuits will ensure the stability of the pull-up node voltage to a certain extent, the complexity of the shift register unit will also increase, and the number of transistors required to be disposed in the shift register unit will also increase accordingly.

Fig. 4A is a schematic circuit structure diagram of a shift register unit according to an embodiment of the present disclosure. As shown in fig. 4A, the shift register unit includes: a display input circuit, a black insertion input circuit, a voltage control circuit 4 and a first anticreeping circuit 3.

The display input circuit includes: a first display input sub-circuit 111, the first display input sub-circuit 111 being coupled to the display cascade signal input IN1 and the first aggregation node Z1, the first display input sub-circuit 111 being configured to write an active level signal to the first aggregation node Z1 under control of the display cascade signal provided at the display cascade signal input IN 1.

The black insertion input circuit includes: a first black insertion input sub-circuit 211, the first black insertion input sub-circuit 211 being coupled to the black insertion cascade signal input IN2, the first aggregation node Z1, the first control clock signal terminal BCK1 and the second control clock signal terminal BCK2, the first black insertion input sub-circuit 211 being configured to write the black insertion cascade signal provided by the black insertion cascade signal input IN2 to the black insertion control node H under control of the first control clock signal provided by the first control clock signal terminal BCK1, and to write an active level signal to the first aggregation node Z1 under control of a voltage at the black insertion control node H and the second control clock signal provided by the second control clock signal terminal BCK 2.

The voltage control circuit 4 is coupled to the voltage control node OFF, the first pull-up node PU1 and the first working voltage terminal, and the voltage control circuit 4 is configured to write the first working voltage VDD provided by the first working voltage terminal to the voltage control node OFF under the control of the voltage at the first pull-up node PU 1; wherein the first aggregation node Z1 is coupled to the control voltage node OFF; the first operating voltage VDD provided by the first operating voltage terminal is an active level signal.

The first leakage prevention circuit 3 is coupled to the first collection node Z1 and the first pull-up node PU1, and the first leakage prevention circuit 3 is configured to write the voltage at the first collection node Z1 to the first pull-up node PU1 under the control of the voltage at the first collection node Z1.

In the embodiment of the present disclosure, the first display input sub-circuit 111 in the display input circuit and the first black insertion sub-circuit 211 in the black insertion input circuit are connected to the first pull-up node PU1 through the same first anti-leakage circuit 3. Compared with the related art, the first anti-leakage circuit 3 is shared, so that the number of anti-leakage circuits can be effectively reduced while the first pull-up node PU1 is prevented from leaking electricity through the first display input sub-circuit 111 and the first black insertion input sub-circuit 211, thereby being beneficial to reducing the complexity of the shift register unit and reducing the number of transistors required to be arranged in the shift register unit.

In some embodiments, the display input circuit further comprises: a second display input sub-circuit 121, the second display input sub-circuit 121 being coupled to the display cascade signal input IN1, the voltage control node OFF, and the second pull-up node PU2, the second display input sub-circuit 121 being configured to write the voltage at the voltage control node OFF to the second pull-up node PU2 under control of the display cascade signal provided by the display cascade signal input IN 1.

The black insertion input circuit further includes: a second black insertion sub-circuit 221, the second black insertion sub-circuit 221 being coupled to the second control clock signal terminal BCK2, the voltage control node OFF and the second pull-up node PU2, the second black insertion sub-circuit 221 being configured to write the voltage at the voltage control node OFF to the second pull-up node PU2 under the control of a second control clock signal provided by the second control clock signal terminal BCK 2.

The shift register unit further includes: a first output circuit 5, the first output circuit 5 being coupled to the first pull-up node PU1, the second pull-up node PU2, the two cascade clock signal terminals CLKD, CLKD ', the two first scan clock signal terminals CLKE, CLKE', the two cascade signal output terminals CR, CR 'and the two first composite signal output terminals OUT1, OUT1', and being configured to write the cascade clock signal provided by one of the cascade clock signal terminals into one of the cascade signal output terminals under control of the voltage at the first pull-up node PU1, and writes a first scan clock signal provided from a first scan clock signal terminal into a first composite signal output terminal, and writes the cascade clock signal provided from the other cascade clock signal terminal to the other cascade signal output terminal under the control of the voltage at the second pull-up node PU2, and writing the first scanning clock signal provided by the other first scanning clock signal terminal into the other first composite signal output terminal.

The working process of the shift register unit provided by the embodiment of the disclosure comprises a display driving process and a black insertion driving process.

In the display driving process, the first display input sub-circuit 111 writes the active level signal to the first pull-up node PU1 through the first anticreeping circuit 3 under the control of the display cascade signal, the second display input sub-circuit 121 writes the active level signal to the second pull-up node PU2 under the control of the display cascade signal, the first output sub-circuit writes the cascade clock signal provided by a cascade clock signal terminal to a cascade signal output terminal under the control of the voltage at the first pull-up node PU1, and writes a first scan clock signal provided from a first scan clock signal terminal into a first composite signal output terminal, and writes the cascade clock signal provided from the other cascade clock signal terminal to the other cascade signal output terminal under the control of the voltage at the second pull-up node PU2, and writing the first scanning clock signal provided by the other first scanning clock signal terminal into the other first composite signal output terminal. At this time, the two first scan clock signal terminals CLKE, CLKE' are both provided with display driving pulses; the cascade clock signal provided by a cascade clock signal terminal corresponding to the display cascade signal output terminal includes a display cascade pulse.

In the black insertion driving process, the first black insertion input sub-circuit 211 writes an active level signal to the first pull-up node PU1 under the control of a black insertion cascade signal and a second control clock signal, the second black insertion input sub-circuit 221 writes an active level signal to the second pull-up node PU2 under the control of a second control clock signal, the first output sub-circuit writes a cascade clock signal provided from one cascade clock signal terminal to one cascade signal output terminal under the control of a voltage at the first pull-up node PU1, and writes a first scan clock signal provided from a first scan clock signal terminal into a first composite signal output terminal, and writes the cascade clock signal provided from the other cascade clock signal terminal to the other cascade signal output terminal under the control of the voltage at the second pull-up node PU2, and writing the first scanning clock signal provided by the other first scanning clock signal terminal into the other first composite signal output terminal. At this time, the two first scan clock signal terminals CLKE, CLKE' are both provided with black insertion drive pulses; the cascade clock signal provided by a cascade clock signal end corresponding to the black insertion cascade signal output end comprises a black insertion cascade pulse.

Based on the above, it can be seen that the two first composite signal output ends OUT1 and OUT1' of the shift register unit provided by the present disclosure may each output a display driving pulse and a black insertion driving pulse to perform display driving and black insertion driving on the corresponding first gate line; meanwhile, two cascade signal output ends CR and CR' in the shift register unit can respectively output a display cascade pulse and a black insertion cascade pulse so as to realize display drive cascade and black insertion drive cascade among a plurality of shift register units in the grid drive circuit.

Fig. 4B is a schematic circuit structure diagram of another shift register unit according to an embodiment of the present disclosure. As shown in fig. 4B, in some embodiments, the first leakage prevention circuit 3 includes: a first anticreeping transistor T1; a control electrode of the first anticreeping transistor T1 is coupled to the first collection node Z1, a first electrode of the first anticreeping transistor T1 is coupled to the first collection node Z1, and a second electrode of the second anticreeping transistor T2 is coupled to the first pull-up node PU 1.

When the shift register unit outputs the display driving pulse and the black insertion driving pulse through the first composite signal output end, the first pull-up node PU1 is in an active level state; in response to the control of the first pull-up node PU1, the voltage control circuit 4 will continuously write the first working voltage in an active level state into the voltage control node OFF and the first collection node Z1 connected to the voltage control node OFF, at which time the first anticreeping transistor T1 is turned on, and the first collection node Z1 is turned on with the first pull-up node PU 1. Since the voltage control circuit 4 continuously charges the first aggregation node Z1 to maintain the first aggregation node Z1 at the active level state, the leakage of the first pull-up node PU1 through the first display input sub-circuit 111 and the first black insertion input sub-circuit 211 can be effectively avoided.

Fig. 5 is a schematic circuit structure diagram of another shift register unit according to an embodiment of the present disclosure. As shown in fig. 5, the shift register unit further includes: show reset circuit and insert black reset circuit, show reset circuit and include: a first display reset sub-circuit 112 and a second display reset sub-circuit 122, the black insertion reset circuit comprising: a first black inserted reset sub-circuit 212 and a second black inserted reset sub-circuit 222.

The first display reset sub-circuit 112 is coupled to the display reset signal input RST and the first pull-up node PU1, and the first display reset sub-circuit 112 is configured to write the inactive level signal to the first pull-up node PU1 under the control of the display reset signal provided by the display reset signal input RST.

The second display reset sub-circuit 122 is coupled to the display reset signal input RST and the second pull-up node PU2, and the second display reset sub-circuit 122 is configured to write the inactive level signal to the second pull-up node PU2 under the control of the display reset signal provided by the display reset signal input RST.

The first black insertion reset sub-circuit 212 is coupled to the black insertion global reset input BTRST, the first pull-up node PU1, and the black insertion control node H, and the first black insertion reset sub-circuit 212 is configured to write an inactive level signal to the first pull-up node PU1 under the control of a black insertion global reset signal provided from the black insertion global reset input BTRST and a voltage at the black insertion control node H.

The second black insertion reset sub-circuit 222 is coupled to the black insertion global reset input BTRST, the second pull-up node PU2, and the black insertion control node H, and the second black insertion reset sub-circuit 222 is configured to write the inactive level signal to the second pull-up node PU2 under the control of the black insertion global reset signal provided from the black insertion global reset input BTRST and the voltage at the black insertion control node H.

In some embodiments, the shift register cell further comprises: an inverter circuit 6, the inverter circuit 6 coupled to the first pull-up node PU1, the second pull-up node PU2, the first pull-down node PD1, and the second pull-down node PD2, the inverter circuit 6 configured to write a voltage inverted from the voltage at the first pull-up node PU1 to the first pull-down node PD1, and write a voltage inverted from the voltage at the second pull-up node PU2 to the second pull-down node PD 2;

at this time, the first output circuit 5 is further coupled to the first and second pull-down nodes PD1 and PD2, and the first output circuit 5 is further configured to write the inactive level signal to the two cascade signal output terminals CR, CR 'and the two first composite signal output terminals OUT1, OUT1' under the control of the voltage at the first and second pull-down nodes PD1 and PD 2.

In some embodiments, the shift register cell further comprises: a feedback circuit 7, the feedback circuit 7 coupled to the first pull-up node PU1, the second pull-up node PU2, the first pull-down node PD1, and the second pull-down node PD2, and configured to write a non-active level signal to the first pull-up node PU1 and the second pull-up node PU2 under control of a voltage at the first pull-down node PD1 and/or a voltage at the second pull-down node PD 2.

Fig. 6 is a schematic circuit structure diagram of another shift register unit according to an embodiment of the present disclosure. As shown in fig. 6, the shift register unit shown in fig. 6 is an embodiment of an alternative embodiment based on the shift register unit shown in fig. 5.

The first display input sub-circuit 111 includes a first transistor M1, the first display reset sub-circuit 112 includes a second transistor M2, the second display input sub-circuit 121 includes a third transistor M3, the second display reset sub-circuit 122 includes a fourth transistor M4, the first black insertion input sub-circuit 211 includes fifth to seventh transistors M5 to M7, the second black insertion input sub-circuit 221 includes an eighth transistor M8, the first black insertion reset sub-circuit 212 includes ninth to tenth transistors M9 and M10, the second black insertion reset sub-circuit 222 includes eleventh to twelfth transistors M11 and M12, the first output sub-circuit includes thirteenth to sixteenth transistors M13 to M16 and twenty-seventh to thirty transistors M27 to M30, the inverter circuit 6 includes seventeenth to twenty-fourth transistors M17 to M24, the feedback circuit 7 includes twenty-fifth to twenty-sixth transistors M25 and twenty-sixth transistors M26, the voltage control circuit 4 includes a first voltage control transistor K1, and the first leakage preventing circuit 3 includes a first leakage preventing transistor T1.

A control electrode of the first transistor M1 is coupled to the display cascade signal input terminal IN1, a first electrode of the first transistor M1 is coupled to the display cascade signal input terminal IN1, and a second electrode of the first transistor M1 is coupled to the first collection node Z1.

The control electrode of the second transistor M2 is coupled to the display reset signal input RST, the first electrode of the second transistor M2 is coupled to the first pull-up node PU1, the second electrode of the second transistor M2 is coupled to the second operating voltage terminal, and the second operating voltage terminal provides the second operating voltage VGL1 in the inactive level state.

A control electrode of the third transistor M3 is coupled to the display cascade signal input terminal IN1, a first electrode of the third transistor M3 is coupled to the display cascade signal input terminal IN1, and a second electrode of the third transistor M3 is coupled to the second pull-up node PU 2.

The control electrode of the fourth transistor M4 is coupled to the display reset signal input RST, the first electrode of the fourth transistor M4 is coupled to the second pull-up node PU2, and the second electrode of the fourth transistor M4 is coupled to the second operating voltage terminal.

A control electrode of the fifth transistor M5 is coupled to the first control clock signal terminal BCK1, a first electrode of the fifth transistor M5 is coupled to the black inserted cascade signal input terminal IN2, and a second electrode of the fifth transistor M5 is coupled to the black inserted control node H.

A control electrode of the sixth transistor M6 is coupled to the black insertion control node H, a first electrode of the sixth transistor M6 is coupled to the second control clock signal terminal BCK2, and a second electrode of the sixth transistor M6 is coupled to the black insertion pull-up node K in the first black insertion input sub-circuit 211.

A control electrode of the seventh transistor M7 is coupled to the second control clock signal terminal BCK2, a first electrode of the seventh transistor M7 is coupled to the black insertion pull-up node K, and a second electrode of the seventh transistor M7 is coupled to the first collection node Z1.

A control electrode of the eighth transistor M8 is coupled to the second control clock signal terminal BCK2, a first electrode of the eighth transistor M8 is coupled to the control voltage node OFF, and a second electrode of the eighth transistor M8 is coupled to the second pull-up node PU 2.

A control electrode of the ninth transistor M9 is coupled to the black insertion control node H, a first electrode of the ninth transistor M9 is coupled to the first pull-up node PU1, and a second electrode of the ninth transistor M9 is coupled to a first electrode of the tenth transistor M10.

A control electrode of the tenth transistor M10 is coupled to the black insertion global reset signal input terminal BTRST, and a second electrode of the tenth transistor M10 is coupled to the second operating voltage terminal.

A control electrode of the eleventh transistor M11 is coupled to the black insertion control node H, a first electrode of the eleventh transistor M11 is coupled to the second pull-up node PU2, and a second electrode of the eleventh transistor M11 is coupled to a first electrode of the twelfth transistor M12.

A control electrode of the twelfth transistor M12 is coupled to the black insertion global reset signal input terminal BTRST, and a second electrode of the twelfth transistor M12 is coupled to the second operating voltage terminal.

A control electrode of the thirteenth transistor M13 is coupled to the first pull-up node PU1, a first electrode of the thirteenth transistor M13 is coupled to a cascade clock signal terminal CLKD, and a second electrode of the thirteenth transistor M13 is coupled to a cascade signal output terminal CR.

A control electrode of the fourteenth transistor M14 is coupled to the first pull-up node PU1, a first electrode of the fourteenth transistor M14 is coupled to a first scan clock signal terminal CLKE, and a second electrode of the fourteenth transistor M14 is coupled to a first composite signal output terminal OUT 1.

A control electrode of the fifteenth transistor M15 is coupled to the second pull-up node PU2, a first electrode of the fifteenth transistor M15 is coupled to another cascade clock signal terminal CLKD ', and a second electrode of the fifteenth transistor M15 is coupled to another cascade signal output terminal CR'.

A control electrode of the sixteenth transistor M16 is coupled to the second pull-up node PU2, a first electrode of the sixteenth transistor M16 is coupled to another first scan clock signal terminal CLKE ', and a second electrode of the sixteenth transistor M16 is coupled to another first composite signal output terminal OUT 1'.

A control electrode of the seventeenth transistor M17 is coupled to a first operating voltage terminal (providing the first operating voltage VDD in an active level state), a first electrode of the seventeenth transistor M17 is coupled to the first operating voltage terminal, and a second electrode of the seventeenth transistor M17 is coupled to a control electrode of the nineteenth transistor M19 and a first electrode of the eighteenth transistor M18;

a control electrode of the eighteenth transistor M18 is coupled to the first pull-up node PU1, and a second electrode of the eighteenth transistor M18 is coupled to the second operating voltage terminal.

A first pole of the nineteenth transistor M19 is coupled to the first operating voltage terminal, and a second pole of the nineteenth transistor M19 is coupled to the first pull-down node PD 1.

A control electrode of the twentieth transistor M20 is coupled to the first pull-up node PU1, a first electrode of the twentieth transistor M20 is coupled to the first pull-down node PD1, and a second electrode of the twentieth transistor M20 is coupled to the second operating voltage terminal.

A control electrode of the twenty-first transistor M21 is coupled to the first operating voltage terminal, a first electrode of the twenty-first transistor M21 is coupled to the first operating voltage terminal, a second electrode of the twenty-first transistor M21 is coupled to a control electrode of the twenty-third transistor M23 and a first electrode of the twenty-second transistor M22;

the control electrode of the twentieth transistor M22 is coupled to the second pull-up node PU2, and the second electrode of the twentieth transistor M22 is coupled to the second operating voltage terminal.

A first pole of the twenty-third transistor M23 is coupled to the first operating voltage terminal, and a second pole of the twenty-third transistor M23 is coupled to the second pull-down node PD 2.

A control electrode of the twenty-fourth transistor M24 is coupled to the second pull-up node PU2, a first electrode of the twenty-fourth transistor M24 is coupled to the second pull-down node PD2, and a second electrode of the twenty-fourth transistor M24 is coupled to the second operating voltage terminal.

A control electrode of the twenty-fifth transistor M25 is coupled to the first pull-down node PD1, a first electrode of the twenty-fifth transistor M25 is coupled to the first pull-up node PU1, and a second electrode of the twenty-fifth transistor M25 is coupled to the second operating voltage terminal.

A control electrode of the twenty-sixth transistor M26 is coupled to the second pull-down node PD2, a first electrode of the twenty-sixth transistor M26 is coupled to the second pull-up node PU2, and a second electrode of the twenty-sixth transistor M26 is coupled to the second operating voltage terminal.

A control electrode of the twenty-seventh transistor M27 is coupled to the first pull-down node PD1, a first electrode of the twenty-seventh transistor M27 is coupled to the cascade signal output terminal CR, and a second electrode of the twenty-seventh transistor M27 is coupled to the second operating voltage terminal.

A control electrode of the twenty-eighth transistor M28 is coupled to the first pull-down node PD1, a first electrode of the twenty-eighth transistor M28 is coupled to the first composite signal output terminal OUT1, and a second electrode of the twenty-eighth transistor M28 is coupled to a third operating voltage terminal (providing a third operating voltage VGL2, VGL2 may be equal to VGL 1).

A control electrode of the twenty-ninth transistor M29 is coupled to the second pull-down node PD2, a first electrode of the twenty-ninth transistor M29 is coupled to the cascade signal output terminal CR', and a second electrode of the twenty-ninth transistor M29 is coupled to the second operating voltage terminal.

A control electrode of the thirtieth transistor M30 is coupled to the second pull-down node PD2, a first electrode of the thirtieth transistor M30 is coupled to the first composite signal output terminal OUT1', and a second electrode of the thirtieth transistor M30 is coupled to the third operating voltage terminal.

In some embodiments, to ensure the stability of the voltage at the black insertion control node H, a first capacitor C1 is further disposed in the first black insertion input sub-circuit 211.

In some embodiments, a second capacitor C2 and a third capacitor C3 are also arranged within the first output circuit 5; a first end of the second capacitor C2 is connected to the first pull-up node PU1, and a second end of the second capacitor C2 is connected to the first composite signal output terminal OUT 1; a first terminal of the third capacitor C3 is connected to the second pull-up node PU2, and a second terminal of the third capacitor C3 is connected to the first composite signal output terminal OUT 1'.

Fig. 7 is a timing chart showing the operation of the shift register unit shown in fig. 6 during the display driving and the black insertion driving. As shown in fig. 6 and 7, the process of the shift register unit performing display driving may include: a display precharge phase t1, a display driving output phase t2 and a display reset phase t 3; the process of black insertion driving of the shift register unit can comprise the following steps: black insertion precharge phase t4, black insertion write phase t5, black insertion drive output phase t6, and black insertion reset phase t 7.

IN the display precharge stage T1, the display cascade signal provided by the display cascade signal input terminal IN1 is IN a high level state, the first transistor M1 and the third transistor M3 are turned on, the display cascade signal IN the high level state is written into the first collecting node Z1 and the second pull-up node PU2, at this time, the first anti-leakage transistor T1 is turned on, the voltage IN the high level state at the first collecting node Z1 is written into the first pull-up node PU1 through the first anti-leakage transistor T1, and the first pull-up node PU1 is IN the high level state. At this time, the first voltage control transistor K1 is turned on, the first operating voltage VDD at the high level state provided by the first operating voltage terminal is written into the voltage control node OFF through the first voltage control transistor K1, and the voltage at the voltage control node OFF is at the high level state. Since the third transistor M3 is turned on, the high level signal at the control voltage node OFF is written to the second pull-up node PU2 node PU2 through the third transistor M3; that is, the first pull-up node PU1 and the second pull-up node PU2 are both in a high state; meanwhile, the first pull-down node PD1 and the second pull-down node PD2 are both in a low state by the seventeenth transistor M17 through the twenty-fourth transistor M24.

In the display driving output stage t2, since the first pull-up node PU1 and the second pull-up node PU2 are both in a high level state, the thirteenth transistor M13 to the sixteenth transistor M16 are all turned on, the cascade clock signal terminal CLKD and the cascade clock signal terminal CLKD 'respectively write corresponding cascade signals into the cascade signal output terminal CR and the cascade signal output terminal CR', and the first scan clock signal terminal CLKE 'respectively write corresponding signals OUT into the first composite signal output terminal OUT1 and the first composite signal output terminal 1' of the cascade signal output terminal. The coupled signal output terminal CR outputs display cascade pulses, and the first composite signal output terminal OUT1 and the first composite signal output terminal OUT1' sequentially output display driving pulses.

It should be noted that, in the operation sequence shown in fig. 7, the cascade signal output terminal CR is used as the display cascade signal output terminal, and the cascade signal output terminal CR 'is used as the black insertion cascade signal output terminal, so that no pulse is output from the cascade signal output terminal CR' in the display drive output stage t 2.

In the display reset period t3, the display reset signal provided by the display reset signal input RST is in a high level state, the second transistor M2 and the fourth transistor M4 are both turned on, and a low level signal (specifically, the second operating voltage VGL1 provided by the second operating voltage terminal) is written into the first pull-up node PU1 and the second pull-up node PU 2; meanwhile, under the action of the seventeenth transistor M17 to the twenty-fourth transistor M24, the first pull-down node PD1 and the second pull-down node PD2 are both in a high level state, and the twenty-seventh transistor M27 to the thirty-third transistor M30 are all turned on, so that the resetting and noise reduction of the cascade signal output end CR, the cascade signal output end CR ', the first composite signal output end OUT1 and the first composite signal output end OUT1' are realized.

It should be noted that, in the display reset phase T3, since the first pull-up node PU1 is in a low state, the first voltage control transistor K1 is turned OFF, and the voltage control node OFF is in a floating state, the first anti-leakage transistor T1 is equivalent to a large resistor, and the voltage at the voltage control node OFF and the voltage at the first collection node Z1 are pulled down to a low state.

IN the black insertion precharging stage t4, the display cascade signal provided by the black insertion cascade signal input terminal IN2 is at a high level state, the first control clock signal provided by the first control clock signal terminal BCK1 is at a high level state, the fifth transistor M5 is turned on, and the black insertion cascade signal IN the high level state is written into the black insertion control node H. The black insertion control node H maintains a high state by the first capacitor C1.

In the black insertion writing period t5, since the black insertion control node H maintains the high state, the sixth transistor M6 is turned on; meanwhile, the second control clock signal provided by the second control clock signal terminal BCK2 is in a high level state, the seventh transistor M7 and the eighth transistor M8 are turned on, the second control clock signal in the high level state is written to the first collection node Z1 through the sixth transistor M6 and the seventh transistor M7, the first leakage prevention transistor T1 is turned on, and the voltage in the high level state at the first collection node Z1 is written to the first pull-up node PU1 through the first leakage prevention transistor T1; at this time, the first voltage control transistor K1 is turned on, the first operating voltage VDD at the high level state provided by the first operating voltage terminal is written into the voltage control node OFF through the first voltage control transistor K1, and the voltage at the voltage control node OFF is at the high level state. Since the eighth transistor M3 is turned on, the high level signal at the voltage control node OFF is written to the second pull-up node PU2 node PU2 through the eighth transistor M8; that is, the first pull-up node PU1 and the second pull-up node PU2 are both in a high state; under the action of the seventeenth to twenty-fourth transistors M17 to M24, the first pull-down node PD1 and the second pull-down node PD2 are both in a low state.

In the black insertion driving output stage t6, since the first pull-up node PU1 and the second pull-up node PU2 are both in a high level state, the thirteenth transistor M13 to the sixteenth transistor M16 are all turned on, the cascade clock signal terminal CLKD and the cascade clock signal terminal CLKD 'respectively write corresponding cascade signals into the cascade signal output terminal CR and the cascade signal output terminal CR', and the first scan clock signal terminal CLKE 'respectively write corresponding signals into the first composite signal output terminal OUT1 and the first composite signal output terminal 1' of the cascade signal output terminal. The joint signal output terminal CR 'outputs a black insertion cascade pulse, and the first composite signal output terminal OUT1 and the first composite signal output terminal OUT1' simultaneously output a black insertion driving pulse.

It should be noted that, in the operation sequence shown in fig. 8, the cascade signal output terminal CR is used as the display cascade signal output terminal, and the cascade signal output terminal CR' is used as the black insertion cascade signal output terminal, so that no pulse is output from the cascade signal output terminal CR in the black insertion drive output stage t 6.

In the black insertion reset period t7, since the black insertion control node H maintains a high level state, both the ninth transistor M9 and the eleventh transistor M11 are turned on, the black insertion global reset signal provided by the black insertion global reset signal input terminal BTRST is in a high level state, both the tenth transistor M10 and the twelfth transistor M12 are turned on, the second operating voltage VGL2 in a low level state is written to the first pull-up node PU1 through the tenth transistor M10 and the ninth transistor M9, and the second operating voltage VGL2 in a low level state is written to the second pull-up node PU2 through the twelfth transistor M12 and the eleventh transistor M11. Meanwhile, under the action of the seventeenth transistor M17 to the twenty-fourth transistor M24, the first pull-down node PD1 and the second pull-down node PD2 are both in a high level state, and the twenty-seventh transistor M27 to the thirty-third transistor M30 are all turned on, so that the resetting and noise reduction of the cascade signal output end CR, the cascade signal output end CR ', the first composite signal output end OUT1 and the first composite signal output end OUT1' are realized.

It should be noted that, in the black insertion reset phase T7, since the first pull-up node PU1 is in a low state, the first voltage control transistor K1 is turned OFF, and at this time, the voltage control node OFF is in a floating state, the first anti-leakage transistor T1 is equivalent to a large resistor, and the voltage at the voltage control node OFF and the voltage at the first collection node Z1 are pulled down to a low state.

In a certain period of time thereafter, the first control clock signal is in a high state and the black insertion cascade input signal terminal is in a low state, and the voltage at the black insertion control node H is pulled down to the low state.

In the embodiment of the present disclosure, since the voltage at the control voltage node OFF is in the inactive level state in both the display reset period t3 and the black insertion reset period t7, the first pull-up node PU1 and the second pull-up node PU2 may be reset by the voltage at the control voltage node OFF.

Fig. 8 is another timing chart of the operation of the shift register unit shown in fig. 6 during the display driving and the black insertion driving. As shown in fig. 8, in the operation timing shown in fig. 8, the cascade signal output terminal CR serves as a black insertion cascade signal output terminal, and the cascade signal output terminal CR' serves as a display cascade signal output terminal. Therefore, in the display driving output stage t2, the cascade signal output terminal CR outputs no pulse and the cascade signal output terminal CR' outputs a display cascade pulse; in the black insertion driving output stage t6, the cascade signal output terminal CR' outputs no pulse and the cascade signal output terminal CR outputs a black insertion cascade pulse.

It should be noted that, the process of the shift register unit shown in fig. 6 performing the operation by using the operation timing sequence shown in fig. 8 can refer to the corresponding description of fig. 7, and is not repeated here.

It should be noted that, the specific circuit structures of the first display input sub-circuit 111, the first display reset sub-circuit 112, the second display input sub-circuit 121, the second display reset sub-circuit 122, the first black insertion input sub-circuit 211, the second black insertion input sub-circuit 221, the first black insertion reset sub-circuit 212, the second black insertion reset sub-circuit 222, the first output sub-circuit, the inverter circuit 6, the feedback circuit 7, the voltage control circuit 4, and the first anti-leakage circuit 3 shown in fig. 6 only serve an exemplary function, and do not limit the technical solution of the present disclosure.

Fig. 9 is a schematic diagram illustrating a circuit result of another shift register according to an embodiment of the present disclosure. As shown in fig. 9, unlike in the previous embodiment, the shift register shown in fig. 9 further includes a second output circuit 8; the second output sub-circuit is coupled to the first pull-up node PU1, the second pull-up node PU2, the two second scan clock signal terminals CLKF, CLKF ' and the two second composite signal output terminals OUT2, OUT2', and the second output circuit 8 is configured to write the second scan clock signal provided by one second scan clock signal terminal CLKF to one second composite signal output terminal CLKF under the control of the voltage at the first pull-up node PU1, and write the second scan clock signal provided by the other second scan clock signal terminal CLKF to the other second composite signal output terminal OUT2' under the control of the voltage at the second pull-up node PU 2.

In the display region, the second gate line G2 extends into the peripheral region and is coupled to the corresponding second composite signal output terminals OUT2, OUT2', and a different second gate line G2 is coupled to a different second composite signal output terminal.

In some embodiments, the second output sub-circuit includes thirty-first through thirty-fourth transistors M31 through M34, a fourth capacitor C4, and a fifth capacitor C5.

A control electrode of the thirty-first transistor M31 is coupled to the first pull-up node PU1, a first electrode of the thirty-first transistor M31 is coupled to a second scan clock signal terminal CLKF, and a second electrode of the thirty-first transistor M31 is coupled to a second composite signal output terminal OUT 2.

A control electrode of the thirty-second transistor M32 is coupled to the second pull-up node PU2, a first electrode of the thirty-second transistor M32 is coupled to another second scan clock signal terminal CLKF ', and a second electrode of the thirty-second transistor M32 is coupled to a second composite signal output terminal OUT 2'.

A control electrode of the thirty-third transistor M33 is coupled to the first pull-down node PD1, a first electrode of the thirty-third transistor M33 is coupled to the second composite signal output terminal OUT2, and a second electrode of the thirty-third transistor M33 is coupled to the third operating voltage terminal.

A control electrode of the thirty-fourth transistor M34 is coupled to the second pull-down node PD2, a first electrode of the thirty-fourth transistor M34 is coupled to the second composite signal output terminal OUT2', and a second electrode of the thirty-fourth transistor M34 is coupled to the third operating voltage terminal.

Fig. 10 is a schematic circuit structure diagram of another shift register unit according to an embodiment of the present disclosure, and fig. 11 is a schematic circuit structure diagram of another shift register unit according to an embodiment of the present disclosure. As shown in fig. 10 and 11, in some embodiments, the shift register unit further comprises: a sensing input circuit; wherein the sensing input circuit comprises: a first sense input sub-circuit 911, the first sense input sub-circuit 911 being coupled to the first aggregation node Z1, the sense cascade signal input terminal, the random sense signal terminal OE, and the sense control signal terminal CLKA, the first sense input sub-circuit 911 being configured to write the sense cascade signal provided by the sense cascade signal input terminal to the sense control node under control of the random sense signal provided by the random sense signal terminal OE, and to write the active level signal to the first aggregation node Z1 under control of the voltage at the sense control node and the sense control signal provided by the sense control signal terminal CLKA.

In the embodiment of the present disclosure, the first sensing input sub-circuit 911 is connected to the first collection node Z1 and writes an active level signal to the first pull-up node PU1 through the first leakage prevention circuit 3. As can be seen from the foregoing description of the "first leakage prevention circuit 3", the first leakage prevention circuit 3 may also function to prevent the first pull-up node PU1 from leaking through the first sensing input sub-circuit 911.

In the implementation of the present disclosure, the first display input sub-circuit 111, the first black insertion input sub-circuit 211, and the first sensing input sub-circuit 911 share the same first anti-leakage circuit 3, which is beneficial to reducing the complexity of the shift register unit and reducing the number of transistors required to be disposed in the shift register unit.

In some embodiments, the sense input circuit further comprises: a second sense input circuit connected to the sense control signal terminal CLKA, the voltage control node OFF, and the second pull-up node PU2, the second sense input circuit configured to write the voltage at the voltage control node OFF to the second pull-up node PU2 under the control of the sense control signal provided by the sense control signal terminal CLKA.

In some embodiments, the shift register cell further comprises: a sensing reset circuit, the sensing reset circuit comprising: a first sensing reset sub-circuit 912 and a second sensing reset sub-circuit 922.

The first sensing reset sub-circuit 912 is coupled to the first pull-up node PU1 and the preset sensing reset control signal input terminal, and the first sensing reset sub-circuit 912 is configured to write the inactive level signal to the first pull-up node PU1 under the control of a preset sensing reset control signal provided by the preset sensing reset control signal input terminal.

The second sensing reset sub-circuit 922 is coupled to the second pull-up node PU2 and the preset sensing reset control signal input terminal, and the second sensing reset sub-circuit 922 is configured to write the inactive level signal to the second pull-up node PU2 under the control of a preset sensing reset control signal provided by the preset sensing reset control signal input terminal.

Referring to fig. 10, in some embodiments, the preset sensing reset control signal input terminal is a sensing global reset signal input terminal TRST, and the preset sensing reset control signal is a sensing global reset signal.

Referring to fig. 11, in some embodiments, the preset sensing reset control signal input terminals are a random sensing signal terminal OE and a sensing control signal terminal CLKA, and the preset sensing reset control signal is a random sensing signal and a sensing control signal. In the case shown in fig. 11, the existing random sense signal terminal OE and the sense control signal terminal CLKA are used to control the sensing global reset, which can effectively reduce the signal terminal types required to be configured for the shift register unit and is beneficial to reducing the wiring.

Referring to fig. 10 and 11, in some embodiments, the first sensing input sub-circuit 911 includes thirty-fifth transistors M35 through thirty-seventh transistors M37, and the second sensing input sub-circuit 921 includes thirty-eighth transistors.

A control electrode of the thirty-fifth transistor M35 is coupled to the random sensing signal terminal OE, a first electrode of the thirty-fifth transistor M35 is coupled to the sensing cascade signal input terminal IN3, and a second electrode of the thirty-fifth transistor M35 is coupled to the sensing control node Q.

A control electrode of the thirty-sixth transistor M36 is coupled to the sensing control node Q, a first electrode of the thirty-sixth transistor M36 is coupled to the sensing control signal terminal CLKA, and a second electrode of the thirty-sixth transistor M36 is coupled to a first electrode of the thirty-seventh transistor M37.

A control electrode of the thirty-seventh transistor M37 is coupled to the sensing control signal terminal CLKA, and a second electrode of the thirty-seventh transistor M37 is coupled to the first aggregation node Z1.

A control electrode of the thirty-eighth transistor M38 is coupled to the sensing control signal terminal CLKA, a first electrode of the thirty-eighth transistor M38 is connected to the voltage control node OFF, and a second electrode of the thirty-eighth transistor M38 is connected to the second pull-up node PU 2.

Referring to fig. 10, the preset sensing reset control signal input terminal is a sensing global reset signal input terminal TRST; in some embodiments, the first sensing reset sub-circuit 912 includes a thirty-ninth transistor M39 and the second sensing reset sub-circuit 922 includes a forty-th transistor M40.

A control electrode of the thirty-ninth transistor M39 is connected to the sensing global reset signal input terminal TRST, a first electrode of the thirty-ninth transistor M39 is connected to the first pull-up node PU1, and a second electrode of the thirty-ninth transistor M39 is connected to the second operating voltage terminal.

A control electrode of the fortieth transistor M40 is connected to the sensing global reset signal input terminal TRST, a first electrode of the fortieth transistor M40 is connected to the second pull-up node PU2, and a second electrode of the fortieth transistor M40 is connected to the second operating voltage terminal.

Referring to fig. 11, the preset sensing reset control signal input terminals are a random sensing signal terminal OE and a sensing control signal terminal CLKA; in some embodiments, the first sensing reset sub-circuit 912 includes a first sensing reset transistor and a second sensing reset transistor, and the second sensing reset sub-circuit 922 includes a third sensing reset transistor and a fourth sensing reset transistor. The first sensing reset transistor is the forty-first transistor M41 in fig. 11, the second sensing reset transistor is the forty-second transistor M42 in fig. 11, the third sensing reset transistor is the forty-third transistor M43 in fig. 11, and the fourth sensing reset transistor is the forty-fourth transistor M44 in fig. 11.

The gate of the forty-first transistor M41 is connected to the random sensing signal terminal OE, the first gate of the forty-first transistor M41 is connected to the first pull-up node PU1, and the second gate of the forty-first transistor M41 is connected to the first gate of the forty-second transistor M42.

A control electrode of the forty-second transistor M42 is connected to the sensing control signal terminal CLKA, and a second electrode of the forty-second transistor M42 is connected to the second operating voltage terminal.

A control electrode of the forty-third transistor M43 is connected to the random sensing signal terminal OE, a first electrode of the forty-third transistor M43 is connected to the second pull-up node PU2, and a second electrode of the forty-third transistor M43 is connected to a first electrode of the forty-fourth transistor M44.

A gate of the forty-fourth transistor M44 is coupled to the sensing control signal terminal CLKA, and a second gate of the forty-fourth transistor M44 is coupled to the second operating voltage terminal.

Fig. 12 is a schematic circuit structure diagram of another shift register unit according to an embodiment of the present disclosure. As shown in fig. 12, in some embodiments, the first display reset sub-circuit 112 is further coupled to the second aggregation node Z2, and the first display reset circuit is specifically configured to write the inactive level signal at the second aggregation node Z2 to the first pull-up node PU1 under the control of a display reset signal provided by a display reset signal input RST; the first black insertion reset sub-circuit 212 is further coupled to the second aggregation node Z2, and the first black insertion reset sub-circuit 212 is specifically configured to write the inactive level signal at the second aggregation node Z2 to the first pull-up node PU1 under the control of the black insertion global reset signal provided by the black insertion global reset input BTRST and the voltage at the black insertion control node H; wherein the second aggregation node Z2 is coupled to the control voltage node OFF.

The shift register unit further includes: a second anticreeping circuit 10; the second leakage prevention circuit 10 is coupled to the second collecting node Z2, the voltage control circuit 4 and the second operating voltage terminal, and is configured to write the second operating voltage in the inactive level state provided by the second operating voltage terminal to the second collecting node Z2 when the first operating voltage is not written to the voltage control node OFF by the voltage control circuit 4.

In the present embodiment, the second leakage-preventing circuit 10 is configured for the first display reset sub-circuit 112 and the first black insertion reset sub-circuit 212; when the shift register unit outputs the display driving pulse and the black insertion driving pulse through the first composite signal output end, the first pull-up node PU1 is in an active level state; in response to the control of the first pull-up node PU1, the voltage control circuit 4 continuously writes the first operation voltage in an active level state to the voltage control node OFF and the second accumulation node Z2 connected to the voltage control node OFF. Since the voltage control circuit 4 continuously charges the second aggregation node Z2 to maintain the second aggregation node Z2 at the active level state, the first pull-up node PU1 can be effectively prevented from leaking through the first display reset sub-circuit 112 and the first black insertion reset sub-circuit 212. Meanwhile, since the first display reset sub-circuit 112 and the first black insertion reset sub-circuit 212 share the same second anti-leakage circuit 10, the number of anti-leakage circuits can be effectively reduced, which is beneficial to reducing the complexity of the shift register unit and reducing the number of transistors required to be arranged in the shift register unit.

In some embodiments, when the first sensing reset sub-circuit 912 is present within the shift register cell, the first sensing reset sub-circuit 912 is coupled to the first pull-up node PU1, the preset sensing reset control signal input, and the second aggregation node Z2, and the first sensing reset sub-circuit 912 is configured to write the inactive level signal at the second aggregation node Z2 to the first pull-up node PU1 under the control of a preset sensing reset control signal provided at the preset sensing reset control signal input. That is, the first display reset sub-circuit 112, the first black insertion reset sub-circuit 212, and the first sensing reset sub-circuit 912 share the same second leakage prevention circuit 10.

In some embodiments, the second leakage preventing circuit 10 includes a second leakage preventing transistor T2; the control electrode of the second anticreeping transistor T2 is coupled to the second collecting node Z2, the first electrode of the second anticreeping transistor T2 is coupled to the second collecting node Z2, and the second electrode of the second anticreeping transistor T2 is coupled to the second operating voltage terminal.

When the first pull-up node PU1 is in the active level state, the voltage control circuit 4 writes the first operating voltage in the active level state to the voltage control node OFF, and the voltage at the second accumulation node Z2 is also in the active level state. When the first pull-up node PU1 is in the inactive level state, the voltage control circuit 4 stops working (i.e. the voltage control circuit 4 does not write the first working voltage into the voltage control node OFF), and the voltage control node OFF can be discharged through the first anti-leakage transistor T1 and the second anti-leakage transistor T2, so that the voltage at the voltage control node OFF is in the inactive level state.

Fig. 13 is a schematic circuit structure diagram of another shift register unit according to an embodiment of the present disclosure. As shown in fig. 13, in some embodiments, the second display reset subcircuit 122 is coupled to the second pull-up node PU2 and the third aggregation node Z3, the second display reset subcircuit being specifically configured to write the inactive level signal at the third aggregation node Z3 to the second pull-up node PU2 under control of a display reset signal provided by a display reset signal input RST; the second black insertion reset sub-circuit 222 is coupled to the second pull-up node PU2 and the third aggregation node Z3, and the second black insertion reset sub-circuit 222 is specifically configured to write the inactive level signal at the third aggregation node Z3 to the second pull-up node PU2 under the control of the black insertion global reset signal provided by the black insertion global reset input BTRST and the voltage at the black insertion control node H; wherein the third collecting node Z3 is coupled to the voltage control node OFF.

The shift register unit further includes: and a third leakage prevention circuit 11, coupled to the third collecting node Z3, the voltage control circuit 4 and the second operating voltage terminal, configured to write the second operating voltage in the inactive level state provided by the second operating voltage terminal to the third collecting node Z3 when the first operating voltage is not written to the voltage control node OFF by the voltage control circuit 4.

In the present embodiment, the third leakage prevention circuit 11 is configured for the second display reset sub-circuit 122 and the second black insertion reset sub-circuit 222; when the shift register unit outputs the display driving pulse and the black insertion driving pulse through the first composite signal output end, the first pull-up node PU1 and the second pull-up node PU2 are in an active level state; in response to the control of the first pull-up node PU1, the voltage control circuit 4 continuously writes the first operation voltage in an active level state to the voltage control node OFF and the third collecting node Z3 connected to the voltage control node OFF. Since the voltage control circuit 4 continuously charges the third collecting node Z3 to maintain the third collecting node Z3 in the active level state, the second pull-up node PU2 can be effectively prevented from leaking electricity through the second display reset sub-circuit 122 and the second black insertion reset sub-circuit 222. Meanwhile, since the second display reset sub-circuit 122 and the second black insertion reset sub-circuit 222 share the same third leakage prevention circuit 11, the number of leakage prevention circuits can be effectively reduced, which is beneficial to reducing the complexity of the shift register unit and reducing the number of transistors required to be arranged in the shift register unit.

In some embodiments, when the second sensing reset sub-circuit 922 is present in the shift register unit, the second sensing reset sub-circuit 922 is coupled to the second pull-up node PU2, the preset sensing reset control signal input terminal, and the third aggregation node Z3, and the second sensing reset sub-circuit 922 is configured to write the inactive level signal at the third aggregation node Z3 to the second pull-up node PU2 under the control of the preset sensing reset control signal provided at the preset sensing reset control signal input terminal. That is, the second display reset sub-circuit 122, the second black insertion reset sub-circuit 222, and the second sensing reset sub-circuit 922 share the same third leakage prevention circuit 11.

In some embodiments, the third leakage prevention circuit 11 includes a third leakage prevention transistor T3; the control electrode of the third leakage prevention transistor T3 is coupled to the third collecting node Z3, the first electrode of the third leakage prevention transistor T3 is coupled to the third collecting node Z3, and the second electrode of the second leakage prevention transistor T2 is coupled to the second operating voltage terminal.

When the first pull-up node PU1 is in the active level state, the voltage control circuit 4 writes the first operating voltage in the active level state to the voltage control node OFF, and the voltage at the third collecting node Z3 is also in the active level state. When the first pull-up node PU1 is in the inactive level state, the voltage control circuit 4 stops working (i.e. the voltage control circuit 4 does not write the first working voltage into the voltage control node OFF), and at this time, the voltage control node OFF can be discharged through the first leakage prevention transistor T1 and the third leakage prevention transistor T3, so that the voltage at the voltage control node OFF is in the inactive level state.

It should be noted that fig. 13 exemplifies a case where the shift register unit may include both the second leakage prevention circuit 10 and the third leakage prevention circuit 11; it should be understood by those skilled in the art that the case where the third leakage prevention circuit 11 and the second leakage prevention circuit 10 are included in the shift register unit also falls within the protection scope of the present disclosure.

Fig. 14 is a schematic circuit structure diagram of another shift register unit according to an embodiment of the present disclosure. As shown IN fig. 14, IN some embodiments, IN order to enhance the display input capability IN the shift register unit, a display auxiliary input circuit 12 is added IN the shift register unit, the display auxiliary input circuit 12 is coupled to the display cascade signal input terminal IN1, the first aggregation node Z1 and the first pull-up node PU1, and the display auxiliary input circuit 12 is configured to write the voltage at the first aggregation node Z1 to the first pull-up node PU1 under the control of the display cascade signal provided by the display cascade signal input terminal IN 1.

That is to say, when the display cascade signal input terminal IN1 provides the display cascade signal IN the active level state, the signal IN the active level state at the first aggregation node Z1 can be written into the first pull-up node PU1 not only through the first anti-leakage circuit 3, but also through the display auxiliary input circuit 12 into the first pull-up node PU1, so as to increase the speed of writing the active level signal into the first pull-up node PU1, that is, the display input capability of the shift register unit is improved.

In some embodiments, the display auxiliary input circuit 12 includes: an auxiliary input transistor M0; a control electrode of the auxiliary input transistor M0 is coupled to the display cascade signal input IN1, a first electrode of the auxiliary input transistor M0 is coupled to the first collection node Z1, and a second electrode of the auxiliary input transistor M0 is coupled to the first pull-up node PU 1.

When the display cascade signal provided by the display cascade signal input terminal IN1 is IN an active level state, the auxiliary input transistor M0 is turned on; when the display cascade signal provided from the display cascade signal input terminal IN1 is IN an active level state, the auxiliary input transistor M0 is turned off.

Fig. 15 is a schematic circuit structure diagram of another shift register unit according to an embodiment of the present disclosure. As shown in fig. 15, in some embodiments, the shift register unit further comprises: at least one of the first pull-down control circuit 21, the second pull-down control circuit 22 and the third pull-down control circuit 23. Note that fig. 15 illustrates a case where the shift register unit includes the first pull-down control circuit 21, the second pull-down control circuit 22, and the third pull-down control circuit 23 at the same time.

Wherein the first pull-down control circuit 21 is coupled to the display cascade signal input terminal IN1, the first pull-down node PD1, the second pull-down node PD2 and the second operation voltage terminal, and the first pull-down control circuit 21 is configured to write the second operation voltage provided by the second operation voltage terminal to the first pull-down node PD1 under the control of the display cascade signal provided by the display cascade signal input terminal IN 1. That is, while the first display input sub-circuit 111 writes the active level signal to the first collection node Z1, the first pull-down control circuit 21 may synchronously write the inactive level signal to the first pull-down node PD1, so that the voltage at the first pull-down node PD1 can quickly reach the inactive level state.

The second pull-down control circuit 22 is coupled to the black insertion control node H, the second control clock signal terminal BCK2, the first pull-down node PD1, and the second operating voltage terminal, and the second pull-down control circuit 22 is configured to write the second operating voltage provided by the second operating voltage terminal to the first pull-down node PD1 under the control of the voltage at the black insertion control node H and the second control clock signal provided by the second control clock signal terminal BCK 2. That is, while the first black insertion input sub-circuit 211 writes the active level signal to the first aggregation node Z1, the second pull-down control circuit 22 may synchronously write the inactive level signal to the first pull-down node PD1, so that the voltage at the first pull-down node PD1 can quickly reach the inactive level state.

The third pull-down control circuit 23 is coupled to the sensing control signal terminal CLKA, the sensing control node Q, the first pull-down node PD1, and the second operating voltage terminal, and the third pull-down control circuit 23 is configured to write the second operating voltage provided by the second operating voltage terminal to the first pull-down node PD1 under the control of the voltage at the sensing control Q node and the sensing control signal provided by the sensing control signal terminal CLKA. That is, while the first sense input sub-circuit 911 writes the active level signal to the first collection node Z1, the third pull-down control circuit 23 may synchronously write the inactive level signal to the first pull-down node PD1, so that the voltage at the first pull-down node PD1 can quickly reach the inactive level state.

In some embodiments, the first pull-down control circuit 21 includes a fifty-th transistor M50, the second pull-down control circuit 22 includes a fifty-first transistor M51 and a fifty-second transistor M52, and the third pull-down control circuit 23 includes a fifty-third transistor M53 and a fifty-fourth transistor M54.

A control electrode of the fifty-fifth transistor M50 is connected to the display cascade signal input terminal IN1, a first electrode of the fifty-fifth transistor M50 is connected to the first pull-down node PD1, and a second electrode of the fifty-fifth transistor M50 is connected to the second operating voltage terminal.

A control electrode of the fifty-first transistor M51 is connected to the black insertion control node H, a first electrode of the fifty-first transistor M51 is connected to the first pull-down node PD1, and a second electrode of the fifty-first transistor M51 is connected to a first electrode of the fifty-second transistor M52.

A control electrode of the fifty-second transistor M52 is connected to the second control clock signal terminal BCK2, and a second electrode of the fifty-second transistor M52 is connected to the second operating voltage terminal.

A control electrode of the fifty-third transistor M53 is connected to the sensing control node Q, a first electrode of the fifty-third transistor M53 is connected to the first pull-down node PD1, and a second electrode of the fifty-third transistor M53 is connected to a first electrode of the fifty-fourth transistor M54.

A control electrode of the fifty-fourth transistor M54 is coupled to the sense control signal terminal CLKA, and a second electrode of the fifty-fourth transistor M54 is coupled to the second operating voltage terminal.

It should be noted that, the case where the first pull-down control circuit 21 includes the fifty-th transistor M50, the second pull-down control circuit 22 includes the fifty-first transistor M51 and the fifty-second transistor M52, and the third pull-down control circuit 23 includes the fifty-third transistor M53 and the fifty-fourth transistor M54 only serves as an exemplary function, which does not limit the technical solution of the present disclosure, and the functional circuits may also adopt other circuit structures capable of realizing corresponding functions, which is not limited by the technical solution of the present disclosure.

In the above embodiments, the parts of different functional circuits may be combined with each other, and the technical solutions obtained by the combination shall also belong to the scope of the present disclosure.

Based on the same inventive concept, the embodiment of the present disclosure further provides a gate driving circuit, where the gate driving circuit includes a plurality of cascaded shift register units, and the shift register unit provided in the foregoing embodiment can be used as the shift register unit.

In the shift register units shown in fig. 6 and 9 to 15, the (a) part and the (b) part can be regarded as one stage of shift register circuit (the one stage of shift register unit includes two stages of shift register circuits), respectively, where the one stage of shift register circuit corresponds to one row of pixel units in the display area. When the M shift register units are sequentially arranged to form a gate driving circuit, the gate driving circuit can be regarded as including 2M cascaded shift register circuits, and the gate driving circuit can be used for driving M rows of pixel units in the display area. In fig. 6 and 9 to 15, (a) the shift register circuits corresponding to the part are shift register circuits located at odd-numbered stages in the gate driver circuit, and (b) the shift register circuits corresponding to the part are shift register circuits located at even-numbered stages in the gate driver circuit; (a) the shift register circuit corresponding to part corresponds to the pixel units positioned in the odd-numbered rows in the display area, and the shift register circuit corresponding to part (b) corresponds to the pixel units positioned in the even-numbered rows in the display area.

Further, in the gate driver circuit, the shift register circuits located at odd-numbered stages (i.e., the shift register circuits corresponding to the part (a)) are used for implementing display driving cascade, and the shift register circuits located at even-numbered stages (i.e., the shift register circuits corresponding to the part (b)) are used for implementing black insertion driving cascade; or, the shift register circuits at the odd-numbered stages are used for realizing the black insertion driving cascade, and the shift register circuits at the even-numbered stages are used for realizing the display driving cascade. In practical application, the design can be carried out according to actual needs.

IN some embodiments, the display cascade signal input terminal IN1 of the M-th stage shift register unit is coupled to the display cascade signal output terminal of the M-a stage shift register unit, the display reset signal input terminal RST of the M-th stage shift register unit is coupled to the display cascade signal output terminal of the M + b stage shift register unit, the black insertion cascade signal input terminal IN2 of the M-th stage shift register unit is coupled to the black insertion cascade signal output terminal of the M-c stage shift register unit, a, b, and c are respectively preset positive integers, a + b is less than or equal to c, and M is a positive integer and satisfies a < M, c < M, and M + b is less than or equal to M. The display cascade signal input terminals IN1 of the first a-stage shift register units SRU 1-SRUa are coupled to the display frame start signal input terminal (for providing the display frame start signal STV), the display reset signal input terminals RST of the second b-stage shift register units SRUM-b + 1-SRUM are coupled to the display frame reset signal input terminal (for providing the display frame reset signal), and the black insertion cascade signal input terminals IN2 of the first c-stage shift register units SRU 1-SRUc are coupled to the black insertion frame start signal input terminal (for providing the black insertion frame start signal BSTV).

Fig. 16 is a circuit structure diagram of a gate driving circuit according to an embodiment of the present disclosure, fig. 17 is a circuit structure diagram of a first shift register unit group according to an embodiment of the present disclosure, and fig. 18 is a circuit structure diagram of a second shift register unit group according to an embodiment of the present disclosure. As shown in fig. 16 to 18, the gate driving circuit is provided with 4 control clock signal lines BK1 to BK4, the M shift register units are divided into a plurality of first shift register unit groups a and a plurality of second shift register unit groups B, and the number of shift register units in the first shift register unit group a and the number of shift registers in the second shift register unit group B are both c.

In some embodiments, c has a value of 4. The values of a and b are as follows: 1) a takes the value 1 and b takes the value 1; 2) a takes the value 1 and b takes the value 2; 3) a takes the value 1 and b takes the value 3; 4) a takes the value of 2 and b takes the value of 1; 5) a takes the value of 2 and b takes the value of 2; 6) a takes the value 3 and b takes the value 1. The values of a and b determine the cascade relation among the shift register units in the driving process.

The gate driving circuit is provided with 4c first scan clock signal lines CKE 1-CKE 16, the 4c first scan clock signal lines CKE 1-CKE 16 are divided into a first signal line group (including the first scan clock signal lines CKE 1-CKE 8) and a second signal line group (including the first scan clock signal lines CKE 9-CKE 16), and the number of the first scan clock signal lines CKE 1-CKE 8 in the first signal line group and the number of the first scan clock signal lines CKE 9-CKE 16 in the second signal line group are both 2 c; two first scan clock signal terminals CLKE, CLKE 'of the i-th shift register unit in the first shift register unit group a are coupled with the 2i-1 st and 2 i-th first scan clock signal lines in the first signal line group, respectively, and two first scan clock signal terminals CLKE, CLKE' of the i-th shift register unit in the second shift register unit group B are coupled with the 2i-1 st and 2 i-th first scan clock signal lines in the second signal line group, respectively.

The gate driving circuit is provided with 4c cascade clock signal lines CKD 1-CKE 16, the 4c cascade clock signal lines are divided into a fourth signal line group (comprising cascade clock signal lines CKD 1-CKD 8) and a fifth signal line group (comprising cascade clock signal lines CKD 9-CKD 16), the number of the cascade clock signal lines CKD 1-CKD 8 in the fourth signal line group and the number of the cascade clock signal lines CKD 9-CKD 16 in the fifth signal line group are both 2 c; two cascade clock signal ends CLKD and CLKD' of the ith shift register unit in the first shift register unit group are respectively coupled with the 2i-1 th cascade clock signal line and the 2i th cascade clock signal line in the fourth signal line group; two cascade clock signal terminals CLKD and CLKD' of the ith shift register unit in the second shift register unit group are respectively coupled with the 2i-1 th cascade clock signal line and the 2i th cascade clock signal line in the fifth signal line group. Wherein i is a positive integer and i is less than or equal to c.

Referring to fig. 16, among the plurality of first shift register unit groups a and the plurality of second shift register unit groups B, one first shift register unit group a and one second shift register unit group B are alternately arranged in sequence. In the first shift register unit group a, the first control clock signal terminal BCK1 of the shift register unit is connected to the control clock signal line BK1, and the second control clock signal terminal BCK2 of the shift register unit is connected to the control clock signal line BK 2. In the second shift register unit group B, the first control clock signal terminal BCK1 of the shift register unit is connected to a control clock signal line BK3, and the second control clock signal terminal BCK2 of the shift register unit is connected to a control clock signal line BK 4.

Fig. 19 is a schematic circuit structure diagram of another gate driving circuit according to an embodiment of the disclosure. As shown in fig. 19, unlike the case where one first shift register cell group a and one second shift register cell group B are alternately arranged in this order as shown in fig. 16, two first shift register cell groups a1, a2 and two second shift register cell groups B1, B2 are alternately arranged in this order as shown in fig. 17.

In the case shown in fig. 19, the connection between the shift register cells in the first shift register cell group a1, a2 and the second shift register cell group B1, B2 and the first scan clock signal lines CKE1 to CKE16 and the cascade clock signal lines CKD1 to CKD16 can be seen in fig. 17 and 18.

In the case shown in fig. 19, in the first shift register cell group a1 located at an odd-numbered order, the first control clock signal terminal BCK1 of the shift register cell is connected to the control clock signal line BK1, and the second control clock signal terminal BCK2 of the shift register cell is connected to the control clock signal line BK 2. In the even-numbered first shift register cell group a2, the first control clock signal terminal BCK1 of the shift register cell is connected to the control clock signal line BK3, and the second control clock signal terminal BCK2 of the shift register cell is connected to the control clock signal line BK 4. In the second shift register cell group B1 located at the odd-numbered order, the first control clock signal terminal BCK1 of the shift register cell is connected to the control clock signal line BK1, and the second control clock signal terminal BCK2 of the shift register cell is connected to the control clock signal line BK 2. In the second shift register cell group B2 located at the even-numbered order, the first control clock signal terminal BCK1 of the shift register cell is connected to the control clock signal line BK3, and the second control clock signal terminal BCK2 of the shift register cell is connected to the control clock signal line BK 4.

Fig. 20 is an operation timing diagram of the gate driving circuit shown in fig. 16, and fig. 21 is an operation timing diagram of the gate driving circuit shown in fig. 19. As shown in fig. 20 and 21, the gate driving circuit alternately performs a display driving period J1 and a black insertion driving period J2 during operation; in addition, the gate driving circuit performs display driving on a certain 8 rows of pixel units in a display driving phase J1, and performs black insertion driving on a certain 8 rows of pixels in a black insertion driving phase J2. The detailed working process is not described herein.

In the embodiment of the present disclosure, the shift register units in the same first/second shift register unit group are simultaneously driven for black insertion, so that the shift register units in the same first/second shift register unit group can share part of the circuits in the first black insertion input sub-circuit 211.

Fig. 22 is a schematic circuit diagram illustrating a circuit structure of the shift register units in the same shift register unit group to implement the sharing of the first black insertion input sub-circuit 211 according to the embodiment of the disclosure. As shown in fig. 22, the first black insertion input sub-circuit 211 includes: the common sub circuit 2111 and a corresponding one of the non-common sub circuits 2112_1, 2112_2, 2112_3, 2112_4 are coupled to the black insertion pull-up node K, and the common sub circuit 2111 and the non-common sub circuits 2112_1, 2112_2, 2112_3, 2112_4 are coupled to the black insertion pull-up node K.

The first black insertion sub-circuits 211 in the shift register units in the same first shift register unit group include the same common sub-circuit 2111, and the first black insertion sub-circuits 211 in the shift register units in the same first shift register unit group include different non-common sub-circuit portions 2112_1, 2112_2, 2112_3, and 2112_ 4.

The first black insertion sub-circuits 211 in the shift register units in the same second shift register unit group include the same common sub-circuit 2111, and the first black insertion sub-circuits 211 in the shift register units in the same second shift register unit group include different non-common sub-circuits 2112_1, 2112_2, 2112_3, and 2112_ 4.

The common part circuit 2111 is coupled to the black insertion cascade signal input terminal IN2 and the first control clock signal terminal BCK1, and the common part circuit 2111 is configured to write the black insertion cascade signal provided from the black insertion cascade signal input terminal IN2 to the black insertion control node H under the control of the first control clock signal provided from the first control clock signal terminal BCK1, and to write an active level signal to the black insertion pull-up node K under the control of the voltage at the black insertion control node H.

The non-shared part circuits 2112_1, 2112_2, 2112_3 and 2112_4, the second control clock signal terminal BCK2 and the first aggregation nodes in the corresponding shift register units are configured to write the voltage at the black inserted pull-up node K to the first aggregation nodes in the corresponding shift register units under the control of the second control clock signal provided by the second control clock signal terminal BCK 2.

In some embodiments, the non-shared portion circuit includes a fifth transistor M5, a sixth transistor M6, and a first capacitor C1, and the non-shared portion circuit includes seventh transistors M7_1, M7_2, M7_3, and M7_ 4. As an example, each shift register unit group includes 4 shift register units, and the first aggregation nodes in the 4 shift register units are respectively denoted as Z1_1, Z1_2, Z1_3, and Z1_4, where the second pole of the seventh transistor M7_1 is connected to the first aggregation node Z1_1, the second pole of the seventh transistor M7_2 is connected to the first aggregation node Z1_2, the second pole of the seventh transistor M7_3 is connected to the first aggregation node Z1_3, and the second pole of the seventh transistor M7_4 is connected to the first aggregation node Z1_ 4. The nodes at the black inserted pull-up node K can be written at the first aggregation nodes Z1_1, Z1_2, Z1_3, and Z1_4 within 4 shift register units, respectively, by the seventh transistors M7_1, M7_2, M7_3, and M7_4 described above.

By sharing part of transistors in the first black insertion input sub-circuit in the shift register unit positioned in the same shift register unit group, the number of transistors in the grid drive circuit can be effectively reduced, so that the occupied area of the grid drive circuit is reduced, and the narrow frame design of a product is facilitated.

Based on the same inventive concept, the disclosed embodiments also provide a display device, which includes the gate driving circuit provided by the previous embodiments.

The display device provided by the embodiment of the disclosure may be: any product or component with a display function, such as a display panel, a flexible wearable device, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, and a navigator. Other essential components of the display device are understood by those skilled in the art, and are not described herein or should not be construed as limiting the invention.

Based on the same inventive concept, the embodiment of the present disclosure further provides a driving method of a shift register unit, wherein the shift register unit adopts the shift register unit provided in the previous embodiment. Fig. 23 is a flowchart of a driving method of a shift register unit according to an embodiment of the present disclosure, and as shown in fig. 23, the driving method includes: a display driving process and a black insertion driving process, wherein the display driving process includes step S101, and the black insertion driving process includes step S201 and step 202.

In step S101, in the display precharge stage, the first display input sub-circuit writes the active level signal into the first collection node under the control of the display cascade signal, and the first leakage prevention circuit writes the voltage at the first collection node into the first pull-up node under the control of the voltage at the first collection node.

In step S201, in the black insertion pre-charging stage, the first black insertion input sub-circuit writes the black insertion cascade signal into the black insertion control node under the control of the first control clock signal.

Step S202, a black insertion writing stage, in which the first black insertion input sub-circuit writes the active level signal to the first aggregation node under the control of the voltage at the black insertion control node and the second control clock signal, and the first leakage prevention circuit writes the voltage at the first aggregation node to the first pull-up node under the control of the voltage at the first aggregation node.

Of course, in some embodiments, the display driving process further includes working steps of a display driving output phase and a display reset phase after step S101, and the black insertion driving process further includes working steps of a black insertion driving output phase and a black insertion reset phase after step S202.

For specific working steps of the shift register unit in the display precharge stage, the display driving output stage, the display reset stage, the black insertion driving output stage, and the black insertion reset stage, reference may be made to corresponding contents in the foregoing embodiments, and details are not described here.

It will be understood that the above embodiments are merely exemplary embodiments taken to illustrate the principles of the present invention, which is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.

Claims

1. A shift register cell, comprising:

2. The shift register cell according to claim 1, wherein the first leakage preventing circuit comprises: a first anticreeping transistor;

3. The shift register cell of claim 1, further comprising:

4. The shift register cell of claim 1, further comprising:

5. The shift register of claim 4, wherein the display auxiliary input circuit comprises: an auxiliary input transistor;

6. The shift register cell of claim 1, further comprising: display reset circuit and black insertion reset circuit, display reset circuit includes: a first display reset sub-circuit and a second display reset sub-circuit, the black insertion reset circuit comprising: a first black insertion reset sub-circuit and a second black insertion reset sub-circuit;

7. The shift register cell of claim 6, wherein the first display reset subcircuit is further coupled to a second aggregation node, the first display reset circuit being specifically configured to write an inactive level signal at the second aggregation node to the first pull-up node under control of a display reset signal provided at the display reset signal input;

the second aggregation node is coupled with the pressure control node;

the shift register unit further includes:

and/or the presence of a gas in the gas,

the third aggregation node is coupled with the voltage control node;

the shift register unit further includes:

8. The shift register cell of claim 7, further comprising:

9. The shift register cell according to claim 7, wherein the second leakage preventing circuit comprises: a second anti-leakage transistor, a control electrode of the second anti-leakage transistor being coupled to the second aggregation node, a first electrode of the second anti-leakage transistor being coupled to the second aggregation node, and a second electrode of the second anti-leakage transistor being coupled to the second operating voltage terminal;

10. The shift register cell of claim 3, further comprising:

11. The shift register cell according to claim 10, wherein the preset sensing reset control signal input terminal is the random sensing signal terminal and the sensing control signal terminal, and the preset sensing reset control signal is the random sensing signal and the sensing control signal;

12. The shift register cell of any one of claims 1 to 11, wherein the display input circuit further comprises: a second display input sub-circuit coupled to the display cascade signal input, the voltage control node, and a second pull-up node, the second display input sub-circuit configured to write a voltage at the voltage control node to the second pull-up node under control of a display cascade signal provided at the display cascade signal input;

the shift register unit further includes:

13. The shift register cell of claim 12, further comprising:

14. The shift register cell of claim 13, wherein the shift register cell further comprises:

15. A gate drive circuit, comprising: a plurality of cascaded shift register cells, said shift register cells employing the shift register cells of any of claims 1-14 above.

16. The gate driving circuit according to claim 15, wherein the gate driving circuit comprises M stages of shift register units, one of the two cascade signal output terminals of each shift register unit is a display cascade signal output terminal, and the other is a black insertion cascade signal output terminal;

17. A gate driver circuit according to claim 16, wherein the shift register cell is the shift register cell of claim 12;

the M shift register units are divided into a plurality of first shift register unit groups and a plurality of second shift register unit groups, and the number of the shift register units in the first shift register unit groups and the number of the shift registers in the second shift register unit groups are both c;

i is a positive integer and i is not more than c;

18. A gate drive circuit as claimed in claim 17, wherein the first black insertion input sub-circuit comprises: a common part circuit and a non-common part circuit, the common part circuit and the non-common part circuit being coupled to a black insertion pull-up node;

19. A gate drive circuit as claimed in any one of claims 15 to 18, wherein c has a value of 4.

20. A display device, comprising: a gate drive circuit as claimed in any one of claims 15 to 19.

21. A driving method applied to the shift register unit according to any one of claims 1 to 14, comprising:

a display driving process comprising:

a black insertion driving process comprising: