KR102009318B1 - Gate driving circuit for organic light emitting display - Google Patents

Abstract

The present invention relates to a gate driving circuit of an organic light emitting display device, comprising: a pull-up transistor supplying a high potential power voltage to an output terminal in response to a voltage of a Q node to charge an output terminal; A pull-down transistor configured to discharge the output terminal by supplying a low potential power voltage to the output terminal in response to a voltage of a QB node; And a switch circuit for supplying the start pulse to the Q node to rise the voltage at the output terminal and polling the voltage at the output terminal in response to the reset pulse. The gate signal output through the output terminal is applied to the gate line of the display panel. The switch circuit includes a first QB node driver configured to charge the QB node with a voltage of the first clock in response to the reset pulse and the first clock.

Description

GATE DRIVING CIRCUIT FOR ORGANIC LIGHT EMITTING DISPLAY}

The present invention relates to a gate driving circuit of an organic light emitting display device.

The organic light emitting display device is a self-light emitting device in which an organic light emitting diode (OLED) is formed for each pixel. Organic Light Emitting Display (LCD) has advantages in that it consumes less power than liquid crystal display (LCD), shows no afterimage, and has a wide viewing angle.

The pixel array of the OLED display includes a plurality of data lines, gate lines orthogonal to the data lines, and pixels arranged in a matrix form. Each of the pixels includes an OLED and a pixel driving circuit for driving the OLED. The pixel driving circuit includes a driving device for adjusting a current supplied to the OLED according to a data voltage, a storage capacitor for maintaining a gate voltage of the driving device, and the like. The pixel driving circuit further includes switch elements for initializing a gate voltage of the driving device, sensing a threshold voltage of the driving device, writing data to the gate of the driving device, and switching a current path between the driving device and the OLED. do. Gate signals for controlling the initialization, sensing, data writing, and light emitting timing of the OLED are supplied to the control terminals (or gates) of the switch elements of the pixel driving circuit through the gate lines. The signal width of the gate control signals may be from one horizontal period to several tens of horizontal periods. Gate signals supplied to one gate line may be continuously supplied as multiple signals, and their signal widths may be different from each other.

The conventional gate driving circuit boosts the voltage of the Q node by supplying a clock signal to the drain of the pull-up transistor while charging the voltage of the Q node controlling the gate of the pull-up transistor. The output voltage was generated by the dynamic control method. In the conventional gate driving circuit, the output voltage is discharged by charging the QB node that controls the gate of the pull-down transistor. When the gate signals supplied to the gate lines overlap, the number of phases of the clock signals supplied to the gate driving circuit must be increased according to the overlapping intervals. This conventional gate driving circuit outputs a gate signal of the same width. Therefore, it is difficult for the conventional gate driving circuit to continuously output multiple signals having different signal widths.

In a conventional gate driving circuit, a layout is determined according to a required gate signal specification. Therefore, when the gate signal specification is changed, the gate driving circuit must be newly designed.

The present invention provides a gate driving circuit of an organic light emitting display device which can output multiple gate signals continuously and easily adjusts the signal width of the gate signals.

The gate driving circuit of the present invention includes a first and a second clock that are generated out of phase with each other, a start pulse synchronized with the first clock, a reset pulse generated after the start pulse and synchronized with the first clock, and a high potential power supply. And a shift register composed of a plurality of stages to which the voltage and the low potential power supply voltage are input and cascaded.

Each of the stages includes: a pull-up transistor configured to charge the output terminal by supplying the high potential power voltage to an output terminal in response to a voltage of a Q node; A pull-down transistor configured to discharge the output terminal by supplying the low potential power voltage to the output terminal in response to a voltage of a QB node; And a switch circuit for supplying the start pulse to the Q node to rise the voltage at the output terminal and polling the voltage at the output terminal in response to the reset pulse.
The gate signal output through the output terminal is applied to the gate line of the display panel.
The switch circuit includes a first QB node driver configured to charge the QB node with a voltage of the first clock in response to the reset pulse and the first clock.

The present invention can easily adjust the signal width of each of the multiple gate signals by adjusting the time difference between the start pulse and the reset pulse. Furthermore, when the gate signal specification is changed, the new gate signal specification can be satisfied by updating only the timing of the start pulse and the reset pulse without redesigning the pixel driving circuit.

1 is a block diagram illustrating an organic light emitting display device according to an exemplary embodiment of the present invention.
FIG. 2 is a diagram illustrating the shift register shown in FIG. 1.
3 is a circuit diagram showing in detail the circuit configuration of the shift register shown in FIG.
4 and 5 are waveform diagrams showing a method of driving a shift register.
6 is a waveform diagram showing another driving method of a shift register.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like numbers refer to like elements throughout. In the following description, when it is determined that a detailed description of known functions or configurations related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

1 and 2, the organic light emitting diode display of the present invention includes a display panel 10 and a display panel driving circuit.

The display panel 10 includes input pixel data including a pixel array in which pixels are formed in a matrix form. Each of the pixels includes an OLED and a pixel driving circuit for driving the OLED. The organic compound layer of the OLED includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (Electron injection) layer, EIL), and the like. When a driving voltage is applied to the anode electrode and the cathode electrode, electrons passing through the hole and the electron injection layer (EIL) and the electron transport layer (ETL) supplied through the hole injection layer (HIL) and the hole transport layer (HTL) are emitted from the emission layer (EML). To form an exciton, which causes the light emitting layer EML to emit visible light. The pixel driving circuit includes a driving device for adjusting a current supplied to the OLED according to a data voltage, a storage capacitor for maintaining a gate voltage of the driving device, an initializing gate voltage of the driving device, and sensing a threshold voltage of the driving device. It includes switch elements that write data to the gate of and switch the current path between the drive element and the OLED. The pixel driving circuit and its driving method can be implemented by any known. For example, the pixel driving circuit and its driving method are described in Korean Patent Application No. 10-2008-0015064 (February 19, 2008), and Korean Patent Application No. 10-2008-0016503 (February 22, 2008) filed by the present applicant. .), Republic of Korea Patent Application 10-2010-0082938 (August 26, 2010), U.S. Patent Application 12 / 292,849 (Nov. 26, 2008), U.S. Patent Application 12 / 289,190 (October 22, 2008), U.S. Patent Application 13 / 213,794 (August 19, 2011) may be applied.

A pixel array and a shift register 30 of a gate driving circuit, which will be described later, may be formed on the lower substrate of the display panel 10. The pixels of the pixel array may include a white OLED in which a red light emitting layer, a green light emitting layer, and a blue light emitting layer are stacked to emit white light. A color filter array including a color filter and a black matrix may be formed on the upper substrate of the display panel 10.

The display panel driver circuit writes data of an input image to pixels of the display panel. The display panel driver circuit includes a data driver circuit, a gate driver circuit, a timing controller 22, and the like.

The data driver circuit includes a plurality of source drive ICs 24. The source drive ICs 24 receive the digital video data RGB from the timing controller 22. The source drive ICs 24 convert the digital video data RGB into a gamma compensation voltage in response to the source timing control signal from the timing controller 22 to supply the data lines to the data lines of the display panel 10. The source drive ICs 24 may be connected to the data lines 11 of the display panel 10 by a chip on glass (COG) process or a tape automated bonding (TAB) process. 3 shows an example in which the source drive ICs 24 are mounted in a tape carrier package (TCP). Each of the TCPs is connected between a printed circuit board 20 in a TAB process and a lower substrate of the display panel 10.

The gate driving circuit may be embedded in the lower substrate of the display panel 10 together with the pixel array by a gate in panel (GIP) process. The gate driving circuit outputs multiple gate signals including a level shifter 26 and a shift register 30. The multiple gate signal is generated as a multiple signal including an initialization pulse for initializing a pixel, a scan pulse synchronized with a data voltage, and an emission control pulse for controlling the emission timing of the pixel.

The level shifter 26 receives a start pulse, a reset pulse, a clock, and the like from the timing controller 22. In addition, the level shifter 26 receives a driving voltage such as a gate high voltage VGH and a gate low voltage VGL. Start pulses, reset pulses, clocks, and the like transmitted from the timing controller 22 to the level shifter 26 swing between 0V and 3.3V. The gate high voltage VGH is a voltage higher than or equal to the threshold voltage of the TFTs formed in the TFT array of the display panel 10, and the gate low voltage VGL is a threshold voltage of the TFTs formed in the TFT array of the display panel 10. The voltage is lower than the voltage, which is about -5V.

The level shifter 26 shifts the voltages of the start pulse, the reset pulse, and the clock inputted from the timing controller 22 to start the swing voltage STGH and resets the swing between the gate high voltage VGH and the gate low voltage VGL. The pulses RST and clocks CLK and CLKB are output. The clocks CLK and CLKB include a first clock CLK and a second clock CLKB generated in an inverse phase of the first clock CLK as shown in FIGS. 4 and 5. The clock signals CLK output from the level shifter 26 are sequentially shifted in phase and transmitted to the shift register 30 formed in the display panel 10.

The shift register 30 is formed on the lower substrate of the display panel 10 by a GIP process. The shift register 30 includes a plurality of stages 30N ˜ 30N + 3 sequentially connected to each other as shown in FIG. 2 to sequentially output gate signals. The shift register 30 rises the voltage of the output terminal connected to the gate line of the display panel 10 in response to the start pulse VST input from the level shifter 26 and responds to the reset pulse RST. To fall the voltage at the output terminal.

Each of the stages of the shift register 30 receives the start pulse ST and the clocks CLK and CLKB and outputs multiple gate signals through the output terminal OUT. The start pulse ST and the reset pulse RST are input from the level shifter 26 only to the first stage 30N in FIG. 2. Stages other than the first stage 30N receive the start pulse ST and the reset pulse RST from the previous stage. In Fig. 2, "NST" is a terminal for supplying the start pulse ST to the next stage, and "NRST" is a terminal for supplying the reset pulse RST to the next stage. Although not shown, the QBA node voltage of the next stage is supplied to the previous stage.

The timing controller 22 is mounted on the PCB 20 to receive digital video data RGB from an external host system, and the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, and the data enable signal Data Enable, A timing signal such as DE) and main clock CLK is received. The host system may be implemented as any one of a television system, a set top box, a DVD player, a navigation system, a Blu-ray player, a personal computer (PC), a home theater system, and a phone system. The timing controller 22 reorders the digital video data received from the host system and sends it to the source drive ICs 24.

The timing controller 22 uses a timing signal Vsync, Hsync, DE, and CLK to control the operation timing of the source drive ICs 24, the level shifter 26 of the gate driving circuit, Gate timing control signals ST, RST, and CLK for controlling the operation timing of the shift register 30 are generated.

The timing controller 22 is connected to a memory 40 in which timing information is stored. The memory is implemented as a data updateable memory, such as electrically erasable and programmable read only memory (EEPROM). The timing information includes rising timing and signal width information of each of the source and gate timing control signals output from the timing controller 22. The timing controller 22 counts the received timing signal by referring to the timing information stored in the memory 40, compares the count value with the timing information, and outputs a source and gate timing control signal. The panel module maker or set maker of the organic light emitting display can update the timing information of the gate signal specification into a memory through a ROM writer to obtain multiple gate signals that meet the new gate signal specification without redesigning the pixel driving circuit. You can get it. For example, the rising time and the falling time of each of the gate signals may be changed by adjusting timing information of the start pulse ST and the reset pulse RST.

3 is a circuit diagram showing the circuit configuration of the shift register 30 in detail. 4 and 5 are waveform diagrams showing a method of driving a shift register.

3 to 5, each of the stages of the shift register 30 may include a pull-up transistor Tu, a pull-down transistor Td1 and Td2, a Q node Q and a pull-down transistor Td1 that control the pull-up transistor Tu. And QB nodes QBA and QBB for controlling Td2, and switch circuits for charging and discharging Q nodes Q and QB nodes QBA and QBB. The pull-down transistors Td1 and Td2 are the first pull-down transistor Td1 and the second pull-down transistor Td2 connected in parallel between the output terminal of the stage and the first low potential power supply voltage source generating the first low potential power supply voltage GVSS1. ). The QB nodes QBA and QBB are divided into a first QB node QBA that controls the first pull-down transistor Td1 and a second QB node QBB that controls the second pull-down transistor Td2.

Although the transistors shown in FIG. 3 illustrate an example formed based on an n type metal-oxide semiconductor field-effect-transistor (MOSFET), the present invention is not limited thereto. For example, the transistors shown in FIG. 3 may be implemented with a p type MOSFET.

Each of the stages includes a start pulse ST, a reset pulse RST, clocks CLK and CLKB, a high potential power voltage GVDD, first and second low potential power voltages GVSS1 and GVSS2, and the like. The start pulse ST is synchronized with the first clock CLK. The reset pulse RST is generated after the start pulse ST and is synchronized with the first clock CLK. The time difference between the start pulse ST and the reset pulse RST is determined according to the signal width of the gate signal. The larger the signal width of the gate signal, the longer the time difference between the start pulse ST and the reset pulse RST.

The high potential supply voltage GVDD is a supply voltage of approximately 10V or more. The first and second low potential power supply voltages GVSS1 and GVSS2 may be set to the same voltage as the power supply voltage of 0 V or less, and may be set to different voltages. The first and second low potential supply voltages GVSS1 and GVSS2 are stably turned off even when the pull-down transistors Td1 and Td2 shift their threshold voltages due to gate bias stress. It is desirable that the voltage be set differently so that it can operate. For example, the second low potential power supply voltage GVSS2 may be set to a lower voltage than the pull-down transistors Td1 and Td2.

The switch circuit supplies the start pulse ST to the Q node to rise the voltage of the output terminal, and supplies the reset pulses RST1 and RST2 to the QB nodes QBA and QBB to poll the voltage of the output terminal. The switch circuit includes a first Q node driver 11, a second Q node driver 12, a third Q node driver 13a and 13b, a first QB node driver 14, and a second QB node driver 15. And a third QB node driver 16, a fourth QB node driver 17, and the like.

The first Q node driver 11 turns on the pull-up transistor Tu by charging the Q node with a voltage of the first clock CLK in response to the start pulse ST and the first clock CLK that are synchronized with each other. Let's do it. The first Q node driver 11 includes first and second transistors T1, T2a, and T2b. The second transistors T2a and T2b may be composed of the second a transistor T2a and the second b transistor T2b, but any one of them may be omitted.

The first transistor T1 is turned on according to the first clock CLK to operate as a diode that transfers the first clock CLK to the second transistors T2a and T2b. The gate and the drain of the first transistor T1 are shorted. The first clock CLK is supplied to the gate and the drain of the first transistor T1. The source of the first transistor T1 is connected to the drain of the second a transistor T2a.

The second transistors T2a and T2b are turned on when the start pulse ST and the first clock CLK are simultaneously input to supply the first clock CLK to the Q node Q. Charges the Q node Q. The second transistors T2a and T2b remain in an off state when the start pulse ST is not input. Gates of the second a transistor T2a and the second b transistor T2b are short-circuited. The start pulse ST is supplied to the gates of the second a transistor T2a and the second b transistor T2b. The drain of the second a transistor T2a is connected to the source of the first transistor T1 and the source of the second a transistor T2a is connected to the drain of the second b transistor T2b. The source of the second b transistor T2b is connected to the Q node Q.

The second Q node driver 12 supplies the second clock CLB to the Q node Q that is already charged to boost the voltage of the Q node Q to turn on the pull-up transistor Tu. time). The signal width of the gate signal boosted by the Q node Q by the second Q node driver 12 and output from the stage is the length of the signal width of the first clock CLK plus the signal width of the second clock CLKB. Longer than The second Q node driver 12 includes third to third transistors T3a to T3c and a capacitor c.

The third a transistor T3a is turned on according to the second clock CLKB to operate as a diode that transfers the second clock CLKB to the second transistors T2a and T2b. The gate and the drain of the third a transistor T3a are shorted. The second clock CLKB is supplied to the gate and the drain of the third a transistor T3a. The source of the third a transistor T3a is connected to the drain of the third b transistor T3b.

The third b transistor T3b is turned on when the Q node Q is charged to supply the voltage of the second clock CLKB to the capacitor C. The third b transistor T3b is turned off when the Q node Q is discharged. The gate of the third b transistor T3b is connected to the Q node Q. The drain of the third b transistor T3b is connected to the source of the third a transistor T3a and the source of the third b transistor T3b is connected to the first electrode of the capacitor C.

The thirdc transistor T3c discharges the capacitor C in response to the voltage of the first QB node QBA when the first QB node QBA is charged. The third c transistor T3c is turned off when the Q node Q is discharged. The gate of the third c transistor T3c is connected to the first QB node QBA. The drain of the third c transistor T3c is connected to the first electrode of the capacitor C, and the source of the third c transistor T3cb is connected to the second low potential power voltage source.

The capacitor C of the Q node Q is equal to the voltage of the second clock CLKB when the second clock CLKB is input to the second Q node driver 12 while the first QB node QBA is discharged. Boost the voltage. The first electrode of the capacitor C is connected to the source of the third b transistor T3b and the drain of the third c transistor T3c. The second electrode of the capacitor C is connected to the Q node Q.

The third Q node drivers 13a and 13b discharge the Q node Q in response to the voltages of the QB nodes QBA and QBB. The third Q node drivers 13a and 13b are configured to discharge the Q node Q in response to the voltage of the first QB node QBA, and the voltage of the second QB node QBB and the second QB node QBB. And a third b Q node driver 13b which discharges the Q node Q in response.

The third a Q node driver 13a includes the ninth and ninth transistors T9a and T9b. The ninth and ninth transistors T9a and T9b may be implemented as one transistor. Gates of the ninth transistor T9a and the ninth transistor T9b are commonly connected to the first QB node QBA. The drain of the ninth transistor T9a is connected to the Q node Q, and the source of the ninth transistor T9a is connected to the drain of the ninth transistor T9b. The source of the ninth transistor T9b is connected to the second low potential power supply voltage source.

The 3b Q node driver 13b includes the 10a and 10b transistors T10a and T10b. The 10a and 10b transistors T10a and T10b may be implemented as one transistor. Gates of the 10a transistor T10a and the 10b transistor T10b are commonly connected to the second QB node QBB. The drain of the 10a transistor T10a is connected to the Q node Q, and the source of the 10a transistor T10a is connected to the drain of the 10b transistor T10b. The source of the 10b transistor T10b is connected to a second low potential power supply voltage source.

The pull-up transistor Tu is turned on while the Q node Q is charged by the voltage of the first clock CLK supplied through the first Q node driver 11 to output the high potential power voltage GVDD. Supply to the terminal. The pull-up transistor Tu remains on while the Q node Q is boosted by the voltage supplied through the second Q node driver 12 to supply the high potential power voltage GVDD to the output terminal. The voltage of the Q node Q is discharged to the low potential power voltage source through the 3a Q node driver 13a or the 3b Q node driver 13b while the QB nodes QBA and QBB are charged. The pull-up transistor Tu is turned off when the Q node is discharged to a voltage lower than its threshold voltage. The gate of the pull-up transistor Tu is connected to the Q node Q. The drain of the pull-up transistor Tu is connected to the output terminal OUT and the drain of the pull-down transistors Td1 and Td2.

The first QB node driver 14 charges the QB nodes QBA and QBB with voltages of the first clock CLK in response to the reset pulse RST and the first clock CLK that are synchronized with each other, thereby pulling down the pull-down transistor Td1. , Turn on Td2). The first QB node driver 14 includes fifth and sixth transistors T5 and T6a to T6d. The sixth transistors T6a to T6d may be composed of sixth to sixth transistors T6a to T6d. One of the sixth and sixth transistors T6a and T6b may be omitted. In addition, any one of the sixth and sixth transistors T6c and T6d may be omitted.

The reset pulse RST controls the polling timing of the gate signal. The reset pulse RST may be divided into first and second reset pulses RST1 and RST2 as shown in FIGS. 3 and 5. The first and second reset pulses RST1 and RST2 may be generated as signals in phase as shown in FIG. 5 or may be generated as signals having different abnormalities.

The fifth transistor T5 is turned on according to the first clock CLK to operate as a diode that transfers the first clock CLK to the sixth transistors T6a to T6d. The gate and the drain of the fifth transistor T5 are shorted. The first clock CLK is supplied to the gate and the drain of the fifth transistor T5. The source of the fifth transistor T5 is connected to the drains of the sixth and sixth transistors T6a and T6c.

The sixth and sixth transistors T6a and T6b are turned on when the first reset pulse RST1 and the first clock CLK are simultaneously input to turn the first clock CLK to the first QB node QBA. To charge the first QB node QBA. The sixth and sixth transistors T6a and T6b remain in an off state when the first reset pulse RST1 is not input. Gates of the sixth transistor T6a and the sixth transistor T6b are short-circuited. The first reset pulse RST1 is supplied to the gates of the sixth a transistor T6a and the sixth b transistor T6b. The drain of the sixth transistor T6a is connected to the source of the fifth transistor T5 and the source of the sixth transistor T6a is connected to the drain of the sixth transistor B6b. The source of the sixth b transistor T6b is connected to the first QB node QBA.

The sixth and sixth transistors T6c and T6d are turned on when the second reset pulse RST2 and the first clock CLK are simultaneously input to transfer the first clock CLK to the second QB node QBB. To charge the second QB node QBB. The sixth and sixth transistors T6c and T6d maintain an off state when the second reset pulse RST2 is not input. Gates of the sixth c transistor T6c and the sixth d transistor T6d are short-circuited. The second reset pulse RST2 is supplied to the gates of the sixth c transistor T6c and the sixth d transistor T6d. The drain of the sixth c transistor T6c is connected to the source of the fifth transistor T5, and the source of the sixth c transistor T6c is connected to the drain of the sixth d transistor T6d. The source of the sixth d transistor T6d is connected to the second QB node QBB.

The second QB node driver 15 discharges the first QB node QBA in response to the voltage of the Q node Q. The second QB node driver 15 includes seventh and seventh transistors T7a and T7b.

Any one of the 7a and 7b transistors T7a and T7b may be omitted so that the 7a and 7b transistors T7a and T7b may be implemented as one transistor. Gates of the seventh transistor T7a and the seventh transistor T7b are connected to the Q node Q in common. The drain of the seventh transistor T7a is connected to the first QB node QBA, and the source of the seventh transistor T7a is connected to the drain of the seventh transistor T7b. The source of the seventh transistor T7b is connected to the second low potential power supply voltage source.

The third QB node driver 16 discharges the voltage of the second QB node QBB in response to the QB node voltage of the next stage. When the stage illustrated in FIG. 3 is the Nth (N is a positive integer) stage, the next stage may be either the N + 1 or N + 2th stage. The QB node voltage of the next stage may be the voltage of the first QB node QBA of the next stage as shown in FIG. 3, but may be selected as the voltage of the first QB node QBA. The third QB node driver 16 includes eighth and eighth transistors T8a and T8b.

One of the eighth and eighth transistors T8a and T8b may be omitted, and the eighth and eighth transistors T8a and T8b may be implemented as one transistor. Gates of the eighth transistor T8a and the eighth transistor T8b are commonly connected to one of the Q nodes QBA and QBB of the next stage. The drain of the eighth transistor T8a is connected to the second QB node QBB, and the source of the eighth transistor T8a is connected to the drain of the eighth transistor T8b. The source of the eighth transistor T8b is connected to a second low potential power voltage source.

The fourth QB node driver 17 operates as an inverter that charges the first QB node QBA to discharge the voltage at the output terminal when the Q node Q is discharged. The fourth QB node driver 17 includes fourth to fourth transistors T4a to T4c.

The fourth transistor T4a operates as a diode by shorting a gate and a drain. The high potential power voltage GVDD is supplied to the gate and the drain of the fourth a transistor T4a. The source of the fourth transistor T4a is commonly connected to the drain of the fourth transistor T4b and the gate of the fourth transistor C4c.

The fourth b transistor T4b is turned off when the Q node Q is discharged to charge the gate voltage of the fourth c transistor T4c. On the other hand, the fourth b transistor T4b is turned on when the Q node Q is charged to discharge the gate voltage of the fourth c transistor T4c. The gate of the fourth b transistor T4b is connected to the Q node Q. The drain of the fourth b transistor T4b is connected to the source of the fourth a transistor T4a and the gate of the fourth c transistor T4c. The source of the fourth b transistor T4b is connected to a second low potential power supply voltage source.

The fourth c transistor T4c operates as a diode supplying the high potential power voltage GVDD to the first QB node QBA when the fourth b transistor T4b is turned off. The fourth c transistor T4c is turned off because the gate voltage is lowered when the fourth b transistor T4b is turned on. The gate of the fourth c transistor T4c is connected to the source of the fourth a transistor T4a and the drain of the fourth b transistor T4b. The drain of the fourth c transistor T4c is connected to the drain of the fourth a transistor T4a. The high potential power voltage GVDD is supplied to the drain of the fourth c transistor T4c. The source of the fourth c transistor T4c is connected to the first QB node QBA.

The first pull-down transistor Td1 is turned on while the first QB node QBA is charged by the voltage of the first clock CLK supplied through the first QB node driver 14 to reduce the voltage of the output terminal. Discharge to the first low potential power supply voltage source. The first pull-down transistor Td1 is turned on while the first QB node QBA is charged by the high potential power voltage GVDD supplied through the fourth QB node driver 17 to reset the voltage of the output terminal. 1 Discharge to low-voltage power supply voltage source. The first pull-down transistor Td1 is turned off while the first QB node QBA is discharged through the second QB node driver 15. The gate of the first pull-down transistor Td1 is connected to the first QB node QBA. The drain of the first pull-down transistor Td1 is connected to the source of the output terminal OUT and the pull-up transistor Tu. The source of the first pull-down transistor Td1 is connected to the first low potential power supply voltage source.

The second pull-down transistor Td2 is turned on while the second QB node QBB is charged by the voltage of the first clock CLK supplied through the first QB node driver 14 to reduce the voltage of the output terminal. Discharge to the first low potential power supply voltage source. The second pull-down transistor Td2 is turned off while the second QB node QBB is discharged through the third QB node driver 16. The gate of the second pull-down transistor Td2 is connected to the second QB node QBB. The drain of the second pull-down transistor Td2 is connected to the source of the output terminal OUT and the pull-up transistor Tu. The source of the second pull-down transistor Td2 is connected to the first low potential power supply voltage source.

In FIG. 3, any one of the first pull-down transistor Td1 and the second pull-down transistor Td2 and the QB node and transistors connected to the pull-down transistor that are omitted may be omitted.

As described above, the gate driving circuit of the present invention can adjust the pulse width of the gate signal using only the start pulse and the reset pulse. As a result, the gate driving circuit of the present invention can continuously supply the gate signals to each of the gate lines within one frame period. These gate signals may have the same signal width or different from each other as shown in FIGS. 4 and 6. For example, the present invention adjusts the time difference between the start pulse ST and the reset pulse RST as shown in the example of FIG. 4, and thus, the first gate signal having the signal width of 2 horizontal periods 2HT and the 4 horizontal periods 4HT. The second gate signal having a signal width of) may be continuously generated. In addition, the gate driving circuit of the present invention may sequentially shift the gate signals as shown in FIG. 5 and overlap the gate signals OUT (N) and OUT (N + 1) supplied to neighboring gate lines.

When the DC voltage is continuously applied to the gates of the transistors for a long time, the threshold voltage may be shifted due to the gate bias stress. In the present invention, the reset pulses RST1 and RST2 can be used as a control signal for controlling the polling timing of the gate signal and can also be used as the gate bias stress compensation voltage. For example, the reset pulses RST1 and RST2 are generated at the polling timing of the gate signal as shown in FIG. 6, and are further generated in synchronization with the first clock CLK during the period in which the gate signal is not generated, thereby pulling down the transistor Td1. , Td2) can compensate for the gate bias stress.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

10: display panel 20: PCB
22: Timing Controller 24: Source Drive IC
26: level shifter 30: shift register

Claims (11)

First and second clocks generated out of phase with each other, a start pulse synchronized with the first clock, a reset pulse generated following the start pulse and synchronized with the first clock, a high potential power supply voltage, and a low potential power supply voltage Includes a shift register composed of a plurality of input and cascaded stages,
Each of the stages,
A pull-up transistor configured to charge the output terminal by supplying the high potential power voltage to an output terminal in response to a voltage of a Q node;
A pull-down transistor configured to discharge the output terminal by supplying the low potential power voltage to the output terminal in response to a voltage of a QB node; And
A switch circuit for supplying the start pulse to the Q node to rise the voltage at the output terminal and polling the voltage at the output terminal in response to the reset pulse;
A gate signal output through the output terminal is applied to a gate line of the display panel,
The switch circuit,
And a first QB node driver configured to charge the QB node with the voltage of the first clock in response to the reset pulse and the first clock. The method of claim 1,
And a plurality of gate signals continuously supplied to one gate line in one frame period. The method of claim 2,
And a gate width of the gate signals is different from each other. The method of claim 3, wherein
The QB node is
Separated into first and second QB nodes,
The pull-down transistor,
A first pull-down transistor configured to discharge the output terminal by supplying the low potential power voltage to the output terminal in response to the voltage of the first QB node; And
And a second pull-down transistor configured to supply the low potential power voltage to the output terminal in response to the voltage of the second QB node to discharge the output terminal. The method of claim 4, wherein
Driving the first QB node charges the first and second QB nodes with the voltage of the first clock in response to the reset pulse and the first clock,
The switch circuit,
A first Q node driver configured to charge the Q node with a voltage of the first clock in response to the start pulse and the first clock;
A second Q node driver configured to boost the voltage of the Q node by supplying the second clock to the Q node;
A third Q node driver configured to discharge the Q node in response to voltages of the first and second QB nodes;
A second QB node driver configured to discharge the first QB node in response to the voltage of the Q node;
A third QB node driver discharging the voltage of the second QB node in response to a first QB node voltage of a next stage; And
And a fourth QB node driver configured to charge the first QB node by supplying the high potential power voltage to the first QB node when the Q node is discharged. in. The method according to any one of claims 1 to 5,
The start pulse is generated at a rising timing at which the output terminal starts to be charged to control the rising timing,
And the reset pulse is generated at a polling timing at which the output terminal starts to be discharged to control the polling timing. The method according to any one of claims 1 to 5,
The start pulse is generated at a rising timing at which the output terminal starts to be charged to control the rising timing,
The reset pulse is generated at a polling timing at which the output terminal starts to be discharged to control the polling timing and is further synchronized with the first clock for a time other than a time at which a gate signal is output through the output terminal. And a gate driving circuit of the organic light emitting display device. First and second clocks generated out of phase with each other, a start pulse synchronized with the first clock, a reset pulse generated following the start pulse and synchronized with the first clock, a high potential power supply voltage, and a low potential power supply voltage Includes a shift register composed of a plurality of input and cascaded stages,
Each of the stages,
A pull-up transistor configured to charge the output terminal by supplying the high potential power voltage to an output terminal in response to a voltage of a Q node;
A pull-down transistor configured to discharge the output terminal by supplying the low potential power voltage to the output terminal in response to a voltage of a QB node; And
A switch circuit for supplying the start pulse to the Q node to rise the voltage at the output terminal and polling the voltage at the output terminal in response to the reset pulse;
A gate signal output through the output terminal is applied to a gate line of the display panel,
And the time difference between the start pulse and the reset pulse increases as the signal width of the gate signal increases. The method of claim 8,
And a plurality of gate signals continuously supplied to one gate line in one frame period. The method of claim 9,
And a gate width of the gate signals is different from each other. The method of claim 9,
The switch circuit,
And a QB node driver configured to charge the QB node with the voltage of the first clock in response to the reset pulse and the first clock.

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