CN106157910A - Drive element of the grid and gate driver circuit thereof and a kind of display - Google Patents
Drive element of the grid and gate driver circuit thereof and a kind of display Download PDFInfo
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- CN106157910A CN106157910A CN201610654560.8A CN201610654560A CN106157910A CN 106157910 A CN106157910 A CN 106157910A CN 201610654560 A CN201610654560 A CN 201610654560A CN 106157910 A CN106157910 A CN 106157910A
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- switch element
- grid
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- Crystallography & Structural Chemistry (AREA)
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- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The present invention proposes a kind of drive element of the grid and gate driver circuit thereof and a kind of display.Drive element of the grid includes the first to the 7th switch element, drive element of the grid is by receiving upper level gate drive signal, next stage gate drive signal, the first clock signal and the second clock signal, control the whether conducting of the first to the 7th switch element, thus control gate drives the level of signal, this grade of grid is made to export twice high level, pixel can be pre-charged by previous high level, it is to avoid is filled with counter charges in pixel, promotes the charging effect of pixel.
Description
Technical field
The present invention relates to electronic applications, show with a kind of particularly to a kind of drive element of the grid and gate driver circuit thereof
Device.
Background technology
Liquid crystal indicator (Liquid Crystal Display, LCD) possesses frivolous, energy-conservation, radiationless etc. many excellent
Point, the most gradually replaces traditional cathode ray tube (CRT) display.Liquid crystal display is widely used in height at present
The electronics such as clear DTV, desk computer, personal digital assistant (PDA), notebook computer, mobile phone, digital camera
In equipment.
As a example by thin film transistor (TFT) (Thin Film Transistor, TFT) liquid crystal indicator, comprising: liquid crystal
Showing panel and drive circuit, wherein, display panels includes a plurality of gate line (Gate) and a plurality of data lines (Data), and phase
Two adjacent gate lines intersect to form a pixel cell with two adjacent data line, and each pixel cell at least includes one
Thin film transistor (TFT).And drive circuit includes: gate driver circuit (Gate drive circuit) and source electrode drive circuit
(Source drive circuit)。
At present, display panels supports multiple inverted pattern, such as puts inverted pattern, row inverted pattern, row turning mould
Formula etc., it is achieved mainly (i.e. signal voltage is positive and negative by the positive and negative polarity of the most alternately TFT source voltage for the approach of upset
Polarity), to reach the purpose that exchange drives.In existing a kind of gate driver circuit, every a line drive element of the grid exports
High level time be 4T (T is the time that a line gate line is opened), therefore, under row reversing mode, the time of front 3 T is defeated
The level signal gone out can be opened this row pixel (Pixel) and be pre-charged, and has a distinct increment the charging effect of pixel.But,
As it is shown in figure 1, be expert at reversing mode or some reversing mode under, front 3 T pre-punching electricity the time can repeatedly be filled with on the contrary to pixel
Electric charge, be unfavorable for the charging of pixel, thus in causing display picture, the bright of each pixel secretly differed, and ultimately results in picture and shows
Effect is uneven.
Summary of the invention
It is an object of the invention to provide a kind of drive element of the grid promoting pixel charging effect and raster data model electricity
Road and a kind of display.
The present invention provides a kind of drive element of the grid, including:
First switch element, controls end, described first path terminal and institute including the first path terminal, alternate path end and first
State the first control end to be connected and receive and upwards differ the upper level gate drive signal that the drive element of the grid of one-level is exported, institute
State alternate path end and the first control node is connected；
Second switch element, controls end including third path end, fourth passage end and second, and described third path end receives
First clock signal, described second controls end is connected with described first control node, and described fourth passage end is as described grid
The outfan of driver element controls node by the first electric capacity with described first and is connected；
3rd switch element, controls end including fifth passage end, clematis stem terminal and the 3rd, and described fifth passage end receives
Low reference voltage, the described 3rd controls end receives the next stage raster data model that the drive element of the grid of difference one-level downwards is exported
Signal, described clematis stem terminal controls node with described first and is connected；
4th switch element, controls end including the 7th path terminal, the 8th path terminal and the 4th, and described 7th path terminal receives
Described low reference voltage, the described 4th controls end is connected with described first control node, and described 8th path terminal controls with second
Node is connected, and described second controls node is connected with the third path end of described second switch element by the second electric capacity；
5th switch element, controls end including the 9th path terminal, the tenth path terminal and the 5th, and described 9th path terminal receives
Described low reference voltage, the described 5th controls end is connected with described second control node, described tenth path terminal and described first
Control node to be connected；
6th switch element, controls end including the 11st path terminal, the 12nd path terminal and the 6th, and the described 6th controls end
Receiving the second clock signal, described 11st path terminal receives described low reference voltage, described 12nd path terminal and described the
The fourth passage end of two switch elements is connected；
7th switch element, controls end, described tenth three-way including the tenth threeway terminal, the 14th path terminal and the 7th
End receive described low reference voltage, described 7th control end with described second control node is connected, described 14th path terminal and
The fourth passage end of described second switch element is connected.
Further, it is provided with separate storage electricity between the second control end and the fourth passage end of described second switch element
Holding, described first electric capacity is the parasitic capacitance of described second switch element and described separate storage electric capacity sum.
Further, described first switch element to described 7th switch element is N-type transistor.
Further, described first control end to control end to the most described 7th to be grid, described first switch element described
First path terminal, the third path end of described second switch element, the fifth passage end of described 3rd switch element, the described 4th
7th path terminal of switch element, the 9th path terminal of described 5th switch element, described 6th switch element the 11st lead to
Terminal, the tenth threeway terminal of described 7th switch element are drain electrode, the alternate path end of described first switch element, described
The fourth passage end of second switch element, the clematis stem terminal of described 3rd switch element, the 8th of described 4th switch element the
Path terminal, the tenth path terminal of described 5th switch element, the 12nd path terminal of described 6th switch element, the described 7th open
The 14th path terminal closing element is source electrode.
Further, described first switch element to described 7th switch element is P-type transistor.
Further, described first clock signal and described second clock signal are complementary signal.
Further, described upper level gate drive signal and described next stage gate drive signal are double wave shape letter
Number.
The present invention also provides for a kind of gate driver circuit, including the drive element of the grid as above of N number of cascade, described
N is the integer more than 1.
Further, the first clock cable and second clock holding wire, described first clock cable and institute are also included
State the clock signal complement of second clock holding wire output.
The present invention also provides for a kind of display, including gate driver circuit as above, in described gate driver circuit
The gated sweep signal output part of drive element of the grid is coupled to corresponding gate line.
In embodiments of the invention, drive element of the grid includes the first to the 7th switch element, and drive element of the grid passes through
Receive upper level gate drive signal, subordinate's gate drive signal, the first clock signal and the second clock signal, control first to
The whether conducting of the 7th switch element, thus control gate drives the level of signal, makes this grade of grid export twice high level, front
Pixel can be pre-charged by high level once, it is to avoid is repeatedly filled with opposite charges in pre-charge process to pixel, thus carries
Rise the charging effect of pixel.
Accompanying drawing explanation
Fig. 1 is the waveform signal of pixel charged state in existing some inverted pattern display or row reversing mode display
Figure.
Fig. 2 is the electrical block diagram of drive element of the grid in one embodiment of the invention.
Fig. 3 is the time diagram of drive element of the grid in one embodiment of the invention.
Fig. 4 is the waveform diagram of pixel charged state in one embodiment of the invention.
Fig. 5 is the structural representation of gate driver circuit in one embodiment of the invention.
Fig. 6 is one-level drive element of the grid mould under the ambient temperature of 27 DEG C in gate driver circuit as shown in Figure 5
Intend result schematic diagram.
Detailed description of the invention
By further illustrating the technological means and effect that the present invention taked by reaching predetermined goal of the invention, below in conjunction with
Accompanying drawing and preferred embodiment, detailed description of the invention, structure, feature and the effect thereof to the present invention, after describing in detail such as.
Although the present invention uses first, second, third, etc. term to describe different element, signal, port, assembly or portions
Point, but these elements, signal, port, assembly or part are not limited by these terms.These terms are intended merely to one
Individual element, signal, port, assembly or part make a distinction with another element, signal, port, assembly or part.In the present invention
In, element, port, assembly or part and another element, port, assembly or part " being connected ", " connection ", it is possible to understand that
For being directly electrically connected with, or it can be appreciated that there is the indirect electric connection of intermediary element.Unless otherwise defined, otherwise originally
All terms (including technical term and scientific terminology) that invention is used have and ordinary skill people of the art
The meaning that member is generally understood that.
The gate driver circuit (also referred to as shift register) of the present invention includes that multistage drive element of the grid (also referred to as shifts
Deposit unit), the drive element of the grid of every one-level is corresponding with the every a line gate line on display floater respectively to be electrically connected with, thus
The most gradually being applied to by gate drive signal often on row gate line, the annexation between drive element of the grid will hereinafter
Elaborate.
Fig. 2 is the electrical block diagram of drive element of the grid in one embodiment of the invention.The grid of the present embodiment drives
Moving cell receives and upwards differs the upper level gate drive signal that the drive element of the grid of one-level is exportedAnd downward phase
The next stage gate drive signal that the drive element of the grid of difference one-level is exportedI.e. assume the present embodiment drive element of the grid
Being N level drive element of the grid, wherein, N >=2, the gate drive signal of its output isThe most upwards differ the grid of one-level
The upper level gate drive signal that driver element is exported isAnd the drive element of the grid differing downwards one-level is exported
Next stage gate drive signal be
As in figure 2 it is shown, the drive element of the grid of the present invention include the first switch element T1, second switch element T2, the 3rd
Switch element T3, the 4th switch element T4, the 5th switch element T5, the 6th switch element T6 and the 7th switch element T7.Tool
Body, the first switch element T1 includes that the first path terminal, alternate path end and first control end, and the first path terminal controls with first
End is connected and receives the upper level gate drive signal of the drive element of the grid output upwards differing one-levelAlternate path end
Control node Q with first to be connected.Second switch element T2 include third path end, fourth passage end and second control end, the 3rd
Path terminal receives the first clock signal VA, the second control end and first controls node Q and is connected, and fourth passage end is as raster data model
The outfan of unit controls node Q by the first electric capacity C1 and first and is connected.3rd switch element T3 include fifth passage end,
Clematis stem terminal and the 3rd controls end, and fifth passage end receives low reference voltage VL, the 3rd controls end receives downward difference one-level
The next stage gate drive signal of drive element of the grid outputClematis stem terminal controls node Q with first and is connected.4th opens
Closing element T4 and include that the 7th path terminal, the 8th path terminal and the 4th control end, the 7th path terminal receives low reference voltage VL, the 4th
Controlling end and first to control node Q and be connected, the 8th path terminal controls node QB with second and is connected, and second controls node QB passes through the
Two electric capacity C2 are connected with the third path end of second switch element T2.5th switch element T5 include the 9th path terminal, the tenth lead to
Terminal and the 5th controls end, and the 9th path terminal receives low reference voltage VL, the 5th control end and second controls node QB and is connected, the
Ten path terminal control node Q with first and are connected.6th switch element T6 includes the 11st path terminal, the 12nd path terminal and the 6th
Controlling end, the 6th controls end receives the second clock signal VB, the 11st path terminal receives low reference voltage VL, the 12nd path terminal
It is connected with the fourth passage end of second switch element T2.7th switch element T7 includes the tenth threeway terminal, the 14th path terminal
And the 7th control end, the tenth three-way end receive low reference voltage VL, the 7th control end and second controls node QB and is connected, and the tenth
Four path terminal are connected with the fourth passage end of second switch element T2.
In the present invention, it is provided with separate storage electricity between the second control end and the fourth passage end of second switch element T2
Holding, the first electric capacity C1 is parasitic capacitance and the separate storage electric capacity sum of second switch element T2, thus promotes pull-up effect.?
In the present invention, the first electric capacity C1 can also be the parasitic electricity between the second control end and the fourth passage end of second switch element T2
Hold.
In the present embodiment, the first switch element T1 to the 7th switch element T7 is N-type transistor.Wherein, the first control
End processed to the 7th control end be grid, first path terminal of the first switch element T1, the third path end of second switch element T2,
The fifth passage end of the 3rd switch element T3, the 7th path terminal of the 4th switch element T4, the 5th switch element T5 the 9th lead to
Terminal, the 11st path terminal of the 6th switch element T6, the tenth threeway terminal of the 7th switch element T7 are drain electrode, and first opens
Close the alternate path end of element T1, the fourth passage end of second switch element T2, the clematis stem terminal of the 3rd switch element T3, the
8th path terminal of four switch element T4, the tenth path terminal of the 5th switch element T5, the tenth two-way of the 6th switch element T6
Terminal, the 14th path terminal of the 7th switch element T7 are source electrode.
Certainly, it will be appreciated by persons skilled in the art that the first switch element T1 to the 7th switch element T7 can also
Other switch element is used to realize, such as P-type transistor.As a example by N-type transistor, specifically introduce the present invention's below
Operation principle.
Referring to Fig. 3, it is the time diagram of drive element of the grid in above-described embodiment, every one-level drive element of the grid
Work process be divided into pre-charging stage t1, for the first time pull-up stage t2, the most drop-down stage t3, for the second time pull-up stage
T4, the most drop-down stage t5 and stabilization sub stage t6.
Pre-charging stage t1:
At pre-charging stage, the second clock signal V of inputBFor high level, the 6th switch element T6 conducting, this grade of grid
This grade of gate drive signal of driver element outputIt is pulled down to low reference voltage V by the 6th switch element T6 of conductingL。
Upwards differ the upper level gate drive signal of the drive element of the grid output of one-levelVoltage be high level, first switch
Element T1 turns on, and first controls node Q is precharged.
In the ending phase of pre-charging stage t1, first controls node Q is charged to high level VH-VT(VHFor upper level grid
Pole drives signalHigh level voltage, VTThreshold voltage for transistor).Grid-source due to second switch element T2
Pole tension VGS2>VT, second switch element T2 is opened.
Pull-up stage t2 for the first time:
In the pull-up stage for the first time, owing to the first control node Q has been precharged, second switch element T2 and the 4th opens
Close element T4 conducting, the first clock signal VALevel uprised by low, this grade of gate drive signalOpen by the second of conducting
Close element T2 by the first clock signal VAHigh level draw high, due to the boot strap of the first electric capacity C1, along with this grade of grid drives
This grade of gate drive signal of moving cell outputVoltage raise, it can make the current potential of the first control node Q by further
Draw high, so that second switch element T2 conducting is more abundant, so that this grade of grid of this grade of drive element of the grid output
Drive signalIt is further pulled up and is reached high level.In the pull-up stage for the first time, the second current potential controlling node QB passes through
4th switch element T4 of conducting is pulled down to low reference voltage VL。
The most drop-down stage t3:
In the drop-down stage for the first time, upwards differ the upper level gate drive signal of the drive element of the grid output of one-levelAnd the next stage gate drive signal of the drive element of the grid output of difference one-level downwardsVoltage be high electricity
Flat, first controls node Q keeps former current potential, second switch element T2 and the 4th switch element T4 constant conduction.First sequential letter
Number VALevel by high step-down, this grade of gate drive signalVoltage by conducting second switch element T2 be pulled low, this
Time, the first electric capacity C1 controls the ground of node Q to relatively electronegative potential by first.Second clock signal VBFor high level, the 6th
Switch element T6 turns on, this grade of gate drive signalBy the 6th switch element T6 of conducting by continual and steady with reference to low
Voltage VL.In the drop-down stage for the first time, due to the 4th switch element T4 constant conduction, second controls the current potential of node QB by leading
The 4th logical switch element T4 is stable in low reference voltage VQ。
Second time pull-up stage t4:
At second time pull-up stage, upper level gate drive signalAnd next stage gate drive signalElectricity
Pressure is low level, and the first switch element T1 and the 3rd switch element T3 disconnects, and first controls node Q keeps former current potential, thus
Make second switch element T2 and the 4th switch element T4 constant conduction.First clock signal VALevel uprised by low, this grade of grid
Pole drives signalBy the second switch element T2 of conducting by the first clock signal VAHigh level draw high, due to the first electric capacity
The boot strap of C1, along with this grade of gate drive signalVoltage raise, it can make the current potential of the first control node Q be entered
One step is drawn high, and first controls node Q place being further pulled up of current potential so that second switch element T2 the most fully,
So that this grade of gate drive signal of this grade of drive element of the grid outputIt is further pulled up and is reached high level.?
In the second time pull-up stage, due to the 4th switch element T4 constant conduction, second controls the current potential of node QB by the 4th of conducting
Switch element T4 is stable in low reference voltage VL。
The most drop-down stage t5:
At second time drop-down stage, the second clock signal VBFor high level, the 6th switch element T6 conducting, this grade of grid drives
Dynamic signalIt is pulled low by the 6th switch element T6 of conducting.Next stage gate drive signalVoltage be high level,
3rd switch element T3 conducting, the first current potential controlling node Q is pulled low by the 3rd switch element T3 of conducting.Due to second
Electric capacity C2 is by the first clock signal VACoupleding to the second control node QB, the second current potential controlling node QB is still low level.
Stabilization sub stage t6:
When the drop-down stage, this grade of gate drive signal that this grade of drive element of the grid is exportedIt has been pulled low to
Low level, therefore, within the follow-up time, i.e. the stabilization sub stage, needs to make this grade of gate drive signalMaintain low level,
Thus the waveform needed for obtaining.
Specifically, within the follow-up time, due to the first clock signal VAWith the second clock signal VBFor contrary mutual of level
Complement signal, as the first clock signal VADuring by low uprising, the second clock signal VBBy high step-down, because the coupling of the second electric capacity C2 is made
With, the second current potential controlling node QB is pulled to high level, the 5th switch element T5 and the 7th switch element T7 conducting, thus
Node Q and this grade of gate drive signal is controlled to first by the 5th switch element T5 and the 7th switch element T7Carry out continuing
Drop-down, make this grade of gate drive signalIt is able to maintain that in low level.As the first clock signal VADuring by high step-down, the second sequential
Signal VBUprised by low, now the 6th switch element T6 conducting, by the 6th switch element T6 to this grade of gate drive signal
Carry out the most drop-down, and then make this grade of gate drive signalIt is able to maintain that in low level.
Fig. 4 is the waveform diagram of pixel charged state in one embodiment of the invention.As shown in Figure 4, the present embodiment
The gate drive signal of drive element of the grid outputFor having double waveshape signals of twice high level, wherein, the first second highest electricity
Ordinary mail number is filled with electric charge to pixel within the time of second T, and the time inner grid line at the 3rd T is low level, so that
Pixel keeps former current potential substantially, it is to avoid be filled with reversed charge, is greatly improved the charging effect of pixel.It is appreciated that upwards phase
The upper level gate drive signal of the drive element of the grid output of difference one-levelAnd differ downwards the drive element of the grid of one-level
The next stage gate drive signal of outputAlso double waveshape signal it is.
Fig. 5 is the structural representation of gate driver circuit in one embodiment of the invention.Gate driver circuit can include N number of
The drive element of the grid of cascade, described N is the integer more than 1.As it is shown in figure 5, which describe first to fourth grade of raster data model list
The driving principle of unit, wherein, the every one-level drive element of the grid shown in Fig. 5 includes M port and N-port.For as shown in Figure 2
For exporting gate drive signalDrive element of the grid, M port is used for receiving upper level gate drive signalN end
Mouth is used for receiving next stage gate drive signalWherein, first order drive element of the grid the most upwards differs the grid of one-level
Pole driver element, therefore, the M port of first order drive element of the grid receives the signal that the first outside source STV1 provides, the
The signal that one outside source STV1 provides is double waveshape signals.
Further, first to fourth grade of drive element of the grid is respectively provided with A port, B port, C port and L port,
Wherein, A port, B port and C port respectively with the first clock cable CLKA, second clock holding wire CLKB and reference
Low voltage signal line VGL connects, to receive the first clock cable CLKA, second clock holding wire CLKB respectively and with reference to low
First clock signal V of voltage signal line VGL outputA, the second clock signal VBAnd low reference voltage VL, the first clock signal
Line CLKA, the clock signal complement of second clock holding wire CLKB, L port is used for exporting this grade of gate drive signal
Fig. 6 is one-level drive element of the grid mould under the ambient temperature of 27 DEG C in gate driver circuit as shown in Figure 5
Intend result schematic diagram.As shown in Figure 6, the one-level drive element of the grid of the present invention receives the first clock signal VA, second sequential letter
Number VB, upper level drive element of the grid output upper level gate drive signalUnder the output of next stage drive element of the grid
One-level gate drive signalAnd low reference voltage VL, export the gate drive signal of this grade of drive element of the gridWherein,
First clock signal VAAnd the second clock signal VBFor complementary clock signal, the upper level of upper level drive element of the grid output
Gate drive signalThis grade of drive element of the grid outputThe next stage grid of next stage drive element of the grid output
Drive signalBetween differ a phase place successively.
The embodiment of the present invention also provides for a kind of display, including gate driver circuit as above, described raster data model
In circuit, the gated sweep signal output part of drive element of the grid is coupled to corresponding gate line.
In embodiments of the invention, drive element of the grid includes the first to the 7th switch element, and drive element of the grid passes through
Receive upper level gate drive signal, next stage gate drive signal, the first clock signal and the second clock signal, control first
To the whether conducting of the 7th switch element, thus control gate drives the level of signal, makes this grade of grid export twice high level,
Pixel can be pre-charged by previous high level, it is to avoid be repeatedly filled with opposite charges in pre-charge process to pixel, thus
Promote the charging effect of pixel.
The above, be only presently preferred embodiments of the present invention, and the present invention not makees any pro forma restriction, though
So the present invention is disclosed above with preferred embodiment, but is not limited to the present invention, any technology people being familiar with this specialty
Member, in the range of without departing from technical solution of the present invention, when the technology contents of available the disclosure above makes a little change or modification
For the Equivalent embodiments of equivalent variations, as long as being without departing from technical solution of the present invention content, according to the technical spirit pair of the present invention
Any simple modification, equivalent variations and the modification that above example is made, all still falls within the range of technical solution of the present invention.
Claims (10)
1. a drive element of the grid, it is characterised in that including:
First switch element, controls end, described first path terminal and described the including the first path terminal, alternate path end and first
One controls end is connected and receives and upwards differ the upper level gate drive signal that the drive element of the grid of one-level is exported, and described the
Two path terminal control node with first and are connected；
Second switch element, controls end including third path end, fourth passage end and second, and described third path end receives first
Clock signal, described second controls end is connected with described first control node, and described fourth passage end is as described raster data model
The outfan of unit controls node by the first electric capacity with described first and is connected；
3rd switch element, controls end including fifth passage end, clematis stem terminal and the 3rd, and described fifth passage end receives reference
Low-voltage, the described 3rd controls end receives the next stage raster data model letter that the drive element of the grid of difference one-level downwards is exported
Number, described clematis stem terminal controls node with described first and is connected；
4th switch element, controls end including the 7th path terminal, the 8th path terminal and the 4th, and described 7th path terminal receives described
Low reference voltage, the described 4th controls end is connected with described first control node, and described 8th path terminal controls node with second
Being connected, described second controls node is connected with the third path end of described second switch element by the second electric capacity；
5th switch element, controls end including the 9th path terminal, the tenth path terminal and the 5th, and described 9th path terminal receives described
Low reference voltage, the described 5th controls end is connected with described second control node, and described tenth path terminal controls with described first
Node is connected；
6th switch element, controls end including the 11st path terminal, the 12nd path terminal and the 6th, and the described 6th controls end receives
Second clock signal, described 11st path terminal receives described low reference voltage, and described 12nd path terminal is opened with described second
The fourth passage end closing element is connected；
7th switch element, controls end, described tenth three-way termination including the tenth threeway terminal, the 14th path terminal and the 7th
Receiving described low reference voltage, the described 7th controls end is connected with described second control node, and described 14th path terminal is with described
The fourth passage end of second switch element is connected.
2. drive element of the grid as claimed in claim 1, it is characterised in that the second control end of described second switch element with
Being provided with separate storage electric capacity between fourth passage end, described first electric capacity is parasitic capacitance and the institute of described second switch element
State separate storage electric capacity sum.
3. drive element of the grid as claimed in claim 1, it is characterised in that described first switch element is to described 7th switch
Element is N-type transistor.
4. drive element of the grid as claimed in claim 3, it is characterised in that described first controls end controls end to the described 7th
For grid, described first path terminal of described first switch element, the third path end of described second switch element, the described 3rd
The fifth passage end of switch element, the 7th path terminal of described 4th switch element, the 9th path of described 5th switch element
End, the 11st path terminal of described 6th switch element, the tenth threeway terminal of described 7th switch element are drain electrode, described
The alternate path end of the first switch element, the fourth passage end of described second switch element, the 6th of described 3rd switch element the
Path terminal, the 8th path terminal of described 4th switch element, the tenth path terminal of described 5th switch element, described 6th switch
12nd path terminal of element, the 14th path terminal of described 7th switch element are source electrode.
5. drive element of the grid as claimed in claim 1, it is characterised in that described first switch element is to described 7th switch
Element is P-type transistor.
6. drive element of the grid as claimed in claim 1, it is characterised in that described first clock signal and described second sequential
Signal is complementary signal.
7. drive element of the grid as claimed in claim 1, it is characterised in that described upper level gate drive signal and described under
One-level gate drive signal is double waveshape signal.
8. a gate driver circuit, it is characterised in that include the grid as according to any one of claim 1-7 of N number of cascade
Pole driver element, described N is the integer more than 1.
9. gate driver circuit as claimed in claim 8, it is characterised in that also include the first clock cable and second clock
Holding wire, the clock signal complement that described first clock cable exports with described second clock holding wire.
10. a display, it is characterised in that including: gate driver circuit as claimed in claim 8, described raster data model
In circuit, the gated sweep signal output part of drive element of the grid is coupled to corresponding gate line.
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| CN201610654560.8A CN106157910A (en) | 2016-08-11 | 2016-08-11 | Drive element of the grid and gate driver circuit thereof and a kind of display |
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Application publication date: 20161123 |