CN103854622A - Gate drive circuit - Google Patents
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- CN103854622A CN103854622A CN201410073196.7A CN201410073196A CN103854622A CN 103854622 A CN103854622 A CN 103854622A CN 201410073196 A CN201410073196 A CN 201410073196A CN 103854622 A CN103854622 A CN 103854622A
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Abstract
The invention provides a gate drive circuit. The gate drive circuit comprises multiple levels of gate drive units, wherein each gate drive unit comprises a first drive module and a second drive module which respectively comprise a regulated voltage module. The first drive modules and the second drive module respectively receive a first sequence signal, a second sequence signal, a reference low voltage, a first reference voltage and a second reference voltage. The electric potential of a third sequence signal received by the first regulated voltage module of each first drive module is opposite to that of a fourth sequence signal received by the second regulated voltage module of the corresponding second drive module. In the gate drive circuit, the first drive modules and the second drive modules output gate drive signals respectively, so that the drive capability of the gate drive circuit is enhanced; besides, the regulated voltage modules work intermittently, so that the service life of the gate drive circuit is prolonged, the abnormal risk caused by threshold voltage deviation is reduced, and stability is good.
Description
Technical field
The present invention relates to a kind of driving circuit, particularly a kind of gate driver circuit that is applicable to liquid crystal indicator.
Background technology
Liquid crystal indicator (Liquid Crystal Display, LCD) possesses the plurality of advantages such as frivolous, energy-conservation, radiationless, has therefore replaced gradually traditional cathode ray tube (CRT) display.Liquid crystal display is widely used in the electronic equipments such as HD digital TV, desk-top computer, PDA(Personal Digital Assistant), notebook computer, mobile phone, digital camera at present.
With thin film transistor (TFT) (Thin Film Transistor, TFT) liquid crystal indicator is example, it comprises: display panels and driving circuit, wherein, display panels comprises many gate lines and many data lines, and adjacent two gate lines and adjacent two data lines intersect to form a pixel cell, and each pixel cell at least comprises a thin film transistor (TFT).And driving circuit comprises: gate driver circuit (gate drive circuit) and source electrode drive circuit (source drive circuit).Along with the producer pursues the cost degradation of liquid crystal indicator and the raising of manufacturing process, originally be arranged on the glass substrate that driving circuit integrated chip beyond display panels is arranged at display panels and become possibility, for example, grid-driving integrated circuit is arranged to array base palte (Gate IC in Array, GIA) thus the upper manufacture process of simplifying liquid crystal indicator and reduces production costs.
The basic functional principle of display panels and driving circuit is: gate driver circuit is by sending gate drive signal with pulling up transistor of gate line electric connection to gate line, sequentially the TFT of every a line is opened, then the pixel cell of a full line is charged to required separately voltage by source electrode drive circuit, to show different GTGs simultaneously.First pull up transistor the thin film transistor (TFT) of the first row is opened by it by the gate driver circuit of the first row, then by source electrode drive circuit, the pixel cell of the first row is charged.When the pixel cell of the first row is charged, gate driver circuit is just closed this row thin film transistor (TFT), then the gate driver circuit of the second row is pulled up transistor the thin film transistor (TFT) of the second row is opened by it, then by source electrode drive circuit, the pixel cell of the second row is discharged and recharged.So sequentially go down, when the pixel cell of the last column of having substituted the bad for the good, just start charging from the first row again.
Wherein, gate driver circuit comprises multiple on-off elements, it utilizes clock signal to apply positive voltage or negative voltage to the grid of multiple on-off elements, to control the conducting of multiple on-off elements and to close, thereby export desirable gate drive signal, and, can export enough large voltage in order to guarantee gate driver circuit, larger the pulling up transistor of general employing channel width-over-length ratio, but, because the channel width-over-length ratio pulling up transistor is larger, can cause again the stray capacitance of the grid that pulls up transistor and source electrode or drain electrode larger, therefore, in the time that multiple clock signals carry out generating positive and negative voltage switching, the stray capacitance of the grid pulling up transistor and source electrode or drain electrode can produce larger coupling effect, pull up transistor on grid and therefore can retain some noise charge, cause the leakage current that pulls up transistor to increase, cause occurring in the low level on grid cabling gate line noise level, gate line noise level can increase along with the increase of temperature, finally will cause the gate drive signal of drive element of the grid output unstable.In addition, in the time that the grid of on-off element is applied in the overlong time of positive voltage, its threshold voltage will increase, will cause like this electric current output of on-off element to decline, in the time that on-off element is applied in the overlong time of negative voltage, its threshold voltage will reduce, and will cause like this leakage current of on-off element excessive, makes the closing property variation of on-off element.Simultaneously, in stabilizing circuit in prior art in gate driver circuit, the grid of stable switch element is always in high level state, in the time that the grid stabilizing circuit working time is long, due to its physical characteristics, stable switch element function is degenerated, and will affect its serviceable life, and due to the skew of the threshold voltage of on-off element, the function of gate driver circuit may entanglement, will affect so the normal work of gate driver circuit.
Therefore, be necessary to provide improved technical scheme to overcome the above technical matters existing in prior art.
Summary of the invention
The main technical problem to be solved in the present invention is to provide that a kind of driving force is strong, the gate driver circuit of long service life and good stability.
For solving the problems of the technologies described above, the invention provides a kind of gate driver circuit, comprise multistage drive element of the grid, wherein every grade of drive element of the grid is for driving respectively a corresponding gate line on display panel.Every grade of drive element of the grid comprises the first driver module and the second driver module, and the first driver module and the second driver module include the first to the 8th on-off element.Described the first on-off element comprises the first path terminal, alternate path end and the first control end, and described the first path terminal receives the first reference voltage, and described the first control end receives the first pulse signal.Described second switch element comprises threeway terminal, four-way terminal and the second control end, described three-way termination is received the first clock signal, described the second control end is connected with the alternate path end of described the first on-off element and is connected with the four-way terminal of second switch element by the first electric capacity, described four-way terminal output gate drive signal.Described the 3rd on-off element comprises five-way terminal, the 6th path terminal and the 3rd control end, described five-way terminal is connected with the alternate path end of described the first on-off element, described the 3rd control end receives the second pulse signal, and the 6th path terminal receives the second reference voltage.Described the 4th on-off element comprises the 7th path terminal, the 8th path terminal and the 4th control end, and described the 7th path terminal receives low reference voltage, and described the 4th control end receives described the first pulse signal.Described the 5th on-off element comprises the 9th path terminal, the tenth path terminal and the 5th control end, described the 9th path terminal is connected with the four-way terminal of described second switch element, described the 5th control end receives described the second pulse signal, and described the tenth path terminal receives described low reference voltage.Described the 6th on-off element comprises the 11 path terminal, the 12 path terminal and the 6th control end, and described the 6th control end receives the second clock signal.Described the 7th on-off element comprises the tenth threeway terminal, the tenth four-way terminal and the 7th control end, described the tenth threeway terminal is connected with the 12 path terminal of described the 6th on-off element, described the tenth four-way terminal receives described low reference voltage, and described the 7th control end is connected with the alternate path end of described the first on-off element.Described the 8th on-off element comprises the tenth five-way terminal, the 16 path terminal and the 8th control end, described the tenth five-way terminal is connected with the four-way terminal of described second switch element, described the 16 path terminal receives described low reference voltage, and described the 8th control end is connected with the 12 path terminal of described the 6th on-off element.Wherein, described the first pulse signal that the second level and above drive element of the grid receive is the upper level gate drive signal that upwards differs the drive element of the grid output of one-level, described the second pulse signal that the first order receives to the drive element of the grid of penultimate stage is the next stage gate drive signal that differs the drive element of the grid output of one-level downwards, the 3rd clock signal that the 11 path terminal of the 6th on-off element of described the first driver module receives is contrary with the current potential of the 4th clock signal that the 11 path terminal of the 6th on-off element of described the second driver module receives.
In gate driver circuit of the present invention, first and second driver module is all exported gate drive signal, not only improve the driving force of gate driver circuit, and its burning voltage module intermittent work, improve the serviceable life of gate driver circuit, and the risk abnormal because of threshold voltage shift, good stability are reduced.
By the detailed description below with reference to accompanying drawing, it is obvious that other side of the present invention and feature become.But it should be known that the only object design for explaining of accompanying drawing, rather than as the restriction of scope of the present invention, this is because it should be with reference to additional claim.Should also be appreciated that, unless otherwise noted, the unnecessary accompanying drawing of drawing to scale, they only try hard to illustrate conceptually structure described herein and flow process.
Accompanying drawing explanation
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Fig. 1 is the electrical block diagram of the every one-level drive element of the grid in the gate driver circuit of first embodiment of the invention.
Fig. 2 is the sequential schematic diagram of the every one-level drive element of the grid in the gate driver circuit of first embodiment of the invention.
Fig. 3 is the structural representation of the every one-level drive element of the grid in the gate driver circuit of second embodiment of the invention.
Fig. 4 a, 4b, 4c and 4d are that every one-level drive element of the grid of the present invention is at stabilization sub stage and analog result schematic diagram afterwards.
Fig. 5 a and Fig. 5 b are the voltage analog result contrast schematic diagram of the 3rd clock signal CLK_L and node D_L, the 4th clock signal CLK_R and node D_R in every one-level drive element of the grid of the present invention.
Fig. 6 a and Fig. 6 b are the voltage difference analog result contrast schematic diagram of the gate drive signal that receives of the two ends of the gate line that drives of every one-level drive element of the grid of the present invention and prior art.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Although the present invention describes different elements, signal, port, assembly or part with first, second, third, etc. term, these elements, signal, port, assembly or part are not subject to the restriction of these terms.These terms are only for an element, signal, port, assembly or part and another element, signal, port, assembly or part are made a distinction.In the present invention, element, port, assembly or part and another element, port, assembly or part " being connected ", " connection ", can be understood as direct electric connection, or also can be understood as the indirect electric connection that has intermediary element.Unless otherwise defined, otherwise all terms used in the present invention (comprising technical term and scientific terminology) have the meaning of conventionally understanding with those skilled in the art.
Gate driver circuit of the present invention (also referred to as shift register) comprises multistage drive element of the grid (also referred to as shifting deposit unit), the drive element of the grid of every one-level respectively with the corresponding electric connection of every a line gate line on display panel, thereby gate drive signal Gn is sequentially successively applied on every row gate line, and the annexation between drive element of the grid will elaborate hereinafter.
The first embodiment
Fig. 1 is the electrical block diagram of the every one-level drive element of the grid in the gate driver circuit of first embodiment of the invention, and every one-level drive element of the grid is used for exporting one-level gate drive signal, to drive respectively a corresponding gate line on display panel.The present embodiment gate driver circuit, comprises multistage drive element of the grid as shown in Figure 1, and drive element of the grid shown in Fig. 1 is used for exporting gate drive signal Gn, and in order to drive a corresponding gate line on display panel.Every grade of drive element of the grid comprises the first driver module 10_L and the second driver module 10_R, the first driver module 10_L and the second driver module 10_R are positioned at corresponding gate line two ends, all for exporting gate drive signal Gn, to drive pull-up resistor Rload, load capacitance Cload, and the first driver module 10_L and the second driver module 10_R alternately open in two adjacent frames, reduce the working time of the first driver module 10_L or the second driver module 10_R, improved the driving force of gate driver circuit.
Particularly, the first driver module 10_L and the second driver module 10_R include the first on-off element M1, second switch element M2, the 3rd on-off element M3, the 4th on-off element M4, the 5th on-off element M5, the 6th on-off element M6, the 7th on-off element M7, the 8th on-off element M8, the connected mode of on-off element M1-M8 in its first driver module 10_L is similar to the connected mode of the on-off element M1-M8 in the second driver module 10_R, that difference is only that one of them path terminal of the 6th on-off element M6 of the first driver module 10_L receives is the 3rd clock signal CLK_L, and that one of them path terminal reception of the 6th on-off element M6 of the second driver module 10_R is the 4th clock signal CLK_R.
Wherein, the first on-off element M1 comprises the first path terminal, alternate path end and the first control end, the first path terminal receives the first reference voltage VDF, and the first control end receives the upper level gate drive signal Gn-1 that drive element of the grid that the first pulse signal upwards differ one-level is exported.Second switch element M2 comprises threeway terminal, four-way terminal and the second control end, three-way termination is received the first clock signal CLK1, the second control end is connected with the alternate path end of the first on-off element M1 and is connected with the four-way terminal of second switch element M2 by the first capacitor C 1, four-way terminal output gate drive signal Gn.The 3rd on-off element M3 comprises five-way terminal, the 6th path terminal and the 3rd control end, and five-way terminal is connected with the alternate path end of the first on-off element M1, and the 3rd control end receives the second pulse signal, and the 6th path terminal receives the second reference voltage VDB.
The 4th on-off element M4 comprises the 7th path terminal, the 8th path terminal and the 4th control end, and the 7th path terminal receives low reference voltage VGL, and the 4th control end receives the first pulse signal Gn-1.The 5th on-off element M5 comprises the 9th path terminal, the tenth path terminal and the 5th control end, the 9th path terminal is connected with the four-way terminal of second switch element M2, the 5th control end receives the next stage gate drive signal Gn+1 that drive element of the grid that the second pulse signal differ one-level is downwards exported, and the tenth path terminal receives low reference voltage VGL.The 6th on-off element M6 comprises the 11 path terminal, the 12 path terminal and the 6th control end, and the 6th control end receives the second clock signal CLK2.The 7th on-off element M7 comprises the tenth threeway terminal, the tenth four-way terminal and the 7th control end, the tenth threeway terminal is connected with the 12 path terminal of the 6th on-off element M6, and the tenth four-way terminal receives low reference voltage VGL, and the 7th control end is connected with the alternate path end of the first on-off element M1.The 8th on-off element M8 comprises the tenth five-way terminal, the 16 path terminal and the 8th control end, the tenth five-way terminal is connected with the four-way terminal of second switch element M2, the 16 path terminal receives low reference voltage VGL, and the 8th control end is connected with the 12 path terminal of the 6th on-off element M6.Wherein, the 6th on-off element M6, the 7th on-off element M7 and the 8th on-off element M8 have formed the first stable module.
Suppose that the present embodiment drive element of the grid is n level drive element of the grid, wherein, n >=2, the gate drive signal of its output is Gn, its first pulse signal receiving for the upper level gate drive signal that upwards differs the drive element of the grid of one-level and export be Gn-1, its second pulse signal receiving for the next stage gate drive signal that differs the drive element of the grid of one-level downwards and export be Gn+1.Because first order drive element of the grid does not upwards differ the drive element of the grid of one-level, afterbody drive element of the grid does not differ the drive element of the grid of one-level downwards, therefore, the first pulse signal that first order drive element of the grid receives is provided by the first outside source, the first pulse signal that the second level and above drive element of the grid receive is the upper level gate drive signal Gn-1 that upwards differs the drive element of the grid output of one-level, the second pulse signal that every one-level drive element of the grid except afterbody receives is the next stage gate drive signal Gn+1 that differs the drive element of the grid output of one-level downwards, the second pulse signal that the drive element of the grid of afterbody receives is provided by the second outside source.
Wherein, the 3rd clock signal CLK_L that the 11 path terminal of the 6th on-off element M6 of the first driver module 10_L receives is contrary with the current potential of the 4th clock signal CLK_R that the 11 path terminal of the 6th on-off element M6 of the second driver module 10_R receives, only has one of them conducting to control the 8th on-off element M8 of the first driver module 10_L or the 8th on-off element M8 of the second driver module 10_R at one time, control the stabilizing circuit of the first driver module 10_L and the stabilizing circuit of the second driver module 10_R according to the 3rd clock signal CLK_L and the 4th clock signal CLK_R intermittent work, thereby make the gate drive signal of every grade of drive element of the grid output stable.
In the present embodiment, the 3rd clock signal CLK_L is high level in the time that display panel shows odd-numbered frame picture, in the time that display panel shows even frame picture, is low level.The 4th clock signal CLK_R is high level in the time that display panel shows even frame picture, in the time that display panel shows odd-numbered frame picture, is low level.Therefore, in the time that display panel shows odd-numbered frame picture, the stabilizing circuit work of the first driver module 10_L, in the time that display panel shows even frame picture, the stabilizing circuit work of the second driver module 10_R, so that the gate drive signal of every grade of drive element of the grid output is stable.
In other embodiments, also can be: the 3rd clock signal CLK_L is high level in the time that display panel shows even frame picture, in the time that display panel shows odd-numbered frame picture, it is low level, the 4th clock signal CLK_R is low level in the time that display panel shows even frame picture, in the time that display panel shows odd-numbered frame picture, is high level.Therefore, in the time that display panel shows even frame picture, the stabilizing circuit work of the first driver module 10_L, in the time that display panel shows odd-numbered frame picture, the stabilizing circuit work of the second driver module 10_R, so that the gate drive signal of every grade of drive element of the grid output is stable.
In one embodiment of the present invention, the first capacitor C 1 is the stray capacitance of second switch element M2.What certainly it will be appreciated by those skilled in the art that is, also can between the second control end of second switch element M2 and four-way terminal, separate, stored electric capacity be set, now, the first capacitor C 1 is stray capacitance and the separate, stored electric capacity sum of second switch element M2, with promote the first capacitor C 1 on draw effect, can reduce second switch element M2 because the capacitance coupling effect that the first clock signal CLK1 saltus step causes simultaneously.
In one embodiment of the present invention, first on-off element to the eight on-off element M1～M8 are N-type transistor.The first control end to the eight control ends are grid.The five-way terminal of the first path terminal of the first on-off element M1, the threeway terminal of second switch element M2, the 3rd on-off element M3, the 7th path terminal of the 4th on-off element M4, the 9th path terminal of the 5th on-off element M5, the 11 path terminal of the 6th on-off element M6, the tenth threeway terminal of the 7th on-off element M7, the tenth five-way terminal of the 8th on-off element M8 are drain electrode.The 6th path terminal of the alternate path end of the first on-off element M1, the four-way terminal of second switch element M2, the 3rd on-off element M3, the 8th path terminal of the 4th on-off element M4, the tenth path terminal of the 5th on-off element M5, the 12 path terminal of the 6th on-off element M6, the tenth four-way terminal of the 7th on-off element M7, the 16 path terminal of the 8th on-off element M8 are source electrode.
Certainly, it will be appreciated by persons skilled in the art that first on-off element to the eight on-off element M1～M8 also can adopt other on-off element and realize for example P transistor npn npn.Introduce particularly the specific embodiment of the present invention and principle of work thereof take first on-off element to the eight on-off element M1～M8 as N-type transistor as example below.
Refer to Fig. 2, it is the sequential schematic diagram of the drive element of the grid of the first embodiment, and please refer to Fig. 1 and Fig. 2, the 4th clock signal CLK_R is high level in the time that display panel shows odd-numbered frame picture, in the time that display panel shows even frame picture, is low level.That is to say, the 3rd clock signal CLK_L that the 11 path terminal of the 6th on-off element M6 of the first driver module 10_L receives is contrary with the current potential of the 4th clock signal CLK_R that the 11 path terminal of the 6th on-off element M6 of the second driver module 10_R receives, to control the 8th one of them conducting of on-off element M8 of the 8th on-off element M8 and the second driver module 10_R of the first driver module 10_L, control the stabilizing circuit of the first driver module 10_L and the stabilizing circuit of the second driver module 10_R according to the variation intermittent work of the frame number of display panel demonstration, be applied in the duration of positive voltage or negative voltage to shorten the grid of the on-off element in every grade of grid unit, reduce the skew of the threshold voltage of on-off element, thereby make the gate drive signal of every grade of drive element of the grid output stable.
Wherein, the first reference voltage VDF is contrary with the current potential of the second reference voltage VDB.In one embodiment of the present invention, the first reference voltage VDF is high voltage, and the second reference voltage VDB is low-voltage.
The course of work of every one-level drive element of the grid be divided into pre-charging stage, on draw stage, drop-down stage, 4 stages of stabilization sub stage:
First stage is pre-charging stage: the upper level gate drive signal Gn-1 that upwards differs the drive element of the grid output of one-level is high level, the first on-off element M1 and the equal conducting of the 4th on-off element M4, because the second reference voltage VDF is high voltage, node Q is precharged by the first on-off element M1 of conducting, second switch element M2 conducting, due to the first clock signal CLK1 now be low level, the gate drive signal Gn of drive element of the grid output at the corresponding levels maintains electronegative potential by the 4th on-off element M4 and the second switch element M2 of conducting.
Subordinate phase is drawn the stage: the level of the first clock signal CLK1 is during by low uprising, owing to being precharged at pre-charging stage node Q, and therefore second switch element M2 conducting.Due to the conducting of second switch element M2, the voltage of the output terminal Gn of drive element of the grid is drawn high by the high level of the first clock signal CLK1, and due to the boot strap of the first capacitor C 1, along with the rising of the voltage of drive element of the grid output terminal, it can make the voltage of node Q further be drawn high, and further drawing high of node Q place voltage, makes second switch element M2 conducting ground more abundant, thereby the voltage of drive element of the grid output terminal is further drawn high.Because node Q is noble potential, therefore, the 7th on-off element M7 conducting, the voltage of node D_L and node D_R is low level, and the 8th on-off element M8 is in cut-off state.
It should be noted that, in the present invention, can directly adopt the stray capacitance of second switch element M2 as the first capacitor C 1, or draw effect on promoting, can also between the second control end of second switch element M2 and four-way terminal, separate, stored electric capacity be set, wherein, the stray capacitance of this separate, stored electric capacity and second switch element M2 is in parallel and jointly as the first capacitor C 1, and the first capacitor C 1 equals the stray capacitance of second switch element M2 and memory capacitance sum independently.
Phase III is the drop-down stage: the gate drive signal Gn+1 that differs the next stage of the drive element of the grid output of one-level downwards becomes high level from low level, the 3rd on-off element M3 and the 5th on-off element M5 conducting, because the second reference voltage VDB is low-voltage, node Q is pulled to electronegative potential by the 3rd on-off element M3 of conducting, and the gate drive signal Gn of drive element of the grid output at the corresponding levels is dragged down by the 5th on-off element M5 of conducting.
Fourth stage is the stabilization sub stage: in the time of the drop-down stage, the gate drive signal Gn at the corresponding levels that drive element of the grid at the corresponding levels is exported has been pulled low to low level, therefore, within the follow-up time, it is the stabilization sub stage, need to make gate drive signal Gn at the corresponding levels maintain low level, thereby obtain desirable waveform.But, because the first clock signal CLK1 is clock signal, its within the follow-up time (after being the stabilization sub stage) also can ceaselessly produce pulse, the gate drive signal Gn of the output of meeting to drive element of the grid at the corresponding levels exerts an influence, in order to eliminate these impacts, the embodiment of the present invention utilizes on-off element M6-M8 to improve.
Particularly, within the follow-up time, when the first clock signal CLK1 is when low level becomes high level, node Q can produce noise because of the stray capacitance coupling between the grid of second switch element M2 and drain electrode, the noise of node Q can make second switch element M2 have conducting to a certain degree, the high level of the first clock signal CLK1 charges to the output terminal of drive element of the grid at the corresponding levels, draws high the voltage of drive element of the grid output terminal at the corresponding levels.Simultaneously, because the second clock signal CLK2 also can become high level from low level, that is to say, the 6th on-off element M6 conducting, and because the current potential of the 11 the 3rd clock signal CLK_L of path terminal reception of the 6th on-off element M6 of the first driver module 10_L and the 4th clock signal CLK_R of the 11 path terminal reception of the 6th on-off element M6 of the second driver module 10_R is contrary all the time, therefore, one of them voltage of node D_L and node D_R is high level, thereby the 8th one of them conducting of on-off element M8 of the 8th on-off element M8 of the first driver module 10_L or the second driver module 10_R, to drag down the gate drive signal Gn of the first driver module 10_L and the second driver module 10_R output in drive element of the grid at the corresponding levels, even and if the second clock signal CLK2 becomes low level from high level, owing to being high level at one of them voltage of node D_L and node D_R on last stage, therefore one of them still conducting of the 8th on-off element M8 of the 8th on-off element M8 of the first driver module 10_L or the second driver module 10_R, to drag down the gate drive signal Gn of the first driver module 10_L and the second driver module 10_R output in drive element of the grid at the corresponding levels.That is to say, the stabilizing circuit energy intermittent work of the stabilizing circuit of the first driver module 10_L and the second driver module 10_R, be applied in the duration of positive voltage or negative voltage to shorten the grid of the on-off element in the first driver module 10_L or the second driver module 10_R, reduce the skew of threshold voltage of on-off element, so that the gate drive signal Gn of the first driver module 10_L and the second driver module 10_R output is all stable in every grade of drive element of the grid.
Therefore, although be subject to the impact of the first clock signal CLK1 high level, the voltage at the output terminal Gn place of node Q and drive element of the grid at the corresponding levels can be by drawing high to a certain degree, but, due to the effect of on-off element M6-M8, it can drag down the voltage of the voltage of node Q and the output terminal Gn of drive element of the grid at the corresponding levels, and then makes the gate drive signal Gn of the first driver module 10_L and the second driver module 10_R output in drive element of the grid at the corresponding levels all can maintain low level.
In like manner, when the first clock signal CLK1 second and pulse subsequently the principle during by high step-down with when the first clock signal CLK1 is second and pulse subsequently during by low uprising, the principle that the voltage of the gate drive signal Gn of node Q, the first driver module 10_L and the second driver module 10_R output is pulled down to low reference voltage VGL is identical, does not repeat them here.
By seeing the description of the present embodiment sequential control, drive element of the grid the first driver module 10_L and the second driver module 10_R of the present embodiment all can export gate drive signal Gn, to drive pull-up resistor Rload, load capacitance Cload, thereby improve the driving force of gate driver circuit.In addition, because the current potential of the 11 the 3rd clock signal CLK_L of path terminal reception of the 6th on-off element M6 of the first driver module 10_L and the 4th clock signal CLK_R of the 11 path terminal reception of the 6th on-off element M6 of the second driver module 10_R is contrary all the time, therefore, the 8th one of them conducting of on-off element M8 of the 8th on-off element M8 of the first driver module 10_L or the second driver module 10_R, to drag down the gate drive signal Gn of the first driver module 10_L and the second driver module 10_R output in drive element of the grid at the corresponding levels, that is to say, the stabilizing circuit intermittent work of the stabilizing circuit of the first driver module 10_L and the second driver module 10_R, be applied in the duration of positive voltage or negative voltage to shorten the grid of the on-off element in the first driver module 10_L or the second driver module 10_R, improve the serviceable life of gate driver circuit, and reduce the risk abnormal because of threshold voltage shift, good stability.
The second embodiment
Fig. 3 is the structural representation of the every one-level drive element of the grid in the gate driver circuit of second embodiment of the invention, and every one-level drive element of the grid is used for exporting one-level gate drive signal, to drive respectively a corresponding gate line on display panel.As shown in Figure 3, in the present embodiment, the first driver module 10_L ' and the second driver module 10_R ' also include the 9th on-off element M9, the tenth on-off element M10, the 11 on-off element M11 and twelvemo and close element M12.The 9th on-off element M9 comprises the 17 path terminal, the 18 path terminal and the 9th control end, and the 17 path and the 9th control end receive the first clock signal CLK1.The tenth on-off element M10, comprise the 19 path terminal, the 20 path terminal and the tenth control end, the 19 path terminal is connected with the 18 path terminal of the 9th on-off element M9, and the tenth control end is connected with the second control end of the first on-off element, and the 20 path terminal receives low reference voltage VGL.The 11 on-off element M11, comprise the 21 path terminal, the 22 path terminal and the 11 control end, the 21 path terminal is connected with the alternate path end of the first on-off element, the 22 path terminal receives low reference voltage VGL, and the 11 control end is connected with the 18 path terminal of the 9th on-off element M9.Twelvemo is closed element M12, comprise the 20 threeway terminal, the 20 four-way terminal and the 12 control end, the 20 threeway terminal is connected with the four-way terminal of second switch element, the 20 four-way terminal receives low reference voltage VGL, and the 12 control end is connected with the 18 path of the 9th on-off element M9.
The course of work of every one-level drive element of the grid is as shown in Figure 3 similar to the course of work principle of every one-level drive element of the grid as shown in Figure 1, and its difference is:
It is the stabilization sub stage in fourth stage, in order to eliminate its pulse that (after being the stabilization sub stage) ceaselessly produces within the follow-up time due to the first clock signal CLK1, and the impact of the stability of the gate drive signal Gn of output on drive element of the grid at the corresponding levels, the present embodiment not only utilizes on-off element M6-M8, also utilizes the 9th on-off element to the twelvemo to close element M9-M12 and improves.
Particularly, within the follow-up time, when the first clock signal CLK1 is when low level becomes high level, node Q can be produced noise by the stray capacitance coupling between the grid of second switch element M2 and drain electrode, second switch element M2 conducting, the high level of the first clock signal CLK1 charges to the output terminal of drive element of the grid at the corresponding levels, draws high the voltage of drive element of the grid output terminal at the corresponding levels.Due to when the first clock signal CLK1 is when low level becomes high level, the 9th on-off element M9 conducting, the voltage at node P place is pulled up to high voltage, the 11 on-off element M11 and twelvemo are closed the equal conducting of element M12, node Q is dragged down by the 11 on-off element M11 of conducting, and the voltage of the gate drive signal Gn of drive element of the grid output closes element M12 by the twelvemo of conducting and dragged down.On-off element M6-M8 is that the principle of work of stabilization sub stage is identical with the principle of work of the gate driver circuit described in Fig. 1 in fourth stage, does not repeat them here.
Therefore, although be subject to the impact of the first clock signal CLK1 high level, the voltage at the output terminal Gn place of node Q and drive element of the grid at the corresponding levels can be drawn high, but, due to the effect of on-off element M6-M8 and M9-M12, it can drag down the voltage of the gate drive signal Gn of the first driver module 10_L and the second driver module 10_R output in the voltage of node Q and drive element of the grid at the corresponding levels, and then makes the gate drive signal Gn of the first driver module 10_L and the second driver module 10_R output in drive element of the grid at the corresponding levels all can maintain low level.
In like manner, when the first clock signal CLK1 second and pulse subsequently the principle during by high step-down with when the first clock signal CLK1 is second and pulse subsequently during by low uprising, the principle that the voltage of node Q and gate drive signal Gn at the corresponding levels is pulled down to low reference voltage VGL is identical, does not repeat them here.
Fig. 4 a, 4b, 4c, 4d are that every one-level drive element of the grid of the present invention is at stabilization sub stage and analog result schematic diagram afterwards.Please refer to Fig. 1, Fig. 3 and Fig. 4 a-4d, Fig. 4 a is that in the first driver module 10_L, 10_L ', node D_L is stabilization sub stage and analog result schematic diagram afterwards in fourth stage.Fig. 4 b is that in the second driver module 10_R, 10_R ', node D_R is stabilization sub stage and analog result schematic diagram afterwards in fourth stage.Fig. 4 c is that the gate drive signal Gn of the first driver module 10_L, 10_L ' output is stabilization sub stage and analog result afterwards in fourth stage.Fig. 4 d is that the gate drive signal Gn of the second driver module 10_R, 10_R ' output is stabilization sub stage and analog result afterwards in fourth stage.As can be seen from Figure 4, node D_L and node D_R are alternately high level, that is to say, the 8th on-off element M8 intermittent conduction of the first driver module 10_L, 10_L ' and the second driver module 10_R, 10_R ', thus make the gate drive signal Gn of the first driver module 10_L, 10_L ' and the second driver module 10_R, 10_R ' output all can keep stable.
In addition, because can making the 7th on-off element M7, the noise of node Q has conducting to a certain degree, and node D_L(D_R) there is certain leaky by the 7th on-off element M7 of conducting, thereby cause node D_L(D_R) can not within the time of a frame, maintain needed high level state always, therefore, circuit in the present invention makes CLK2(CLK1 within the time of a frame) in the constantly state of conversion of low and high level, like this, the CLK_L(CLK_R in high level state always in a frame time) can ceaselessly give node D_L(D_R) with high level pulse, make it maintain needed high level state always, and be not subject to effect of leakage.As CLK2(CLK1) in the time of the continuous state of changing of low and high level, due to the impact of the stray capacitance of the 6th on-off element M6, do like this and make node D_L(D_R simultaneously) voltage can produce certain noise phenomenon, as Fig. 4 a(Fig. 4 b) as shown in, but node D_L(D_R) within most times of a frame, be in high level state, can meet the needs of circuit completely, compared to effect of leakage, noise phenomenon is little on circuit impact, can ignore completely.
Fig. 5 a is the voltage analog result contrast schematic diagram of the 3rd clock signal CLK_L and node D_L in every one-level drive element of the grid of the present invention, and Fig. 5 b is that in every one-level drive element of the grid of the present invention, the 4th clock signal CLK_R contrasts schematic diagram with the voltage analog result of node D_R.As shown in Fig. 5 a, 5b, node D_L is synchronizeed with the 3rd clock signal CLK_L and the 4th clock signal CLK_R respectively with the voltage of node D_R, therefore, the voltage of node D_L and node D_R only changes according to the 3rd clock signal CLK_L and the 4th clock signal CLK_R respectively, therefore, can be by adjusting the low and high level size of the 3rd clock signal CLK_L and the 4th clock signal CLK_R, thereby make the threshold voltage at dwell period of the 8th on-off element M8 obtain compensation, and then further reduce the threshold voltage shift amount of gate driver circuit.
In addition, because can making the 7th on-off element M7, the noise of node Q has conducting to a certain degree, and node D_L(D_R) there is certain leaky by the 7th on-off element M7 of conducting, thereby cause node D_L(D_R) can not within the time of a frame, maintain needed high level state always, therefore, circuit in the present invention makes CLK2(CLK1 within the time of a frame) in the constantly state of conversion of low and high level, like this, the CLK_L(CLK_R in high level state always in a frame time) can ceaselessly give node D_L(D_R) with high level pulse, make it maintain needed high level state always, and be not subject to effect of leakage.As CLK2(CLK1) in the time of the continuous state of changing of low and high level, due to the impact of the stray capacitance of the 6th on-off element M6, do like this and make node D_L(D_R simultaneously) voltage can produce certain noise phenomenon, as Fig. 5 a(Fig. 5 b) as shown in, but node D_L(D_R) within most times of a frame, be in high level state, can meet the needs of circuit completely, compared to effect of leakage, noise phenomenon is little on circuit impact, can ignore completely.
Fig. 6 a and Fig. 6 b are the voltage difference analog result contrast schematic diagram of the gate drive signal that receives of the two ends of the gate line that drives of every one-level drive element of the grid of the present invention and prior art.Wherein, Fig. 6 a is the voltage difference analog result schematic diagram of the gate drive signal that receives of the load at the two ends of the corresponding gate line that drives of every one-level drive element of the grid of the second embodiment of the present invention, and Fig. 6 b is the voltage difference analog result schematic diagram of the gate drive signal that receives of the load at the two ends of the corresponding gate line that drives of every one-level drive element of the grid of the prior art.Please refer to Fig. 1, shown in Fig. 3 and Fig. 6 a, every one-level drive element of the grid of the present invention adopts the first identical driver module 10_L of structure, 10_L ' and the second driver module 10_R, 10_R ' exports respectively the two ends of gate drive signal Gn to gate line, the load connecting with driving grid line, therefore, in the every a line pixel cell being driven by same gate line, first pixel cell and last pixel cell are also that the voltage difference of the gate drive signal Gn that receives of the two ends of gate line is about 0.2 volt (V), although the impact of ordering due to Q, can there is certain noise problem in the voltage difference of gate drive signal Gn, but all in the scope in 0.2 volt (V).And the drive element of the grid of prior art is only inputted gate drive signal from one end of gate line, and stabilizing circuit is always in high level, therefore, as shown in Figure 6 b, in the every a line pixel cell being driven by same gate line, due to the decay of gate drive signal, the about 2.5V of voltage difference of the gate drive signal that on this row, first pixel cell receives with last pixel cell, it is obviously greater than 0.2V.Therefore, gate driver circuit of the present invention can reduce the voltage differences of every row pixel cell because of the gate drive signal Gn that receives, and causes the risk of picture inequality.
In sum, the first driver module 10_L in gate driver circuit of the present invention, 10_L ' and the second driver module 10_R, 10_R ' all can export gate drive signal Gn, to drive pull-up resistor Rload, load capacitance Cload, and the first driver module 10_L, 10_L ' and the second driver module 10_R, 10_R ' alternately opens in two adjacent frames, reduce by the first driver module 10_L, 10_L ' or the second driver module 10_R, the working time of 10_R ', thereby improve the driving force of gate driver circuit, and the two ends that reduced every row pixel cell are because of the voltage differences of the gate drive signal Gn that receives, and the risk of the picture inequality causing.In addition, due to the first driver module 10_L, the 3rd clock signal CLK_L and the second driver module 10_R that the 11 path terminal of the 6th on-off element M6 of 10_L ' receives, the current potential of the 4th clock signal CLK_R that the 11 path terminal of the 6th on-off element M6 of 10_R ' receives is contrary all the time, therefore, the 8th on-off element M8 of the first driver module 10_L or the second driver module 10_R, the 8th one of them conducting of on-off element M8 of 10_R ', to drag down the first driver module 10_L in drive element of the grid at the corresponding levels, 10_L ' and the second driver module 10_R, the gate drive signal Gn of 10_R ' output, that is to say, the first driver module 10_L, the stabilizing circuit intermittent work of the stabilizing circuit of 10_L ' and the second driver module 10_R, be applied in the duration of positive voltage or negative voltage to shorten the grid of the on-off element in the first driver module 10_L or the second driver module 10_R, and because CLK_L and CLK_R are independent of gate driver circuit clock signal, can take different low and high level settings according to threshold voltage drift situation, improve the serviceable life of gate driver circuit, and reduce the risk abnormal because of threshold voltage shift, good stability.
Applied specific case herein gate driver circuit of the present invention and embodiment are set forth, the explanation of above embodiment is just for helping to understand method of the present invention and core concept thereof; Meanwhile, for one of ordinary skill in the art, according to thought of the present invention; all will change in specific embodiments and applications; to sum up, this description should not be construed as limitation of the present invention, and protection scope of the present invention should be as the criterion with appended claim.
Claims (10)
1. a gate driver circuit, comprise multistage drive element of the grid, every grade of drive element of the grid is for driving respectively a corresponding gate line on display panel, it is characterized in that, every grade of drive element of the grid comprises the first driver module and the second driver module, and the first driver module and the second driver module include:
The first on-off element, comprises the first path terminal, alternate path end and the first control end, and described the first path terminal receives the first reference voltage, and described the first control end receives the first pulse signal;
Second switch element, comprise threeway terminal, four-way terminal and the second control end, described three-way termination is received the first clock signal, described the second control end is connected with the alternate path end of described the first on-off element and is connected with the four-way terminal of second switch element by the first electric capacity, described four-way terminal output gate drive signal;
The 3rd on-off element, comprise five-way terminal, the 6th path terminal and the 3rd control end, described five-way terminal is connected with the alternate path end of described the first on-off element, and described the 3rd control end receives the second pulse signal, and the 6th path terminal receives the second reference voltage;
The 4th on-off element, comprises the 7th path terminal, the 8th path terminal and the 4th control end, and described the 7th path terminal receives low reference voltage, and described the 4th control end receives described the first pulse signal;
The 5th on-off element, comprise the 9th path terminal, the tenth path terminal and the 5th control end, described the 9th path terminal is connected with the four-way terminal of described second switch element, and described the 5th control end receives described the second pulse signal, and described the tenth path terminal receives described low reference voltage;
The 6th on-off element, comprises the 11 path terminal, the 12 path terminal and the 6th control end, and described the 6th control end receives the second clock signal;
The 7th on-off element, comprise the tenth threeway terminal, the tenth four-way terminal and the 7th control end, described the tenth threeway terminal is connected with the 12 path terminal of described the 6th on-off element, described the tenth four-way terminal receives described low reference voltage, and described the 7th control end is connected with the alternate path end of described the first on-off element;
The 8th on-off element, comprise the tenth five-way terminal, the 16 path terminal and the 8th control end, described the tenth five-way terminal is connected with the four-way terminal of described second switch element, described the 16 path terminal receives described low reference voltage, and described the 8th control end is connected with the 12 path terminal of described the 6th on-off element;
Wherein, described the first pulse signal that the second level and above drive element of the grid receive is the upper level gate drive signal that upwards differs the drive element of the grid output of one-level, described the second pulse signal that the first order receives to the drive element of the grid of penultimate stage is the next stage gate drive signal that differs the drive element of the grid output of one-level downwards, the 3rd clock signal that the 11 path terminal of the 6th on-off element of described the first driver module receives is contrary with the current potential of the 4th clock signal that the 11 path terminal of the 6th on-off element of described the second driver module receives.
2. gate driver circuit as claimed in claim 1, is characterized in that, the first driver module and the second driver module also include:
The 9th on-off element, comprises the 17 path terminal, the 18 path terminal and the 9th control end, and described the 17 path and described the 9th control end receive described the first clock signal;
The tenth on-off element, comprise the 19 path terminal, the 20 path terminal and the tenth control end, described the 19 path terminal is connected with the 18 path terminal of described the 9th on-off element, described the tenth control end is connected with the second control end of described the first on-off element, and described the 20 path terminal receives described low reference voltage;
The 11 on-off element, comprise the 21 path terminal, the 22 path terminal and the 11 control end, described the 21 path terminal is connected with the alternate path end of described the first on-off element, described the 22 path terminal receives described low reference voltage, and described the 11 control end is connected with the 18 path terminal of described the 9th on-off element; And
Twelvemo is closed element, comprise the 20 threeway terminal, the 20 four-way terminal and the 12 control end, described the 20 threeway terminal is connected with the four-way terminal of described second switch element, described the 20 four-way terminal receives described low reference voltage, and described the 12 control end is connected with the 18 path of described the 9th on-off element.
3. gate driver circuit as claimed in claim 1, it is characterized in that, described the 3rd clock signal is high level in the time that described display panel shows odd-numbered frame picture, in the time that described display panel shows even frame picture, it is low level, described the 4th clock signal is high level in the time that described display panel shows even frame picture, in the time that described display panel shows odd-numbered frame picture, is low level.
4. gate driver circuit as claimed in claim 1, it is characterized in that, described the 3rd clock signal is high level in the time that described display panel shows even frame picture, in the time that described display panel shows odd-numbered frame picture, it is low level, described the 4th clock signal is high level in the time that described display panel shows odd-numbered frame picture, in the time that described display panel shows even frame picture, is low level.
5. gate driver circuit as claimed in claim 1, is characterized in that, described the first electric capacity is the stray capacitance between the second control end and the four-way terminal of second switch element.
6. gate driver circuit as claimed in claim 1, it is characterized in that, between the second control end of described second switch element and four-way terminal, be provided with separate, stored electric capacity, described the first electric capacity is stray capacitance and the described separate, stored electric capacity sum between the second control end and the four-way terminal of second switch element.
7. gate driver circuit as claimed in claim 1, is characterized in that, described the first on-off element to the eight on-off elements are N-type transistor.
8. gate driver circuit as claimed in claim 7, it is characterized in that, described the first control end to described the tenth control end is grid, described first path terminal of described the first on-off element, the threeway terminal of described second switch element, the five-way terminal of described the 3rd on-off element, the 7th path terminal of described the 4th on-off element, the 9th path terminal of described the 5th on-off element, the 11 path terminal of described the 6th on-off element, the tenth threeway terminal of described the 7th on-off element, the tenth five-way terminal of described the 8th on-off element is drain electrode, and the alternate path end of described the first on-off element, the four-way terminal of described second switch element, the 6th path terminal of described the 3rd on-off element, the 8th path terminal of described the 4th on-off element, the tenth path terminal of described the 5th on-off element, the 12 path terminal of described the 6th on-off element, the tenth four-way terminal of described the 7th on-off element, the 16 path terminal of described the 8th on-off element is source electrode.
9. gate driver circuit as claimed in claim 1, is characterized in that, to described the 8th on-off element, at least one of them is P transistor npn npn to described the first on-off element.
10. gate driver circuit as claimed in claim 2, is characterized in that, described the 9th on-off element to described twelvemo is closed element and is N-type transistor.
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