CN101587700B - Liquid crystal display and method for driving same - Google Patents
Liquid crystal display and method for driving same Download PDFInfo
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Abstract
The embodiment of the invention provides a liquid crystal display and method for driving same. The liquid crystal display comprises a grid drive circuit, a control circuit and a charge sharing circuit. The control circuit provides a charge sharing signal according to the parasitic capacitance values of a first and second output ends of the grid drive circuit. The charge sharing circuit shares charges with a first and second clock signals based on the charge sharing signal to generate a third and fourth clock signals corresponding to each other, wherein the third clock signal comprises the waveform drop edge from a high potential to a first potential, while the fourth clock signal comprises the waveform drop edge from high potential to a second potential. The grid drive circuit respectively outputs a first and second grid drive signals at the first and second output ends according to the third and fourth clock signals. The flicker can be effectively removed by regulating the shared voltage V<COM> by using the invention.
Description
Technical field
The present invention is relevant to a kind of LCD, refers to a kind of method of improving the LCD of film flicker and driving LCD especially.
Background technology
LCD (liquid crystal display, LCD) have low radiation, volume is little and advantage such as low power consuming, replace traditional cathode-ray tube display (cathode ray tube display gradually, CRT), thereby be widely used in laptop, personal digital assistant (personal digital assistant, PDA), flat-surface television, or on the information products such as mobile phone.The type of drive of conventional liquid crystal is to utilize external source driving circuit (source driver) and gate driver circuit (gate driver) to drive pixel on the panel with display image, developing into gradually in recent years directly is made in driving circuit structure on the display panel, for example gate driver circuit (gate driver) is integrated in liquid crystal panel (gate driver on array, technology GOA).
Please refer to Fig. 1, Fig. 1 is the synoptic diagram of the liquid crystal indicator 100 of an employing GOA technology in the prior art.Liquid crystal indicator 100 comprises one source pole driving circuit 110, a gate driver circuit 120, a sequential control circuit 130, many data line DL
1～DL
m, many gate lines G L
1～GL
n, and a picture element matrix.Picture element matrix comprises a plurality of pixel cell PX, and each pixel cell PX comprises a thin film transistor (TFT) (thin film transistor, TFT) switching TFT, a liquid crystal capacitance C
LCWith a storage capacitors C
ST, be respectively coupled to corresponding data line, corresponding gate line, and a common voltage V
COM Sequential control circuit 130 can produce source electrode drive circuit 110 and the required signal of gate driver circuit 120 runnings, for example initial pulse signal VST and clock signal C K, XCK.Source electrode drive circuit 110 can produce the data drive signal SD corresponding to display image
1～SD
m Gate driver circuit 120 includes multi-stage shift registering units connected in series SR
1～SR
n, its output terminal OUT
1～OUT
nBe respectively coupled to corresponding gate lines G L
1～GL
n, can export the required gate drive signal SG of turn-on transistor switch in regular turn according to clock signal C K, XCK and initial pulse signal VST
1～SG
nIn order to provide enough driving forces, shifting deposit unit SR
1～SR
nGenerally can use large-sized output film transistor.
Please refer to Fig. 2, Fig. 2 is the synoptic diagram of the driving method of prior art liquid crystal indicator 100.Fig. 2 has shown clock signal C K and XCK, initial pulse signal VST, and gate drive signal SG
1～SG
nWaveform.Under ideal case, gate drive signal SG
1～SG
nBe all complete square wave.Therefore, when closing corresponding thin film transistor switch TFT, gate drive signal SG
1～SG
nBe all Δ V at the pressure reduction that its grid caused
GWhen thin film transistor (TFT) TFT closes, pixel electrode is not connected to any voltage source, but be in unsteady (floating) state, this moment pixel electrode around if any variation in voltage arranged, will be coupled to pixel electrode by its stray capacitance, and change its voltage, so can allow be applied to liquid crystal capacitance C
LCWith storage capacitors C
STOn the original setting value of voltage deviation.The variation in voltage amount that this kind causes because of stray capacitance is called feed-trough voltage (feed-through voltage), and it is worth V
FDCan be expressed as:
V
FD＝[C
GD/(C
LC+C
ST+C
GD)]*ΔV
G
Wherein, C
GDRepresent the grid of thin film transistor switch TFT and the stray capacitance between the drain electrode, and Δ V
GThen represent gate drive signal when closing thin film transistor switch TFT at pressure reduction that its grid caused.Feed-trough voltage V
FDCan cause the situation of film flicker (image flicker), because thin film transistor switch TFT can't exist stray capacitance with avoiding, general type of drive can manage to reduce Δ V
GValue, simultaneously again by adjusting the common voltage V of common ends
COMCompensate, so could reduce film flicker effectively.
Please refer to Fig. 3, Fig. 3 is the synoptic diagram of the liquid crystal indicator 200 of an employing GOA technology in the prior art.Liquid crystal indicator 200 comprises one source pole driving circuit 210, a gate driver circuit 220, a sequential control circuit 230, an electric charge sharing circuit 240, many data line DL
1～DL
m, many gate lines G L
1～GL
n, and a picture element matrix.Picture element matrix comprises a plurality of pixel cell PX, and each pixel cell PX comprises a thin film transistor switch TFT, a liquid crystal capacitance C
LCWith a storage capacitors C
ST, be respectively coupled to corresponding data line, corresponding gate line, and a common voltage V
COM Sequential control circuit 230 can produce source electrode drive circuit 110 and the required signal of gate driver circuit 120 runnings, for example initial pulse signal VST, clock signal C K, XCK and output enable signal OE.Source electrode drive circuit 210 can produce the data drive signal SD corresponding to display image
1～SD
mElectric charge sharing circuit 240 can come that clock signal C K and XCK are carried out electric charge according to output enable signal OE to be shared, to produce corresponding clock signal O_CK and O_XCK.Gate driver circuit 220 includes multi-stage shift registering units connected in series SR
1～SR
n, its output terminal OUT
1～OUT
nBe respectively coupled to corresponding gate lines G L
1～GL
n, can export the required gate drive signal SG of turn-on transistor switching TFT in regular turn according to clock signal C K, XCK and initial pulse signal VST
1～SG
nIn order to provide enough driving forces, shifting deposit unit SR
1～SR
nGenerally can use large-sized output film transistor, output terminal OUT
1～OUT
nParasitic capacitance value respectively by C
1～C
nRepresent.
Please refer to Fig. 4, Fig. 4 is the synoptic diagram of the driving method of prior art liquid crystal indicator 200.Fig. 4 has shown clock signal C K, XCK, O_CK and O_XCK, output enable signal OE, initial pulse signal VST, and gate drive signal SG
1～SG
nWaveform.In driving method shown in Figure 4, clock signal C K and XCK tool opposite phase switch between high electronegative potential with a predetermined period, and this predetermined period then determines gate drive signal SG
1～SG
nIn enable the length in cycle.When output enable signal OE tool noble potential, time schedule controller 230 meeting clock signal CK and XCK are to provide corresponding clock signal O_CK and O_XCK; When output enable signal OE tool electronegative potential, time schedule controller 230 stops output, can carry out electric charge between clock signal O_CK and the O_XCK this moment and share, and then reach the effect of top rake in the waveform drop edge.Gate driver circuit 220 is exported the required gate drive signal SG of turn-on transistor switch in regular turn according to clock signal O_CK, O_XCK and initial pulse signal VST again
1～SG
nBecause output enable signal OE incapacitation time length of tool electronegative potential in each cycle is all T, can be to gate drive signal SG
1～SG
nCause identical top rake amplitude.Therefore, when closing corresponding thin film transistor switch TFT, gate drive signal SG
1～SG
nBe all Δ V at the pressure reduction that its grid caused
G'.As previously mentioned, the value of feed-trough voltage is proportional to grid pressure reduction, owing to carry out the grid pressure differential deltap V after electric charge is shared
G' less than not carrying out the grid pressure differential deltap V of electric charge when sharing
GTherefore, can reduce the effect of feed-trough voltage.
Fig. 2 and the signal waveform that Figure 4 shows that under the ideal case, wherein gate drive signal SG
1～SG
nBe all complete square wave, or have the waveform drop edge of identical top rake amplitude.Yet under actual conditions, because shifting deposit unit SR
1～SR
nThe transistorized parasitic capacitance value of interior large scale output film is bigger, and gate driver circuit 120 and 220 is to export every grade of signal in regular turn, so gate drive signal SG
1～SG
nSignaling path length different.In other words, output signals at different levels are at output terminal OUT
1～OUT
nCan run into signal delay in various degree.
Please refer to Fig. 5 a～Fig. 5 c, Fig. 5 a has shown the ideal waveform of each grade gate drive signal in the prior art liquid crystal indicator 100 and 200, and Fig. 5 b has shown first order gate drive signal SG in prior art liquid crystal indicator 100 and 200
1Actual waveform, and Fig. 5 c has shown n level gate drive signal SG in prior art liquid crystal indicator 100 and 200
nActual waveform.Because sequential control circuit 130 or 230 is to output terminal OUT
1Signal transmission path the shortest, output terminal OUT
1The parasitic capacitance value minimum, the waveform rise time and the fall time of signal are the shortest, so gate drive signal SG
1Waveform near ideal square wave (shown in Fig. 5 b left) or waveform drop edge (shown in Fig. 5 b is right-hand) with desirable top rake amplitude, the pressure differential deltap V that when closing corresponding thin film transistor switch TFT, is caused
G1With desirable pressure differential deltap V
GBetween the difference minimum, shown in Fig. 5 b.On the other hand, sequential control circuit 130 or 230 is to output terminal OUT
nSignal transmission path the longest, output terminal OUT
nThe parasitic capacitance value maximum, the waveform rise time and the fall time of signal are the longest, so gate drive signal SG
nWaveform depart from ideal square wave (shown in Fig. 5 c left) most, or the waveform drop edge departs from desirable top rake amplitude (shown in Fig. 5 c is right-hand) most, the pressure differential deltap V that is caused when closing corresponding thin film transistor switch TFT
Gn' and desirable pressure differential deltap V
G' between the difference maximum, shown in Fig. 5 c.
Reduce the grid cross-pressure at prior art driving method shown in Figure 4 with same magnitude, though can reduce the effect of feed-trough voltage, the feed-trough voltage of each pixel cell is difference to some extent still, therefore can't be effectively by adjusting common voltage V
COMEliminate the situation of film flicker.
Summary of the invention
The invention provides a kind of LCD, it comprises a gate driver circuit, be used for producing a first grid drive signal and a second grid drive signal according to one first clock signal or a second clock signal, described gate driver circuit comprises one first output terminal, is used for exporting described first grid drive signal; And one second output terminal, be used for exporting described second grid drive signal; One control circuit, be used for providing a charge sharing signal according to the pairing parasitic capacitance value of described first and second output terminals of described gate driver circuit, and provide one the 3rd clock signal and one the 4th clock signal, the polarity of wherein said third and fourth clock signal is reversed with a predetermined period, and the described third and fourth clock signal tool opposite polarity; Described charge sharing signal comprises one first anergy period and one second anergy period, the described first anergy period is corresponding to the output cycle of described first output terminal, the described second anergy period is corresponding to the output cycle of described second output terminal, and the parasitic capacitance value of described second output terminal is greater than the parasitic capacitance value of described first output terminal, and the length of the described first anergy period is greater than the length of the described second anergy period; An and electric charge sharing circuit, in period described the 3rd clock signal and described the 4th clock signal being carried out electric charge in described first anergy shares to produce described first clock signal, in period described the 3rd clock signal and described the 4th clock signal being carried out electric charge in described second anergy shares to produce described second clock signal, wherein said first clock signal comprises the waveform drop edge of reducing to one first current potential from a noble potential, and described second clock signal comprises the waveform drop edge of reducing to one second current potential from described noble potential.
The present invention provides a kind of method that drives LCD in addition, comprise one first clock signal and a second clock signal are provided, the polarity of wherein said first and second clock signals is reversed with a predetermined period, and the described at one time first and second clock signal tool opposite polarities; Parasitic capacitance value according to one first output terminal correspondence decides a very first time length; Parasitic capacitance value according to one second output terminal correspondence decides one second time span; Wherein, when the parasitic capacitance value of described second output terminal during greater than the parasitic capacitance value of described first output terminal, described very first time length is greater than described second time span; In cycle corresponding to described first output terminal, described first and second clock signals are carried out electric charge and are shared so that one the 3rd clock signal to be provided in described very first time length, wherein said the 3rd clock signal comprises the waveform drop edge of reducing to one first current potential from a noble potential; And in cycle corresponding to described second output terminal, described first and second clock signals are carried out electric charge and are shared so that one the 4th clock signal to be provided in described second time span, wherein said the 4th clock signal comprises the waveform drop edge of reducing to one second current potential from described noble potential.
The present invention can be effectively by adjusting common voltage V
COMEliminate the situation of film flicker.
Description of drawings
Fig. 1 is the synoptic diagram of a liquid crystal indicator in the prior art;
Fig. 2 is the synoptic diagram of the driving method of liquid crystal indicator shown in Figure 1;
Fig. 3 is the synoptic diagram of another liquid crystal indicator in the prior art;
Fig. 4 is the synoptic diagram of the driving method of liquid crystal indicator shown in Figure 3;
Fig. 5 a is the synoptic diagram of each grade gate drive signal ideal waveform in the liquid crystal indicator of Fig. 1 and Fig. 3;
Fig. 5 b is the synoptic diagram of first order gate drive signal actual waveform in the liquid crystal indicator of Fig. 1 and Fig. 3;
Fig. 5 c is the synoptic diagram of n level gate drive signal actual waveform in the liquid crystal indicator of Fig. 1 and Fig. 3;
Fig. 6 is the synoptic diagram of a liquid crystal indicator among the present invention;
Fig. 7 is the synoptic diagram of the driving method of liquid crystal indicator of the present invention;
Fig. 8 is the synoptic diagram of electric charge sharing circuit in one embodiment of the invention.
Drawing reference numeral
C
LCLiquid crystal capacitance DL
1～DL
mData line
C
STStorage capacitors GL
1～GL
nGate line
RS resistance OUT
1～OUT
nOutput terminal
PX pixel cell SR
1～SR
nShifting deposit unit
V
COMCommon voltage TFT thin film transistor switch
330 ASIC circuit SD
1～SD
mData drive signal
OE output enable signal SG
1～SG
nGate drive signal
VCS charge sharing signal 130,230 sequential control circuits
VST initial pulse signal 240,340 electric charge sharing circuits
100,200,300 liquid crystal indicators
110,210,310 source electrode drive circuits
120,220,320 gate driver circuits
CK, XCK, O_CK, O_XCK clock signal
Δ V
G, Δ V
G', Δ V
G1～Δ V
Gn, Δ V
G1', Δ V
Gn' grid pressure reduction
Embodiment
Please refer to Fig. 6, Fig. 6 is the synoptic diagram of the liquid crystal indicator 300 of an employing GOA technology among the present invention.Liquid crystal indicator 300 comprises one source pole driving circuit 310, a gate driver circuit 320, an ASIC(Application Specific Integrated Circuit) (application-specific integrated circuit, ASIC) circuit 330, an electric charge sharing circuit 340, many data line DL
1～DL
m, many gate lines G L
1～GL
n, and a picture element matrix.Picture element matrix comprises a plurality of pixel cell PX, and each pixel cell PX comprises a thin film transistor switch TFT, a liquid crystal capacitance C
LCWith a storage capacitors C
ST, be respectively coupled to corresponding data line, corresponding gate line, and a common voltage V
COMSource electrode drive circuit 310 can produce the data drive signal SD corresponding to display image
1～SD
m Gate driver circuit 320 includes multi-stage shift registering units connected in series SR
1～SR
n, its output terminal OUT
1～OUT
nBe respectively coupled to corresponding gate lines G L
1～GL
n ASIC circuit 330 can produce required initial pulse signal VST, clock signal C K, the XCK of gate driver circuit 320 runnings, with charge sharing signal VCS, wherein in each grade output cycle the incapacitation time of charge sharing signal VCS (tool electronegative potential) length by corresponding to output terminal OUT
1～OUT
nGate lines G L
1～GL
nCapacitance decide, also promptly by output terminal OUT
1～OUT
nParasitic capacitance value C
1～C
nDecide.So, electric charge sharing circuit 340 can come that clock signal C K and XCK are carried out electric charge according to charge sharing signal VCS to be shared to produce corresponding clock signal O_CK and O_XCK, and gate driver circuit 320 is exported the required gate drive signal SG of turn-on transistor switch in regular turn according to clock signal O_CK or O_XCK again
1～SG
n
Please refer to Fig. 7, Fig. 7 is the synoptic diagram of the driving method of liquid crystal indicator 300 of the present invention.Fig. 7 has shown clock signal C K, XCK, O_CK and O_XCK, charge sharing signal VCS, and gate drive signal SG
1～SG
nWaveform.In driving method shown in Figure 7, clock signal C K and XCK tool opposite phase, and switch between high electronegative potential with a predetermined period, and this predetermined period decision gate drive signal SG
1～SG
nIn enable the length in cycle.ASIC circuit 330 is at first according to output terminal OUT
1～OUT
nParasitic capacitance value C
1～C
nProduce the different charge sharing signal VCS of incapacitation time (tool electronegative potential) length T 1～Tn.When charge sharing signal VCS tool noble potential, gate driver circuit 320 meeting clock signal CK and XCK are to provide corresponding clock signal O_CK and O_XCK; When charge sharing signal VCS tool electronegative potential, gate driver circuit 320 stops output, can carry out electric charge between clock signal O_CK and the O_XCK this moment and share, and then reach the effect of top rake in the waveform drop edge.Gate driver circuit 320 produces the gate drive signal SG of the different top rake amplitudes of tool again according to clock signal O_CK and O_XCK
1～SG
n, cause grid pressure differential deltap V when between high electronegative potential, switching respectively at corresponding clock signal C K and XCK
G1～Δ V
GnAs previously mentioned, gate drive signal SG
1～SG
nAt output terminal OUT
1～OUT
nThe signal delay that is run into is cumulative in regular turn, also is parasitic capacitance value C
1＜C
2＜...＜C
nCause in various degree feed-trough voltage effect in order to compensate different parasitic capacitance value, the present invention is according to output terminal OUT
1～OUT
nParasitic capacitance value C
1～C
nProduce the different charge sharing signal VCS of incapacitation time (tool electronegative potential) length, make T1＞T2＞...＞Tn.Therefore, gate drive signal SG of the present invention
1～SG
nTool Δ V is provided
G1＜Δ V
G2＜...＜Δ V
GnThe pressure reduction of magnitude relationship allows the identical value of feed-trough voltage tool of each pixel cell, therefore can be effectively by adjusting common voltage V
COMEliminate the situation of film flicker.
Please refer to Fig. 8, Fig. 8 is the synoptic diagram of electric charge sharing circuit 340 in one embodiment of the invention.In this embodiment, electric charge sharing circuit 340 is designed to an integrated circuit, can bring in by unlike signal and receive or export corresponding signal or bias voltage.Signal end O_CK and O_XCK at clock signal O_CK and O_XCK, when charge sharing signal VCS tool noble potential, electric charge sharing circuit 340 can in signal end O_CK and O_XCK respectively clock signal CK and XCK with as clock signal O_CK and O_XCK; When charge sharing signal VCS tool electronegative potential, signal end O_CK and O_XCK can be coupled to each other by resistance R S, can carry out electric charge between clock signal O_CK and the O_XCK this moment and share, and then reach the effect of top rake in the waveform drop edge.Simultaneously, electric charge sharing circuit 340 can comprise a position quasi displacement circuit, is used for amplifying clock signal C K and XCK.Shown in Figure 8ly only be the embodiment of electric charge sharing circuit 340 of the present invention, do not limit category of the present invention.
The present invention carries out electric charge according to the parasitic capacitance value of each grade output terminal and shares, and makes gate drive signal SG
1～SG
nTool Δ V can be provided
G1＜Δ V
G2＜...＜Δ V
GnThe pressure reduction of magnitude relationship allows the identical value of feed-trough voltage tool of each pixel cell, therefore can be effectively by adjusting common voltage V
COMEliminate the situation of film flicker.
The above only is preferred embodiment of the present invention, and all equalizations of being done according to claim scope of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (12)
1. a LCD is characterized in that, described LCD comprises:
One gate driver circuit is used for producing a first grid drive signal and a second grid drive signal according to one first clock signal or a second clock signal, and described gate driver circuit comprises:
One first output terminal is used for exporting described first grid drive signal; And
One second output terminal is used for exporting described second grid drive signal;
One control circuit, be used for providing a charge sharing signal according to the pairing parasitic capacitance value of described first and second output terminals of described gate driver circuit, and provide one the 3rd clock signal and one the 4th clock signal, the polarity of wherein said third and fourth clock signal is reversed with a predetermined period, and the described third and fourth clock signal tool opposite polarity; Described charge sharing signal comprises one first anergy period and one second anergy period, the described first anergy period is corresponding to the output cycle of described first output terminal, the described second anergy period is corresponding to the output cycle of described second output terminal, and the parasitic capacitance value of described second output terminal is greater than the parasitic capacitance value of described first output terminal, and the length of the described first anergy period is greater than the length of the described second anergy period; And
One electric charge sharing circuit, in period described the 3rd clock signal and described the 4th clock signal being carried out electric charge in described first anergy shares to produce described first clock signal, in period described the 3rd clock signal and described the 4th clock signal being carried out electric charge in described second anergy shares to produce described second clock signal, wherein said first clock signal comprises the waveform drop edge of reducing to one first current potential from a noble potential, and described second clock signal comprises the waveform drop edge of reducing to one second current potential from described noble potential.
2. LCD as claimed in claim 1, it is characterized in that, signal transmission path length between second output terminal of described electric charge sharing circuit and described gate driver circuit is greater than the signal transmission path length between first output terminal of described electric charge sharing circuit and described gate driver circuit, and described second current potential is higher than described first current potential.
3. LCD as claimed in claim 1 is characterized in that, the parasitic capacitance value of second output terminal described in the described gate driver circuit is greater than the parasitic capacitance value of described first output terminal, and described second current potential is higher than described first current potential.
4. LCD as claimed in claim 1 is characterized in that, described electric charge sharing circuit also comprises a position quasi displacement circuit, is used for amplifying described third and fourth clock signal.
5. LCD as claimed in claim 1 is characterized in that, described electric charge sharing circuit comprises:
One first output terminal is used for exporting described first clock signal;
One second output terminal is used for exporting described second clock signal; And
One resistance is coupled between first output terminal and second output terminal of described electric charge sharing circuit.
6. LCD as claimed in claim 1 is characterized in that, described gate driver circuit is to make with the integrated circuit technique that is integrated in panel.
7. LCD as claimed in claim 1 is characterized in that, described gate driver circuit comprises:
One first shifting deposit unit is used for exporting described first clock signal with as described first grid drive signal; And
One second shifting deposit unit is used for exporting described second clock signal with as described second grid drive signal.
8. LCD as claimed in claim 7, it is characterized in that, described first shifting deposit unit is to export described first grid drive signal by a first film transistor switch, described second shifting deposit unit is to export described second grid drive signal by one second thin film transistor switch, wherein, the parasitic capacitance value of described first output terminal is relevant to the transistorized stray capacitance of described the first film, and the parasitic capacitance value of described second output terminal is relevant to the stray capacitance of described first and second thin film transistor (TFT)s.
9. LCD as claimed in claim 1 is characterized in that, described control circuit is an Application Specific Integrated Circuit.
10. a method that drives LCD is characterized in that, described method comprises:
One first clock signal and a second clock signal are provided, and the polarity of wherein said first and second clock signals is reversed with a predetermined period, and the described at one time first and second clock signal tool opposite polarities;
Parasitic capacitance value according to one first output terminal correspondence decides a very first time length;
Parasitic capacitance value according to one second output terminal correspondence decides one second time span;
Wherein, when the parasitic capacitance value of described second output terminal during greater than the parasitic capacitance value of described first output terminal, described very first time length is greater than described second time span;
In cycle corresponding to described first output terminal, described first and second clock signals are carried out electric charge and are shared so that one the 3rd clock signal to be provided in described very first time length, wherein said the 3rd clock signal comprises the waveform drop edge of reducing to one first current potential from a noble potential; And
In cycle corresponding to described second output terminal, described first and second clock signals are carried out electric charge and are shared so that one the 4th clock signal to be provided in described second time span, wherein said the 4th clock signal comprises the waveform drop edge of reducing to one second current potential from described noble potential.
11. method as claimed in claim 10 is characterized in that, described first and second clock signals are to carry out electric charge by a resistance to share.
12. method as claimed in claim 10 is characterized in that, described method also comprises:
In cycle, export described the 3rd clock signal in described first output terminal corresponding to described first output terminal; And
In cycle, export described the 4th clock signal in described second output terminal corresponding to described second output terminal.
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|---|---|---|---|
| CN2009101500460A CN101587700B (en) | 2009-06-26 | 2009-06-26 | Liquid crystal display and method for driving same |
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|---|---|---|---|
| CN2009101500460A CN101587700B (en) | 2009-06-26 | 2009-06-26 | Liquid crystal display and method for driving same |
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| TWI415051B (en) | 2010-09-15 | 2013-11-11 | Au Optronics Corp | Lcd driving circuit and related driving method |
| TWI420457B (en) | 2010-09-30 | 2013-12-21 | Chunghwa Picture Tubes Ltd | Gate driving voltage supply device and method for a display panel |
| CN101950526A (en) * | 2010-10-15 | 2011-01-19 | 华映光电股份有限公司 | Display panel driving voltage feed device and method |
| CN102005197B (en) * | 2010-10-28 | 2013-02-27 | 友达光电股份有限公司 | Drive circuit and related drive method of liquid crystal display |
| CN103578433B (en) * | 2012-07-24 | 2015-10-07 | 北京京东方光电科技有限公司 | A kind of gate driver circuit, method and liquid crystal display |
| CN103198804B (en) * | 2013-03-27 | 2015-09-16 | 深圳市华星光电技术有限公司 | A kind of liquid crystal indicator and driving method thereof |
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