CN101763900A - Shift register circuit - Google Patents

Shift register circuit Download PDF

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Publication number
CN101763900A
CN101763900A CN201010003774A CN201010003774A CN101763900A CN 101763900 A CN101763900 A CN 101763900A CN 201010003774 A CN201010003774 A CN 201010003774A CN 201010003774 A CN201010003774 A CN 201010003774A CN 101763900 A CN101763900 A CN 101763900A
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CN
China
Prior art keywords
end
electrically connected
transistor
gate terminal
signal
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CN201010003774A
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Chinese (zh)
Inventor
徐国华
刘俊欣
陈勇志
林致颖
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友达光电股份有限公司
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Priority to CN201010003774A priority Critical patent/CN101763900A/en
Publication of CN101763900A publication Critical patent/CN101763900A/en

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Abstract

The invention relates to a shift register circuit with waveform chamfering function, which comprises multi-level shift registers. Each level of shift register comprises a first input unit, a pulling-up unit, a pulling-down circuit, a second input unit, a control unit and a waveform chamfering unit. The first input unit is used for outputting a first drive control voltage according to a first grid signal. The pulling-up unit is used for pulling a second grid signal up according to the first drive control voltage. The pulling-down circuit is used for pulling the first drive control voltage and the second grid signal down. The second input unit is used for outputting a second drive control voltage according to the first grid signal. The control unit is used for generating a control signal according to the second drive control voltage and an auxiliary signal. The waveform chamfering unit is used for executing waveform chamfering operation on the second grid signal according to the control signal. The invention can remarkably shorten the pressure difference of a pulse failing edge of a grid signal output by the shift register circuit so as to reduce the feed through effect, and can also lighten the image flicker phenomenon so as to improve the image display quality.

Description

Shift-register circuit

Technical field

The present invention relates to a kind of shift-register circuit, relate in particular to a kind of shift-register circuit with waveform chamfering (waveform-shaping) function.

Background technology

Liquid crystal indicator (Liquid Crystal Display; LCD) be present widely used a kind of flat-panel screens, it has, and external form is frivolous, power saving and advantage such as radiationless.The voltage difference that the principle of work utilization of liquid crystal indicator changes the liquid crystal layer two ends changes the ordered state of the liquid crystal molecule in the liquid crystal layer, in order to change the light transmission of liquid crystal layer, to cooperate backlight module again the light source that provided with display image.Generally speaking, liquid crystal indicator comprises a plurality of pixel cells, source electrode driver and shift-register circuit.Source electrode driver is used to provide a plurality of data-signals to a plurality of pixel cells.Shift-register circuit comprises multi-stage shift register to produce a plurality of pixel cells of a plurality of signal feed-ins, controls the write operation of a plurality of data-signals according to this.Therefore, shift-register circuit is the key element of control data signal write operation.

Fig. 1 is the synoptic diagram of known shift-register circuit.As shown in Figure 1, shift-register circuit 100 comprises multi-stage shift register, wherein only shows (N-1) level shift register 111, N level shift register 112 and (N+1) level shift register 113.Each grade shift register is used for being fed into corresponding gate line with anti-phase second clock pulse CK2 in the first time clock CK1 to produce corresponding signal according to the first time clock CK1, for example (N-1) level shift register 111 is used for producing signal SGn-1 and is fed into gate lines G Ln-1, N level shift register 112 is used for producing signal SGn and is fed into gate lines G Ln, and (N+1) level shift register 113 is used for producing signal SGn+1 and is fed into gate lines G Ln+1.N level shift register 112 comprises pull-up unit 120, input block 130, energy-storage units 125, discharge cell 140, drop-down unit 150 and control module 160.Pull-up unit 120 is used for according to drawing signal SGn more than the drive control voltage VQn.Discharge cell 140 and drop-down unit 150 are used for the drop-down control signal that produced according to control module 160 with drop-down drive control voltage VQn and signal SGn respectively.

In the operation of shift-register circuit 100, multi-stage shift register provides a plurality of signals with recurrent pulses to a plurality of pixel cells, is used for a plurality of data-signals are written as a plurality of pixel voltages.Yet, each pulse of a plurality of signals is essentially ideal square wave, so the negative edge of each pulse can be via the coupling operation of the stray capacitance of pixel cell and the drop-down pixel voltage that writes, this is feedthrough effect (Feed-through effect), it easily causes the phenomenon of image flicker (Image Flicker), thereby reduces display quality.

Summary of the invention

According to embodiments of the invention, it discloses a kind of shift-register circuit with waveform chamfering function that is used to provide a plurality of signals to a plurality of gate lines.This kind shift-register circuit comprises multi-stage shift register, and wherein N level shift register comprises first input block, pull-up unit, pull-down circuit, second input block, control module, waveform chamfering unit and drop-down unit.First input block is electrically connected on (N-1) level shift register to receive (N-1) signal, is used for exporting first drive control voltage according to (N-1) signal.Pull-up unit is electrically connected on first input block and N gate line, is used for according to first drive control voltage and draws the N signal more than the system clock pulse, and wherein the N gate line is in order to transmit the N signal.Pull-down circuit is electrically connected on first input block and pull-up unit, is used for drop-down first drive control voltage and N signal.Second input block is electrically connected on (N-1) level shift register to receive (N-1) signal, is used for exporting second drive control voltage according to (N-1) signal.Control module is electrically connected on second input block, is used for according to second drive control voltage and auxiliary signal to produce control signal.Waveform chamfering unit is electrically connected on control module and N gate line, is used for according to control signal the N signal being carried out waveform chamfering operation.Drop-down unit is electrically connected on (N+1) level shift register to receive (N+1) signal, is used for according to (N+1) signal with drop-down second drive control voltage.

According to embodiments of the invention, it discloses a kind of shift-register circuit with waveform chamfering function that is used to provide a plurality of signals to a plurality of gate lines in addition.This kind shift-register circuit comprises multi-stage shift register, and wherein N level shift register comprises input block, pull-up unit, pull-down circuit, control module and waveform chamfering unit.Input block is electrically connected on (N-1) level shift register to receive (N-1) signal, is used for according to (N-1) signal output drive control voltage.Pull-up unit is electrically connected on input block and N gate line, is used for drawing the N signal according to drive control voltage and more than the system clock pulse, and wherein the N gate line is in order to transmit the N signal.Pull-down circuit is electrically connected on input block and pull-up unit, is used for drop-down drive control voltage and N signal.Control module is electrically connected on input block, is used for according to drive control voltage and auxiliary signal to produce control signal.Waveform chamfering unit is electrically connected on control module and N gate line, is used for according to control signal the N signal being carried out waveform chamfering operation.

Compared to known shift-register circuit, shift-register circuit of the present invention can significantly be dwindled the pressure reduction of pulse negative edge of the signal of its output, reduces the feedthrough effect according to this, also can alleviate the film flicker phenomenon to improve the image display quality.In addition, in the structure of shift-register circuit of the present invention, pull-down circuit is not limited to the foregoing description, any circuit that can be used to drop-down drive control voltage and signal all can replace the pull-down circuit of the foregoing description, and shift-register circuit of the present invention can't influence its waveform chamfering function because of different pull-down circuits.

Description of drawings

Fig. 1 is the synoptic diagram of known shift-register circuit.

Fig. 2 is the synoptic diagram of the shift-register circuit of first embodiment of the invention.

Fig. 3 is the work coherent signal waveform synoptic diagram of the shift-register circuit of Fig. 2, and wherein transverse axis is a time shaft.

Fig. 4 is the synoptic diagram of the shift-register circuit of second embodiment of the invention.

Fig. 5 is the synoptic diagram of the shift-register circuit of third embodiment of the invention.

Fig. 6 is the work coherent signal waveform synoptic diagram of the shift-register circuit of Fig. 5, and wherein transverse axis is a time shaft.

Fig. 7 is the synoptic diagram of the shift-register circuit of fourth embodiment of the invention.

Description of reference numerals in the above-mentioned accompanying drawing is as follows:

100,200,400,500,700 shift-register circuits

111,211,411,511,711 (N-1) level shift register

112,212,412,512,712 N level shift registers

113,213,413,513,713 (N+1) level shift register

120,220,520 pull-up units

125,225,525 energy-storage units

130,530 input blocks

140 discharge cells

150 drop-down unit

160 control modules

221,521 the first transistors

226,526 electric capacity

230 first input blocks

231,531 transistor secondses

240,440,540,740 pull-down circuits

245,445,545,745 second control modules

246,446,748 the 9th transistors

247,447,749 the tenth transistors

250,450 the 3rd drop-down unit

251,451,547,747 the 8th transistors

255,455 second drop-down unit

256,456,546,746 the 7th transistors

280 second input blocks

281,586 the 3rd transistors

285,585 first control modules

286,596 the 4th transistors

290 first drop-down unit

291,556,756 the 5th transistors

295,595 waveform chamfering unit

296,551,751 the 6th transistors

448 the 11 transistors

449 the tenth two-transistors

460 the 4th drop-down unit

461 the 13 transistors

GLn-1, GLn, GLn+1 gate line

CK1 first time clock

The pulse of CK2 second clock

The Saux auxiliary signal

Sc1 first control signal

Sc2 second control signal

SGn-2, SGn-1, SGn, SGn+1, SGn+2 signal

T1, T2, T3, T4 period

Vh1 first high voltage

Vh2 second high voltage

Vh3 the 3rd high voltage

Vh4 the 4th high voltage

Vh5 the 5th high voltage

The VQn drive control voltage

VQn1 first drive control voltage

VQn2 second drive control voltage

The Vss low supply voltage

Embodiment

Hereinafter, elaborate, but the embodiment that is provided not is the scope that contains in order to restriction the present invention especially exemplified by the embodiment conjunction with figs. according to shift-register circuit of the present invention.

Fig. 2 is the synoptic diagram of the shift-register circuit of first embodiment of the invention.As shown in Figure 2, shift-register circuit 200 comprises multi-stage shift register, for convenience of description, 200 of shift-register circuits show (N-1) level shift register 211, N level shift register 212 and (N+1) level shift register 213, wherein have only N level shift register 212 to show the built-in function unit structure, all the other grades shift register is analogous to N level shift register 212, so do not give unnecessary details in addition.In the operation of shift-register circuit 200, (N-1) level shift register 211 is fed into gate lines G Ln-1 in order to signal SGn-1 to be provided, N level shift register 212 is fed into gate lines G Ln in order to signal SGn to be provided, and (N+1) level shift register 213 is fed into gate lines G Ln+1 in order to signal SGn+1 to be provided.

N level shift register 212 comprises pull-up unit 220, first input block 230, energy-storage units 225, pull-down circuit 240, second input block 280, first control module, 285, first drop-down unit 290 and the waveform chamfering unit 295.First input block 230 be electrically connected on (N-1) level shift register 211, be used for exporting the first drive control voltage VQn1 according to signal SGn-1, thus N level shift register 212 with signal SGn-1 as enabling required initial pulse signals.Energy-storage units 225 is electrically connected on first input block 230 and pull-up unit 220, is used for storing the first drive control voltage VQn1.Pull-up unit 220 is electrically connected on first input block 230 and gate lines G Ln, is used for according to the first drive control voltage VQn1 and draws the signal SGn of gate lines G Ln more than the first time clock CK1.Pull-down circuit 240 comprises second control module, 245, second drop-down unit 255 and the 3rd drop-down unit 250.Second control module 245 is electrically connected on first input block 230, is used for according to the first drive control voltage VQn1 and anti-phase second clock pulse CK2 in the first time clock CK1 to produce the second control signal Sc2.The second drop-down unit 255 is electrically connected on second control module 245 and gate lines G Ln, is used for according to the second control signal Sc2 with drop-down signal SGn.The 3rd drop-down unit 250 is electrically connected on second control module 245 and first input block 230, is used for according to the second control signal Sc2 with the drop-down first drive control voltage VQn1.

Second input block 280 is electrically connected on (N-1) level shift register 211, is used for exporting the second drive control voltage VQn2 according to signal SGn-1.First control module 285 is electrically connected on second input block 280, is used for according to the second drive control voltage VQn2 and auxiliary signal Saux to produce the first control signal Sc1.The first drop-down unit 290 is electrically connected on (N+1) the level shift register 213 and second input block 280, is used for according to signal SGn+1 with the drop-down second drive control voltage VQn2.Waveform chamfering unit 295 is electrically connected on first control module 285 and gate lines G Ln, is used for according to the first control signal Sc1 signal SGn being carried out waveform chamfering operation.

In the embodiment of Fig. 2, pull-up unit 220 comprises the first transistor 221, first input block 230 comprises transistor seconds 231, energy-storage units 225 comprises electric capacity 226, second input block 280 comprises the 3rd transistor 281, first control module 285 comprises the 4th transistor 286, the first drop-down unit 290 comprises the 5th transistor 291, waveform chamfering unit 295 comprises the 6th transistor 296, the second drop-down unit 255 comprises the 7th transistor 256, the 3rd drop-down unit 250 comprises the 8th transistor 251, the second control modules 245 and comprises the 9th transistor 246 and the tenth transistor 247.The first transistor 221 to the tenth transistors 247 are thin film transistor (TFT) (Thin Film Transistor) or field effect transistor (FieldEffect Transistor).

The first transistor 221 comprises first end, second end and gate terminal, and wherein first end is in order to receive the first time clock CK1, and second end is electrically connected on gate lines G Ln, and gate terminal is electrically connected on first input block 230.Electric capacity 226 is electrically connected between the gate terminal and second end of the first transistor 221.Transistor seconds 231 comprises first end, second end and gate terminal, and wherein first end is electrically connected on (N-1) level shift register 211 to receive signal SGn-1, and gate terminal is electrically connected on first end, and second end is electrically connected on the gate terminal of the first transistor 221.The 3rd transistor 281 comprises first end, second end and gate terminal, and wherein first end is electrically connected on (N-1) level shift register 211 to receive signal SGn-1, and gate terminal is electrically connected on first end, and second end is electrically connected on first control module 285.The 4th transistor 286 comprises first end, second end and gate terminal, and wherein first end is in order to receive auxiliary signal Saux, and second end is electrically connected on waveform chamfering unit 295, and gate terminal is electrically connected on second end of the 3rd transistor 281.The 5th transistor 291 comprises first end, second end and gate terminal, wherein first end is electrically connected on second end of the 3rd transistor 281, second end is in order to receive low supply voltage Vss, and gate terminal is electrically connected on (N+1) level shift register 213 to receive signal SGn+1.The 6th transistor 296 comprises first end, second end and gate terminal, and wherein first end is electrically connected on gate lines G Ln, and second end is in order to receive low supply voltage Vss, and gate terminal is electrically connected on second end of the 4th transistor 286.

The 7th transistor 256 comprises first end, second end and gate terminal, and wherein first end is electrically connected on gate lines G Ln, and gate terminal is electrically connected on second control module 245 to receive the second control signal Sc2, and second end is in order to receive low supply voltage Vss.The 8th transistor 251 comprises first end, second end and gate terminal, wherein first end is electrically connected on second end of transistor seconds 231, gate terminal is electrically connected on second control module 245 to receive the second control signal Sc2, and second end is in order to receive low supply voltage Vss.The 9th transistor 246 comprises first end, second end and gate terminal, and wherein first end is in order to receive second clock pulse CK2, and gate terminal is electrically connected on first end, and second end is electrically connected on the gate terminal of the 7th transistor 256 and the gate terminal of the 8th transistor 251.The tenth transistor 247 comprises first end, second end and gate terminal, and wherein first end is electrically connected on second end of the 9th transistor 246, and gate terminal is electrically connected on second end of transistor seconds 231, and second end is in order to receive low supply voltage Vss.

Fig. 3 is the work coherent signal waveform synoptic diagram of the shift-register circuit 200 of Fig. 2, and wherein transverse axis is a time shaft.In Fig. 3, basipetal signal is respectively auxiliary signal Saux, the first time clock CK1, second clock pulse CK2, signal SGn-1, the first drive control voltage VQn1, the second drive control voltage VQn2, the first control signal Sc1, signal SGn and signal SGn+1.As shown in Figure 3, in period T1, signal SGn-1 switches to high level voltage by low level voltage, conducting transistor seconds 231 and the 3rd transistor 281 according to this, and the first drive control voltage VQn1 and the second drive control voltage VQn2 also just and then rise to the first high voltage Vh1 and then conducting the first transistor 221 and the 4th transistor 286.At this moment, electric capacity 226 is used for storing the first drive control voltage VQn1, and the first drive control voltage VQn1 in addition can conducting the tenth transistor 247 with the drop-down second control signal Sc2 to low supply voltage Vss, and then by the 7th transistor 256 and the 8th transistor 251.

In period T2, signal SGn-1 drops to low level voltage by high level voltage, according to this by transistor seconds 231 and the 3rd transistor 281, and then makes the first drive control voltage VQn1 and the second drive control voltage VQn2 all become suspension joint voltage.Simultaneously, the first time clock CK1 switches to high level voltage by low level voltage, so can the first drive control voltage VQn1 be pulled to the second high voltage Vh2 by the first high voltage Vh1 by the element capacitive coupling effect of the first transistor 221, and continue conducting the first transistor 221 according to this, and then signal SGn is pulled to the 3rd high voltage Vh3 by low level voltage.

In period T3, auxiliary signal Saux switches to high level voltage by low level voltage, so can the second drive control voltage VQn2 be pulled to the 4th high voltage Vh4 by the first high voltage Vh1 by the element capacitive coupling effect of the 4th transistor 286, and continue conducting the 4th transistor 286 according to this, and then the first control signal Sc1 is pulled to high level voltage by low level voltage.At this moment, first control signal Sc1 meeting conducting the 6th transistor 296, and signal SGn promptly drops to the 5th high voltage Vh5 from the 3rd high voltage Vh3 in period T3.

In period T4, the first time clock CK1 switches to low level voltage by high level voltage, so signal SGn also and then switches to low level voltage from the 5th high voltage Vh5, and the coupling by electric capacity 226, the first drive control voltage VQn1 also is pulled down to low level voltage, the tenth transistor 247 thereby end.Simultaneously, because second clock pulse CK2 switches to high level voltage by low level voltage, and then make the second control signal Sc2 switch to high level voltage, so the 7th transistor 256 and the 8th transistor 251 switch to conducting state, according to this signal SGn and the first drive control voltage VQn1 are pulled down to low level voltage.In addition, 213 in shift register of (N+1) level utilizes signal SGn as enabling required initial pulse signals, and in period T4, produce the signal SGn+1 of high level, make the 5th transistor 291 conducting in period T4, and then the second drive control voltage VQn2 is pulled down to low supply voltage Vss from the 4th high voltage Vh4.Please note, the negative edge of signal SGn drops to low level voltage from the 5th high voltage Vh5, but not drop to low level voltage from the 3rd high voltage Vh3, so can significantly dwindle the pressure reduction of its negative edge, reduce the feedthrough effect according to this, also can alleviate the film flicker phenomenon to improve the image display quality.

Fig. 4 is the synoptic diagram of the shift-register circuit of second embodiment of the invention.As shown in Figure 4, shift-register circuit 400 comprises multi-stage shift register, wherein only shows (N-1) level shift register 411, N level shift register 412 and (N+1) level shift register 413.N level shift register 412 is similar to N level shift register 212 shown in Figure 2, and main difference is pull-down circuit 240 is replaced into pull-down circuit 440.Pull-down circuit 440 comprises second control module, 445, second the 455, the 3rd drop-down unit 450, drop-down unit and the 4th drop-down unit 460.Second control module 445 is electrically connected on first input block 230, is used for according to the first drive control voltage VQn1 and second clock pulse CK2 to produce the second control signal Sc2.The second drop-down unit 455 is electrically connected on second control module 445 and gate lines G Ln, is used for according to the second control signal Sc2 with drop-down signal SGn.The 3rd drop-down unit 450 is electrically connected on second control module 445 and first input block 230, is used for according to the second control signal Sc2 with the drop-down first drive control voltage VQn1.The 4th drop-down unit 460 is electrically connected on (N+1) level shift register 413 and gate lines G Ln, is used for according to signal SGn+1 with drop-down signal SGn.

In the embodiment of Fig. 4, the second drop-down unit 455 comprises the 7th transistor 456, the 3rd drop-down unit 450 comprises the 8th transistor 451, second control module 445 comprises the 9th transistor 446, the tenth transistor the 447, the 11 transistor 448 and the tenth two-transistor 449, the four drop-down unit 460 and comprises the 13 transistor 461.The 7th transistor the 456 to the 13 transistor 461 is thin film transistor (TFT) or field effect transistor.The 7th transistor 456 comprises first end, second end and gate terminal, and wherein first end is electrically connected on gate lines G Ln, and gate terminal is electrically connected on second control module 445 to receive the second control signal Sc2, and second end is in order to receive low supply voltage Vss.The 8th transistor 451 comprises first end, second end and gate terminal, wherein first end is electrically connected on second end of transistor seconds 231, gate terminal is electrically connected on second control module 445 to receive the second control signal Sc2, and second end is in order to receive low supply voltage Vss.

The 9th transistor 446 comprises first end, second end and gate terminal, and wherein first end is in order to receive second clock pulse CK2, and second end is electrically connected on the gate terminal of the 7th transistor 456 and the gate terminal of the 8th transistor 451.The tenth transistor 447 comprises first end, second end and gate terminal, and wherein first end is electrically connected on second end of the 9th transistor 446, and gate terminal is electrically connected on second end of transistor seconds 231, and second end is in order to receive low supply voltage Vss.The 11 transistor 448 comprises first end, second end and gate terminal, and wherein first end is in order to receive second clock pulse CK2, and gate terminal is electrically connected on first end, and second end is electrically connected on the gate terminal of the 9th transistor 446.The tenth two-transistor 449 comprises first end, second end and gate terminal, and wherein first end is electrically connected on second end of the 11 transistor 448, and gate terminal is electrically connected on second end of transistor seconds 231, and second end is in order to receive low supply voltage Vss.The 13 transistor 461 comprises first end, second end and gate terminal, and wherein first end is electrically connected on gate lines G Ln, and gate terminal is electrically connected on (N+1) level shift register 413 to receive signal SGn+1, and second end is in order to receive low supply voltage Vss.

The work coherent signal waveform of shift-register circuit 400 is same as signal waveform shown in Figure 3.In the operation of shift-register circuit 400, in period T4, the 13 transistor 461 can be according to signal SGn+1 with drop-down signal SGn, and also promptly the 7th transistor 456 and the 13 transistor 461 all are used for drop-down signal SGn.The inner structure of second control module 445 is a known circuits, so repeat no more its principle of work.

Fig. 5 is the synoptic diagram of the shift-register circuit of third embodiment of the invention.As shown in Figure 5, shift-register circuit 500 comprises multi-stage shift register, for convenience of description, 500 of shift-register circuits show (N-1) level shift register 511, N level shift register 512 and (N+1) level shift register 513, wherein have only N level shift register 512 to show the built-in function unit structure, all the other grades shift register is analogous to N level shift register 512, so do not give unnecessary details in addition.In the operation of shift-register circuit 500, (N-1) level shift register 511 is fed into gate lines G Ln-1 in order to signal SGn-1 to be provided, N level shift register 512 is fed into gate lines G Ln in order to signal SGn to be provided, and (N+1) level shift register 513 is fed into gate lines G Ln+1 in order to signal SGn+1 to be provided.

N level shift register 512 comprises pull-up unit 520, input block 530, energy-storage units 525, pull-down circuit 540, first control module 585 and waveform chamfering unit 595.Input block 530 is electrically connected on (N-1) level shift register 511, be used for according to signal SGn-1 output drive control voltage VQn, so N level shift register 512 with signal SGn-1 as enabling required initial pulse signals.Energy-storage units 525 is electrically connected on input block 530 and pull-up unit 520, is used for storing driver control voltage VQn.Pull-up unit 520 is electrically connected on input block 530 and gate lines G Ln, is used for according to drive control voltage VQn and draws the signal SGn of gate lines G Ln more than the first time clock CK1.

Pull-down circuit 540 comprises second control module, 545, the first drop-down unit 555 and the second drop-down unit 550.Second control module 545 is electrically connected on input block 530, is used for according to drive control voltage VQn and anti-phase second clock pulse CK2 in the first time clock CK1 to produce the second control signal Sc2.The first drop-down unit 555 is electrically connected on second control module 545 and gate lines G Ln, is used for according to the second control signal Sc2 with drop-down signal SGn.The second drop-down unit 550 is electrically connected on second control module 545 and input block 530, is used for according to the second control signal Sc2 with drop-down drive control voltage VQn.First control module 585 is electrically connected on input block 530, is used for according to drive control voltage VQn and auxiliary signal Saux to produce the first control signal Sc1.Waveform chamfering unit 595 is electrically connected on first control module 585 and gate lines G Ln, is used for according to the first control signal Sc1 signal SGn being carried out waveform chamfering operation.

In the embodiment of Fig. 5, pull-up unit 520 comprises the first transistor 521, input block 530 comprises transistor seconds 531, energy-storage units 525 comprises electric capacity 526, first control module 585 comprises the 3rd transistor 586, and waveform chamfering unit 595 comprises the 4th transistor 596, the first drop-down unit 555 and comprises the 5th transistor 556, the second drop-down unit 550 comprises the 6th transistor 551, the second control modules 545 and comprises the 7th transistor 546 and the 8th transistor 547.The first transistor 521 to the 8th transistors 547 are thin film transistor (TFT) or field effect transistor.

The first transistor 521 comprises first end, second end and gate terminal, and wherein first end is in order to receive the first time clock CK1, and second end is electrically connected on gate lines G Ln, and gate terminal is electrically connected on input block 530.Electric capacity 526 is electrically connected between the gate terminal and second end of the first transistor 521.Transistor seconds 531 comprises first end, second end and gate terminal, and wherein first end is electrically connected on (N-1) level shift register 511 to receive signal SGn-1, and gate terminal is electrically connected on first end, and second end is electrically connected on the gate terminal of the first transistor 521.The 3rd transistor 586 comprises first end, second end and gate terminal, and wherein first end is in order to receive auxiliary signal Saux, and second end is electrically connected on waveform chamfering unit 595, and gate terminal is electrically connected on second end of transistor seconds 531.The 4th transistor 596 comprises first end, second end and gate terminal, and wherein first end is electrically connected on gate lines G Ln, and second end is in order to receive low supply voltage Vss, and gate terminal is electrically connected on second end of the 3rd transistor 586.

The 5th transistor 556 comprises first end, second end and gate terminal, and wherein first end is electrically connected on gate lines G Ln, and gate terminal is electrically connected on second control module 545 to receive the second control signal Sc2, and second end is in order to receive low supply voltage Vss.The 6th transistor 551 comprises first end, second end and gate terminal, wherein first end is electrically connected on second end of transistor seconds 531, gate terminal is electrically connected on second control module 545 to receive the second control signal Sc2, and second end is in order to receive low supply voltage Vss.The 7th transistor 546 comprises first end, second end and gate terminal, and wherein first end is in order to receive second clock pulse CK2, and gate terminal is electrically connected on first end, and second end is electrically connected on the gate terminal of the 5th transistor 556 and the gate terminal of the 6th transistor 551.The 8th transistor 547 comprises first end, second end and gate terminal, and wherein first end is electrically connected on second end of the 7th transistor 546, and gate terminal is electrically connected on second end of transistor seconds 531, and second end is in order to receive low supply voltage Vss.

Fig. 6 is the work coherent signal waveform synoptic diagram of the shift-register circuit 500 of Fig. 5, and wherein transverse axis is a time shaft.In Fig. 6, basipetal signal is respectively auxiliary signal Saux, the first time clock CK1, second clock pulse CK2, signal SGn-1, drive control voltage VQn, the first control signal Sc1, signal SGn and signal SGn+1.As shown in Figure 6, in period T1, signal SGn-1 switches to high level voltage by low level voltage, and the conducting transistor seconds 531 according to this, and drive control voltage VQn also just and then rises to the first high voltage Vh1 and then conducting the first transistor 521 and the 3rd transistor 586.At this moment, electric capacity 526 is used for storing driver control voltage VQn, and drive control voltage VQn in addition can conducting the 8th transistor 547 with the drop-down second control signal Sc2 to low supply voltage Vss, and then by the 5th transistor 556 and the 6th transistor 551.

In period T2, signal SGn-1 drops to low level voltage by high level voltage, according to this by transistor seconds 531, and then makes drive control voltage VQn become suspension joint voltage.Simultaneously, the first time clock CK1 switches to high level voltage by low level voltage, so can drive control voltage VQn be pulled to the second high voltage Vh2 by the first high voltage Vh1 by the element capacitive coupling effect of the first transistor 521, and continue conducting the first transistor 521 and the 3rd transistor 586 according to this, and then signal SGn is pulled to the 3rd high voltage Vh3 by low level voltage.

In period T3, auxiliary signal Saux switches to high level voltage by low level voltage, so can drive control voltage VQn be pulled to the 4th high voltage Vh4 by the second high voltage Vh2 by the element capacitive coupling effect of the 3rd transistor 586, and continue conducting the first transistor 521 and the 3rd transistor 586 according to this, and then the first control signal Sc1 is pulled to high level voltage by low level voltage.The voltage difference that note that the 4th high voltage Vh4 and the second high voltage Vh2 is influenced by the element capacitance size of the 3rd transistor 586.At this moment, first control signal Sc1 meeting conducting the 4th transistor 596, and signal SGn promptly drops to the 5th high voltage Vh5 from the 3rd high voltage Vh3 in period T3.

In period T4, the first time clock CK1 switches to low level voltage by high level voltage, so signal SGn also and then switches to low level voltage from the 5th high voltage Vh5, and the coupling by electric capacity 526, drive control voltage VQn also is pulled down to low level voltage, the 8th transistor 547 thereby end.Simultaneously, because second clock pulse CK2 switches to high level voltage by low level voltage, and then make the second control signal Sc2 switch to high level voltage, so the 5th transistor 556 and the 6th transistor 551 switch to conducting state, according to this signal SGn and drive control voltage VQn are pulled down to low level voltage.In addition, 513 in shift register of (N+1) level utilizes signal SGn conduct to enable required initial pulse signals, and produces the signal SGn+1 of high level in period T4.In like manner, the negative edge of signal SGn drops to low level voltage from the 5th high voltage Vh5, but not drop to low level voltage from the 3rd high voltage Vh3, so can significantly dwindle the pressure reduction of its negative edge, reduce the feedthrough effect according to this, also can alleviate the film flicker phenomenon to improve the image display quality.

Fig. 7 is the synoptic diagram of the shift-register circuit of fourth embodiment of the invention.As shown in Figure 7, shift-register circuit 700 comprises multi-stage shift register, wherein only shows (N-1) level shift register 711, N level shift register 712 and (N+1) level shift register 713.N level shift register 712 is similar to N level shift register 512 shown in Figure 5, and main difference is pull-down circuit 540 is replaced into pull-down circuit 740.Pull-down circuit 740 comprises second control module, 745, first 755, second drop-down unit 750, drop-down unit and the 3rd drop-down unit 760.Second control module 745 is electrically connected on input block 530, is used for according to drive control voltage VQn and second clock pulse CK2 to produce the second control signal Sc2.The first drop-down unit 755 is electrically connected on second control module 745 and gate lines G Ln, is used for according to the second control signal Sc2 with drop-down signal SGn.The second drop-down unit 750 is electrically connected on second control module 745 and input block 530, is used for according to the second control signal Sc2 with drop-down drive control voltage VQn.The 3rd drop-down unit 760 is electrically connected on (N+1) level shift register 713 and gate lines G Ln, is used for according to signal SGn+1 with drop-down signal SGn.

In the embodiment of Fig. 7, the first drop-down unit 755 comprises the 5th transistor 756, the second drop-down unit 750 comprises the 6th transistor 751, second control module 745 comprises the 7th transistor 746, the 8th transistor 747, the 9th transistor 748 and the tenth transistor 749, the three drop-down unit 760 and comprises the 11 transistor 761.The 5th transistor the 756 to the 11 transistor 761 is thin film transistor (TFT) or field effect transistor.The 5th transistor 756 comprises first end, second end and gate terminal, and wherein first end is electrically connected on gate lines G Ln, and gate terminal is electrically connected on second control module 745 to receive the second control signal Sc2, and second end is in order to receive low supply voltage Vss.The 6th transistor 751 comprises first end, second end and gate terminal, wherein first end is electrically connected on second end of transistor seconds 531, gate terminal is electrically connected on second control module 745 to receive the second control signal Sc2, and second end is in order to receive low supply voltage Vss.

The 7th transistor 746 comprises first end, second end and gate terminal, and wherein first end is in order to receive second clock pulse CK2, and second end is electrically connected on the gate terminal of the 5th transistor 756 and the gate terminal of the 6th transistor 751.The 8th transistor 747 comprises first end, second end and gate terminal, and wherein first end is electrically connected on second end of the 7th transistor 746, and gate terminal is electrically connected on second end of transistor seconds 531, and second end is in order to receive low supply voltage Vss.The 9th transistor 748 comprises first end, second end and gate terminal, and wherein first end is in order to receive second clock pulse CK2, and gate terminal is electrically connected on first end, and second end is electrically connected on the gate terminal of the 7th transistor 746.The tenth transistor 749 comprises first end, second end and gate terminal, and wherein first end is electrically connected on second end of the 9th transistor 748, and gate terminal is electrically connected on second end of transistor seconds 531, and second end is in order to receive low supply voltage Vss.The 11 transistor 761 comprises first end, second end and gate terminal, and wherein first end is electrically connected on gate lines G Ln, and gate terminal is electrically connected on (N+1) level shift register 713 to receive signal SGn+1, and second end is in order to receive low supply voltage Vss.

The work coherent signal waveform of shift-register circuit 700 is same as signal waveform shown in Figure 6.In the operation of shift-register circuit 700, in period T4, the 11 transistor 761 can be according to signal SGn+1 with drop-down signal SGn, and also promptly the 5th transistor 756 and the 11 transistor 761 all are used for drop-down signal SGn.The inner structure of second control module 745 is a known circuits, so repeat no more its principle of work.

In sum, compared to known shift-register circuit, shift-register circuit of the present invention can significantly be dwindled the pressure reduction of pulse negative edge of the signal of its output, reduces the feedthrough effect according to this, also can alleviate the film flicker phenomenon to improve the image display quality.In addition, in the structure of shift-register circuit of the present invention, pull-down circuit is not limited to the foregoing description, any circuit that can be used to drop-down drive control voltage and signal all can replace the pull-down circuit of the foregoing description, and shift-register circuit of the present invention can't influence its waveform chamfering function because of different pull-down circuits.

Though the present invention discloses as above with embodiment; yet it is not in order to limit the present invention; any general technical staff of the technical field of the invention; without departing from the spirit and scope of the present invention; when can doing various changes and retouching, so protection scope of the present invention is as the criterion when looking appended the scope that claim defined.

Claims (22)

1. shift-register circuit, in order to provide a plurality of signals to a plurality of gate lines, this shift-register circuit comprises multi-stage shift register, and a N level shift register of described multi-stage shift register comprises:
One first input block, one (N-1) level shift register that is electrically connected on described multi-stage shift register is used for exporting one first drive control voltage according to this (N-1) signal to receive one (N-1) signal of described a plurality of signals;
One pull-up unit, be electrically connected on a N gate line of this first input block and described a plurality of gate lines, be used for according to this first drive control voltage and draw a N signal of described a plurality of signals more than one first time clock, wherein this N gate line is in order to transmit this N signal;
One pull-down circuit is electrically connected on this first input block and this pull-up unit, is used for drop-down this first drive control voltage and this N signal;
One second input block is electrically connected on this (N-1) level shift register to receive this (N-1) signal, is used for exporting one second drive control voltage according to this (N-1) signal;
One first control module is electrically connected on this second input block, is used for according to this second drive control voltage and an auxiliary signal to produce one first control signal;
One waveform chamfering unit is electrically connected on this first control module and this N gate line, is used for according to this first control signal this N signal being carried out waveform chamfering operation; And
One first drop-down unit, one (N+1) level shift register that is electrically connected on described multi-stage shift register is used for according to this (N+1) signal with drop-down this second drive control voltage to receive one (N+1) signal of described a plurality of signals.
2. shift-register circuit as claimed in claim 1, wherein this N level shift register comprises in addition:
One electric capacity is electrically connected between this first input block and this N gate line, is used for storing this first drive control voltage.
3. shift-register circuit as claimed in claim 1, wherein this first input block comprises a transistor, and this transistor comprises:
One first end is electrically connected on this (N-1) level shift register to receive this (N-1) signal;
One gate terminal is electrically connected on this transistorized first end; And
One second end is electrically connected on this pull-up unit and this pull-down circuit.
4. shift-register circuit as claimed in claim 1, wherein this pull-up unit comprises a transistor, and this transistor comprises:
One first end is in order to receive this first time clock;
One gate terminal is electrically connected on this first input block to receive this first drive control voltage; And
One second end is electrically connected on this N gate line.
5. shift-register circuit as claimed in claim 1, wherein this second input block comprises a transistor, and this transistor comprises:
One first end is electrically connected on this (N-1) level shift register to receive this (N-1) signal;
One gate terminal is electrically connected on this transistorized first end; And
One second end is electrically connected on this first control module and this first drop-down unit.
6. shift-register circuit as claimed in claim 1, wherein this first control module comprises a transistor, and this transistor comprises:
One first end is in order to receive this auxiliary signal;
One gate terminal is electrically connected on this second input block to receive this second drive control voltage; And
One second end is electrically connected on this waveform chamfering unit.
7. shift-register circuit as claimed in claim 1, wherein this first drop-down unit comprises a transistor, and this transistor comprises:
One first end is electrically connected on this second input block;
One gate terminal is electrically connected on this (N+1) level shift register to receive this (N+1) signal; And
One second end is in order to receive a low supply voltage.
8. shift-register circuit as claimed in claim 1, wherein this waveform chamfering unit comprises a transistor, and this transistor comprises:
One first end is electrically connected on this N gate line;
One gate terminal is electrically connected on this first control module to receive this first control signal; And
One second end is in order to receive a low supply voltage.
9. shift-register circuit as claimed in claim 1, wherein this pull-down circuit comprises:
One second control module is electrically connected on this first input block, is used for according to this first drive control voltage and an anti-phase second clock pulse in this first time clock to produce one second control signal;
One second drop-down unit is electrically connected on this second control module and this N gate line, is used for according to this second control signal with drop-down this N signal; And
One the 3rd drop-down unit is electrically connected on this second control module and this first input block, is used for according to this second control signal with drop-down this first drive control voltage.
10. shift-register circuit as claimed in claim 9, wherein:
This second control module comprises:
One the first transistor, comprise one first end, one second end and a gate terminal, wherein this first end is in order to receive this second clock pulse, and this gate terminal is electrically connected on first end of this first transistor, and this second end is electrically connected on this second drop-down unit and the 3rd drop-down unit; And
One transistor seconds, comprise one first end, one second end and a gate terminal, wherein this first end is electrically connected on second end of this first transistor, and this gate terminal is electrically connected on this first input block to receive this first drive control voltage, and this second end is used for receiving a low supply voltage;
This second drop-down unit comprises:
One the 3rd transistor, comprise one first end, one second end and a gate terminal, wherein this first end is electrically connected on this N gate line, and this gate terminal is electrically connected on second end of this first transistor to receive this second control signal, and this second end is used for receiving this low supply voltage; And
The 3rd drop-down unit comprises:
One the 4th transistor, comprise one first end, one second end and a gate terminal, wherein this first end is electrically connected on this first input block, and this gate terminal is electrically connected on second end of this first transistor to receive this second control signal, and this second end is used for receiving this low supply voltage.
11. shift-register circuit as claimed in claim 9, wherein this pull-down circuit comprises in addition:
One the 4th drop-down unit is electrically connected on this N gate line and this (N+1) level shift register, is used for according to this (N+1) signal with drop-down this N signal.
12. shift-register circuit as claimed in claim 11, wherein:
This second control module comprises:
One the first transistor comprises one first end, one second end and a gate terminal, and wherein this first end is in order to receive this second clock pulse, and this second end is electrically connected on this second drop-down unit and the 3rd drop-down unit;
One transistor seconds, comprise one first end, one second end and a gate terminal, wherein this first end is electrically connected on second end of this first transistor, and this gate terminal is electrically connected on this first input block to receive this first drive control voltage, and this second end is used for receiving a low supply voltage;
One the 3rd transistor comprises one first end, one second end and a gate terminal, and wherein this first end is in order to receive this second clock pulse, and this gate terminal is electrically connected on the 3rd transistorized first end, and this second end is electrically connected on the gate terminal of this first transistor; And
One the 4th transistor, comprise one first end, one second end and a gate terminal, wherein this first end is electrically connected on the 3rd transistorized second end, and this gate terminal is electrically connected on this first input block to receive this first drive control voltage, and this second end is used for receiving this low supply voltage;
This second drop-down unit comprises:
One the 5th transistor, comprise one first end, one second end and a gate terminal, wherein this first end is electrically connected on this N gate line, and this gate terminal is electrically connected on second end of this first transistor to receive this second control signal, and this second end is used for receiving this low supply voltage;
The 3rd drop-down unit comprises:
One the 6th transistor, comprise one first end, one second end and a gate terminal, wherein this first end is electrically connected on this first input block, and this gate terminal is electrically connected on second end of this first transistor to receive this second control signal, and this second end is used for receiving this low supply voltage; And
The 4th drop-down unit comprises:
One the 7th transistor, comprise one first end, one second end and a gate terminal, wherein this first end is electrically connected on this N gate line, and this gate terminal is electrically connected on this (N+1) level shift register to receive this (N+1) signal, and this second end is used for receiving this low supply voltage.
13. a shift-register circuit, in order to provide a plurality of signals to a plurality of gate lines, this shift-register circuit comprises multi-stage shift register, and a N level shift register of described multi-stage shift register comprises:
One input block, one (N-1) level shift register that is electrically connected on described multi-stage shift register is used for exporting a drive control voltage according to this (N-1) signal to receive one (N-1) signal of described a plurality of signals;
One pull-up unit, be electrically connected on a N gate line of this input block and described a plurality of gate lines, be used for according to this drive control voltage and draw a N signal of described a plurality of signals more than one first time clock, wherein this N gate line is in order to transmit this N signal;
One pull-down circuit is electrically connected on this input block and this pull-up unit, is used for drop-down this drive control voltage and this N signal;
One first control module is electrically connected on this input block, is used for according to this drive control voltage and an auxiliary signal to produce one first control signal; And
One waveform chamfering unit is electrically connected on this first control module and this N gate line, is used for according to this first control signal this N signal being carried out waveform chamfering operation.
14. shift-register circuit as claimed in claim 13, wherein this N level shift register comprises in addition:
One electric capacity is electrically connected between this input block and this N gate line, is used for storing this drive control voltage.
15. shift-register circuit as claimed in claim 13, wherein this input block comprises a transistor, and this transistor comprises:
One first end is electrically connected on this (N-1) level shift register to receive this (N-1) signal;
One gate terminal is electrically connected on this transistorized first end; And
One second end is electrically connected on this pull-up unit, this pull-down circuit and this first control module.
16. shift-register circuit as claimed in claim 13, wherein this pull-up unit comprises a transistor, and this transistor comprises:
One first end is in order to receive this first time clock;
One gate terminal is electrically connected on this input block to receive this drive control voltage; And
One second end is electrically connected on this N gate line.
17. shift-register circuit as claimed in claim 13, wherein this first control module comprises a transistor, and this transistor comprises:
One first end is in order to receive this auxiliary signal;
One gate terminal is electrically connected on this input block to receive this drive control voltage; And
One second end is electrically connected on this waveform chamfering unit.
18. shift-register circuit as claimed in claim 13, wherein this waveform chamfering unit comprises a transistor, and this transistor comprises:
One first end is electrically connected on this N gate line;
One gate terminal is electrically connected on this first control module to receive this first control signal; And
One second end is in order to receive a low supply voltage.
19. shift-register circuit as claimed in claim 13, wherein this pull-down circuit comprises:
One second control module is electrically connected on this input block, is used for according to this drive control voltage and an anti-phase second clock pulse in this first time clock to produce one second control signal;
One first drop-down unit is electrically connected on this second control module and this N gate line, is used for according to this second control signal with drop-down this N signal; And
One second drop-down unit is electrically connected on this second control module and this input block, is used for according to this second control signal with drop-down this drive control voltage.
20. shift-register circuit as claimed in claim 19, wherein:
This second control module comprises:
One the first transistor, comprise one first end, one second end and a gate terminal, wherein this first end is in order to receive this second clock pulse, and this gate terminal is electrically connected on first end of this first transistor, and this second end is electrically connected on this first drop-down unit and this second drop-down unit; And
One transistor seconds, comprise one first end, one second end and a gate terminal, wherein this first end is electrically connected on second end of this first transistor, and this gate terminal is electrically connected on this input block to receive this drive control voltage, and this second end is used for receiving a low supply voltage;
This first drop-down unit comprises:
One the 3rd transistor, comprise one first end, one second end and a gate terminal, wherein this first end is electrically connected on this N gate line, and this gate terminal is electrically connected on second end of this first transistor to receive this second control signal, and this second end is used for receiving this low supply voltage; And
This second drop-down unit comprises:
One the 4th transistor, comprise one first end, one second end and a gate terminal, wherein this first end is electrically connected on this input block, and this gate terminal is electrically connected on second end of this first transistor to receive this second control signal, and this second end is used for receiving this low supply voltage.
21. shift-register circuit as claimed in claim 19, wherein this pull-down circuit comprises in addition:
One the 3rd drop-down unit, one (N+1) level shift register that is electrically connected on described multi-stage shift register is used for according to this (N+1) signal this N signal with drop-down this N gate line to receive one (N+1) signal of described a plurality of signals.
22. shift-register circuit as claimed in claim 21, wherein:
This second control module comprises:
One the first transistor comprises one first end, one second end and a gate terminal, and wherein this first end is in order to receive this second clock pulse, and this second end is electrically connected on this first drop-down unit and this second drop-down unit;
One transistor seconds, comprise one first end, one second end and a gate terminal, wherein this first end is electrically connected on second end of this first transistor, and this gate terminal is electrically connected on this input block to receive this drive control voltage, and this second end is used for receiving a low supply voltage;
One the 3rd transistor comprises one first end, one second end and a gate terminal, and wherein this first end is in order to receive this second clock pulse, and this gate terminal is electrically connected on the 3rd transistorized first end, and this second end is electrically connected on the gate terminal of this first transistor; And
One the 4th transistor, comprise one first end, one second end and a gate terminal, wherein this first end is electrically connected on the 3rd transistorized second end, and this gate terminal is electrically connected on this input block to receive this drive control voltage, and this second end is used for receiving this low supply voltage;
This first drop-down unit comprises:
One the 5th transistor, comprise one first end, one second end and a gate terminal, wherein this first end is electrically connected on this N gate line, and this gate terminal is electrically connected on second end of this first transistor to receive this second control signal, and this second end is used for receiving this low supply voltage;
This second drop-down unit comprises:
One the 6th transistor, comprise one first end, one second end and a gate terminal, wherein this first end is electrically connected on this input block, and this gate terminal is electrically connected on second end of this first transistor to receive this second control signal, and this second end is used for receiving this low supply voltage; And
The 3rd drop-down unit comprises:
One the 7th transistor, comprise one first end, one second end and a gate terminal, wherein this first end is electrically connected on this N gate line, and this gate terminal is electrically connected on this (N+1) level shift register to receive this (N+1) signal, and this second end is used for receiving this low supply voltage.
CN201010003774A 2010-01-18 2010-01-18 Shift register circuit CN101763900A (en)

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CN102063858B (en) * 2010-12-06 2013-02-13 友达光电股份有限公司 Shift register circuit
CN102024415A (en) * 2010-12-10 2011-04-20 友达光电股份有限公司 Shifting register circuit
CN103366822A (en) * 2013-02-07 2013-10-23 友达光电股份有限公司 Shift register circuit and chamfered waveform generating method
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US10685615B2 (en) 2017-09-13 2020-06-16 Boe Technology Group Co., Ltd. Shift register and driving method thereof, gate driving circuit, and display device

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