CN103854622B - A kind of gate driver circuit - Google Patents
A kind of gate driver circuit Download PDFInfo
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- CN103854622B CN103854622B CN201410073196.7A CN201410073196A CN103854622B CN 103854622 B CN103854622 B CN 103854622B CN 201410073196 A CN201410073196 A CN 201410073196A CN 103854622 B CN103854622 B CN 103854622B
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Abstract
The present invention proposes a kind of gate driver circuit, and it comprises multistage drive element of the grid, and wherein every grade of drive element of the grid comprises the first driver module and the second driver module, and the first driver module and the second driver module include burning voltage module. The first driver module and the second driver module all receive the first clock signal, the second clock signal, low reference voltage, the first reference voltage and the second reference voltage. The 3rd clock signal of the reception of the first burning voltage module of the first driver module is contrary with the current potential of the 4th clock signal that the second burning voltage module of the second driver module receives. In gate driver circuit of the present invention, first and second driver module is all exported gate drive signal, not only improve the driving force of gate driver circuit, and its burning voltage module intermittent work, improve the service life of gate driver circuit, and the risk abnormal because of threshold voltage shift, good stability are reduced.
Description
Technical field
The present invention relates to a kind of drive circuit, particularly a kind of grid that is applicable to liquid crystal indicatorDrive circuit.
Background technology
Liquid crystal indicator (LiquidCrystalDisplay, LCD) possesses frivolous, energy-conservation, nothingThe plurality of advantages such as radiation, have therefore replaced traditional cathode-ray tube (CRT) display gradually.Liquid crystal display is widely used in HD digital TV, desktop computer, individual digital at presentIn the electronic equipments such as assistant (PDA), notebook computer, mobile phone, digital camera.
Taking thin film transistor (TFT) (ThinFilmTransistor, TFT) liquid crystal indicator as example, itsComprise: display panels and drive circuit, wherein, display panels comprise many gate lines withMany data wires, and adjacent two gate lines and adjacent two data wires intersect to form a pixelUnit, each pixel cell at least comprises a thin film transistor (TFT). And drive circuit comprises: grid drivesMoving circuit (gatedrivecircuit) and source electrode drive circuit (sourcedrivecircuit). Along withThe producer pursues the cost degradation of liquid crystal indicator and the raising of manufacturing process, is originally arranged atDrive circuit integrated chip beyond display panels is arranged at the glass-based of display panelsOn plate, become possibility, for example, grid-driving integrated circuit is arranged to array base palte (GateICinArray, GIA) thus the upper manufacture process of simplifying liquid crystal indicator, and reduce production costs.
The basic functional principle of display panels and drive circuit is: gate driver circuit by with gridWhat polar curve was electrically connected pulls up transistor and sends gate drive signal to gate line, sequentially by every a lineTFT opens, and then the pixel cell of a full line is charged to institute separately by source electrode drive circuit simultaneouslyThe voltage needing, to show different GTGs. first passed through on it by the gate driver circuit of the first rowPull transistor is opened the thin film transistor (TFT) of the first row, then the picture to the first row by source electrode drive circuitElement unit charges. When the pixel cell of the first row is charged, gate driver circuit is just by thin this rowFilm transistor is closed, and then the gate driver circuit of the second row pulls up transistor the second row by itThin film transistor (TFT) is opened, then by source electrode drive circuit, the pixel cell of the second row is discharged and recharged. AsThis sequentially goes down, and when the pixel cell of the last column of having substituted the bad for the good, just starts charging from the first row again.
Wherein, gate driver circuit comprises multiple switch elements, and it utilizes clock signal to multiple switchesThe grid of element applies positive voltage or negative voltage, to control the conducting of multiple switch elements and to close, fromAnd export desirable gate drive signal, and, in order to ensure that gate driver circuit can export enoughLarge voltage, generally adopts larger the pulling up transistor of channel width-over-length ratio, still, and due to upper crystal pullingThe channel width-over-length ratio of pipe is larger, can cause again the grid that pulls up transistor and the parasitism electricity of source electrode or drain electrodeHold larger, therefore, when multiple clock signals carry out generating positive and negative voltage switch time, the grid pulling up transistorCan produce larger coupling effect with the parasitic capacitance of source electrode or drain electrode, on the grid that pulls up transistor thereforeCan retain some noise charge, cause the leakage current that pulls up transistor to increase, cause low on grid cablingOn level, occur gate line noise level, gate line noise level can increase along with the increase of temperature,Finally will cause the gate drive signal of drive element of the grid output unstable. In addition, when switch unitWhen the grid of part is applied in the overlong time of positive voltage, its threshold voltage will increase, and will lead like thisThe electric current output that causes switch element declines, in the time that switch element is applied in the overlong time of negative voltage, itsThreshold voltage will reduce, will cause like this leakage current of switch element excessive, makes switch elementClosing property variation. Meanwhile, stable switch in the stabilizing circuit in gate driver circuit in prior artThe grid of element is always in high level state, in the time that the grid stabilizing circuit working time is long, due toIts physical characteristic, stable switch element function is degenerated, and will affect its service life, and due to switchThe skew of the threshold voltage of element, the function of gate driver circuit may entanglement, will affect like thisThe normal work of gate driver circuit.
Therefore, be necessary to provide improved technical scheme to overcome the above technology existing in prior artProblem.
Summary of the invention
The main technical problem to be solved in the present invention is to provide that a kind of driving force is strong, long service life,And the gate driver circuit of good stability.
For solving the problems of the technologies described above, the invention provides a kind of gate driver circuit, comprise multistage gridUtmost point driver element, wherein every grade of drive element of the grid is for driving respectively a correspondence on display floaterGate line. Every grade of drive element of the grid comprises the first driver module and the second driver module, and first drivesDynamic model piece and the second driver module include the first to the 8th switch element. Described the first switch element bagDraw together the first path terminal, alternate path end and the first control end, described the first path terminal receives the first referenceVoltage, described the first control end receives the first pulse signal. Described second switch element comprises threewayTerminal, four-way terminal and the second control end, described three-way termination is received the first clock signal, instituteState that the second control end is connected with the alternate path end of described the first switch element and by the first electric capacity withThe four-way terminal of second switch element is connected, described four-way terminal output gate drive signal. InstituteState the 3rd switch element and comprise five-way terminal, the 6th path terminal and the 3rd control end, described five-wayTerminal is connected with the alternate path end of described the first switch element, and described the 3rd control end receives the second arteries and veinsRush signal, the 6th path terminal receives the second reference voltage. Described the 4th switch element comprises the 7th pathEnd, the 8th path terminal and the 4th control end, described the 7th path terminal receives low reference voltage, and described theFour control ends receive described the first pulse signal. Described the 5th switch element comprises the 9th path terminal,Ten path terminal and the 5th control end, the four-way road of described the 9th path terminal and described second switch elementEnd is connected, and described the 5th control end receives described the second pulse signal, and described the tenth path terminal receives instituteState low reference voltage. Described the 6th switch element comprises the 11 path terminal, the 12 path terminal andSix control ends, described the 6th control end receives the second clock signal. Described the 7th switch element comprisesTen threeway terminals, the tenth four-way terminal and the 7th control end, described the tenth threeway terminal and the described the 6thThe 12 path terminal of switch element is connected, and described the tenth four-way terminal receives described low reference voltage,Described the 7th control end is connected with the alternate path end of described the first switch element. Described the 8th switch unitPart comprises the tenth five-way terminal, the 16 path terminal and the 8th control end, described the tenth five-way terminal withThe four-way terminal of described second switch element is connected, and it is low that described the 16 path terminal receives described referenceVoltage, described the 8th control end is connected with the 12 path terminal of described the 6th switch element. Wherein,Described the first pulse signal that the second level and above drive element of the grid receive is for upwards differing one-levelThe upper level gate drive signal of drive element of the grid output, the first order is to the grid of penultimate stageDescribed the second pulse signal that driver element receives is the drive element of the grid output that differs one-level downwardsNext stage gate drive signal, the 11 path of the 6th switch element of described the first driver moduleThe 11 of the 3rd clock signal that termination is received and the 6th switch element of described the second driver module leads toThe current potential of the 4th clock signal that terminal receives is contrary.
In gate driver circuit of the present invention, first and second driver module is all exported gate drive signal,Not only improve the driving force of gate driver circuit, and its burning voltage module intermittent work,Improve the service life of gate driver circuit, and reduced the risk abnormal because of threshold voltage shift,Good stability.
By the detailed description below with reference to accompanying drawing, it is obvious that other side of the present invention and feature become.But it should be known that the only object design for explaining of accompanying drawing, instead of as scope of the present inventionLimit, this is because it should be with reference to additional claim. Should also be appreciated that, unless otherwise noted,The unnecessary accompanying drawing of drawing to scale, they only try hard to illustrate conceptually structure described herein and flow process.
Brief description of the drawings
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Fig. 1 is the every one-level drive element of the grid in the gate driver circuit of first embodiment of the inventionElectrical block diagram.
Fig. 2 is the every one-level drive element of the grid in the gate driver circuit of first embodiment of the inventionSequential schematic diagram.
Fig. 3 is the every one-level drive element of the grid in the gate driver circuit of second embodiment of the inventionStructural representation.
Fig. 4 a, 4b, 4c and 4d are every one-level drive element of the grid of the present invention at stabilization sub stage and itAfter analog result schematic diagram.
Fig. 5 a and Fig. 5 b are the 3rd clock signal in every one-level drive element of the grid of the present inventionThe voltage analog result of CLK_L and node D_L, the 4th clock signal CLK_R and node D_RContrast schematic diagram.
Fig. 6 a and Fig. 6 b are the grid that every one-level drive element of the grid of the present invention and prior art drivesThe voltage difference analog result contrast schematic diagram of the gate drive signal that the two ends of line receive.
Detailed description of the invention
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with attachedFigure is described in detail the specific embodiment of the present invention.
Although the present invention with first, second, third, etc. term describe different elements, signal,Port, assembly or part, but these elements, signal, port, assembly or part are not subject to theseThe restriction of term. These terms be only for by an element, signal, port, assembly or part withAnother element, signal, port, assembly or part make a distinction. In the present invention, element,Port, assembly or part and another element, port, assembly or part " being connected ", " connection ",Can be understood as direct electric connection, or also can be understood as and have indirectly electrically connecting of intermediary elementConnect. Unless otherwise defined, otherwise all terms used in the present invention (comprise technical term and scienceTerm) there is the meaning of conventionally understanding with those skilled in the art.
Gate driver circuit of the present invention (also referred to as shift register) comprises multistage drive element of the grid(also referred to as shifting deposit unit), the drive element of the grid of every one-level respectively with display floater on everyA line gate line is corresponding to be electrically connected, thereby gate drive signal Gn is sequentially successively applied to every rowOn gate line, the annexation between drive element of the grid will elaborate hereinafter.
The first embodiment
Fig. 1 is the every one-level drive element of the grid in the gate driver circuit of first embodiment of the inventionElectrical block diagram, every one-level drive element of the grid is used for exporting one-level gate drive signal, withDrive respectively a corresponding gate line on display floater. The present embodiment gate driver circuit, comprisesMultistage drive element of the grid as shown in Figure 1, drive element of the grid shown in Fig. 1 is used for exporting grid and drivesMoving signal Gn, and in order to drive a corresponding gate line on display floater. Every grade of grid drivesUnit comprises the first driver module 10_L and the second driver module 10_R, the first driver module 10_LAnd second driver module 10_R be positioned at corresponding gate line two ends, all drive for exporting gridSignal Gn, to drive load resistance Rload, load capacitance Cload, and the first driver module 10_LAlternately open in two adjacent frames with the second driver module 10_R, reduced by the first driver moduleThe working time of 10_L or the second driver module 10_R, improve the driving energy of gate driver circuitPower.
Particularly, the first driver module 10_L and the second driver module 10_R include the first switchElement M1, second switch element M2, the 3rd switch element M3, the 4th switch element M4,Five switch element M5, the 6th switch element M6, the 7th switch element M7, the 8th switch elementM8, the connected mode of the switch element M1-M8 in its first driver module 10_L and second drivesThe connected mode of switch element M1-M8 in module 10_R is similar, and difference is only the first drivingWhat one of them path terminal of the 6th switch element M6 of module 10_L received is the 3rd clock signalCLK_L, and one of them path termination of the 6th switch element M6 of the second driver module 10_RThat receive is the 4th clock signal CLK_R.
Wherein, the first switch element M1 comprises the first path terminal, alternate path end and the first control end,The first path terminal receives the first reference voltage VDF, the first control end receive the first pulse signal toOn differ the upper level gate drive signal Gn-1 that the drive element of the grid of one-level is exported. Second opensClose element M2 and comprise threeway terminal, four-way terminal and the second control end, three-way termination is receivedThe first clock signal CLK1, the second control end is connected with the alternate path end of the first switch element M1And be connected with the four-way terminal of second switch element M2 by the first capacitor C 1, four-way terminalOutput gate drive signal Gn. The 3rd switch element M3 comprises five-way terminal, the 6th path terminalWith the 3rd control end, five-way terminal is connected with the alternate path end of the first switch element M1, and the 3rdControl end receives the second pulse signal, and the 6th path terminal receives the second reference voltage VDB.
The 4th switch element M4 comprises the 7th path terminal, the 8th path terminal and the 4th control end, the 7thPath terminal receives low reference voltage VGL, and the 4th control end receives the first pulse signal Gn-1. The 5thSwitch element M5 comprises the 9th path terminal, the tenth path terminal and the 5th control end, the 9th path terminal withThe four-way terminal of second switch element M2 is connected, the 5th control end receive the second pulse signal toUnder differ the next stage gate drive signal Gn+1 that the drive element of the grid of one-level is exported, the tenth is logicalTerminal receives low reference voltage VGL. The 6th switch element M6 comprises the 11 path terminal, the tenthTwo path terminal and the 6th control end, the 6th control end receives the second clock signal CLK2. Minion is closedElement M7 comprises the tenth threeway terminal, the tenth four-way terminal and the 7th control end, the tenth threeway terminalBe connected with the 12 path terminal of the 6th switch element M6, the tenth four-way terminal receives low reference voltageVGL, the 7th control end is connected with the alternate path end of the first switch element M1. The 8th switch elementM8 comprises the tenth five-way terminal, the 16 path terminal and the 8th control end, the tenth five-way terminal andThe four-way terminal of two switch element M2 is connected, and the 16 path terminal receives low reference voltage VGL,The 8th control end is connected with the 12 path terminal of the 6th switch element M6. Wherein, the 6th switch unitPart M6, the 7th switch element M7 and the 8th switch element M8 have formed the first stable module.
Suppose that the present embodiment drive element of the grid is n level drive element of the grid, wherein, n >=2, itsThe gate drive signal of output is Gn, and its first pulse signal receiving is upwards to differ one-levelThe upper level gate drive signal that drive element of the grid is exported is Gn-1, the second arteries and veins that it receivesRushing signal for the next stage gate drive signal that differs the drive element of the grid of one-level downwards and export isGn+1. Because first order drive element of the grid does not upwards differ the drive element of the grid of one-level,Rear one-level drive element of the grid does not differ the drive element of the grid of one-level downwards, therefore, and first order gridThe first pulse signal that utmost point driver element receives is provided by the first outside source, the second level and aboveThe first pulse signal that drive element of the grid receives is the drive element of the grid output that upwards differs one-levelUpper level gate drive signal Gn-1, the every one-level drive element of the grid except afterbody connectsThe second pulse signal of receiving is that the next stage grid that differs the drive element of the grid output of one-level downwards drivesMoving signal Gn+1, the second pulse signal that the drive element of the grid of afterbody receives is by the second outsideSignal source provides.
Wherein, the 11 path terminal of the 6th switch element M6 of the first driver module 10_L receivesThe 3rd clock signal CLK_L and the 6th switch element M6 of the second driver module 10_RThe current potential of the 4th clock signal CLK_R that 11 path terminal receive is contrary, to control the first driving mouldThe 8th switch element M8 of piece 10_L or the 8th switch element M8 of the second driver module 10_RAt one time, only have one of them conducting, control the stabilizing circuit of the first driver module 10_LWith the stabilizing circuit of the second driver module 10_R according to the 3rd clock signal CLK_L and the 4th sequentialSignal CLK_R intermittent work, thereby the gate drive signal that every grade of drive element of the grid is exportedStable.
In the present embodiment, the 3rd clock signal CLK_L is in the time that display floater shows odd-numbered frame pictureFor high level, in the time that display floater shows even frame picture, be low level. The 4th clock signal CLK_RIn the time that display floater shows even frame picture, be high level, in the time that display floater shows odd-numbered frame picture, beLow level. Therefore,, in the time that display floater shows odd-numbered frame picture, the first driver module 10_L's is steadyDetermine circuit working, in the time that display floater shows even frame picture, the second driver module 10_R's is stableCircuit working, so that the gate drive signal of every grade of drive element of the grid output is stable.
In other embodiments, can be also: the 3rd clock signal CLK_L is aobvious at display floaterWhile showing even frame picture, be high level, be low level in the time that display floater shows odd-numbered frame picture, the 4thClock signal CLK_R is low level in the time that display floater shows even frame picture, aobvious at display floaterIt while showing odd-numbered frame picture, is high level. Therefore,, in the time that display floater shows even frame picture, first drivesThe stabilizing circuit work of dynamic model piece 10_L, in the time that display floater shows odd-numbered frame picture, second drivesThe stabilizing circuit work of module 10_R, so that the gate drive signal of every grade of drive element of the grid outputStable.
In one embodiment of the present invention, the first capacitor C 1 is the parasitism of second switch element M2Electric capacity. Certainly it will be appreciated by those skilled in the art that, also can be at second switch element M2The second control end and four-way terminal between separate storage electric capacity is set, now, the first capacitor C 1For parasitic capacitance and the separate storage electric capacity sum of second switch element M2, to promote the first electric capacityOn C1, draw effect, can reduce second switch element M2 simultaneously because the first clock signal CLK1The capacitance coupling effect that saltus step causes.
In one embodiment of the present invention, first switch element to the eight switch element M1～M8 areN-type transistor. The first control end to the eight control ends are grid. First of the first switch element M1The threeway terminal of path terminal, second switch element M2, the five-way road of the 3rd switch element M3The 9th path terminal of the 7th path terminal, the 5th switch element M5 of end, the 4th switch element M4,The 11 path terminal of the 6th switch element M6, the tenth threeway terminal of the 7th switch element M7,The tenth five-way terminal of the 8th switch element M8 is drain electrode. Second of the first switch element M1 leads toThe four-way terminal of terminal, second switch element M2, the 6th path terminal of the 3rd switch element M3,The 8th path terminal of the 4th switch element M4, the tenth path terminal, the 6th of the 5th switch element M5The 12 path terminal of switch element M6, the tenth four-way terminal, the 8th of the 7th switch element M7The 16 path terminal of switch element M8 is source electrode.
Certainly, it will be appreciated by persons skilled in the art that the first switch element to the eight switch elementsM1～M8 also can adopt other switch element and realize for example P transistor npn npn. Below withOne switch element to the eight switch element M1～M8 are that N-type transistor is that example is introduced this particularlyDetailed description of the invention and the operation principle thereof of invention.
Refer to Fig. 2, it is the sequential schematic diagram of the drive element of the grid of the first embodiment, please be simultaneouslyConsult Fig. 1 and Fig. 2, the 4th clock signal CLK_R is in the time that display floater shows odd-numbered frame pictureHigh level is low level in the time that display floater shows even frame picture. That is to say, first drives mouldThe 3rd clock signal CLK_L that the 11 path terminal of the 6th switch element M6 of piece 10_L receivesReceive with the 11 path terminal of the 6th switch element M6 of the second driver module 10_R the 4th o'clockThe current potential of sequential signal CLK_R is contrary, to control the 8th switch element of the first driver module 10_LThe 8th one of them conducting of switch element M8 of M8 and the second driver module 10_R, controlsThe stabilizing circuit of the stabilizing circuit of one driver module 10_L and the second driver module 10_R is according to demonstrationThe variation intermittent work of the frame number of Display panel, to shorten switch element in every grade of grid unitGrid is applied in the duration of positive voltage or negative voltage, reduces the skew of the threshold voltage of switch element,Thereby make the gate drive signal of every grade of drive element of the grid output stable.
Wherein, the first reference voltage VDF is contrary with the current potential of the second reference voltage VDB. At thisIn one embodiment of invention, the first reference voltage VDF is high voltage, the second reference voltage VDBFor low-voltage.
The course of work of every one-level drive element of the grid be divided into pre-charging stage, on draw stage, drop-down rankSection, 4 stages of stabilization sub stage:
First stage is pre-charging stage: the upper level that upwards differs the drive element of the grid output of one-levelGate drive signal Gn-1 is high level, and the first switch element M1 and the 4th switch element M4 are equalConducting, because the second reference voltage VDF is high voltage, node Q is by the first switch unit of conductingPart M1 is precharged, and second switch element M2 conducting, due to the first clock signal CLK1 nowBe low level, the gate drive signal Gn of drive element of the grid at the corresponding levels output is by the 4th of conductingSwitch element M4 and second switch element M2 maintain electronegative potential.
Second stage is drawn the stage: the level of the first clock signal CLK1 is during by low uprising, due toAt pre-charging stage node, Q is precharged, therefore second switch element M2 conducting. Due to secondThe conducting of switch element M2, the voltage of the output Gn of drive element of the grid is by the first clock signalThe high level of CLK1 is drawn high, and due to the boot strap of the first capacitor C 1, along with grid drives singleThe rising of the voltage of unit's output, it can make the voltage of node Q further be drawn high, and nodeFurther drawing high of Q place voltage, makes second switch element M2 conducting ground more abundant, thereby makesThe voltage that obtains drive element of the grid output is further drawn high. Because node Q is high potential, because ofThis, the 7th switch element M7 conducting, the voltage of node D_L and node D_R is low level,The 8th switch element M8 is in cut-off state.
It should be noted that in the present invention, can directly adopt the parasitism of second switch element M2Electric capacity is as the first capacitor C 1, or draws effect on promoting, can also be at second switch elementBetween the second control end of M2 and four-way terminal, separate storage electric capacity is set, wherein, this is independently depositedAccumulate holds in parallel also jointly as the first capacitor C 1, with the parasitic capacitance of second switch element M2The first capacitor C 1 equals the parasitic capacitance of second switch element M2 and memory capacitance sum independently.
Phase III is the drop-down stage: differ the next stage of the drive element of the grid output of one-level downwardsGate drive signal Gn+1 becomes high level from low level, the 3rd switch element M3 and the 5th switchElement M5 conducting, because the second reference voltage VDB is low-voltage, node Q is by of conductingThree switch element M3 are pulled to electronegative potential, the gate drive signal of drive element of the grid output at the corresponding levelsGn is dragged down by the 5th switch element M5 of conducting.
Fourth stage is the stabilization sub stage: in the time of the drop-down stage, and the basis that drive element of the grid at the corresponding levels is exportedLevel gate drive signal Gn has been pulled low to low level, therefore, within the follow-up time, steadyDetermine the stage, need to make gate drive signal Gn at the corresponding levels maintain low level, thereby obtain desirable rippleShape. But, because the first clock signal CLK1 is clock signal, its within the follow-up time (After stabilization sub stage) also can ceaselessly produce pulse, can be to the grid of the output of drive element of the grid at the corresponding levelsThe utmost point drives signal Gn to exert an influence, and in order to eliminate these impacts, the embodiment of the present invention is utilized switch unitPart M6-M8 improves.
Particularly, within the follow-up time, when the first clock signal CLK1 becomes high electricity from low levelAt ordinary times, node Q can be because of the parasitic capacitance coupling between the grid of second switch element M2 and drain electrodeProduce noise, the noise of node Q can make second switch element M2 have conducting to a certain degree, theThe high level of one clock signal CLK1 charges to the output of drive element of the grid at the corresponding levels, draws highThe voltage of drive element of the grid output at the corresponding levels. Meanwhile, because the second clock signal CLK2 also can be byLow level becomes high level, that is to say, and the 6th switch element M6 conducting, and drive due to firstThe 3rd clock signal that the 11 path terminal of the 6th switch element M6 of dynamic model piece 10_L receivesThe 11 path terminal of the 6th switch element M6 of CLK_L and the second driver module 10_R receivesThe current potential of the 4th clock signal CLK_R is contrary all the time, therefore, node D_L and node D_R itsIn one of voltage be high level, thereby the 8th switch element M8 of the first driver module 10_L orThe 8th one of them conducting of switch element M8 of the second driver module 10_R, to drag down grid at the corresponding levelsIn driver element, the grid of the first driver module 10_L and the second driver module 10_R output drives letterNumber Gn, even and the second clock signal CLK2 become low level from high level, due at upper single orderOne of them voltage of Duan Jiedian D_L and node D_R is high level, therefore the first driver moduleThe 8th switch element M8 of 10_L or the 8th switch element M8 of the second driver module 10_R are whereinOne of still conducting, drive to drag down the first driver module 10_L and second in drive element of the grid at the corresponding levelsThe gate drive signal Gn of dynamic model piece 10_R output. That is to say, the first driver module 10_L'sThe stabilizing circuit energy intermittent work of stabilizing circuit and the second driver module 10_R, drives to shorten firstThe grid of the switch element in dynamic model piece 10_L or the second driver module 10_R be applied in positive voltage orThe duration of negative voltage, reduces the skew of the threshold voltage of switch element, so that every grade of grid drivesThe gate drive signal Gn of the first driver module 10_L and the second driver module 10_R output in unitAll stable.
Therefore, although be subject to the impact of the first clock signal CLK1 high level, node Q and grid at the corresponding levelsThe voltage at the output Gn place of utmost point driver element can be by drawing high to a certain degree, still, and due to switchThe effect of element M6-M8, it can drag down the defeated of the voltage of node Q and drive element of the grid at the corresponding levelsGo out to hold the voltage of Gn, and then make the first driver module 10_L and second in drive element of the grid at the corresponding levelsThe gate drive signal Gn of driver module 10_R output all can maintain low level.
In like manner, when the first clock signal CLK1 second and pulse subsequently former during by high step-downReason with when the first clock signal CLK1 is second and pulse subsequently during by low uprising, node Q,The voltage of the gate drive signal Gn of the first driver module 10_L and the second driver module 10_R outputThe principle that is pulled down to low reference voltage VGL is identical, does not repeat them here.
By seeing the description of the present embodiment SECO, the drive element of the grid of the present embodimentThe first driver module 10_L and the second driver module 10_R all can export gate drive signal Gn, withDrive load resistance Rload, load capacitance Cload, thus the driving that has improved gate driver circuitAbility. In addition, due to the 11 path of the 6th switch element M6 of the first driver module 10_LThe 3rd clock signal CLK_L that termination is received and the 6th switch element M6 of the second driver module 10_RThe current potential of the 4th clock signal CLK_R that receives of the 11 path terminal contrary all the time, therefore, theThe 8th switch element M8 of one driver module 10_L or the 8th switch of the second driver module 10_ROne of them conducting of element M8, to drag down the first driver module 10_L in drive element of the grid at the corresponding levelsAnd the gate drive signal Gn of the second driver module 10_R output, that is to say, first drives mouldThe stabilizing circuit intermittent work of the stabilizing circuit of piece 10_L and the second driver module 10_R, to contractThe grid of the switch element in short the first driver module 10_L or the second driver module 10_R is applied inThe duration of positive voltage or negative voltage, improve the service life of gate driver circuit, and reducedBecause of the abnormal risk of threshold voltage shift, good stability.
The second embodiment
Fig. 3 is the every one-level drive element of the grid in the gate driver circuit of second embodiment of the inventionStructural representation, every one-level drive element of the grid is used for exporting one-level gate drive signal, with respectivelyDrive a corresponding gate line on display floater. As shown in Figure 3, in the present embodiment, firstDriver module 10_L ' and the second driver module 10_R ' also include the 9th switch element M9, the tenthSwitch element M10, the 11 switch element M11 and twelvemo are closed element M12. The 9th switchElement M9 comprises the 17 path terminal, the 18 path terminal and the 9th control end, the 17 path andThe 9th control end receives the first clock signal CLK1. The tenth switch element M10, comprises that the 19 is logicalTerminal, the 20 path terminal and the tenth control end, the 19 path terminal and the 9th switch element M9The 18 path terminal be connected, the tenth control end is connected with the alternate path end of the first switch element, the20 path terminal receive low reference voltage VGL. The 11 switch element M11, comprises the 21Path terminal, the 22 path terminal and the 11 control end, the 21 path terminal and the first switch unitThe alternate path end of part is connected, and the 22 path terminal receives low reference voltage VGL, the 11 controlSystem end is connected with the 18 path terminal of the 9th switch element M9. Twelvemo is closed element M12,Comprise the 20 threeway terminal, the 20 four-way terminal and the 12 control end, the 20 threeway terminalBe connected with the four-way terminal of second switch element, the 20 four-way terminal receives low reference voltageVGL, the 12 control end is connected with the 18 path of the 9th switch element M9.
The course of work of every one-level drive element of the grid as shown in Figure 3 and every one-level as shown in Figure 1The course of work principle of drive element of the grid is similar, and its difference is:
Be the stabilization sub stage in fourth stage, for eliminate due to the first clock signal CLK1 its follow-upTime in (be stabilization sub stage after) pulse of ceaselessly producing, and to drive element of the grid at the corresponding levelsThe impact of stability of gate drive signal Gn of output, the present embodiment not only utilizes switch elementM6-M8, also utilizes the 9th switch element to the twelvemo to close element M9-M12 and improves.
Particularly, within the follow-up time, when the first clock signal CLK1 becomes high electricity from low levelAt ordinary times, node Q can be by the parasitic capacitance coupling between the grid of second switch element M2 and drain electrode andProduce noise, second switch element M2 conducting, the high level of the first clock signal CLK1 is to the corresponding levelsThe output of drive element of the grid charges, and draws high the voltage of drive element of the grid output at the corresponding levels.Due to when the first clock signal CLK1 is when low level becomes high level, the 9th switch element M9 leadsLogical, the voltage at node P place is pulled up to high voltage, the 11 switch element M11 and twelvemoClose the equal conducting of element M12, node Q is dragged down by the 11 switch element M11 of conducting, gridThe voltage of the gate drive signal Gn of utmost point driver element output closes element by the twelvemo of conductingM12 is dragged down. Switch element M6-M8 is operation principle and Fig. 1 of stabilization sub stage in fourth stageThe operation principle of described gate driver circuit is identical, does not repeat them here.
Therefore, although be subject to the impact of the first clock signal CLK1 high level, node Q and grid at the corresponding levelsThe voltage at the output Gn place of utmost point driver element can be drawn high, still, and due to switch element M6-M8And the effect of M9-M12, it can drag down in the voltage of node Q and drive element of the grid at the corresponding levelsThe voltage of the gate drive signal Gn of one driver module 10_L and the second driver module 10_R output,And then make in drive element of the grid at the corresponding levels the first driver module 10_L and the second driver module 10_R defeatedThe gate drive signal Gn going out all can maintain low level.
In like manner, when the first clock signal CLK1 second and pulse subsequently former during by high step-downReason with when the first clock signal CLK1 is second and pulse subsequently during by low uprising, node QAnd the voltage of gate drive signal Gn at the corresponding levels to be pulled down to the principle of low reference voltage VGL identical,Do not repeat them here.
Fig. 4 a, 4b, 4c, 4d are every one-level drive element of the grid of the present invention at stabilization sub stage and itAfter analog result schematic diagram. Please refer to Fig. 1, Fig. 3 and Fig. 4 a-4d, Fig. 4 a first drivesIn dynamic model piece 10_L, 10_L ', node D_L is stabilization sub stage and the knot of simulation afterwards in fourth stageFruit schematic diagram. Fig. 4 b is that in the second driver module 10_R, 10_R ', node D_R is in fourth stageStabilization sub stage and analog result schematic diagram afterwards. Fig. 4 c is the first driver module 10_L, 10_L 'The gate drive signal Gn of output is stabilization sub stage and analog result afterwards in fourth stage. Fig. 4 dThe gate drive signal Gn that is the second driver module 10_R, 10_R ' output is stable in fourth stageStage and analog result afterwards. As can be seen from Figure 4, node D_L and node D_R are alternatelyHigh level, that is to say, the first driver module 10_L, 10_L ' and the second driver module 10_R,The 8th switch element M8 intermittent conduction of 10_R ', thus make the first driver module 10_L, 10_L 'And the gate drive signal Gn of the second driver module 10_R, 10_R ' output all can keep stablizing.
In addition, because can making the 7th switch element M7, the noise of node Q has conducting to a certain degree,And node D_L (D_R) has certain leaky by the 7th switch element M7 of conducting,Thereby cause node D_L (D_R) can not within the time of a frame, maintain needed high electricity alwaysLevel state, therefore, the circuit in the present invention within the time of a frame, make CLK2 (CLK1) inLow and high level is the state of conversion constantly, like this, in a frame time always in high level stateCLK_L (CLK_R) can ceaselessly give node D_L (D_R) with high level pulse, makes oneDirectly maintain needed high level state, and be not subject to effect of leakage. When CLK2 (CLK1) locatesIn low and high level constantly when the state of conversion, due to the impact of the parasitic capacitance of the 6th switch element M6,Do like this and make the voltage of node D_L (D_R) can produce certain noise phenomenon simultaneously, as Fig. 4 a(Fig. 4 b) shown in, but node D_L (D_R) is in height within most times of a frameLevel state, can meet the needs of circuit completely, and compared to effect of leakage, noise phenomenon is to circuitImpact is little, can ignore completely.
Fig. 5 a is the 3rd clock signal CLK_L and joint in every one-level drive element of the grid of the present inventionThe voltage analog result contrast schematic diagram of point D_L, Fig. 5 b is that every one-level grid of the present invention drives listThe voltage analog result of the 4th clock signal CLK_R and node D_R contrast schematic diagram in unit. AsShown in Fig. 5 a, 5b, the voltage of node D_L and node D_R respectively with the 3rd clock signal CLK_LAnd the 4th clock signal CLK_R synchronous, therefore, the voltage of node D_L and node D_R is onlyChange according to the 3rd clock signal CLK_L and the 4th clock signal CLK_R respectively, therefore, canBy adjusting the low and high level size of the 3rd clock signal CLK_L and the 4th clock signal CLK_R,Thereby make the threshold voltage at dwell period of the 8th switch element M8 obtain compensation, and then furtherReduce the threshold voltage shift amount of gate driver circuit.
In addition, because can making the 7th switch element M7, the noise of node Q has conducting to a certain degree,And node D_L (D_R) has certain leaky by the 7th switch element M7 of conducting,Thereby cause node D_L (D_R) can not within the time of a frame, maintain needed high electricity alwaysLevel state, therefore, the circuit in the present invention within the time of a frame, make CLK2 (CLK1) inLow and high level is the state of conversion constantly, like this, in a frame time always in high level stateCLK_L (CLK_R) can ceaselessly give node D_L (D_R) with high level pulse, makes oneDirectly maintain needed high level state, and be not subject to effect of leakage. When CLK2 (CLK1) locatesIn low and high level constantly when the state of conversion, due to the impact of the parasitic capacitance of the 6th switch element M6,Do like this and make the voltage of node D_L (D_R) can produce certain noise phenomenon simultaneously, as Fig. 5 a(Fig. 5 b) shown in, but node D_L (D_R) is in height within most times of a frameLevel state, can meet the needs of circuit completely, and compared to effect of leakage, noise phenomenon is to circuitImpact is little, can ignore completely.
Fig. 6 a and Fig. 6 b are the grid that every one-level drive element of the grid of the present invention and prior art drivesThe voltage difference analog result contrast schematic diagram of the gate drive signal that the two ends of line receive. Wherein, figure6a is the corresponding gate line that drives of every one-level drive element of the grid of the second embodiment of the present inventionThe voltage difference analog result schematic diagram of the gate drive signal that the load at two ends receives, Fig. 6 b is for existingThere is the load at the two ends of the corresponding gate line of the every one-level drive element of the grid driving in technology to receiveThe voltage difference analog result schematic diagram of the gate drive signal arriving. Please refer to Fig. 1, Fig. 3 and figureShown in 6a, every one-level drive element of the grid of the present invention adopts the first identical driver module of structure10_L, 10_L ' and the second driver module 10_R, 10_R ' export respectively gate drive signal Gn extremelyThe two ends of gate line, the load connecting with driving grid line, therefore, is being driven by same gate lineEvery a line pixel cell in, first pixel cell and last pixel cell are also gate lineThe voltage difference of the gate drive signal Gn that two ends receive is about 0.2 volt (V), although due toThe impact that Q is ordered, can there is certain noise problem in the voltage difference of gate drive signal Gn, but all locateIn the scope of 0.2 volt (V). And the drive element of the grid of prior art is only from gate lineOne end input gate drive signal, and stabilizing circuit is always in high level, therefore, and as Fig. 6 b instituteShow, in the every a line pixel cell being driven by same gate line, due to declining of gate drive signalSubtract, the gate drive signal that on this row, first pixel cell receives with last pixel cellThe about 2.5V of voltage difference, it is obviously greater than 0.2V. Therefore, gate driver circuit of the present invention can reduceEvery row pixel cell is because of the voltage differences of the gate drive signal Gn that receives, and causes picture inequalityRisk.
In sum, the first driver module 10_L, the 10_L ' in gate driver circuit of the present inventionAnd the second driver module 10_R, 10_R ' all can export gate drive signal Gn, to drive load electricityResistance Rload, load capacitance Cload, and the first driver module 10_L, 10_L ' drive mould with secondPiece 10_R, 10_R ' alternately open in two adjacent frames, reduced the first driver module 10_L,The working time of 10_L ' or the second driver module 10_R, 10_R ', drive electricity thereby improved gridThe driving force on road, and the gate drive signal of the two ends that reduced every row pixel cell because receivingThe voltage differences of Gn, and the risk of the picture inequality causing. In addition, due to the first driver module 10_L,The 6th switch element M6 of 10_L ' the 11 path terminal receive the 3rd clock signal CLK_L withThe 11 path terminal of the 6th switch element M6 of the second driver module 10_R, 10_R ' receive theThe current potential of four clock signal CLK_R is contrary all the time, therefore, and the 8th of the first driver module 10_LThe 8th switch element M8 of switch element M8 or the second driver module 10_R, 10_R ' one of themConducting, drives to drag down the first driver module 10_L, 10_L ' and second in drive element of the grid at the corresponding levelsThe gate drive signal Gn of module 10_R, 10_R ' output, that is to say, the first driver module 10_L,The stabilizing circuit intermittent work of the stabilizing circuit of 10_L ' and the second driver module 10_R, to shortenThe grid of the switch element in the first driver module 10_L or the second driver module 10_R is just applied inThe duration of voltage or negative voltage, and because CLK_L and CLK_R are independent of grid to driveMoving circuit clock signal, can take different low and high levels to establish according to threshold voltage drift situationPut, improved the service life of gate driver circuit, and reduced because of threshold voltage shift abnormalRisk, good stability.
Having applied specific case has herein carried out gate driver circuit of the present invention and embodimentSet forth, the explanation of above embodiment is just for helping to understand method of the present invention and core concept thereof;Meanwhile, for one of ordinary skill in the art, according to thought of the present invention, in detailed description of the inventionAnd all will change in range of application, to sum up, this description should not be construed as the present inventionRestriction, protection scope of the present invention should be as the criterion with appended claim.
Claims (10)
1. a gate driver circuit, comprises multistage drive element of the grid, every grade of drive element of the gridFor driving a corresponding gate line on display floater respectively, it is characterized in that, every grade of grid drivesMoving cell comprises the first driver module and the second driver module, the first driver module and the second driver moduleInclude:
The first switch element, comprises the first path terminal, alternate path end and the first control end, describedOne path terminal receives the first reference voltage, and described the first control end receives the first pulse signal;
Second switch element, comprises threeway terminal, four-way terminal and the second control end, describedThree-way termination is received the first clock signal, second of described the second control end and described the first switch elementPath terminal is connected and is connected with the four-way terminal of second switch element by the first electric capacity, and the described the 4thPath terminal output gate drive signal;
The 3rd switch element, comprises five-way terminal, the 6th path terminal and the 3rd control end, describedFive-way terminal is connected with the alternate path end of described the first switch element, and described the 3rd control end receives theTwo pulse signals, the 6th path terminal receives the second reference voltage;
The 4th switch element, comprises the 7th path terminal, the 8th path terminal and the 4th control end, describedSeven path terminal receive low reference voltage, and described the 4th control end receives described the first pulse signal;
The 5th switch element, comprises the 9th path terminal, the tenth path terminal and the 5th control end, describedNine path terminal are connected with the four-way terminal of described second switch element, and described the 5th control end receives instituteState the second pulse signal, described the tenth path terminal receives described low reference voltage;
The 6th switch element, comprises the 11 path terminal, the 12 path terminal and the 6th control end, instituteState the 6th control end and receive the second clock signal;
The 7th switch element, comprises the tenth threeway terminal, the tenth four-way terminal and the 7th control end, instituteState the tenth threeway terminal and be connected with the 12 path terminal of described the 6th switch element, described the tenth four-wayTerminal receives described low reference voltage, and second of described the 7th control end and described the first switch element leads toTerminal is connected;
The 8th switch element, comprises the tenth five-way terminal, the 16 path terminal and the 8th control end, instituteState the tenth five-way terminal and be connected with the four-way terminal of described second switch element, described the 16 pathTermination is received described low reference voltage, the tenth two-way of described the 8th control end and described the 6th switch elementTerminal is connected;
Wherein, described the first pulse signal that the second level and above drive element of the grid receive is for upwardsThe upper level gate drive signal that differs the drive element of the grid output of one-level, the first order is to second from the bottomDescribed the second pulse signal that the drive element of the grid of level receives is that the grid that differs one-level downwards drivesThe next stage gate drive signal of unit output, the of the 6th switch element of described the first driver moduleThe 3rd clock signal that 11 path terminal receive and the 6th switch element of described the second driver moduleThe current potential of the 4th clock signal that the 11 path terminal receives is contrary.
2. gate driver circuit as claimed in claim 1, is characterized in that, the first driver moduleAnd second driver module also include:
The 9th switch element, comprises the 17 path terminal, the 18 path terminal and the 9th control end, instituteState the 17 path and described the 9th control end receives described the first clock signal;
The tenth switch element, comprises the 19 path terminal, the 20 path terminal and the tenth control end, instituteState the 19 path terminal and be connected with the 18 path terminal of described the 9th switch element, the described the tenth controlsEnd is connected with the alternate path end of described the first switch element, and described the 20 path terminal receives described ginsengExamine low-voltage;
The 11 switch element, comprises the 21 path terminal, the 22 path terminal and the 11 controlSystem end, described the 21 path terminal is connected with the alternate path end of described the first switch element, described inThe 22 path terminal receives described low reference voltage, described the 11 control end and described the 9th switchThe 18 path terminal of element is connected; And
Twelvemo is closed element, comprises the 20 threeway terminal, the 20 four-way terminal and the 12 controlSystem end, described the 20 threeway terminal is connected with the four-way terminal of described second switch element, described inThe 20 four-way terminal receives described low reference voltage, described the 12 control end and described the 9th switchThe 18 path of element is connected.
3. gate driver circuit as claimed in claim 1, is characterized in that, described the 3rd sequentialSignal is high level in the time that described display floater shows odd-numbered frame picture, shows even at described display floaterWhen number frame picture, be low level, described the 4th clock signal shows even frame picture at described display floaterTime be high level, in the time that described display floater shows odd-numbered frame picture, be low level.
4. gate driver circuit as claimed in claim 1, is characterized in that, described the 3rd sequentialSignal is high level in the time that described display floater shows even frame picture, shows strange at described display floaterWhen number frame picture, be low level, described the 4th clock signal shows odd-numbered frame picture at described display floaterTime be high level, in the time that described display floater shows even frame picture, be low level.
5. gate driver circuit as claimed in claim 1, is characterized in that, described the first electric capacityFor the parasitic capacitance between the second control end and the four-way terminal of second switch element.
6. gate driver circuit as claimed in claim 1, is characterized in that, described second switchBetween the second control end of element and four-way terminal, be provided with separate storage electric capacity, described the first electric capacityFor parasitic capacitance and described independence between the second control end and the four-way terminal of second switch elementMemory capacitance sum.
7. gate driver circuit as claimed in claim 1, is characterized in that, described the first switchElement to the eight switch elements are N-type transistor.
8. gate driver circuit as claimed in claim 7, is characterized in that, described first controlsEnd to described the 8th control end is grid, described first path terminal of described the first switch element, described inThe threeway terminal of second switch element, the five-way terminal of described the 3rd switch element, the described the 4thThe 7th path terminal of switch element, the 9th path terminal of described the 5th switch element, described the 6th switchThe 11 path terminal of element, the tenth threeway terminal of described the 7th switch element, described the 8th switchThe tenth five-way terminal of element is drain electrode, and the alternate path end of described the first switch element, described inThe four-way terminal of second switch element, the 6th path terminal of described the 3rd switch element, the described the 4thThe 8th path terminal of switch element, the tenth path terminal of described the 5th switch element, described the 6th switchThe 12 path terminal of element, the tenth four-way terminal of described the 7th switch element, described the 8th switchThe 16 path terminal of element is source electrode.
9. gate driver circuit as claimed in claim 1, is characterized in that, described the first switchTo described the 8th switch element, at least one of them is P transistor npn npn to element.
10. gate driver circuit as claimed in claim 2, is characterized in that, described the 9th switchElement to described twelvemo is closed element and is N-type transistor.
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| CN104992673B (en) | 2015-07-23 | 2017-09-22 | 京东方科技集团股份有限公司 | A kind of phase inverter, gate driving circuit and display device |
| CN107045846B (en) * | 2016-02-05 | 2019-10-18 | 奕力科技股份有限公司 | Panel drive circuit |
| CN106531100B (en) * | 2016-12-15 | 2019-04-02 | 昆山龙腾光电有限公司 | Display device and driving method |
| CN108665838A (en) * | 2017-03-27 | 2018-10-16 | 昆山工研院新型平板显示技术中心有限公司 | Scan drive circuit and its driving method and panel display apparatus |
| CN108665837B (en) * | 2017-03-27 | 2021-07-30 | 昆山工研院新型平板显示技术中心有限公司 | Scanning driving circuit, driving method thereof and flat panel display device |
| CN107146592B (en) * | 2017-07-20 | 2019-12-06 | 京东方科技集团股份有限公司 | Driving method and driving circuit of liquid crystal display panel and display device |
| CN107564450B (en) * | 2017-09-14 | 2021-03-12 | 昆山龙腾光电股份有限公司 | Gate drive circuit and display device |
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| CN101739960A (en) * | 2009-12-29 | 2010-06-16 | 友达光电股份有限公司 | Electrophoretic display device and driving method thereof |
| CN102402936A (en) * | 2011-11-23 | 2012-04-04 | 北京大学深圳研究生院 | Gate drive circuit unit, gate drive circuit and display device |
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| KR20100083370A (en) * | 2009-01-13 | 2010-07-22 | 삼성전자주식회사 | Gate driving circuit and display device having the same |
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| CN101510403A (en) * | 2009-02-23 | 2009-08-19 | 上海广电光电子有限公司 | Grid line drive device of liquid crystal display |
| CN101739960A (en) * | 2009-12-29 | 2010-06-16 | 友达光电股份有限公司 | Electrophoretic display device and driving method thereof |
| CN102402936A (en) * | 2011-11-23 | 2012-04-04 | 北京大学深圳研究生院 | Gate drive circuit unit, gate drive circuit and display device |
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Address after: 215301, 1, Longteng Road, Kunshan, Jiangsu, Suzhou Patentee after: Kunshan Longteng Au Optronics Co Address before: 215301, 1, Longteng Road, Kunshan, Jiangsu, Suzhou Patentee before: Kunshan Longteng Optronics Co., Ltd. |