CN104715732A - Grid driving circuit and display device - Google Patents
Grid driving circuit and display device Download PDFInfo
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- 239000004973 liquid crystal related substance Substances 0.000 description 7
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- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
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- 229910052738 indium Inorganic materials 0.000 description 2
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- 230000015556 catabolic process Effects 0.000 description 1
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Abstract
The invention discloses a grid driving circuit which comprises multiple stages of grid driving units. Each stage of grid driving unit comprises switch elements from first to tenth, wherein a first stable unit is composed of the fourth switch element and the fifth switch element, the control end, namely, the fourth control end of the fourth switch element and the fifth control end of the fifth switch element, of the first stable unit is connected with the public end of the sixth switch element and the seventh switch element, and a second stable unit is composed of the tenth switch element. The invention further provides a display device. The stable units of the grid driving circuit and the display device are composed of the switch elements, the control end of each first stable unit is charged through the corresponding switch elements each time a clock signal hops, the stability of the voltage of the control end of each first stable unit is ensured, and therefore the stability of a grid driving signal is improved; each stage of grid driving unit is only composed of the corresponding ten switch elements, and therefore the design of a narrow frame is facilitated, cost is low, and power consumption is low.
Description
Technical field
The present invention relates to display technique field, particularly a kind of gate driver circuit and display device.
Background technology
Liquid crystal indicator (Liquid Crystal Display, LCD) possesses the plurality of advantages such as frivolous, energy-conservation, radiationless, has therefore replaced traditional cathode-ray tube (CRT) (CRT) display gradually.Current liquid crystal display is widely used in the electronic equipments such as HD digital TV, desk-top computer, personal digital assistant (PDA), notebook computer, mobile phone, digital camera.
With thin film transistor (TFT) (Thin Film Transistor, TFT) liquid crystal indicator is example, it comprises: display panels and driving circuit, wherein, display panels comprises many gate lines and a plurality of data lines, and adjacent two gate lines and adjacent two data lines intersect to form a pixel cell, each pixel cell at least comprises a TFT.Driving circuit comprises gate driver circuit (gatedrive circuit) and source electrode drive circuit (source drive circuit).Along with the cost degradation pursuit of the producer to liquid crystal indicator and the raising of manufacturing process, originally the glass substrate that the driving circuit integrated chip be arranged at beyond display panels is arranged at display panels becomes possibility, such as, grid-driving integrated circuit is arranged at array base palte (Gate IC in Array, GIA) upper thus simplify the manufacture process of liquid crystal indicator, and reduce production cost.
The basic functional principle of display panels and driving circuit is: gate driver circuit is by sending gate drive signal with pulling up transistor to gate line of being electrically connected of gate line, sequentially the TFT of every a line is opened, then the pixel cell of a full line is charged to voltage required separately, to show different GTGs by source electrode drive circuit simultaneously.Namely first to be pulled up transistor by it by the gate driver circuit of the first row and the thin film transistor (TFT) of the first row opened, then charged by the pixel cell of source electrode drive circuit to the first row.When the pixel cell of the first row is charged, this row thin film transistor (TFT) just cuts out by gate driver circuit, then the gate driver circuit of the second row is pulled up transistor by it and to be opened by thin film transistor (TFT) of the second row, then carries out discharge and recharge by source electrode drive circuit to the pixel cell of the second row.So sequentially go down, when the pixel cell of substituting the bad for the good last column, just charge from the first row again.
At present, gate driver circuit adopts the TFT of amorphous silicon mostly, but because amorphous silicon mobility is lower, and the threshold voltage drift characteristic of amorphous silicon, the TFT playing transmission effect in gate driver circuit cannot under long-time stable be operated in a stable grid voltage, therefore, the difference of this operating characteristic of TFT finally easily causes the failure of signal transmission.In addition, gate driver circuit adopts gate drive signal as transmission of signal mostly, the grid voltage of the TFT of output action has been made to reach ideal height, thus the time delays that gate drive signal is exported, even make gate drive signal cannot realize effective transmission.
Prior art generally adopts novel TFT manufacture craft such as to adopt indium gallium zinc oxide IGZO (indium gallium zinc oxide, the breadth length ratio of TFT IGZO) or employing bistable system or increase TFT solves the problems referred to above, but said method is unfavorable for the design of the narrow frame of liquid crystal indicator, and cost is high and power consumption is large.
Summary of the invention
The main technical problem to be solved in the present invention is to provide a kind of gate driver circuit, and it while the gate drive signal of stable output, can be conducive to the design of narrow frame, and cost is low and power consumption is little.
For solving the problems of the technologies described above, the invention provides a kind of gate driver circuit, it comprises multiple drive element of the grid, and described every grade of drive element of the grid comprises the first on-off element, second switch element, the 3rd on-off element, the 4th on-off element, the 5th on-off element, the 6th on-off element, the 7th on-off element, the 8th on-off element, the 9th on-off element, the tenth on-off element.
Wherein, the first on-off element comprises the first path terminal, the first control end, alternate path end, and described first path terminal receives the first pulse signal, and described first control end receives the first transmission of signal, and described alternate path end is the output terminal of transmission of signal at the corresponding levels.Second switch element comprises third path end, the second control end, the 4th path terminal, described third path termination receives the first clock signal, described second control end is connected with the described alternate path end of described first on-off element, and be connected with described 4th path terminal by the first electric capacity, described 4th path terminal is the output terminal of every grade of drive element of the grid.
3rd on-off element comprises five-way terminal, the 3rd control end, the 6th path terminal, described five-way terminal is connected with the described alternate path end of described first on-off element, described 3rd control end receives the second transmission of signal, and the 6th path terminal receives the second pulse signal.4th on-off element comprises the 7th path terminal, the 4th control end, the 8th path terminal, and described 7th path terminal is connected with described 4th path terminal of described second switch element, and described 8th path terminal receives low reference voltage.
5th on-off element comprises the 9th path terminal, the 5th control end, the tenth path terminal, described 9th path terminal is connected with described second control end of described second switch element, described 5th control end is connected with described 4th control end of described 4th on-off element, and described tenth path terminal receives described low reference voltage.6th on-off element comprises the 11 path terminal, the 6th control end, the 12 path terminal, described 11 path terminal receives described first clock signal, described 6th control end is connected with described 11 path terminal, and the 12 path terminal is connected with described 5th control end of described 5th on-off element.7th on-off element comprises the tenth threeway terminal, the 7th control end, the 14 path terminal, described tenth threeway terminal and described 7th control end are all connected with described 5th control end of described 5th on-off element, and described 14 path terminal receives described low reference voltage.
8th on-off element comprises the tenth five-way terminal, the 8th control end, the 16 path terminal, described tenth five-way terminal is connected with described 5th control end of described 5th on-off element, described 8th control end is connected with described second control end of described second switch element, and described 16 path terminal receives described low reference voltage.9th on-off element comprises the 17 path terminal, the 9th control end, the 18 path terminal, described 17 path terminal is connected with described 5th control end of described 5th on-off element, described 9th control end receives second clock signal, and described 18 path terminal receives described low reference voltage.Tenth on-off element comprises the 19 path terminal, the tenth control end, the 20 path terminal, described 19 path terminal is connected with described 4th path terminal of described second switch element, described tenth control end receives described second clock signal, and described 20 path terminal receives described low reference voltage.
Preferably, described first electric capacity is the stray capacitance between described 4th path terminal of described second switch element and described second control end.
Preferably, be provided with separate, stored electric capacity between described second control end of described second switch element and described 4th path terminal, described first electric capacity is stray capacitance between described 4th path terminal of described second switch element and described second control end and described separate, stored electric capacity sum.
Preferably, if described gate driver circuit comprises N level drive element of the grid, described first transmission of signal that then described first control end of described first on-off element of n-th grade of drive element of the grid receives is the upper two-stage transmission of signal that the drive element of the grid upwards differing two-stage with n-th grade of drive element of the grid exports, wherein, n is integer, and n >=3.
Preferably, if described gate driver circuit comprises N level drive element of the grid, described second transmission of signal that then described 3rd control end of described 3rd on-off element of n-th grade of drive element of the grid receives is the lower two-stage transmission of signal that the drive element of the grid differing two-stage downwards with n-th grade of drive element of the grid exports, n≤N-2.
Preferably, if described gate driver circuit comprises N level drive element of the grid, described first pulse signal that then described first path terminal of described first on-off element of n-th grade of drive element of the grid receives is the upper level gate drive signal that the drive element of the grid upwards differing one-level with n-th grade of drive element of the grid exports, wherein, n is integer, and n >=2.
Preferably, if described gate driver circuit comprises N level drive element of the grid, described second pulse signal that then described 6th path terminal of described 3rd on-off element of n-th grade of drive element of the grid receives is the next stage gate drive signal that the drive element of the grid differing one-level downwards with n-th grade of drive element of the grid exports, wherein, n is integer, and 0≤n≤N-1.
Preferably, described first clock signal and described second clock signal are inversion signal.
Preferably, the breadth length ratio of described 6th on-off element is more than or equal to the breadth length ratio of described 7th on-off element.
The present invention also provides a kind of display device, and described display device comprises above-mentioned gate driver circuit.
In gate driver circuit of the present invention and display device, the first stabilization element (the 4th on-off element and the 5th on-off element) and the second stabilization element (the tenth on-off element) form by on-off element, and each saltus step of the first clock signal is all charged by the control end (the 4th control end of the 4th on-off element and the 5th control end of the 5th on-off element) of the 6th on-off element to the first stabilization element, ensure that the stability of the voltage of the control end of the first stabilization element, thus improve the stability of gate drive signal, and every grade of drive element of the grid is only made up of to the tenth on-off element the first on-off element, be conducive to the design of narrow frame, cost is low and power consumption is little.
By the detailed description below with reference to accompanying drawing, other side of the present invention and feature become obvious.But it should be known that accompanying drawing is only the object design of explanation, instead of as the restriction of scope of the present invention, this is because it should with reference to additional claim.Should also be appreciated that, unless otherwise noted, unnecessaryly draw accompanying drawing to scale, they only try hard to structure described herein and flow process are described conceptually.
Accompanying drawing explanation
Fig. 1 is the electrical block diagram of n-th grade of drive element of the grid in the gate driver circuit of first embodiment of the invention.
Fig. 2 is the time diagram of n-th grade of drive element of the grid in the gate driver circuit of first embodiment of the invention.
Fig. 3 is that the analog result of the magnitude of voltage of node QB at normal temperatures and under high temperature in the gate driver circuit of first embodiment of the invention and the gate driver circuit of prior art contrasts schematic diagram.
Fig. 4 is the current analog Comparative result schematic diagram of the gate driver circuit of first embodiment of the invention and first stabilization element of the gate driver circuit of prior art after the same time that works.
Fig. 5 is the analog result schematic diagram of the gate drive signal that the first order drive element of the grid of the gate driver circuit of first embodiment of the invention under cryogenic exports to level V drive element of the grid.
Embodiment
For further setting forth the present invention for the technological means reaching predetermined goal of the invention and take and effect, below in conjunction with accompanying drawing and preferred embodiment, to its embodiment of display panels proposed according to the present invention, method, step, structure, feature and effect, be described in detail as follows.
Aforementioned and other technology contents, feature and effect for the present invention, can clearly present in the detailed description of following cooperation with reference to graphic preferred embodiment.By the explanation of embodiment, when can to the present invention for the technological means reaching predetermined object and take and effect be able to more deeply and concrete understanding, however institute's accompanying drawings be only to provide with reference to and the use of explanation, be not used for being limited the present invention.
Although the present invention uses first, second, third, etc. term to describe different elements, signal, port, assembly or part, these elements, signal, port, assembly or part be not by the restriction of these terms.These terms are only used to an element, signal, port, assembly or part and another element, signal, port, assembly or part to make a distinction.In the present invention, element, port, assembly or a part and another element, port, assembly or part " being connected ", " connection ", can be understood as direct electric connection, or also can be understood as the indirect electric connection that there is intermediary element.Unless otherwise defined, otherwise all terms used in the present invention (comprising technical term and scientific terminology) have the meaning usually understood with those skilled in the art.
Gate driver circuit of the present invention (also referred to as shift register) comprises multistage drive element of the grid (also referred to as shifting deposit unit), the drive element of the grid of every one-level is corresponding with the every a line gate line on display panel to be respectively electrically connected, thus gate drive signal is sequentially successively applied to often on row gate line, the annexation between drive element of the grid will elaborate hereinafter.
Fig. 1 is the electrical block diagram of n-th grade of drive element of the grid in the gate driver circuit of first embodiment of the invention.The present embodiment gate driver circuit, comprises multistage drive element of the grid as shown in Figure 1, n-th grade of drive element of the grid for exporting gate drive signal Gn, to drive on display panel corresponding gate line respectively.As shown in Figure 1, every grade of drive element of the grid comprises the first on-off element M1, second switch element M2, the 3rd on-off element M3, the 4th on-off element M4, the 5th on-off element M5, the 6th on-off element M6, the 7th on-off element M7, the 8th on-off element M8, the 9th on-off element M9, the tenth on-off element M10.
Wherein, first on-off element M1 comprises the first path terminal, the first control end, alternate path end, and the first path terminal receives the first pulse signal, and the first control end receives the first transmission of signal, alternate path end is the output terminal of transmission of signal at the corresponding levels, for exporting transmission of signal Qn at the corresponding levels.Second switch element M2 comprises third path end, the second control end, the 4th path terminal, third path termination receives the first clock signal clk A, second control end is connected with the alternate path end of the first on-off element M1, and be connected with the 4th path terminal by the first electric capacity C1,4th path terminal is the output terminal of every grade of drive element of the grid, for exporting gate drive signal Gn at the corresponding levels.
3rd on-off element M3 comprises five-way terminal, the 3rd control end, the 6th path terminal, and five-way terminal is connected with the alternate path end of the first on-off element M1, and the 3rd control end receives the second transmission of signal, and the 6th path terminal receives the second pulse signal.4th on-off element M4 comprises the 7th path terminal, the 4th control end, the 8th path terminal, and the 7th path terminal is connected with the 4th path terminal of second switch element M2, and the 8th path terminal receives low reference voltage VGL.
5th on-off element M5 comprises the 9th path terminal, the 5th control end, the tenth path terminal, 9th path terminal is connected with second control end of second switch element M2,5th control end is connected with the 4th control end of the 4th on-off element M4, and the tenth path terminal receives low reference voltage VGL.6th on-off element M6 comprises the 11 path terminal, the 6th control end, the 12 path terminal, 11 path terminal receives the first clock signal clk A, 6th control end is connected with the 11 path terminal, and the 12 path terminal is connected with the 5th control end of the 5th on-off element M5.7th on-off element M7 comprises the tenth threeway terminal, the 7th control end, the 14 path terminal, and the tenth threeway terminal and the 7th control end are all connected with the 5th control end of the 5th on-off element M5, and the 14 path terminal receives low reference voltage VGL.
8th on-off element M8 comprises the tenth five-way terminal, the 8th control end, the 16 path terminal, tenth five-way terminal is connected with the 5th control end of the 5th on-off element M5,8th control end is connected with second control end of second switch element M2, and the 16 path terminal receives low reference voltage VGL.9th on-off element M9 comprises the 17 path terminal, the 9th control end, the 18 path terminal, 17 path terminal is connected with the 5th control end of the 5th on-off element M5,9th control end receives second clock signal CLKC, and the 18 path terminal receives low reference voltage VGL.Tenth on-off element M10 comprises the 19 path terminal, the tenth control end, the 20 path terminal, 19 path terminal is connected with the 4th path terminal of second switch element M2, tenth control end receives second clock signal CLKC, and the 20 path terminal receives low reference voltage VGL.
Wherein, the 4th on-off element M4 and the 5th on-off element M5 forms the first stabilization element, and the tenth on-off element M10 forms the second stabilization element.
Wherein, the common port of the alternate path end of the first on-off element M1, second control end of second switch element M2, the 9th path terminal of the 5th on-off element M5 and the 8th control end of the 8th on-off element M8 is designated as node Q, and the common port of the 17 path terminal of the 12 path terminal of the 4th control end of the 4th on-off element M4, the 5th control end of the 5th on-off element M5, the 6th on-off element M6, the tenth threeway terminal of the 7th on-off element M7, the tenth five-way terminal of the 8th on-off element M8 and the 9th on-off element M9 is designated as node QB.
Wherein, the first electric capacity C1 is the stray capacitance between the 4th path terminal of second switch element M2 and the second control end.What certainly it will be appreciated by those skilled in the art that is, separate, stored electric capacity can also be set between second control end of second switch element M2 and the 4th path terminal, now, the first electric capacity C1 is stray capacitance between the 4th path terminal of second switch element M2 and the second control end and separate, stored electric capacity sum.
In an embodiment of the present invention, if gate driver circuit comprises N level drive element of the grid, the first transmission of signal that then first control end of the first on-off element M1 of n-th grade of drive element of the grid receives is the upper two-stage transmission of signal Qn-2 that the drive element of the grid upwards differing two-stage with n-th grade of drive element of the grid exports, wherein, n is integer, and n >=3.
In an embodiment of the present invention, if gate driver circuit comprises N level drive element of the grid, the second transmission of signal that then the 3rd control end of the 3rd on-off element M3 of n-th grade of drive element of the grid receives is lower two-stage transmission of signal Qn+2, the n≤N-2 that the drive element of the grid differing two-stage with n-th grade of drive element of the grid downwards exports.
In an embodiment of the present invention, if gate driver circuit comprises N level drive element of the grid, the first pulse signal that then first path terminal of the first on-off element M1 of n-th grade of drive element of the grid receives is the upper level gate drive signal Gn-1 that the drive element of the grid upwards differing one-level with n-th grade of drive element of the grid exports, wherein, n is integer, and n >=2.
In an embodiment of the present invention, if gate driver circuit comprises N level drive element of the grid, the second pulse signal that then the 6th path terminal of the 3rd on-off element M3 of n-th grade of drive element of the grid receives is the next stage gate drive signal Gn+1 that the drive element of the grid differing one-level downwards with n-th grade of drive element of the grid exports, wherein, n is integer, and 0≤n≤N-1.
It should be noted that, because first order drive element of the grid does not upwards differ the drive element of the grid of one-level, first order drive element of the grid and second level drive element of the grid upwards do not differ the drive element of the grid of two-stage, afterbody drive element of the grid does not differ the drive element of the grid of one-level downwards, last two-stage drive element of the grid does not differ the drive element of the grid of two-stage downwards, so the first pulse signal that first order drive element of the grid receives, first order drive element of the grid, the first transmission of signal that second level drive element of the grid receives, afterbody drive element of the grid receives described second pulse signal, transmission No. the second that last two-stage drive element of the grid receives all will be provided by external signal circuit.
In the present embodiment, the first on-off element is N-type transistor to the tenth on-off element M1 ~ M10.First control end is grid to the tenth control end.The five-way terminal of first path terminal of the first on-off element M1, the third path end of second switch element M2, the 3rd on-off element M3, the 7th path terminal of the 4th on-off element M4, the 9th path terminal of the 5th on-off element M5, the 11 path terminal of the 6th on-off element M6, the tenth threeway terminal of the 7th on-off element M7, the tenth five-way terminal of the 8th on-off element M8, the 17 path terminal of the 9th on-off element M9, the 19 path terminal of the tenth on-off element M10 are drain electrode.6th path terminal of the alternate path end of the first on-off element M1, the 4th path terminal of second switch element M2, the 3rd on-off element M3, the 8th path terminal of the 4th on-off element M4, the tenth path terminal of the 5th on-off element M5, the 12 path terminal of the 6th on-off element M6, the 14 path terminal of the 7th on-off element M7, the 16 path terminal of the 8th on-off element M8, the 18 path terminal of the 9th on-off element M9, the 20 path terminal of the tenth on-off element M10 are source electrode.
Certainly, it will be appreciated by persons skilled in the art that the first on-off element also can adopt other on-off element to the tenth on-off element M1 ~ M10 and realize, such as P-type crystal pipe.Below for the first on-off element M1 to the tenth on-off element M1 ~ M10 for N-type transistor introduces the specific embodiment of the present invention and principle of work thereof particularly.
Refer to Fig. 2, it is the time diagram of n-th grade of drive element of the grid in the gate driver circuit of first embodiment of the invention.Wherein, n is integer, and 3≤n≤N-2.As shown in Figure 2, first clock signal clk A and second clock signal CLKC is inversion signal, that is, first clock signal clk A is identical with the cycle of second clock signal CLKC, dutycycle is identical, and when the first clock signal clk A is high level, second clock signal CLKC is low level, when the first clock signal clk A is low level, second clock signal CLKC is high level.
The course of work of every one-level drive element of the grid is divided into pre-charging stage, pull-up stage, drop-down stage, 4 stages of stabilization sub stage:
Pre-charging stage and first stage: the first on-off element M1 first control end receive the first transmission of signal namely upwards differ two-stage drive element of the grid export upper two-stage transmission of signal Qn-2 be high level, and its magnitude of voltage is about the twice of the high level of the first clock signal clk A, the abundant conducting of first on-off element M1, when the upper level gate drive signal Gn-1 that the drive element of the grid that namely the first pulse signal upwards differs one-level exports is high level, the voltage at node Q place is upwards differed the upper level gate drive signal Gn-1 precharge of the drive element of the grid output of one-level by the first on-off element M1 of conducting, second switch element M2 conducting, in addition, because the voltage at node Q place is precharged, the 8th on-off element M8 conducting, the voltage at node QB place is pulled low to low reference voltage VGL by the 8th on-off element M8 of conducting, thus the 5th on-off element M5 is closed, drop-down with what stop node Q.
Pull-up stage and subordinate phase: when the level of the first clock signal clk A is by low uprising, owing to being precharged at pre-charging stage node Q, therefore, second switch element M2 conducting, due to the conducting of second switch element M2, and due to the boot strap of the first electric capacity C1, the voltage at node Q place is drawn high further, and the drawing high further of node Q place's voltage, make second switch element M2 conductively more abundant, thus the gate drive signal Gn at the corresponding levels making the output terminal of drive element of the grid at the corresponding levels export is drawn high by the first clock signal clk A by the second switch element M2 of conducting.
It should be noted that, in the present invention, can directly adopt stray capacitance between the 4th path terminal of second switch element M2 and the second control end as the first electric capacity C1, or in order to promote pull-up effect, separate, stored electric capacity can also be set between second control end of second switch element M2 and the 4th path terminal, the parasitic capacitance in parallel of separate, stored electric capacity and second switch element M2 is also common as the first electric capacity C1, and namely the first electric capacity C1 equals stray capacitance between the 4th path terminal of second switch element M2 and the second control end and separate, stored electric capacity sum.
Drop-down stage and phase III: the first clock signal clk A becomes low level from high level, due to being drawn high further at pull-up stage node Q place's voltage, and the second transmission of signal i.e. transmission of signal Qn+2 of the lower two-stage of the drive element of the grid output of difference two-stage downwards about becomes the twice of the first clock signal clk A high level, 3rd on-off element M3 conducting, when the second pulse signal next stage gate drive signal Gn+1 that namely drive element of the grid of difference one-level exports downwards is high level, the voltage at node Q place is remained high level by the 3rd on-off element M3 of conducting by the second pulse signal next stage gate drive signal Gn+1 that namely drive element of the grid of difference one-level exports downwards, second switch element M2 is in conducting state, the gate drive signal Gn that the output terminal of drive element of the grid at the corresponding levels exports is dragged down by the first clock signal clk A by the second switch element M2 of conducting, when the second pulse signal next stage gate drive signal Gn+1 that namely drive element of the grid of difference one-level exports downwards becomes low level from high level, the voltage at node Q place is dragged down by the second pulse signal next stage gate drive signal Gn+1 that namely drive element of the grid of difference one-level exports downwards by the 3rd on-off element M3 of conducting.
Stabilization sub stage and fourth stage: due in the drop-down stage, the voltage at node Q place is dragged down, therefore, second switch element M2 closes, avoid the first clock signal clk A to the impact of gate drive signal Gn, simultaneously the 8th on-off element M8 closes, and what stopped node QB point is drop-down.When the first clock signal clk A becomes high level from low level, 6th on-off element M6 conducting, node QB is charged by the 6th on-off element M6 of conducting, the grid of the 7th on-off element M7 and the voltage of node QB are greater than the voltage of the grid of the 8th on-off element M8 and the voltage of node Q, and the voltage of the source electrode of the 7th on-off element M7 is identical with the voltage of the source electrode of the 8th on-off element M8, therefore, the grid of the 7th on-off element M7 and the voltage difference of source electrode are greater than the grid of the 8th on-off element M8 and the voltage difference of source electrode, therefore, the impedance of the 7th on-off element M7 is less than the impedance of the 8th on-off element, it is drop-down negligible that 8th electric leakage of on-off element M8 to node QB causes, the voltage of node QB point is driven high by the 6th on-off element M6 of conducting.4th on-off element M4 and the 5th on-off element M5 conducting, node Q maintains low level by the 5th on-off element M5 of conducting, and gate drive signal Gn maintains low level by the 4th on-off element of conducting.When second clock signal CLKC becomes high level from low level, tenth on-off element M10 conducting, gate drive signal Gn maintains low level by the tenth on-off element M10 of conducting, simultaneously, 9th on-off element M9 conducting, node QB is dragged down by the 9th on-off element M9 of conducting, and the 4th on-off element M4 and the 5th on-off element M5 closes.
The magnitude of voltage of the upper two-stage transmission of signal Qn-2 that the drive element of the grid that namely the first transmission of signal that first control end of the first on-off element M1 of gate driver circuit of the present invention receives upwards differs two-stage exports is about the twice of the high level of the first clock signal clk A, thus make the first on-off element M1 can all can fully conducting under the condition of or low temperature low in mobility, node Q can be pre-charged to the high level of the first clock signal clk A, and then made on-off element (second switch element M2) the energy fully conducting of output action, the efficiency for charge-discharge of the first electric capacity C1 improves, and then while the harmless transmission ensureing the signal between drive element of the grid, gate driver circuit is made to export desirable gate drive signal.
In an embodiment of the present invention, the breadth length ratio of the 6th on-off element M6 is greater than the breadth length ratio of the 7th on-off element M7.When the breadth length ratio of the 6th on-off element M6 is greater than the breadth length ratio of the 7th on-off element M7, the impedance of the 6th on-off element M6 is less than the impedance of the 7th on-off element M7, voltage difference between the grid of the 6th on-off element M6 and source electrode is less than the voltage difference between the grid of the 7th on-off element M7 and source electrode, therefore, after gate driver circuit long-time running, the threshold voltage drift of the 6th on-off element M6 can be less than the threshold voltage drift of the 7th on-off element M7, and then the 7th the impedance of on-off element M7 relative to larger the 6th on-off element M6, therefore the voltage difference between the grid of the 7th on-off element M7 and source electrode becomes large, that is, the magnitude of voltage of node QB increases, and then namely the problem that compensate for the electric current reduction that the 4th on-off element M4 and the 5th on-off element M5 brings due to threshold voltage drift to a certain extent compensate for the stabilizing power of the first stabilization element, improve the stability of gate driver circuit.
Certainly it will be appreciated by those skilled in the art that, the breadth length ratio of the 6th on-off element M6 also can equal the breadth length ratio of the 7th on-off element M7.When the breadth length ratio of the 6th on-off element M6 equals the 7th on-off element M7, the magnitude of voltage of node QB equals the high level of the first clock signal clk A and low level and half, the magnitude of voltage avoiding node QB is excessive, and cause the threshold values of the 4th on-off element M4 and the 5th on-off element M5 to drift about excessive situation, no matter and under any manufacturing process condition, temperature conditions, the magnitude of voltage of node QB remains constant, considerably increases the stability of gate driver circuit.
Fig. 3 is that the analog result of the magnitude of voltage of node QB at normal temperatures and under high temperature in the gate driver circuit of first embodiment of the invention and the gate driver circuit of prior art contrasts schematic diagram.Wherein, 1. be the analog result of the magnitude of voltage of the node QB in the gate driver circuit of (27 degrees Celsius) first embodiment of the invention at normal temperatures, 2. be the analog result of the magnitude of voltage of the node QB in the gate driver circuit of (27 degrees Celsius) prior art under normal temperature, 3. be the analog result of the magnitude of voltage of the node QB in the gate driver circuit of at high temperature first embodiment of the invention under (70 degrees Celsius), 4. be the analog result of the magnitude of voltage of the node QB in the gate driver circuit of (70 degrees Celsius) prior art under high temperature, please also refer to Fig. 1 and Fig. 3, because each saltus step of the first clock signal clk A is all charged to the control end (the 4th control end of the 4th on-off element M4 and the 5th control end of the 5th on-off element M5) of the first stabilization element by the 6th on-off element M6, ensure that the stability of the control end of the first stabilization element and the voltage of node QB, therefore, the magnitude of voltage of magnitude of voltage under high temperature and normal temperature of the node QB of the gate driver circuit of first embodiment of the invention is all more stable.
Fig. 4 is the current analog Comparative result schematic diagram of the gate driver circuit of first embodiment of the invention and first stabilization element of the gate driver circuit of prior art after the same time that works.Wherein, 5. be the current analog result of the first stabilization element of the first moment gate driver circuit, 6. for being later than the current analog result of the first stabilization element of the gate driver circuit of the second moment first embodiment of the invention in the first moment, be 7. the current analog result of the first stabilization element of the gate driver circuit of the second moment prior art.Wherein, the electric current of the first stabilization element refers to the electric current sum on the 4th on-off element M4 and the 5th on-off element M5.Please also refer to Fig. 1 and Fig. 4, the breadth length ratio i.e. impedance of the 6th on-off element M6 that breadth length ratio due to the 6th on-off element M6 is greater than the 7th on-off element M7 is less than the impedance of the 7th on-off element M7, voltage difference between the grid of the 6th on-off element M6 and source electrode is less than the voltage difference between the grid of the 7th on-off element M7 and source electrode, therefore, after gate driver circuit long-time running, the threshold voltage drift of the 6th on-off element M6 can be less than the threshold voltage drift of the 7th on-off element M7, and then the 7th the impedance of on-off element M7 relative to larger the 6th on-off element M6, so, voltage difference between the grid of the 7th on-off element M7 and source electrode becomes large, that is, the magnitude of voltage of node QB increases, and then namely electric current that is that bring reduces problem compensate for the stabilizing power of the first stabilization element because threshold voltage positive excursion makes impedance become large to compensate for the 4th on-off element M4 and the 5th on-off element M5 to a certain extent, therefore, the electric current drop-out value of the first stabilization element of the gate driver circuit of first embodiment of the invention is significantly less than the electric current drop-out value of the stabilization element of prior art, therefore, relative to prior art, gate driver circuit stability of the present invention is higher.
Fig. 5 is the analog result schematic diagram of the gate drive signal that the first order drive element of the grid of the gate driver circuit of first embodiment of the invention under cryogenic exports to level V drive element of the grid.Wherein, G1 is the analog result of the gate drive signal that the first order drive element of the grid of the gate driver circuit of first embodiment of the invention under low temperature (negative 20 degrees Celsius) condition exports, G2 is the analog result of the gate drive signal that the second level drive element of the grid of the gate driver circuit of first embodiment of the invention under low temperature (negative 20 degrees Celsius) condition exports, G3 is the analog result of the gate drive signal that the third level drive element of the grid of the gate driver circuit of first embodiment of the invention under low temperature (negative 20 degrees Celsius) condition exports, G4 is the analog result of the gate drive signal that the fourth stage drive element of the grid of the gate driver circuit of first embodiment of the invention under low temperature (negative 20 degrees Celsius) condition exports, G5 is the analog result of the gate drive signal that the level V drive element of the grid of the gate driver circuit of first embodiment of the invention under low temperature (negative 20 degrees Celsius) condition exports.
Please also refer to Fig. 1 and Fig. 5, the magnitude of voltage of the upper two-stage transmission of signal Qn-2 that the drive element of the grid that namely the first transmission of signal that first control end of the first on-off element M1 of gate driver circuit of the present invention receives upwards differs two-stage exports is about the twice of the high level of the first clock signal clk A, thus make the first on-off element M1 can all can fully conducting under the condition of or low temperature low in mobility, node Q can be pre-charged to the high level of the first clock signal clk A, and then made on-off element (second switch element M2) the energy fully conducting of output action, the efficiency for charge-discharge of the first electric capacity C1 improves, and then while the harmless transmission ensureing the signal between drive element of the grid, gate driver circuit is made to export desirable gate drive signal.Therefore, rise time of gate drive signal of exporting to level V drive element of the grid of the first order drive element of the grid of the gate driver circuit of first embodiment of the invention is all shorter with fall time under cryogenic, and the gate drive signal namely exported is more satisfactory.
The present invention also provides a kind of display device, it comprises gate driver circuit, gate driver circuit comprises multistage drive element of the grid as shown in Figure 1, n-th grade of drive element of the grid for exporting gate drive signal Gn, to drive on display panel corresponding gate line respectively.As shown in Figure 1, every grade of drive element of the grid comprises the first on-off element M1, second switch element M2, the 3rd on-off element M3, the 4th on-off element M4, the 5th on-off element M5, the 6th on-off element M6, the 7th on-off element M7, the 8th on-off element M8, the 9th on-off element M9, the tenth on-off element M10.
Wherein, first on-off element M1 comprises the first path terminal, the first control end, alternate path end, and the first path terminal receives the first pulse signal, and the first control end receives the first transmission of signal, alternate path end is the output terminal of transmission of signal at the corresponding levels, for exporting transmission of signal Qn at the corresponding levels.Second switch element M2 comprises third path end, the second control end, the 4th path terminal, third path termination receives the first clock signal clk A, second control end is connected with the alternate path end of the first on-off element M1, and be connected with the 4th path terminal by the first electric capacity C1,4th path terminal is the output terminal of every grade of drive element of the grid, for exporting gate drive signal Gn at the corresponding levels.
3rd on-off element M3 comprises five-way terminal, the 3rd control end, the 6th path terminal, and five-way terminal is connected with the alternate path end of the first on-off element M1, and the 3rd control end receives the second transmission of signal, and the 6th path terminal receives the second pulse signal.4th on-off element M4 comprises the 7th path terminal, the 4th control end, the 8th path terminal, and the 7th path terminal is connected with the 4th path terminal of second switch element M2, and the 8th path terminal receives low reference voltage VGL.
5th on-off element M5 comprises the 9th path terminal, the 5th control end, the tenth path terminal, 9th path terminal is connected with second control end of second switch element M2,5th control end is connected with the 4th control end of the 4th on-off element M4, and the tenth path terminal receives low reference voltage VGL.6th on-off element M6 comprises the 11 path terminal, the 6th control end, the 12 path terminal, 11 path terminal receives the first clock signal clk A, 6th control end is connected with the 11 path terminal, and the 12 path terminal is connected with the 5th control end of the 5th on-off element M5.7th on-off element M7 comprises the tenth threeway terminal, the 7th control end, the 14 path terminal, and the tenth threeway terminal and the 7th control end are all connected with the 5th control end of the 5th on-off element M5, and the 14 path terminal receives low reference voltage VGL.
8th on-off element M8 comprises the tenth five-way terminal, the 8th control end, the 16 path terminal, tenth five-way terminal is connected with the 5th control end of the 5th on-off element M5,8th control end is connected with second control end of second switch element M2, and the 16 path terminal receives low reference voltage VGL.9th on-off element M9 comprises the 17 path terminal, the 9th control end, the 18 path terminal, 17 path terminal is connected with the 5th control end of the 5th on-off element M5,9th control end receives second clock signal CLKC, and the 18 path terminal receives low reference voltage VGL.Tenth on-off element M10 comprises the 19 path terminal, the tenth control end, the 20 path terminal, 19 path terminal is connected with the 4th path terminal of second switch element M2, tenth control end receives second clock signal CLKC, and the 20 path terminal receives low reference voltage VGL.
Wherein, the 4th on-off element M4 and the 5th on-off element M5 forms the first stabilization element, and the tenth on-off element M10 forms the second stabilization element.
Wherein, the common port of the alternate path end of the first on-off element M1, second control end of second switch element M2, the 9th path terminal of the 5th on-off element M5 and the 8th control end of the 8th on-off element M8 is designated as node Q, and the common port of the 17 path terminal of the 12 path terminal of the 4th control end of the 4th on-off element M4, the 5th control end of the 5th on-off element M5, the 6th on-off element M6, the tenth threeway terminal of the 7th on-off element M7, the tenth five-way terminal of the 8th on-off element M8 and the 9th on-off element M9 is designated as node QB.
In an embodiment of the present invention, if gate driver circuit comprises N level drive element of the grid, the first transmission of signal that then first control end of the first on-off element M1 of n-th grade of drive element of the grid receives is the upper two-stage transmission of signal Qn-2 that the drive element of the grid upwards differing two-stage with n-th grade of drive element of the grid exports, wherein, n is integer, and n >=3.
In an embodiment of the present invention, if gate driver circuit comprises N level drive element of the grid, the second transmission of signal that then the 3rd control end of the 3rd on-off element M3 of n-th grade of drive element of the grid receives is lower two-stage transmission of signal Qn+2, the n≤N-2 that the drive element of the grid differing two-stage with n-th grade of drive element of the grid downwards exports.
In an embodiment of the present invention, if gate driver circuit comprises N level drive element of the grid, the first pulse signal that then first path terminal of the first on-off element M1 of n-th grade of drive element of the grid receives is the upper level gate drive signal Gn-1 that the drive element of the grid upwards differing one-level with n-th grade of drive element of the grid exports, wherein, n is integer, and n >=2.
In an embodiment of the present invention, if gate driver circuit comprises N level drive element of the grid, the second pulse signal that then the 6th path terminal of the 3rd on-off element M3 of n-th grade of drive element of the grid receives is the next stage gate drive signal Gn+1 that the drive element of the grid differing one-level downwards with n-th grade of drive element of the grid exports, wherein, n is integer, and 0≤n≤N-1.
In gate driver circuit of the present invention and display device, the first stabilization element (the 4th on-off element M4 and the 5th on-off element M5) and the second stabilization element (the tenth on-off element M10) form by on-off element, and each saltus step of the first clock signal clk A is all charged to the control end (the 4th control end of the 4th on-off element M4 and the 5th control end of the 5th on-off element M5) of the first stabilization element by the 6th on-off element M6, ensure that the stability of the voltage of the control end of the first stabilization element, thus improve the stability of gate drive signal, and every grade of drive element of the grid is only made up of to the tenth on-off element M1 ~ M10 the first on-off element, be conducive to the design of narrow frame, cost is low and power consumption is little.
The above, it is only preferred embodiment of the present invention, not any pro forma restriction is done to the present invention, although the present invention discloses as above with preferred embodiment, but and be not used to limit the present invention, any those skilled in the art, do not departing within the scope of technical solution of the present invention, make a little change when the technology contents of above-mentioned announcement can be utilized or be modified to the Equivalent embodiments of equivalent variations, in every case be do not depart from technical solution of the present invention content, according to any simple modification that technical spirit of the present invention is done above embodiment, equivalent variations and modification, all still belong in the scope of technical solution of the present invention.
Claims (10)
1. a gate driver circuit, comprises multiple drive element of the grid, and wherein every grade of drive element of the grid is for driving a gate line corresponding on display panel respectively, and it is characterized in that, described every grade of drive element of the grid comprises:
First on-off element, comprises the first path terminal, the first control end, alternate path end, and described first path terminal receives the first pulse signal, and described first control end receives the first transmission of signal, and described alternate path end is the output terminal of transmission of signal at the corresponding levels;
Second switch element, comprise third path end, the second control end, the 4th path terminal, described third path termination receives the first clock signal, described second control end is connected with the described alternate path end of described first on-off element, and be connected with described 4th path terminal by the first electric capacity, described 4th path terminal is the output terminal of every grade of drive element of the grid;
3rd on-off element, comprise five-way terminal, the 3rd control end, the 6th path terminal, described five-way terminal is connected with the described alternate path end of described first on-off element, and described 3rd control end receives the second transmission of signal, and the 6th path terminal receives the second pulse signal;
4th on-off element, comprises the 7th path terminal, the 4th control end, the 8th path terminal, and described 7th path terminal is connected with described 4th path terminal of described second switch element, and described 8th path terminal receives low reference voltage;
5th on-off element, comprise the 9th path terminal, the 5th control end, the tenth path terminal, described 9th path terminal is connected with described second control end of described second switch element, described 5th control end is connected with the 4th control end of described 4th on-off element, and described tenth path terminal receives described low reference voltage;
6th on-off element, comprise the 11 path terminal, the 6th control end, the 12 path terminal, described 11 path terminal receives described first clock signal, described 6th control end is connected with described 11 path terminal, and the 12 path terminal is connected with described 5th control end of described 5th on-off element;
7th on-off element, comprise the tenth threeway terminal, the 7th control end, the 14 path terminal, described tenth threeway terminal and described 7th control end are all connected with described 5th control end of described 5th on-off element, and described 14 path terminal receives described low reference voltage;
8th on-off element, comprise the tenth five-way terminal, the 8th control end, the 16 path terminal, described tenth five-way terminal is connected with described 5th control end of described 5th on-off element, described 8th control end is connected with described second control end of described second switch element, and described 16 path terminal receives described low reference voltage;
9th on-off element, comprise the 17 path terminal, the 9th control end, the 18 path terminal, described 17 path terminal is connected with described 5th control end of described 5th on-off element, and described 9th control end receives second clock signal, and described 18 path terminal receives described low reference voltage; And
Tenth on-off element, comprise the 19 path terminal, the tenth control end, the 20 path terminal, described 19 path terminal is connected with described 4th path terminal of described second switch element, described tenth control end receives described second clock signal, and described 20 path terminal receives described low reference voltage.
2. gate driver circuit as claimed in claim 1, it is characterized in that, described first electric capacity is the stray capacitance between described 4th path terminal of described second switch element and described second control end.
3. gate driver circuit as claimed in claim 1, it is characterized in that, be provided with separate, stored electric capacity between described second control end of described second switch element and described 4th path terminal, described first electric capacity is stray capacitance between described 4th path terminal of described second switch element and described second control end and described separate, stored electric capacity sum.
4. gate driver circuit as claimed in claim 1, it is characterized in that, if described gate driver circuit comprises N level drive element of the grid, described first transmission of signal that then described first control end of described first on-off element of n-th grade of drive element of the grid receives is the upper two-stage transmission of signal that the drive element of the grid upwards differing two-stage with n-th grade of drive element of the grid exports, wherein, n is integer, and n >=3.
5. gate driver circuit as claimed in claim 1, it is characterized in that, if described gate driver circuit comprises N level drive element of the grid, described second transmission of signal that then described 3rd control end of described 3rd on-off element of n-th grade of drive element of the grid receives is the lower two-stage transmission of signal that the drive element of the grid differing two-stage downwards with n-th grade of drive element of the grid exports, n≤N-2.
6. gate driver circuit as claimed in claim 1, it is characterized in that, if described gate driver circuit comprises N level drive element of the grid, described first pulse signal that then described first path terminal of described first on-off element of n-th grade of drive element of the grid receives is the upper level gate drive signal that the drive element of the grid upwards differing one-level with n-th grade of drive element of the grid exports, wherein, n is integer, and n >=2.
7. gate driver circuit as claimed in claim 1, it is characterized in that, if described gate driver circuit comprises N level drive element of the grid, described second pulse signal that then described 6th path terminal of described 3rd on-off element of n-th grade of drive element of the grid receives is the next stage gate drive signal that the drive element of the grid differing one-level downwards with n-th grade of drive element of the grid exports, wherein, n is integer, and 0≤n≤N-1.
8. gate driver circuit as claimed in claim 1, it is characterized in that, described first clock signal and described second clock signal are inversion signal.
9. gate driver circuit as claimed in claim 1, it is characterized in that, the breadth length ratio of described 6th on-off element is more than or equal to the breadth length ratio of described 7th on-off element.
10. a display device, is characterized in that, comprises gate driver circuit as claimed in any one of claims 1 to 9 wherein.
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| CN105355187A (en) * | 2015-12-22 | 2016-02-24 | 武汉华星光电技术有限公司 | GOA (gate driver on array) circuit based on LTPS (low temperature poly-silicon) semiconductor thin film transistor |
| CN105355187B (en) * | 2015-12-22 | 2018-03-06 | 武汉华星光电技术有限公司 | GOA circuits based on LTPS semiconductor thin-film transistors |
| CN106601201A (en) * | 2016-12-09 | 2017-04-26 | 昆山龙腾光电有限公司 | Grid driving circuit |
| CN106601201B (en) * | 2016-12-09 | 2019-06-11 | 昆山龙腾光电有限公司 | Gate driving circuit |
| WO2018107533A1 (en) * | 2016-12-15 | 2018-06-21 | 武汉华星光电技术有限公司 | Gate drive circuit, driving method and display device |
| WO2018107534A1 (en) * | 2016-12-15 | 2018-06-21 | 武汉华星光电技术有限公司 | Gate drive circuit and driving method therefor, and display device |
| CN106782366A (en) * | 2016-12-15 | 2017-05-31 | 武汉华星光电技术有限公司 | A kind of gate driving circuit and its driving method, display device |
| US10657919B2 (en) | 2016-12-15 | 2020-05-19 | Wuhan China Star Optoelectronics Technology Co., Ltd. | Gate driving circuit, driving method, and display device |
| CN107507554A (en) * | 2017-07-06 | 2017-12-22 | 友达光电股份有限公司 | Shift register |
| CN107507554B (en) * | 2017-07-06 | 2020-07-14 | 友达光电股份有限公司 | Shift register |
| CN107689219A (en) * | 2017-09-12 | 2018-02-13 | 昆山龙腾光电有限公司 | Gate driving circuit and its display device |
| CN108447448A (en) * | 2018-01-19 | 2018-08-24 | 昆山国显光电有限公司 | A kind of scan drive circuit, scanner driver and display device |
| CN108447448B (en) * | 2018-01-19 | 2020-10-30 | 昆山国显光电有限公司 | Scanning drive circuit, scanning driver and display device |
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Address after: 215301, 1, Longteng Road, Kunshan, Jiangsu, Suzhou Patentee after: InfoVision Optoelectronics(Kunshan)Co.,Ltd. Address before: 215301, 1, Longteng Road, Kunshan, Jiangsu, Suzhou Patentee before: INFOVISION OPTOELECTRONICS (KUNSHAN) Co.,Ltd. |