CN104464645B - Shift register and display device - Google Patents

Shift register and display device Download PDF

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Publication number
CN104464645B
CN104464645B CN201510007408.6A CN201510007408A CN104464645B CN 104464645 B CN104464645 B CN 104464645B CN 201510007408 A CN201510007408 A CN 201510007408A CN 104464645 B CN104464645 B CN 104464645B
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China
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shift register
film transistor
output
tft
thin film
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CN201510007408.6A
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Chinese (zh)
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CN104464645A (en
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青海刚
祁小敬
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to CN201510007408.6A priority Critical patent/CN104464645B/en
Priority to CN201210266145.7A priority patent/CN102819998B/en
Publication of CN104464645A publication Critical patent/CN104464645A/en
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Abstract

The present invention provides a kind of shift register and display device.The shift register includes multi-stage shift register unit;The shift register cell includes:First output control module;Second output control module;Classification output module, it is connected with pull-up node, pull-down node, carry signal output end and drive signal outfan respectively, for passing through to be classified output carry signal and drive signal, and cause to maintain high level in the evaluation stage and maintain low level in reseting stage, pre-charging stage and non-operational phase in drive signal;Pull-up node level maintains electric capacity, it is connected between the source electrode of the first film transistor that the first low level output end and the first output control module include, it is high level for maintaining the level of the pull-up node by first output control module in the evaluation stage, so that the drive signal maintains high level.The present invention can solve the impact of the leakage problem to shift register of depletion type TFT.

Description

Shift register and display device

The present invention is to be on July 30th, 2012 applying date, Application No. 201210266145.7, entitled " displacement The divisional application of the invention of register cell, shift register and display device ".

Technical field

The present invention relates to organic light emitting display field, more particularly to a kind of shift register and display device.

Background technology

With the development of flat pannel display, high-resolution, narrow frame become the trend of development, and will realize high-resolution, narrow Frame shows that integrated gate drive circuitry is most important solution on panel.For a-si (non-crystalline silicon) and p-si (polycrystalline Silicon) technology, existing various ripe shift register circuits can be very good to realize this target.Oxide TFT (transistor) makees For a kind of very potential semiconductor technology, simpler compared to p-si techniques, cost is lower, compared to a-si mobilitys more Height, thus be increasingly taken seriously, future is likely to OLED (Organic Light Emitting Diode), and the main flow backboard of Flexible Displays drives Technology.But oxide TFT is a kind of depletion mode transistor, and above-mentioned a-si TFT and p-si TFT are enhancement mode Transistor.

Fig. 1 is the circuit diagram of traditional basic shift register cell.As shown in figure 1, the basic shift register Unit include pull up thin film transistor (TFT) T1, pull-down thin film T2, bootstrap capacitor C1, pull-up control thin film transistor (TFT) T3, under Draw control thin film transistor (TFT) T4, storage capacitance C2, the first clock signal input terminal CK, second clock signal input part CKB, input End Input, reset terminal Reset and outfan Output;

Pull-up node (PU points) is the node being connected with the grid of T1, and pull-down node (PD points) is to be connected with the grid of T2 Node;

And initial signal STV is input into from input Input, VGL is low level.

Fig. 2 is the sequential chart of basic shift register cell as shown in Figure 1 operationally each signal, and VGH is high electricity It is flat.

When the circuit of the basic shift register cell is made using enhancement mode TFT technology, the basic displacement is posted The circuit of storage unit can be shown in Fig. 2 bold portions, but if used oxide transistor (depletion type crystal with normal work Pipe) when making the circuit, as pull-down transistor cannot be closed, circuit malfunction is shown in Fig. 2 dotted portions.

The difference of enhancement transistor and depletion mode transistor is shown in Fig. 3 and Fig. 4, Fig. 3 for the characteristic song of enhancement transistor Line chart, the longitudinal axis of Fig. 3 are the drain current i of enhancement transistorD, the transverse axis of Fig. 3 is the gate source voltage V of enhancement transistorgs, Can see from Fig. 3, when Vgs is zero, iDIt is zero, when to illustrate Vgs be zero, enhancement transistor is completely closed;Fig. 4 is consumption The performance diagram of most transistor npn npn, the longitudinal axis of same Fig. 4 are the drain current i of depletion mode transistorD, the transverse axis of Fig. 4 is consumption What the to the greatest extent gate source voltage Vgs of transistor npn npn, but Fig. 4 showed is Vgs when being zero, iDMuch larger than zero, and only in gate source voltage When Vgs is -6V, iDIt is just zero, therefore, when gate source voltage Vgs is 0, depletion mode transistor is still within conducting state, it is impossible to Close, therefore the circuit of existing use a-si technologies or p-si technology energy normal works, making with oxide transistor When, as oxide transistor can not be closed, leakage current is larger, therefore traditional basic shift register as described in Figure 1 The circuit of unit is just no longer suitable for.

The content of the invention

Present invention is primarily targeted at a kind of shift register and display device are provided, to solve the leakage of depletion type TFT Impact of the current problems to shift register.

In order to achieve the above object, the invention provides a kind of shift register, including multi-stage shift register unit;

Input and upper level displacement in addition to first order shift register cell, per one-level shift register cell The carry signal output end connection of register cell;

Except afterbody shift register cell, the reset terminal and next stage displacement per one-level shift register cell is posted The carry signal output end connection of storage unit;

The input of first order shift register cell accesses initial signal;

The reset terminal of afterbody shift register cell accesses the driving letter of afterbody shift register cell output Number;

The shift register cell includes:

First output control module, which is connected with pull-up node, for pull-up node is pulled upward to high electricity in the evaluation stage It is flat, and the first low level is pulled down in reseting stage;

Second output control module, which is connected with pull-down node, in reseting stage and non-operational phase by drop-down section Point is pulled upward to high level;

Classification output module, is connected with pull-up node, pull-down node, carry signal output end and drive signal outfan respectively Connect, for passing through to be classified output carry signal and drive signal, and cause to remain high electric in the evaluation stage in the drive signal Put down and low level is maintained in reseting stage, pre-charging stage and non-operational phase;

Pull-up node level maintains electric capacity, is connected to the first low level output end and the first film transistor Between source electrode, it is high electricity for maintaining the level of the pull-up node by first output control module in the evaluation stage It is flat.

During enforcement, first output control module includes first film transistor, the second thin film transistor (TFT), the 3rd thin film Transistor and the 4th thin film transistor (TFT);The first film transistor, grid and drain electrode are connected with the input, source electrode and institute State the drain electrode connection of the second thin film transistor (TFT);Second thin film transistor (TFT), grid are connected with the input, source electrode with it is described Pull-up node connects;3rd thin film transistor (TFT), grid are connected with reset terminal, source electrode respectively with the 4th thin film transistor (TFT) Drain electrode and first film transistor source electrode connection, drain electrode be connected with the pull-up node;4th thin film transistor (TFT), grid Pole is connected with the reset terminal, and source electrode is connected with the first low level output end.

During enforcement, the classification output module includes:

Carry-out unit, in pre-charging stage, reseting stage and non-operational phase in first output control Cause carry signal output end to export the first low level under the control of module and the second output control module, and exist in the evaluation stage Carry signal output end output high level is caused under the control of first output control module and the second output control module;

Drive output unit, in the evaluation stage in first output control module and the second output control module Control is lower to cause drive signal outfan output high level, and in pre-charging stage, reseting stage and non-operational phase described Drive signal outfan is caused to export the second low level under the control of the first output control module and the second output control module.

During enforcement, the carry-out unit includes that the first carry-out thin film transistor (TFT) and the second carry-out thin film are brilliant Body pipe;The driving output unit includes that the first driving thin film transistor (TFT), second drive thin film transistor (TFT) and bootstrap capacitor;

The first carry-out thin film transistor (TFT), grid are connected with first output control module, source electrode with it is described Carry signal output end connects, and drain electrode is connected with clock signal input terminal;

The second carry-out thin film transistor (TFT), grid are connected with second output control module, source electrode and first Low level output end connects, and drain electrode is connected with the carry signal output end;

The bootstrap capacitor is parallel between the grid and source electrode of the first driving thin film transistor (TFT);

Described first drives thin film transistor (TFT), and grid is connected with first output control module, source electrode and the driving Signal output part connects, and drain electrode is connected with the clock signal input terminal;

Described second drives thin film transistor (TFT), and grid is connected with second output control module, source electrode and the second low electricity Flat outfan connection, drain electrode are connected with the drive signal outfan.

During enforcement, the second low level is more than the first low level.

During enforcement, second output control module includes drop-down control thin film transistor (TFT) and drop-down electric capacity, wherein:

The drop-down control thin film transistor (TFT), grid are connected with the pull-up node, source electrode and the first low level output end Connection, drain electrode are connected with the first end of the pull-down node and the drop-down electric capacity respectively;

Second end of the drop-down electric capacity is connected with the clock signal input terminal.

During enforcement, the first carry-out thin film transistor (TFT), the second carry-out thin film transistor (TFT), described first Thin film transistor (TFT) and described second is driven to drive thin film transistor (TFT) to be all depletion type thin film transistor (TFT).

Present invention also offers a kind of display device, it is characterised in that including above-mentioned shift register.

Compared with prior art, shift register of the present invention and display device, maintain with pull-up node level It is high level that electric capacity maintains the level of pull-up node in the evaluation stage, so as to go to stablize the classification output module includes with it is upper Draw the existing current potential of the source electrode of the thin film transistor (TFT) for pulling drive of node connection so that this is used for pulling drive signal When grid potential is drop-down, grid is less than zero simultaneously less than threshold voltage with the voltage difference of source electrode to thin film transistor (TFT), therefore for Depletion mode transistor, which is closed, and greatly reduces leakage current, it is therefore prevented that pull-up node current potential is pulled down, so as to Solve the electrical leakage problems of depletion type shift register circuit, it is ensured that the normal work of shift register cell;And employ Classification output module, by being classified output carry signal and drive signal, and causes to tie up in the evaluation stage in the drive signal Hold high level and low level is maintained in reseting stage, pre-charging stage and non-operational phase, so as to solve the electric leakage of depletion type TFT Impact of the flow problem to the drive signal of shift register cell.

Description of the drawings

Fig. 1 is the circuit diagram of traditional basic shift register cell;

Fig. 2 is the sequential chart of the basic shift register cell operationally each signal;

Fig. 3 is the performance diagram of enhancement transistor;

Fig. 4 is the performance diagram of depletion mode transistor;

Fig. 5 is the circuit diagram of the first embodiment of the shift register cell that shift register of the present invention includes;

Fig. 6 is the circuit diagram of the second embodiment of the shift register cell that shift register of the present invention includes;

Fig. 7 is the circuit diagram of the 3rd embodiment of the shift register cell that shift register of the present invention includes;

Fig. 8 be the 3rd embodiment of the shift register cell that shift register of the present invention includes operationally The sequential chart of each signal;

Fig. 9 is the circuit diagram of the fourth embodiment of the shift register cell that shift register of the present invention includes;

Figure 10 is the circuit diagram of an embodiment of shift register of the present invention.

Specific embodiment

For cause the object, technical solutions and advantages of the present invention express and must become more apparent, below in conjunction with the accompanying drawings and tool Body embodiment is further described in detail again to the present invention.

The invention provides a kind of shift register and display device, to solve the leakage problem of depletion type TFT to moving The impact of bit register.

As shown in figure 5, the first embodiment of shift register cell that shift register of the present invention includes, bag Include:

First output control module 51, which is connected with pull-up node PU, for being pulled upward to pull-up node in the evaluation stage Pull-up node is pulled down to the first low level in reseting stage by high level;

Second output control module 52, which is connected with pull-down node PD, under inciting somebody to action in reseting stage and non-operational phase Node is drawn to be pulled upward to high level;

First output control module 51 includes first film transistor T1, the second thin film transistor (TFT) T2, the 3rd thin film Transistor T3 and the 4th thin film transistor (TFT) T4;

First film transistor T1, grid and drain electrode are connected with input Input (n), the second thin film described in source electrode The drain electrode connection of transistor T2;

The second thin film transistor (TFT) T2, grid are connected with input Input (n), source electrode and the pull-up node PU connects;

The 3rd thin film transistor (TFT) T3, grid are connected with reset terminal RST (n), and source electrode is brilliant with the 4th thin film respectively The drain electrode of body pipe T4 and the source electrode connection of first film transistor T1, drain electrode are connected with pull-up node PU;

The 4th thin film transistor (TFT) T4, grid are connected with reset terminal RST (n), and source electrode and the first low level output end connect Connect;

The first embodiment of the shift register cell that shift register of the present invention includes also includes:

Classification output module 53, respectively with pull-up node (PU points), pull-down node (PD points), carry signal output end CA N () and drive signal outfan OUT (n) connect, for passing through to be classified output carry signal and drive signal, and cause described Drive signal maintains high level in the evaluation stage and maintains low level in reseting stage and pre-charging stage and non-operational phase;

Pull-up node level maintains electric capacity C1, is connected to the first low level output end and the first film transistor Source electrode T1 between, for the pull-up node (PU point) being maintained by first output control module 51 in the evaluation stage Level is high level;

The carry signal output of the first embodiment of the shift register cell that shift register of the present invention includes End is connected with the input Input (n+1) of next stage shift register cell, the also reset with upper level shift register cell End RST (n-1) connection (not showing in Fig. 5);

M points are the nodes being connected with the source electrode of first film transistor T1, the first low level output end output First low level VGL1.

The first embodiment of the shift register cell that shift register of the present invention includes, mainly with pull-up It is high level that node level maintains electric capacity C1 to maintain the level of the pull-up node (PU points) in the evaluation stage.Specific operation master If the existing current potential of the source electrode by the stable thin film transistor (TFT)s (not showing in Fig. 5) being connected with PU points of electric capacity C1 so that this is thin When grid potential is drop-down, grid is less than threshold voltage simultaneously with the voltage difference of source electrode to film transistor less than zero, therefore for consumption Most transistor npn npn, which is closed, and greatly reduces leakage current, it is therefore prevented that PU point current potentials are pulled down, so as to solve The electrical leakage problems of depletion type shift register circuit, it is ensured that the normal work of shift register cell.

Also, in the first embodiment of the shift register cell that shift register of the present invention includes, adopt The classification output module 53, by being classified output carry signal and drive signal, and causes asking in the drive signal The value stage maintains high level and maintains low level in reseting stage and pre-charging stage and non-operational phase, so as to solve depletion type Impact of the leakage problem of TFT to the drive signal of shift register cell.

As shown in fig. 6, the electricity of the second embodiment of shift register cell that shift register of the present invention includes Lu Tu.The second embodiment of shift register cell of the present invention based on shift register cell of the present invention One embodiment.In this second embodiment, the classification output module 53 includes driving output unit 531 and carry-out unit 532, wherein,

The carry-out unit 532 is driven using the first low level output end;

The driving output unit 531 is driven using the second low level output end;

The carry-out unit 532, for defeated described first in pre-charging stage, reseting stage and non-operational phase Go out and export the first low level VGL1, and exist in the evaluation stage Carry signal output end output high level is caused under the control of the second output control module;

The driving output unit 531, for exporting in second output control module 52 and first in the evaluation stage Drive signal outfan OUT (n) output high level is caused under the control of control module 51, and in reseting stage in the first output control Drive signal outfan OUT (n) is caused to export the second low level under the control of molding block 51 and the second output control module 52 VGL2。

The first low level output end exports the first low level VGL1, and the second low level output end output second is low Level VGL2;

First low level VGL1 and the second low level VGL2 are different, so as to avoid the leakage problem of depletion type TFT Impact to the drive signal of shift register cell.

As shown in fig. 7, the electricity of the 3rd embodiment of shift register cell that shift register of the present invention includes Lu Tu.The 3rd embodiment of the shift register cell that shift register of the present invention includes is based on shifting of the present invention The second embodiment of the shift register cell that bit register includes.In the 3rd embodiment,

The carry-out unit 532 includes the first carry-out thin film transistor (TFT) T5 and the second carry-out film crystal Pipe T6;

It is described driving output unit 531 include the first driving thin film transistor (TFT) T7, second drive thin film transistor (TFT) T8 and from Lift electric capacity C2;

The first carry-out thin film transistor (TFT) T5, grid are connected with first output control module 51, source electrode with Carry signal output end CA (n) connection, drain electrode are connected with clock signal input terminal;

The bootstrap capacitor C2 is parallel between the grid and source electrode of the first driving thin film transistor (TFT) T7;

Described first drives thin film transistor (TFT) T7, and grid is connected with first output control module 51, source electrode with it is described Drive signal outfan OUT (n) connects, and drain electrode is connected with the clock signal input terminal;

The second carry-out thin film transistor (TFT) T6, grid are connected with second output control module 52, source electrode with First low level output end connects, and drain electrode is connected with carry signal output end CA (n);

Described second drives thin film transistor (TFT) T8, grid to be connected with second output control module 52, source electrode and second Low level output end connects, and drain electrode is connected with drive signal outfan OUT (n);

First output control module 51 is also connected with the first low level output end and input Input (n) respectively Connect;

Second output control module 52 is also connected with the first low level output end.

Further, T5, T6, T7 and T8 are N-shaped TFT (thin film transistor (TFT)s);

Further, the first carry-out thin film transistor (TFT) T5, the second carry-out thin film transistor (TFT) T6, institute It is all depletion type thin film transistor (TFT) to state the first driving thin film transistor (TFT) T7 and described second and drive thin film transistor (TFT) T8;

Wherein, from clock signal input terminal input clock signal CK, the first low level output end exports the first low electricity Flat VGL1, the second low level output end export the second low level VGL2, and VGL1<VGL2.

In the 3rd embodiment of the shift register cell that shift register of the present invention includes, PU points are and institute The node of the grid connection of the first carry-out thin film transistor (TFT) T5 is stated, PD points are and the second carry-out thin film transistor (TFT) The node of the grid connection of T6.PU point current potentials, PD points current potential are respectively by the first output control module 51, the second output control module 52 are controlled.

The 3rd embodiment of the shift register cell that shift register of the present invention includes used two it is different Drop-down current potential:VGL1 and VGL2, a drop-down current potential VGL2 are exported for drive signal, and a drop-down current potential VGL1 is used for instead Feedback and carry signal output, and VGL2 is more than VGL1, while the importation of this grade of shift register cell and reset portion make Connected with two TFT, the centre of two TFT connects together, and is connected to M points with electric capacity C1.Shifting of the present invention in addition Clock signal CK of the 3rd embodiment needs of the shift register cell that bit register includes, high level is VGH, low level For VGL1;In PD points, high level is VGH to the signal function of the output of the second output control module 52, and low level is VGL1;According to this Level shift register cell is with the reset terminal RST (n-1) of upper level shift register cell and to next stage shift register list The connection of the input Input (n+1) of unit, it is known that input Input (n) and reset terminal RST of this grade of shift register cell The high level of n signal that () receives, low level are respectively VGH, VGL1.

As shown in figure 8, the work of the 3rd embodiment of shift register cell that shift register of the present invention includes It is divided into three phases as process:

First stage is pre-charging stage S1:Clock signal input terminal and reset terminal RST (n) export the first low level VGL1, input Input (n) output high level VGH, therefore T1, T2 unlatching, are charged to bootstrap capacitor C2 by PU points, while C1 is charged also by M points;As the source voltage of T4 is VGL1, while the current potential of RST (n) is also VGL1, therefore for T4 For Vgs (gate source voltage) (its characteristic curve is corresponded to, it can be seen which be in linearly in certain opening for 0, T4 , there is certain resistance in area), with charging of input Input (n) to C1, M point current potentials are raised rapidly, for T3, its source potential For the current potential of M points, and the grid potential of T3 is VGL1, therefore the Vgs of T3 is less than 0, after M point current potentials rise to certain value, T3 Thoroughly close, as T3 is closed, the current potential of PU points can reach VGH quickly;And the current potential of PD points is VGL1, the Vgs of T6 is 0, T6 Open;For T8, as VGL2 is more than VGL1, the Vgs of T8 is less than 0, therefore T8 is closed.Due to the rising of PU point current potentials, T5, T7 Open, OUT (n) output low levels VGL1, CA (n) output low levels VGL1;

Second stage is evaluation stage S2:CK saltus steps are high level, and the jump in potential of input Input (n) is first Low level VGL1, RST (n) still export the first low level VGL1, and the Vgs of the Vgs and T4 of T1 is 0, therefore T1 and T4 is in one Fixed opening (being in linear zone, have certain resistance);The grid potential of the grid potential and T3 of T2 is all VGL1, the source of T2 The source potential of electrode potential and T3 is M point current potentials, and M points are due to being connected with C1, although C1 can slowly be discharged by T1 and T4, but M Point current potential will not quickly saltus step into VGL1, but it is slow decline, as long as the capacitance of C1 reaches a certain predetermined value, in half pulsewidth Time in the potential difference at C1 two ends can be remained above VGL1 certain values, therefore the grid source electricity of the gate source voltage Vgs and T3 of T2 Pressure Vgs is less than 0 and can ensure which is closed, and the closing of T2 and T3 can cause PU point current potentials to continue as high level guarantor Hold constant, therefore T5 and T7 are continued on, the current potential of PD points continues to keep low level VGL1, therefore T8 to continue to close, and T6 keeps Certain opening, now CK is high level, is further improved PU point current potentials by C2, and T5 and T7 are further opened, because This OUT (n) exports high level VGH, while CA (n) output high level VGH;

Phase III is reseting stage S3:CK saltus steps are the first low level VGL1, and RST (n) and PD points export high level VGH, therefore T6 and T8 fully open, T3 and T4 are fully opened, therefore PU points and M point current potentials are pulled down to VGL1, T6 and T8 Open and cause OUT (n) output VGL2, and CA (n) output VGL1;

Operation to this shift register cell terminates, after PU point current potentials are pulled down to VGL1, as OUT (n) exports VGL2, The Vgs of T7 is closed less than 0, T7, therefore the output of OUT (n) is not interfered with when CK is high level again yet.Though and T5 So be likely to be in it is crack open, but due to the unlatching of T6, therefore CA (n) output VGL1.

Fig. 9 is the circuit diagram of the fourth embodiment of the shift register cell that shift register of the present invention includes. The fourth embodiment of the shift register cell that shift register of the present invention includes is posted based on displacement of the present invention The 3rd embodiment of the shift register cell that storage includes.

As shown in figure 9, in the fourth embodiment, second output control module 52 includes drop-down control film crystal Pipe T9 and pull-up electric capacity C3, wherein:

Drop-down control thin film transistor (TFT) T9, grid are connected with the pull-up node (PU points), and source electrode is defeated with the first low level Go out end connection, drain electrode is connected with the first end of the pull-down node (PD points) and the pull-up electric capacity C3 respectively;

Second end of the pull-up electric capacity C3 is connected with the clock signal input terminal.

It should be noted that:Second output control module 52 of the present invention has a variety of schemes, the second output as shown in Figure 9 Control module is exactly one of embodiment, but the difference of the second output control module is not the essential area of this patent and other schemes Not, as long as having used technical scheme, the second output control module is using which kind of embodiment all of the invention special In the protection domain of profit.

Present invention also offers a kind of shift register, including multistage above-mentioned shift register cell;

Input and upper level displacement in addition to first order shift register cell, per one-level shift register cell The carry signal output end connection of register cell;

Except afterbody shift register cell, the reset terminal and next stage displacement per one-level shift register cell The carry signal output end connection of register cell;

The input of first order shift register cell accesses initial signal;

The reset terminal of afterbody shift register cell accesses the driving letter of afterbody shift register cell output Number.

As shown in Figure 10, an embodiment of shift register of the present invention connects structure by N levels shift register cell Into using the line scanner as active matrix, N is usually the line number of active matrix, and N is positive integer;

S1, S2 ..., Sn ..., SN indicated respectively is first order shift register cell, second level shift register list Unit ..., n-th grade of shift register cell ..., N level shift register cells;

The clock signal of the first clock signal input terminal output and the clock signal phase of second clock signal input part input Position is conversely, dutycycle is 50%;

Wherein, the input IN of first order shift register accesses inceptive impulse signal STV, and STV is that high level is effective;

The reset terminal of afterbody shift register cell accesses the driving letter of afterbody shift register cell output Number;

Input and upper level displacement in addition to first order shift register cell, per one-level shift register cell The carry signal output end connection of register cell;There are two outfans per one-level shift register:CA (n) is defeated for carry signal Go out end, its respectively with the input Input (n+1) of next stage shift register cell and answering for upper level shift register cell Position end RST (n-1) connection;OUT (n) is drive signal outfan, and which is connected with the horizontal scanning line Gn of active matrix;Wherein, n is Positive integer, and n is less than or equal to N;

The clock signal of adjacent two-stage shift register cell is anti-phase each other, such as:If first order shift register list The input end of clock of unit connects then adjacent with the first order shift register cell second level shift register of clock signal CK The clock signal input terminal of unit connects clock signal CKB, and clock signal CK and clock signal CKB are anti-phase each other.

Embodiments of the invention also provide a kind of display device, including shift register as described above in Example, institute Stating display device can include liquid crystal indicator, such as liquid crystal panel, LCD TV, mobile phone, liquid crystal display.Except liquid crystal Outside display device, the display device can also include OLED or other kinds of display device, such as electricity Sub- reader etc..The shift register can as the scanning circuit of display device or gate driver circuit etc., with provide by Scanning signal is delivered to viewing area by row scan function.

It is described above to be merely exemplary for the purpose of the present invention, and it is nonrestrictive, and those of ordinary skill in the art understand, In the case of the spirit and scope limited without departing from claims, many modifications, change or equivalent can be made, but all To fall within the scope of protection of the present invention.

Claims (8)

1. a kind of shift register, it is characterised in that including multi-stage shift register unit;
Input and upper level shift LD in addition to first order shift register cell, per one-level shift register cell The carry signal output end connection of device unit;
In addition to afterbody shift register cell, the reset terminal and next stage displacement per one-level shift register cell is posted The carry signal output end connection of storage unit;
The input of first order shift register cell accesses initial signal;
The reset terminal of afterbody shift register cell accesses the drive signal of afterbody shift register cell output;
The shift register cell includes:
First output control module, which is connected with pull-up node, for pull-up node is pulled upward to high level in the evaluation stage, and The first low level is pulled down in reseting stage;
Second output control module, which is connected with pull-down node, in reseting stage and non-operational phase by pull-down node Move high level to;
Classification output module, is connected with pull-up node, pull-down node, carry signal output end and drive signal outfan respectively, For passing through to be classified output carry signal and drive signal, and cause in the drive signal in evaluation stage maintenance high level Low level is maintained in reseting stage, pre-charging stage and non-operational phase;
Pull-up node level maintains electric capacity, is connected between the first low level output end and the source electrode of first film transistor, uses It is high level in the level of the pull-up node is maintained by first output control module in the evaluation stage;
The classification output module included per one-level shift register cell is connected with a clock signal input terminal respectively;
The clock signal of the clock signal input terminal input being connected with adjacent level shift register cell is mutually anti-phase.
2. shift register as claimed in claim 1, it is characterised in that first output control module includes the first film Transistor, the second thin film transistor (TFT), the 3rd thin film transistor (TFT) and the 4th thin film transistor (TFT);The first film transistor, grid It is connected with the input with drain electrode, source electrode is connected with the drain electrode of second thin film transistor (TFT);Second thin film transistor (TFT), Grid is connected with the input, and source electrode is connected with the pull-up node;3rd thin film transistor (TFT), grid are connected with reset terminal Connect, source electrode is connected with the drain electrode of the 4th thin film transistor (TFT) and the source electrode of first film transistor respectively, drain with it is described on Draw node connection;4th thin film transistor (TFT), grid are connected with the reset terminal, and source electrode and the first low level output end connect Connect.
3. shift register as claimed in claim 2, it is characterised in that the classification output module includes:
Carry-out unit, in pre-charging stage, reseting stage and non-operational phase in first output control module Carry signal output end is caused to export the first low level under control with the second output control module, and in the evaluation stage described Carry signal output end output high level is caused under the control of the first output control module and the second output control module;
Drive output unit, for the evaluation stage first output control module and the second output control module control Down so that drive signal outfan output high level, and in pre-charging stage, reseting stage and non-operational phase described first Drive signal outfan is caused to export the second low level under the control of output control module and the second output control module.
4. shift register as claimed in claim 3, it is characterised in that
The carry-out unit includes the first carry-out thin film transistor (TFT) and the second carry-out thin film transistor (TFT);The drive Dynamic output unit includes that the first driving thin film transistor (TFT), second drive thin film transistor (TFT) and bootstrap capacitor;
The first carry-out thin film transistor (TFT), grid are connected with first output control module, source electrode and the carry Signal output part connects, and drain electrode is connected with clock signal input terminal;
The second carry-out thin film transistor (TFT), grid are connected with second output control module, source electrode and the first low electricity Flat outfan connection, drain electrode are connected with the carry signal output end;
The bootstrap capacitor is parallel between the grid and source electrode of the first driving thin film transistor (TFT);
Described first drives thin film transistor (TFT), and grid is connected with first output control module, source electrode and the drive signal Outfan connects, and drain electrode is connected with the clock signal input terminal;
Described second drives thin film transistor (TFT), grid to be connected with second output control module, and source electrode is defeated with the second low level Go out end connection, drain electrode is connected with the drive signal outfan.
5. shift register as claimed in claim 4, it is characterised in that the second low level is more than the first low level.
6. the shift register as described in claim 4 or 5, it is characterised in that second output control module includes drop-down Control thin film transistor (TFT) and drop-down electric capacity, wherein:
The drop-down control thin film transistor (TFT), grid are connected with the pull-up node, and source electrode is connected with the first low level output end, Drain electrode is connected with the first end of the pull-down node and the drop-down electric capacity respectively;
Second end of the drop-down electric capacity is connected with the clock signal input terminal.
7. shift register as claimed in claim 6, it is characterised in that
The first carry-out thin film transistor (TFT), the second carry-out thin film transistor (TFT), described first drive thin film brilliant Body pipe and described second drives thin film transistor (TFT) to be all depletion type thin film transistor (TFT).
8. a kind of display device, it is characterised in that include the shift LD as described in any claim in claim 1 to 7 Device.
CN201510007408.6A 2012-07-30 2012-07-30 Shift register and display device CN104464645B (en)

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CN105161134B (en) * 2015-10-09 2018-10-23 京东方科技集团股份有限公司 Shift register cell and its operating method, shift register
CN105427786B (en) * 2015-11-19 2018-03-20 北京大学深圳研究生院 A kind of gate drive circuit unit and gate driving circuit
CN105702297B (en) * 2016-04-15 2019-12-31 京东方科技集团股份有限公司 Shift register, driving method, driving circuit, array substrate and display device
CN106486049B (en) * 2017-01-04 2017-10-31 京东方科技集团股份有限公司 Shift register cell, driving method, GOA circuits and display device
CN108538244B (en) * 2018-04-20 2020-04-24 上海天马有机发光显示技术有限公司 Shift register and driving method thereof, emission driving circuit and display device
CN110148383A (en) * 2019-06-19 2019-08-20 京东方科技集团股份有限公司 Shift register cell and its driving method and gate driving circuit

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