JP2002197885A - Shift register circuit, its drive control method, display driving device, and readout driving device - Google Patents

Shift register circuit, its drive control method, display driving device, and readout driving device

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Publication number
JP2002197885A
JP2002197885A JP2000400899A JP2000400899A JP2002197885A JP 2002197885 A JP2002197885 A JP 2002197885A JP 2000400899 A JP2000400899 A JP 2000400899A JP 2000400899 A JP2000400899 A JP 2000400899A JP 2002197885 A JP2002197885 A JP 2002197885A
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signal
output
voltage
level
transistor
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JP2000400899A
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JP4501048B2 (en
Inventor
Shinobu Sumi
忍 角
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Casio Comput Co Ltd
カシオ計算機株式会社
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Abstract

PROBLEM TO BE SOLVED: To provide a shift register circuit which is constituted by using field effect transistors and in which malfunction and an operation characteristic can be improved by suppressing variation of a transistor characteristic caused by a time integration value of a signal level applied to a gate electrode, its drive control method, a display driving device, and a readout driving device. SOLUTION: Each signal holding block RSAk constituting a shift register has a MOS transistor T11 taking an input signal OTk-1 in a contact point NA side, a MOS transistor T12 discharging a potential of a connection contact point NB based on a potential of the contact point NA, a MOS transistor T13 outputting an output signal OTk based on a pulse signal CK1 based on a potential of NA, a MOS transistor T14 outputting an output signal OTk based on an output control signal SET based on a potential of the connection contact point NB, and a MOS transistor T15 discharging a potential of the contact point NA.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shift register circuit and a drive control method therefor, and more particularly, to a shift register circuit, a drive control method thereof, and a display drive method which are suitably applied to a drive circuit of a liquid crystal display device or an image reading device. Device and a reading drive device.

[0002]

2. Description of the Related Art In recent years, information devices such as computers, portable telephones, and portable information terminals, and image processing-related devices such as digital video cameras, digital still cameras, and scanners have been widely used. In such a device, a liquid crystal display (LCD) is used as a display means.
Further, an image reading apparatus provided with a photosensor array as an image reading unit or an image pickup unit is frequently used.

For example, in an active matrix liquid crystal display device, display pixels (liquid crystal pixels) each having a pixel transistor such as a thin film transistor are arranged in a matrix, and each display pixel is connected in a row direction to a scanning line connecting the display pixels in a row direction. Scan lines are sequentially selected by a scan driver for a display panel having data lines to be applied, a predetermined signal voltage is applied to each data line by the data driver, and the selected display pixels are displayed. By writing a signal voltage corresponding to the image information, the liquid crystal alignment state in each display pixel is controlled to display desired image information with a predetermined contrast.
Here, the scan driver is provided with a shift register circuit as a configuration for sequentially outputting scan signals for setting each scan line to a selected state.

Also, in an image reading apparatus provided with a photosensor array in which photosensors (read pixels) are arranged in a matrix, a photosensor of each row is required for a photosensor reset operation or an image reading operation. Are sequentially provided in the selected state, and a shift register circuit is provided similarly to the scan driver of the liquid crystal display device.

As shown in FIG. 24, such a shift register circuit generally includes a plurality of (multiple stages) flip-flop circuits RP k−1 , RP k , R
P k + 1 , RP k + 2 ... Are arranged in series, and the output terminal OUT and the input terminal IN are sequentially connected to each other, and are synchronized with the application timing of the clock signal CKP as shown in FIG. , RP k−1 , R
Via P k , RP k + 1 , RP k + 2 .
While being transferred (shifted), each flip-flop circuit RP k−1 , RP k , RP k + 1 , RP k + 2
An output signal output from... OUT k− 1 , O
Scan signals based on UT k , OUT k + 1 , OUT k + 2 ... Are sequentially applied to the scan lines of the liquid crystal display device or the image reading device. Thus, a line-sequential selection operation is performed in which the display pixels and the photo sensors connected to each scanning line are in a selected state for each row.

[0006]

However, the conventional shift register circuit as described above has the following problems. (1) That is, a scan driver including a shift register circuit has been developed in recent years with the development of high definition and finer processing technology of display images and read images, downsizing of mounted devices, or the same as display panels and photo sensor arrays. Along with the modularization by forming on a substrate, a circuit configuration using a field-effect transistor that can be greatly miniaturized and has excellent ON-OFF operation characteristics has been applied. .

In a field effect transistor, a threshold signal characteristic is obtained by repeatedly applying a control signal (gate signal) to a gate electrode according to a relative potential relationship between a gate electrode, a source electrode, and a drain electrode. It is known experimentally to fluctuate.

Specifically, for example, an n-channel type electric field
In an effect transistor, as shown in FIG.
The gate voltage Vg (gate-drain) with respect to the rain voltage Vd
The relationship between the gate voltage Vg and the gate voltage Vg is relatively small.
(Vg <Vd) so that the gate voltage
When a control signal is continuously applied to the pole, the drain current I
Vg-Id characteristic curve SP showing change in d1But the early features
Sex curve SP0In the negative direction of the gate voltage Vg (see FIG.
(A left side of the surface). Such a V
When the g-Id characteristic curve changes, the thin film transistor
The gate voltage Vg applied to the gate electrode to 0V
The drain current Id 0Is flowing down
An elephant arises.

When the relationship between the gate and the drain voltage Vgd is set so that the gate voltage Vg becomes relatively large (condition Vg> Vd) and the voltage is continuously applied to the gate electrode, the Vg-Id characteristic curve is obtained. SP 2, compared to the initial characteristic curve SP 0, a phenomenon that changes in the positive direction (the right direction) of the gate voltage Vg is observed. Such Vg-I
If the change d characteristic curve occurs, even when the application of a high gate voltage Vg 1, without falling the desired drain current Id 1, the amount of current is low (the drain current Id 2) phenomenon.

In other words, such a phenomenon is, in other words, due to the bias of the time integration value (or the integrated voltage) of the signal level applied to the gate electrode of the field effect transistor between the positive and negative polarities. Means that the threshold characteristics fluctuate. Therefore, when a shift register circuit is formed using such a field-effect transistor, the signal level of the output signal (drain current Id) changes with time, and a favorable switching operation of the field-effect transistor cannot be performed. In addition, there has been a problem that a malfunction of the shift register circuit and a deterioration of operation characteristics may occur.

(2) Some image reading apparatuses have a field effect transistor (thin film transistor) structure as a photo sensor constituting a photo sensor array. ), A drive control for reading a two-dimensional image is performed by sequentially applying (scanning) a reset pulse or a readout pulse.

Here, since each pulse applied to the photo sensor selects only a photo sensor in a specific row and performs a reset operation, a read operation, and the like, for example,
As shown in FIG. 27, each pulse φG1, φG2, φG
3, a relatively high signal level Vgh (for example, +15 V) is applied to the gate electrode for a very short period Tg, and a relatively low signal level Vgl (for example,-) is applied to the gate electrode during other periods. 15V) is applied. By applying a pulse having such a large potential difference (signal amplitude; approximately 25 to 30 V) to a photosensor (field effect transistor), ON-OFF operation is performed instantaneously, and digital driving is performed. It becomes possible.

For this reason, as shown in FIG. 27, when focusing on a predetermined operation period (scanning period), each pulse φG1, φG2, φG3, φG4,.
Is not symmetrical with respect to 0 V (GND level), and the average value Vp of the time integration value (integrated voltage) is
It was largely biased toward the negative voltage side. Such a bias in the polarity of the average value Vp of the time integration value causes a change in the threshold characteristic of the field-effect transistor as in the case shown in FIG. There is a problem that sensitivity characteristics may be deteriorated. The specific configurations of the image reading device and the photo sensor will be described later.

In view of the above problems, the present invention provides a shift register circuit and an image reading device using field effect transistors, which are capable of reducing the bias of the polarity of the time integral of the signal level applied to the gate electrode. It is an object of the present invention to provide a shift register circuit, a driving control method thereof, a display driving device, and a reading driving device, which can suppress a change in transistor characteristics due to a malfunction and improve operation characteristics.

[0015]

According to the first aspect of the present invention,
In a shift register circuit including a plurality of signal holding units connected in series, the shift register circuit sequentially receives, through the plurality of signal holding units, input signals input to the first-stage signal holding unit, A first signal output operation of sequentially outputting a first output signal from each of the signal holding units while shifting to the signal holding unit in the next stage and the following; Each of the signal holding means has a predetermined signal level and a predetermined signal width for adjusting the bias of the polarity of the time integrated value of the signal level of the first output signal output by the first signal output operation. And a second signal output operation for simultaneously outputting the second output signal.

That is, in the first signal output operation, a first output signal (shift signal) having a predetermined signal level is sequentially output from the signal holding means of each stage, and a normal shift operation is realized. . On the other hand, in the second signal output operation, the input of the output control signal is used as a trigger to output a second output signal (adjustment signal) having a predetermined signal waveform (signal level and signal width) from the signal holding means of each stage. ) Are simultaneously output, and an integrated voltage adjustment operation for adjusting the bias of the polarity of the time integration value of the first output signal in the first signal output operation is performed.

By selectively and repetitively performing such first and second signal output operations, in the shift operation (first signal output operation), the field effect transistors constituting the signal holding means of each stage can be used. Even if the threshold characteristic of the field-effect transistor fluctuates due to the application of the gate signal (first output signal) having biased positive and negative polarities to the gate electrode, the integrated voltage adjustment is performed. Operation (second
The signal output operation), the adjustment signal (second output signal) having a predetermined signal waveform is simultaneously applied to the gate electrodes of the field effect transistors of the signal holding means of each stage, so that the gate signal in the shift operation Bias of the time integral value (integrated voltage) of the signal level of the shift register circuit to the positive or negative polarity can be canceled or adjusted. Can be suppressed, and a highly reliable shift register circuit can be provided.

Further, when the shift register circuit having such a configuration is applied to a reading driving device of an image reading device using a photo sensor having a field effect transistor structure as an image reading means, the first and second shift registers are used. By selectively and repeatedly executing the signal output operation, in the image reading operation (first signal output operation), when each photo sensor is scanned, a scanning signal (first signal) having a biased positive and negative polarity is applied to each photo sensor. Output signal) is applied, even if the element characteristics of the photosensor fluctuate,
In the integrated voltage adjustment operation (second signal output operation), an adjustment signal (second output signal) having a predetermined signal waveform is
Since the voltage is simultaneously applied to each photosensor, it is possible to cancel or adjust the bias of the time integration value (integrated voltage) of the signal level of the scanning signal in the image reading operation to the positive or negative polarity. It is possible to provide a highly reliable image reading apparatus by suppressing a malfunction of the image reading apparatus and a deterioration in reading sensitivity due to a change in characteristics.

In the above shift register circuit,
Each of the plurality of signal holding units captures the input signal at a first signal timing and holds a signal level based on the input signal; and a predetermined signal level based on the held signal level. And a discharge control unit that discharges the held signal level at a second signal timing. The output control unit outputs the first or second output signal.

According to this structure, the input control unit and the output control unit take in and output the input signal at a predetermined timing, and sequentially shift the first output signal to the signal holding means of the next stage. And the discharge control unit discharges the signal level of the input signal held after the output of the first or second output signal satisfactorily and initializes (resets) the signal holding means of each stage. )can do.

In the above shift register circuit,
The signal holding unit can be configured to take in an input signal based on the application timing of the input control signal applied to the input control unit or the input timing of the input signal at the time of the first signal output operation. .

According to such a configuration, in the former, the capture of the input signal can be controlled according to the first or second signal output operation, and the input signal can be controlled in the second signal output operation. Since it is not affected by the signal level, the degree of freedom in designing the signal holding means in each stage can be improved. In the latter case, the input signal is taken only depending on the input timing of the input signal,
The input control of the input signal is simplified, and the application of the gate signal to the field effect transistor constituting the input control unit is reduced as much as possible, so that the fluctuation of the threshold characteristic of the field effect transistor can be suppressed.

In the above shift register circuit,
The signal holding unit is configured to periodically supply a first voltage signal having a predetermined high signal level and at least a second voltage signal whose signal level can be changed to the output control unit, Outputting a first output signal having a signal level based on the first voltage signal during a signal output operation, and using the second voltage signal as the output control signal during the second signal output operation; By inputting, it can be configured to output the second output signal having an arbitrary signal level based on the second voltage signal.
Here, at the time of the first signal output operation, the second voltage signal supplied to the output control unit is set to have a predetermined low signal level.

According to such a configuration, in the first signal output operation (shift operation), the first voltage signal having a predetermined high signal level and the second voltage signal having a predetermined low signal level are set. A first output signal (shift signal) having a predetermined signal level is sequentially output based on the voltage signal of (1). In the second signal output operation (integrated voltage adjustment operation), the signal level and the arbitrarily set signal level are set. Since the second output signal (adjustment signal) having an arbitrary signal waveform is output simultaneously based on the second voltage signal having the signal width,
An adjustment signal having a signal level and a signal width according to the time integration value of the first output signal is appropriately generated and output, and the bias of the polarity of the time integration value can be canceled or adjusted. Variations in the threshold characteristics can be suppressed well.

In the above shift register circuit,
The signal holding unit is configured to supply at least a third voltage signal whose signal width can be changed and a second voltage signal whose signal level can be changed to the output control unit, and to output the second signal In operation, by inputting the second voltage signal as the output control signal, a first output state for outputting the second output signal based on the second voltage signal; A second output state in which the second output signal is output based on a voltage signal may be switched to output the second output signal having an arbitrary signal level and signal width. . Here, at the time of the first signal output operation, the second voltage signal supplied to the output control unit is set to have a predetermined low signal level.

According to such a configuration, in the first signal output operation (shift operation), the third voltage signal set to a predetermined high signal level and the second voltage signal set to a predetermined low signal level , A first output signal (shift signal) having a predetermined signal level is sequentially output based on the voltage signal, and is set to a predetermined high signal level in the second signal output operation (integrated voltage adjustment operation). Using the second voltage signal as a trigger, a second output signal (adjustment signal) having an arbitrary signal waveform is generated based on a third voltage signal having a signal level and a signal width substantially arbitrarily set. Since they are output at the same time, it is possible to cancel or adjust the bias of the polarity of the time integrated value of the first output signal, and it is possible to favorably suppress the fluctuation of the threshold characteristic of the field effect transistor.

In the above shift register circuit,
The signal holding means includes at least a third voltage signal whose signal width can be changed and a fourth voltage signal having a predetermined low signal level.
Is supplied to the output control unit, and outputs the first output signal having a first signal width based on the third voltage signal during the first signal output operation. 2
At the time of the signal output operation, the second signal based on the third voltage signal
The second output signal having a signal width of

According to such a configuration, in the first signal output operation (shift operation), the first signal width having the first signal width is determined based on the third voltage signal set to the predetermined signal width. Are sequentially output, and in the second signal output operation (integrated voltage adjustment operation), an arbitrary signal waveform is generated based on a third voltage signal having an arbitrarily changed and set signal width. Are output simultaneously, so that the bias of the polarity of the time integrated value of the first output signal can be offset by a simple control method for adjusting the signal width of the third voltage signal. Or can be adjusted,
Variations in the threshold characteristics of the field effect transistor can be suppressed well.

In the above shift register circuit,
In the first signal output operation, the first voltage signal or the third voltage signal is supplied in a first cycle to the odd-numbered signal holding means of the signal holding means. Then, the signal holding means of the even-numbered stages are set so as to be supplied in a second cycle having an inversion relationship with the first cycle. Accordingly, in the plurality of signal holding units connected in series, the input signal fetching, holding operation, and output operation of the output signal (first output signal) are alternately performed for each of the odd-numbered and even-numbered stages. The shift operation of the input signal to the signal holding means at the next and subsequent stages can be performed well.

In the shift register circuit according to the present invention, in each of the plurality of signal holding units, the input control section turns on at the first signal timing to which the input control signal is applied, and A first transistor for capturing a signal to the voltage holding contact side, wherein the output control unit is turned on based on the signal level of the input signal captured to the voltage holding contact side, and via a predetermined load, A second transistor for discharging a signal level supplied from a fifth voltage signal having a predetermined high signal level, and an on-operation based on a signal level of the input signal taken into the voltage holding contact side; A third transistor that outputs the first output signal based on a first voltage signal; and a third transistor that outputs the first output signal via the load when the second transistor is turned off. A fourth transistor that is turned on based on a high signal level supplied from the fifth voltage signal and outputs a first or a second output signal based on the second voltage signal; A fifth transistor that turns on based on the signal level of the first or second output signal output from the signal holding unit in the next stage and discharges the signal level on the voltage holding contact side; Configuration can be applied.

Further, in the shift register circuit according to the present invention, in each of the plurality of signal holding means, the input control section turns on at the first signal timing to which the input signal is applied, and A first transistor that takes in the voltage holding contact side, wherein the output control unit comprises:
Turns on based on the signal level of the input signal taken into the voltage holding contact side, and discharges a signal level supplied from a fifth voltage signal having a predetermined high signal level via a predetermined load. A second transistor that turns on based on a signal level of the input signal taken into the voltage holding contact side and outputs the first or second output signal based on the third voltage signal; 3 and the second transistor are turned on based on a high signal level supplied from the fifth voltage signal via the load when the second transistor is turned off, and based on the second voltage signal. A fourth transistor for outputting a first or second output signal, wherein the discharge control unit outputs a signal level of the first or second output signal output from the signal holding unit in the next stage. A fifth transistor, which is turned on based on the voltage and is capable of discharging the signal level on the voltage holding contact side, and a sixth voltage signal connected in series to the fifth transistor and capable of changing at least the signal level. And a sixth transistor that performs an on operation based on the signal and discharges the signal level on the voltage holding contact side.

Further, in the shift register circuit according to the present invention, in each of the plurality of signal holding means, the input control section is turned on at the first signal timing to which the input signal is applied, and A first transistor that takes in the voltage holding contact side, wherein the output control unit comprises:
A second transistor that is turned on based on the signal level of the voltage holding contact side and discharges a signal level supplied from a fifth voltage signal having a predetermined high signal level via a predetermined load; A third transistor that is turned on based on the signal level of the voltage holding contact side and outputs the first or second output signal based on the third voltage signal, and when the second transistor is turned off. A fourth transistor that performs an on operation based on a high signal level supplied from the fifth voltage signal via the load and outputs a first output signal based on the fourth voltage signal; A seventh transistor that is turned on based on the signal level of the second voltage signal and supplies a high signal level based on the fifth voltage signal to the voltage holding contact side; A fifth control unit that performs an on-operation based on the signal level of the first or second output signal output from the signal holding unit in the next stage, and discharges the signal level on the voltage holding contact side. A sixth transistor that is connected in series with the fifth transistor and that is turned on based on at least a sixth voltage signal whose signal level can be changed, and that discharges the signal level on the voltage holding contact side; , Can be applied.

Further, in the shift register circuit according to the present invention, in each of the plurality of signal holding means, the input control section turns on at the first signal timing to which the input signal is applied, and A first transistor that takes in the voltage holding contact side, wherein the output control unit comprises:
A second transistor that is turned on based on the signal level of the voltage holding contact side and discharges a signal level supplied from a fifth voltage signal having a predetermined high signal level via a predetermined load; A third transistor that is turned on based on the signal level of the voltage holding contact side and outputs the first or second output signal based on the third voltage signal, and when the second transistor is turned off. A fourth transistor that performs an on operation based on a high signal level supplied from the fifth voltage signal via the load and outputs a first output signal based on the fourth voltage signal; An eighth transistor that is turned on based on a signal level of the second voltage signal and supplies a signal level based on the second voltage signal to the voltage holding contact side; A fifth transistor that is turned on based on the signal level of the first or second output signal output from the signal holding unit in the next stage, and that can discharge the signal level on the voltage holding contact side; A sixth transistor that is connected in series with the fifth transistor, that is turned on based on at least a sixth voltage signal whose signal level can be changed, and that discharges the signal level on the voltage holding contact side; The provided configuration can be applied.

In the shift register circuit,
The sixth voltage signal may be set to have an inversion relationship with the second voltage signal. Accordingly, the discharge state of the signal level of the voltage holding contact can be controlled in synchronization with the timing of applying the second voltage signal that triggers the second signal output operation to the output control unit. The second output signal in the signal output operation of (1) can be held at a predetermined signal level.

In the above shift register circuit,
The same channel type field effect transistor can be applied to each of the transistors constituting the signal holding unit. According to such a configuration, compared to a circuit configuration in which both p-channel type and n-channel type field effect transistors are mixed, efficiency in circuit design, simplification and efficiency of the manufacturing process are achieved. Therefore, product cost can be reduced.

The configuration and drive control method of the shift register circuit described above can be suitably applied to a driver (display drive, read drive) of a liquid crystal display device or an image reading device. According to such a configuration, a malfunction of the shift register circuit and a change in the signal level of the shift signal (first output signal) output from each signal holding unit do not occur. Malfunction and display image quality due to abnormal drive signal output to
It is possible to provide a highly reliable liquid crystal display device or image reading device by suppressing deterioration of the reading sensitivity.

In particular, in an image reading apparatus provided with reading means using a photo sensor (read pixel) having a field-effect transistor structure, the photo sensor is used for the image reading operation (first signal output operation). Although the operating characteristics of the photosensor deteriorate due to the bias of the polarity of the time integration value of the applied scanning signal, a predetermined signal level and signal width can be reduced by the integrated voltage adjustment operation (second signal output operation). By applying the adjustment signal, the bias of the polarity of the time integration value can be canceled or adjusted, so that malfunction of the image reading apparatus and deterioration of sensitivity characteristics can be prevented.

[0038]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a shift register circuit and a drive control method thereof according to the present invention will be described with reference to the drawings. <First Embodiment> FIG. 1 is a schematic diagram showing a first embodiment of a shift register circuit according to the present invention.

First, the overall structure of the shift register will be described with reference to FIG. Here, for convenience of explanation, of the n-stage (n is an integer of 2 or more) signal holding blocks (signal holding means) constituting the shift register circuit, for convenience, the <k-1> th stage to the <k + 2> stage Stage (1≤k-1 ~
Only four stages (k + 2 ≦ n) will be described.

As shown in FIG. 1, the shift according to this embodiment is
The register circuit has the same signal as the flip-flop circuit.
Each signal holding block RSA having a holding functionk-1~ R
SA k + 2Are arranged in series, and each signal holding block RS
Ak-1~ RSAk + 2Input terminal IN and output terminal OU
T are sequentially connected, and each output signal OTk- 1
~ OTk + 2Is the signal holding block RSA of each next stage.
k~ RSAk + 3Is supplied as an input signal.

Each of the signal holding blocks RSA k-1 to RSA
k + 2 is connected to the reset terminal RST of each of the preceding signal holding blocks RSA k−2 to RSA k + 1.
And the output signals OT k−1 to OT k + 2 are respectively connected to the signal holding blocks RSA k−2 to RSA at the preceding stage.
It is supplied as a k + 1 reset signal. The signal holding blocks RSA k-1 to RSA k + 2 are commonly supplied with a high-potential power supply Vdd as a high-potential-side operating voltage and a low-potential power supply Vss as a low-potential-side operating voltage.

A plurality of signal holding blocks RSA
k-1~ RSAk + 2Of the odd-numbered signal holding blocks
(For example, RSAk, RSAk + 2)
The pulse signal CK1 having a period is also used as the signal of the even-numbered stage.
No. holding block (for example, RSA k-1, RS
Ak + 1) Has an inverted waveform of the pulse signal CK1.
Cycle when each pulse signal CK2 outputs an output signal
Is supplied as a signal defining

The odd-numbered signal holding blocks (for example,
For example, RSAk, RSAk + 2) Includes the pulse signal CK2
Having a predetermined period corresponding to the application timing of
The signal φ1 (input control signal) is
Holding block (for example, RSA k-1, RSAk + 1)
Is a predetermined value corresponding to the application timing of the pulse signal CK1.
A pulse signal φ2 (input control signal) having a cycle of
Each signal is provided as a signal that defines the
Paid.

Further, each signal holding block RSA k-1
To the RSA k + 2 control terminals CTL, the output signals OT from the respective signal holding blocks RSA k−1 to RSA k + 2.
k-1 to OT k + 2 (first output signal), a shift operation (first signal output operation; details will be described later), and signal holding blocks RSA k-1 to RSA.
k + 2, any signal level and an output signal having a signal width OT k-1 ~OT k + 2 ( second output signal) output simultaneously integrating the voltage adjustment operation (second signal output operation; details will be described later) , And an output control signal SET for controlling the switching between.

[0045] Although not shown, of the signal holding blocks constituting the shift register circuit according to the present embodiment, the next stage of the signal holding block RSA n of the final stage outputs an output signal as a shift register For example, a dummy signal holding block having a circuit configuration equivalent to at least one of the signal holding blocks RSA k−1 to RSA k + 2 is provided, and an output signal from the dummy signal holding block is used as a signal held in the final stage. It is supplied as a reset signal to the reset terminal RST of the block RSA n. Here, the method for supplying a reset signal to the reset terminal RST of the signal holding block RSA n of the last stage, is not limited to the structure by the dummy signal holding block, in the shift operation and the integrated voltage adjusting operation will be described later , Each signal holding block RSA at a predetermined timing
It may have another configuration as long as it resets k-1 to RSA k + 2 .

Next, a specific circuit configuration of each signal holding block applied to the shift register according to the present embodiment will be described with reference to the drawings. FIG. 2 is a circuit configuration diagram showing a specific configuration of a signal holding block applied to the shift register circuit according to the present embodiment. Here, in order to correspond to the configuration of the shift register circuit shown in FIG. 1, the circuit configuration of the signal holding block at the <k> stage (1 ≦ k ≦ n) will be described.

As shown in FIG. 2, the signal holding block RS
A k is, as a basic configuration, six field-effect transistors (hereinafter, referred to as "MOS transistor") T11~T1
6. Specifically, the output signal OT k −1 from the output signal holding block RSA k−1 in the preceding stage
(In the case of the first-stage signal holding block, a start signal; hereinafter, collectively referred to as an “input signal”).
Source and drain terminals are connected between N and a contact NA (voltage holding contact), and a predetermined pulse signal φ1 is connected to the gate terminal.
(Or φ2; input control signal), a source and a drain terminal are connected between the contact point NA and a constant low-potential power supply Vss (fourth voltage signal). , The output signal OT from the next-stage output signal holding block RSA k + 1 to the gate terminal
a MOS transistor T15 (fifth transistor) to which k + 1 is applied, and a constant high-potential power supply Vdd (fifth voltage signal) and a low-potential power supply Vss (fourth voltage signal) connected in series; MOS transistor T16 (load) that is diode-connected and functions as a load, and contact NA
MOS transistor T12 having a gate terminal connected to
(Second transistor) and a predetermined pulse signal CK1
(Or CK2; first voltage signal) is connected in series between the input terminal CLK to which the output control signal SET (second voltage signal) is applied and the control terminal CTL to which the output control signal SET (second voltage signal) is applied.
MOS transistor T13 whose gate terminal is connected to A
(Third transistor) and MOS transistor T
A MOS transistor T14 (fourth transistor) having a gate terminal connected to a connection contact point NB between T12 and T16,
And an output contact Nout (output terminal OUT) provided at a connection contact between the MOS transistors T13 and T14.

That is, the input control unit according to the present invention
The output control unit according to the present invention includes an OS transistor T11, and includes MOS transistors T12, T13, T
The discharge control unit according to the present invention includes a MOS transistor T15.
Here, M which constitutes the circuit of the signal holding block described above.
The OS transistors T11 to T16 are all n-channel thin film transistors (TFTs).
, And its gate voltage-drain current characteristic initially shows a characteristic curve S shown in FIG.
It is assumed to be equivalent to P 0 (solid line).

Next, the operation of each of the MOS transistors (T11 to T16) constituting the signal holding block as described above, and the respective terminals and contacts (IN, φ, CLK, NA, N)
B, CLT, OUT, RST)
This will be described with reference to the drawings. FIG. 3 is a timing chart showing changes in the potential of each terminal and contact of the signal holding block applied to the present embodiment. Here, description will be made with reference to the configuration of the above-described signal holding block (FIG. 2) as appropriate.

[0050] In the signal holding block RSA k having the above-described configuration, MOS transistor T11,
High level V H (≒ Vdd) pulse signal φ1 (or φ1)
Since 2) is turned on when it is supplied, as shown in FIG. 3, based on the application timing of the pulse signal .phi.1, the input signal (preceding the signal of the high level V H to be supplied to the input terminal IN retention Output signal O of block RSA k-1
T k−1 ) is taken in, and the potential of the contact NA increases according to the signal level of the input signal.

On the other hand, the MOS transistor T12 is
High-level input signal V H via the S transistor T11 is taken, since the ON operation when the potential of the contact NA becomes high, the low-potential power source Vss connected to the MOS transistor T12, the potential of the connection contact NB It will be low. In addition, the state V L (V
In ss), the MOS transistor T12 is turned off, and the potential of the connection node NB is set to a high state by the high-potential power supply Vdd supplied via the MOS transistor T16.

The MOS transistor T13 is connected to the MOS transistor T13.
High-level input signal V H via the S transistor T11 is captured and turned ON when the potential of the contact NA becomes high. At this time, the MOS transistor T12
Is in an on state, the potential of the connection contact NB is in a low state, and the MOS transistor T14 is in an off state. Therefore, the input terminal C connected to the MOS transistor T13
In accordance with the signal level (V L → V H ) of the pulse signal CK1 supplied via the LK, the output contact Nout (the output terminal O)
UT) increases. When the potential of the contact NA is low, the MOS transistor T13 is turned off, and the supply of the pulse signal CK1 to the output contact Nout is cut off.

Here, when the potential of the contact point NA is high and the MOS transistor T13 is on,
By pulse signal CK1 of high level V H is supplied to the accumulation of charge in the parasitic capacitance between the gate electrode and the source electrode (charge-up) occurs gate - source voltage is increased, the gate voltage, i.e., A bootstrap phenomenon in which the potential of the contact NA relatively further rises occurs.
Thus, when the gate voltage reaches the saturation voltage, the source - the drain current is saturated, (the signal level of the output signal OT k) the potential of the output contact Nout is rapidly and substantially pulse signal CK1 (or CK2) (High level V H ).

[0054] Incidentally, the signal level V H of the high-level side in the pulse signal CK1 is connected to the shift register circuit, it can be set as appropriate based on the driven device side of the circuit design by the output signal OT k it can. Specifically, when the shift register circuit according to the present embodiment is applied to a scan driver of a liquid crystal display device or an image reading device to be described later, for example, it is set so that V H = + 15V.

The MOS transistor T14 is turned on when the potential of the connection node NB is high. At this time, the potential of the node NA is low and the MOS transistor T13 is off. the output signal OT k having a signal level corresponding to the output control signal SET supplied through the is output. Here, the output control signal SET is set to a low level equivalent to the low potential power supply Vss in a shift operation described later, and is set to a signal waveform having a predetermined high level in the integrated voltage adjustment operation. Details will be described later.

[0056] Note that even if the signal level V L of the low-level side which is set to the output control signal SET, is connected to the shift register circuit, appropriately set on the basis of the driven device side of the circuit design by the output signal OT k More specifically, when the shift register circuit according to the present embodiment is applied to a scan driver of a liquid crystal display device or an image reading device described later, for example, VL is set to about −5 V to about −15 V. Is done.

The MOS transistor T15 is turned on when the output signal OT k + 1 of the high level VH is output from the signal holding block RSA k + 1 of the next stage, and the potential of the contact point NA (the accumulated charge) is lowered. Discharge to potential power supply Vss. Thereby, the MOS transistor T12,
T13 is turned off, and the MOS transistor T
14 is turned on operation, set the signal level to the output control signal SET is outputted as an output signal OT k. Thus, in a shift operation in which the output control signal SET is set to the low level, by the MOS transistor T15 is turned on, the signal level of the output signal OT k is switched from the high level V H to the low level V L. In addition,
The signal level of the output signal OT k in the integrated voltage adjustment operation will be described later.

Next, a drive control method of a shift register circuit to which the above-described signal holding block is applied will be described with reference to the drawings. FIG. 4 is a timing chart illustrating the operation of the shift register circuit according to the present embodiment. Here, the configuration and operation (FIGS. 2 and 3) of the above-described shift register circuit (FIG. 1) and the signal holding block will be described as appropriate.

(Shift Operation) First, a shift operation by the shift register circuit according to the present embodiment will be described.
First, as shown in FIG. 4, prior to the start of the shift operation, the output control signal S supplied via the control terminal CTL is controlled.
ET is set to low level Vss.

Next, the input terminal I of the signal holding block RSA k of the first stage (first stage) or the <k> stage (not shown) is shown.
While the start signal or the output signal OT k-1 of the signal holding block RSA k-1 at the preceding stage (<k-1> stage) is supplied to N , the input control signal φ1 is applied at a predetermined timing. As in the case shown in FIG. 3, the potential of the contact point NA rises according to the signal level of the input signal. As a result, the MOS transistors T12 and T13 turn on, and the MOS transistor T14 turns off.

Next, when the signal level of the pulse signal CK1 supplied to the input terminal CLK switches from the low level VL to the high level VH , the potential at the contact point NA further increases due to the bootstrap effect. falling to the drain - source current is saturated, via an output signal OT k is the output terminal OUT with a signal level substantially equal and the pulse signal CK1 supplied to the input terminal CLK (high level V H), the next stage The signal is output to the signal holding block RSA k + 1 .

Next, the next-stage signal holding block RSA
At k + 1 , the input control signal φ2
When is inputted, the output signal OT k is taken as the input signal, in the same manner as the operations of the signal holding block RSA k, at the timing when the signal level of the pulse signal CK2 changes from low level V L to the high level V H ,
A signal level substantially equal to the pulse signal CK2 (high level V
Via an output signal OT k + 1 output terminal OUT with H), it is output to the next stage of the signal holding block RSA k + 2 (signal shift operation).

[0063] Here, the output signal OT k + 1 output from the signal holding block RSA k + 1 is supplied as a reset signal to the preceding stage of the signal holding block RSA k, MOS transistor T15 in the signal holding block RSA k
Is turned on, the electric charge accumulated at the contact point NA is released to the low potential power supply Vss, and the potential of the contact point NA is set to the low level Vss. Thereby, the MOS transistors T12 and T1
3 is turned OFF, the MOS transistor T14 is turned on, the output terminal OUT of the signal holding block RSA k
Output control signal SET supplied to the control terminal CTL
Low level V corresponding to the signal level (low level Vss)
Output signal OT k of L is output (reset operation).

Hereinafter, the same signal shift operation and reset operation are sequentially repeated for each signal holding block in synchronization with the application timing of the pulse signals CK1 and CK2, so that a predetermined signal level from each signal holding block is obtained. Output signals having (high level V H ) are sequentially output,
A specific configuration provided outside the shift register circuit (for example, a liquid crystal display panel or a photosensor array to be described later)
Is supplied as a scanning signal.

[0065] Although not shown, the output signal OT n output from the output terminal OUT of the signal holding block RSA n of the last stage is inputted to the signal holding block RSA d dummy provided in the next stage . Then, the pulse signal CK
1 (or CK2) output signal OT d outputted from the dummy signal holding block RSA d in application timing of, is supplied as the signal holding block RSA n of the reset signal of the last stage, the output signal OT n of the low level Vss Is output.

(Integrated Voltage Adjusting Operation) Next, an integrated voltage adjusting operation by the shift register circuit according to the present embodiment will be described. First, prior to the start of the integrated voltage adjustment operation, by setting the input control signals φ1 and φ2 to the low level VL as shown in FIG. 4, the signal holding blocks of each stage... RSA k−1 , RSA k , RSA k + 1 ,
The MOS transistor T11 constituting the input control unit of RSA k + 2 ... Is kept in the off state. Further, by the end of the above-described series of shift operations, the signal holding blocks at each stage... RSA k−1 , RSA k , RSA k + 1 , RS
Are reset and the potential of the contact NA is set to the low level Vss, so that the MOS transistors T12 and T13 are kept in the off state, and the potential of the connection contact NB is set to the high level Vdd. So M
The OS transistor T14 is kept on.

At this time, each signal holding block... RS
A k−1 , RSA k , RSA k + 1 , RSA k + 2.
Since a potential corresponding to the signal level (low level Vss) of the output control signal SET is applied to the output contact Nout,
From the output terminal OUT, an output signal of low level VL
OT k−1 , OT k , OT k + 1 , OT k + 2.
Is output.

In such an initial state, the signal waveform of the output control signal SET is controlled so that an arbitrary signal level Va is obtained.
(For example, a high level where Va ≒ Vdd) and a signal waveform having an arbitrary signal width Tw (corresponding to an integrated voltage adjustment operation period), at an arbitrary timing, all signal holding blocks... RSA k−1 , RSA k , RSA k + 1 , RSA
k + 2 ... are applied to the control terminals CTL.

Thus, only during the period in which the output control signal SET having the signal level Va is applied (signal width Tw), each signal holding block... RSA k−1 , RSA
Output terminals O of A k , RSA k + 1 , RSA k + 2.
The control signal SE applied to the control terminal CTL from the UT.
An output signal having a signal waveform corresponding to the signal level Va of T and the signal width Tw: OT k−1 , OT k , OT
., k + 1 , OT k + 2, ... are simultaneously output and supplied as adjustment signals to a specific configuration (for example, a photosensor array described later) provided outside the shift register circuit.

Here, in the integrated voltage adjustment operation, each signal holding block... RSA k−1 , RSA k , RSA
k + 1 , RSA k + 2, ..., will be specifically described with reference to the drawings.
FIG. 5 is a diagram illustrating a relationship between signal waveforms of output signals in the shift operation and the integrated voltage adjustment operation of the shift register circuit according to the present embodiment. Here, the signal waveform of the output signal OT k output from the signal holding block of the <k> stage is shown as an example.

[0071] As shown in FIG. 5, in the shift operation described above, <k> time output signal OT k high level V H from stage signal holding block is output (output time) T
f is a time (Ttotal / n or less) shorter than the time of the entire shift operation period (that is, the total time when the output signals are sequentially output in the signal holding blocks of all n stages) Ttotal. Here, the shift register circuit is, for example,
When applied to the scanning driver of a high-precision image reading device,
Since the number of output signals from the shift register circuit (the number of stages n of the signal holding block) is enormous, an extremely short time T
f (= Ttotal / n or less), the signal holding block SR
An output signal of a high level VH is output from A k, and the output signal OT k of a low level VL is output during most of the shift operation period (Ttotal−Tf) except during this output operation (output time Tf). Will be done.

Thus, the average value Ve of the time integrated value of the output signal OT k during the shift operation period in the signal holding block SRA k is expressed by the following equation. Ve = { VH × Tf + VL × (Ttotal−Tf)} / Ttotal (1) Here, Ttotal≫Tf, and VL is a negative signal level. The time integration value { VH × Tf + VL × (Ttotal−Tf)} is largely biased toward the negative voltage side.

[0073] Therefore, by the state in which the output signal OT k biased to such specific polarity is applied to continue, for example, in the case of applying the shift register circuit in the scan driver of the image reading device, Charges (holes or electrons) are trapped in the gate electrode of the field effect transistor included in the photo sensor of the image reading device, which causes malfunction of the photo sensor and deterioration of element characteristics.

Similarly, the gates of the MOS transistor T15 and the drain of the MOS transistor T11 are also connected to the output signals OT k + 1 and OT k−1 having a biased polarity as a whole.
, The element characteristics such as the threshold value of the MOS transistors T11 and 15 have also changed over time.

[0075] In particular, the MOS transistors T11, per shift operation once, the input control signal φ1 at the high level V H to the gate, despite φ2 is frequently input, input from a preceding stage of the signal holding block to the drain Since the output signal OTk -1 to be output only once becomes the high level VH and always becomes the low level VL before and after that, the threshold value shifts in the positive direction as shown in FIG. put away, the input control signal of a high level V H to the gate φ1
Even if (φ2) is input, there is a problem that the MOS transistor T11 is hard to be turned on.

Then, in the MOS transistor T14,
During the shift operation, while the potential of the gate continues to be almost at the high level Vdd, the drain (control terminal CTL)
26), the low level Vss continues, so that Vg− shown in FIG.
Tended to be Id characteristic curve SP 2.

Therefore, in the present embodiment, the bias of the polarity of the time integrated value (or the polarity of the time integrated value during the integrated voltage adjustment period, for example, with respect to the GND level (0 V)) is compared with the time integrated value during the shift operation period. , The average value V of the time integration value
signal waveform for canceling the e), i.e., output as an output signal OT k output signal generated by the adjustment signal having any combination of the signal level Va and the signal width Tw with as shown in the following equation relationship, the Applied to the gate electrode of a field effect transistor. { VH × Tf + VL × (Ttotal−Tf)} + Va × Tw = 0 (2) Here, as the signal level Va of the adjustment signal, for example, a constant high-potential power supply Vdd supplied to the shift register circuit Is used (Va = Vdd), the signal waveform of the adjustment signal is obtained by adjusting only the signal width Tw to an arbitrary length (time).
What is necessary is just to set so as to satisfy or approach the relationship of the above equation (2).

As described above, in the shift register circuit and the drive control method according to the present embodiment, the output from each signal holding block is performed in the entire output operation of the shift register circuit including the shift operation period and the integrated voltage adjustment period. The time integrated value of each output signal and the output control signal SET reduces the bias toward either positive or negative polarity.
The adjustment signal is set to have a predetermined signal waveform. Therefore, for example, in an image reading apparatus using the output signal as a scanning signal, a field effect transistor or a MOS transistor T1 constituting a photo sensor is used.
Variations in the threshold characteristics of T1, T14, and T15 (see FIG. 26) can be suppressed.
Deterioration of element characteristics of the S transistors T11, T14, and T15, malfunction of the image reading device, and deterioration of reading sensitivity can be suppressed, and a highly reliable image reading device can be provided.

In the above-described embodiment, as shown in the above equation (2), the bias of the polarity of the time integration value Ve can be offset or adjusted based on the GND level (0 V). Although the example in which the adjustment signal having the signal waveform is applied during the integrated voltage adjustment period has been described, the present invention is not limited to this configuration. That is, FIG.
As long as the fluctuation of the threshold characteristic shown in FIG. 6 can be suppressed, it is not necessary to refer to the GND level.
The reference level of the characteristic corresponding to the threshold characteristic of the field effect transistor to be adjusted may be used.

In the above-described embodiment, the integrated voltage adjustment operation (integrated voltage adjustment) for applying the adjustment signal having the signal waveform (signal level Va and signal width Tw) having the relationship shown in the above equation (2). The period has been described immediately after a series of shift operations (shift operation period). However, the present invention is not limited to this. For example, the integrated voltage adjustment operation is performed immediately before the shift operation. Alternatively, the shift operation may be performed periodically at predetermined time intervals.

<Second Embodiment> Next, a second embodiment of the shift register circuit according to the present invention will be described with reference to the drawings. FIG. 6 is a schematic configuration diagram showing a second embodiment of the shift register circuit according to the present invention. Here, for convenience of explanation, of the signal holding blocks of n stages (n is an integer of 2 or more) constituting the shift register circuit, the <k-1> th stage to the <k + 2> th stage (1 ≦ k-1 to k
+ 2 ≦ n) will be described. The same components as those of the above-described shift register circuit (FIG. 1) are denoted by the same reference numerals, and description thereof will be simplified or omitted.

As shown in FIG. 6, the shift according to this embodiment is
Register circuit, each signal holding block RSBk-1~
RSBk + 2Are connected in series, and each signal holding block R
SB k-1~ RSBk + 2Output signal OTk-1~ OT
k + 2Is the signal holding block RSB of each next stage.k~ R
SBk + 3That is supplied as an input signal
You. Also, each signal holding block RSBk-1~ RSB
k + 2Output signal OT fromk -1~ OTk + 2Are each
Signal holding block RSB beforek-2~ RSBk + 1
Is supplied as a reset signal.

Further, a plurality of signal holding blocks RSB
k-1~ RSBk + 2Of the odd-numbered signal holding blocks
(For example, RSBk, RSBk + 2)
The pulse signal CK1 having a period is also used as the signal of the even-numbered stage.
Signal holding block (for example, RSB k-1, RS
Bk + 1) Has an inverted waveform of the pulse signal CK1.
Cycle when each pulse signal CK2 outputs an output signal
Is supplied as a signal defining

Further, each signal holding block RSB k-1
A shift operation (first output signal) for sequentially outputting output signals OT k-1 to OT k + 2 (first output signals) from the respective signal holding blocks RSB k-1 to RSB k + 2 to the control terminals CTLA and CTLB of RSB k + 2 to RSB k + 2 . Signal output operation), and output signals OT k−1 to O having arbitrary signal levels and signal widths from the signal holding blocks RSB k−1 to RSB k + 2.
Integrated voltage adjustment operation for simultaneously outputting T k + 2 (second output signal) (second signal output operation; details will be described later)
And output control signals SETA and SET for controlling switching between
B is supplied. Here, the output control signal SETA and the output control signal SETB are in an inverted signal relationship with each other.

Although not shown, as in the first embodiment described above, the last-stage signal holding block RSB n
Next stage is, for example, the dummy signal holding block is provided, the output signal from the dummy signal holding block is provided as a reset signal to the reset terminal RST of the signal holding block RSB n of the final stage.

Next, a specific circuit configuration of each signal holding block applied to the shift register according to the present embodiment will be described with reference to the drawings. FIG. 7 is a circuit configuration diagram showing a specific configuration of a signal holding block applied to the shift register circuit according to the present embodiment. Here, only the circuit configuration of the signal holding block at the <k> stage (1 ≦ k ≦ n) will be described. As shown in FIG. 7, the signal holding block RSB k has seven M
It is configured to include OS transistors T21 to T27.

More specifically, the input terminal IN to which the input signal (output signal OT k-1 or start signal) from the preceding output signal holding block RSB k-1 is supplied and the contact N
A MOS transistor T21 (first transistor) whose source and drain terminals are connected to the input terminal IN, and a gate terminal is connected to the input terminal IN;
Are connected in series between the contacts NC and the low potential power supply Vss (fourth voltage signal), MOS transistors T25 output signal OT k + 1 from the next stage of the output signal holding block RSB k + 1 to the gate terminal is applied (the 5 transistors),
And a control terminal CTLB, to which an output control signal SETB (sixth voltage signal) is applied, having a gate terminal connected to the control terminal CTLB.
An OS transistor T26 (sixth transistor), a diode-connected MOS transistor T27 connected in series between a high potential power supply Vdd (fifth voltage signal) and a low potential power supply Vss (fourth voltage signal) (Load) and a MOS transistor T having a gate terminal connected to the contact NC.
22 (second transistor), an input terminal CLK to which a pulse signal CK1 (or CK2; third voltage signal) whose signal waveform can be changed, and an output control signal SETA (second voltage signal) are applied. Connected in series between the control terminal CTLA and the gate terminal connected to the contact NC.
OS transistor T23 (third transistor) and connection node ND between MOS transistors T22 and T27
MOS transistor T24 having a gate terminal connected to
(Fourth transistor) and a MOS transistor T23
And an output contact Nout provided at the connection contact of T24.

That is, the input control unit according to the present invention
The output control unit according to the present invention includes an OS transistor T21, and includes MOS transistors T22, T23, T
The discharge control unit according to the present invention includes MOS transistors T25 and T26. Here, the MOS transistors T21 to T27 constituting the circuit of the above-described signal holding block are all constituted by n-channel thin film transistors, similarly to the above-described first embodiment, and have a gate voltage-drain current characteristic. In the initial state is equivalent to the characteristic curve SP 0 (solid line) shown in FIG.

Next, the operation of each of the MOS transistors (T21 to T27) and the terminals and contacts (IN, CLK, NC, ND, C) constituting the signal holding block as described above.
The relationship between the potentials of LTA, CTLB, OUT, and RST) will be described with reference to the drawings. FIG. 8 is a timing chart showing changes in the potential of each terminal and contact of the signal holding block applied to the present embodiment. Here, description will be made with reference to the configuration of the above-described signal holding block (FIG. 7) as appropriate.

[0090] In the signal holding block RSB k having the above-described configuration, as shown in FIG. 8, MOS transistor T21 is a high level V through the input terminal IN
When the input signal of H (the output signal OT k-1 of the preceding signal holding block RSB k-1 ) is supplied, the input signal is turned on, the input signal of the high level V H is taken in, and the potential of the contact point NC is set to the corresponding level. It increases according to the signal level of the input signal.

On the other hand, MOS transistors T22 to T25
Is the signal holding block RSA shown in the above-described embodiment.
The same operation as the MOS transistors T12 to T15 at k is performed. That is, the MOS transistor T22 is
When an input signal is taken in through the MOS transistor T21 and the potential of the contact NC becomes high, it turns on,
The potential of the contact NB is set to a low state based on the low potential power supply Vss. Note that when the potential of the contact NC is low, the MOS transistor T22 is turned off, and the potential of the connection contact ND becomes high based on the high potential power supply Vdd supplied via the MOS transistor T27.

The MOS transistor T23 is connected to the MOS transistor T23.
An input signal is taken in through the S transistor T21,
When the potential of the contact NC is in a high state, it turns on. At this time, the potential of the connection contact ND is low and the MOS
Since the transistor T24 is turned off, the output contact Nout (output terminal OU) is output according to the signal level of the pulse signal CK1 supplied via the MOS transistor T23.
The potential of T) changes. When the potential of the contact NC is low, the MOS transistor T23 is turned off,
The supply of the pulse signal CK1 to the output contact Nout is cut off.

[0093] Here, the MOS transistor T23, as in the case of MOS transistors T13 described above, when in the ON state the potential of the contact NC is a high state, the pulse signal CK1 of high level V H is supplied by results bootstrap phenomenon gate voltage (potential of the contact NA) is relatively further increased, thereby, the potential of the output contact Nout (output signal OT k signal level) is rapidly and substantially pulse signal CK1 (or CK
The signal level is substantially equal to the signal level (high level V H ) of 2).

The MOS transistor T24 is turned on when the potential of the connection node ND becomes high. At this time, since the potential of the contact NC is in a low state and the MOS transistor T23 is turned off, the output control signal S
The output signal OT k having a signal level corresponding to the ETA is output. Here, the output control signal SETA is set to a low level V L (= Vss) in a shift operation described later, and is set to a signal waveform having a predetermined high level V H in an integrated voltage adjustment operation.

The MOS transistor T25 is turned on when the output signal OT k + 1 of the high level VH is output from the signal holding block RSB k + 1 of the next stage, and the contact N
The potential of C is set to a dischargeable state. At this time, when the MOS transistor T26 is turned on in response to the output control signal SETB, the potential of the contact NC is discharged. This allows
Together with the MOS transistors T22, T23 are turned OFF, the MOS transistor T24 since turned ON, the signal level set to the output control signal SETA is output as an output signal OT k.

Here, the output control signal SETB is set to the high level Vdd in the shift operation described later,
In the integrated voltage adjustment operation, a signal waveform having a low level Vss is set. Therefore, the output control signal SE
In the shift operation TB is set to the high level Vdd, by MOS transistors T25 and T26 is turned on, the signal level of the output signal OT k is switched from the high level V H to the low level V L. In the integrated voltage adjustment operation output control signal SETB it is set to the low level Vss, by MOS transistors T26 is turned OFF, a predetermined signal level in accordance with the signal level of the output signal OT k is the potential of the contact NC the output signal OT k having is output. Note that the signal level of the output signal OT k in the integrated voltage adjustment operation will be described later.

Next, a drive control method of a shift register circuit to which the above-described signal holding block is applied will be described with reference to the drawings. FIG. 9 is a timing chart illustrating the operation of the shift register circuit according to the present embodiment. Here, the configuration and operation (FIGS. 7 and 8) of the above-described shift register circuit (FIG. 6) and the signal holding block will be described appropriately.

(Shift Operation) First, a shift operation by the shift register circuit according to the present embodiment will be described.
First, as shown in FIG. 9, prior to the start of the shift operation, the output control signal SETA supplied via the control terminal CTLA is set to the low level Vss, and the output control signal supplied via the control terminal CTLB is set. The signal SETB is set to the high level Vdd.

Next, the input terminal I of the first-stage (first-stage) or <k> -stage signal holding block RSB k (not shown) is omitted.
In N, the high level of the input signal (output signal OT k-1 of the start signal or the preceding stage of the signal holding block RSB k-1)
Is applied, the MOS transistor T21 is turned on, as in the case shown in FIG. 8, and the potential of the contact NC increases according to the signal level of the input signal. This gives M
The OS transistors T22 and T23 are turned on, and the MO transistors
The S transistor T24 turns off.

Next, when the signal level of the pulse signal CK1 supplied to the input terminal CLK switches from the low level VL to the high level VH , the potential of the contact point NC further increases due to the bootstrap effect. falling to the drain - source current is saturated, via an output signal OT k is the output terminal OUT with a signal level substantially equal and the pulse signal CK1 supplied to the input terminal CLK (high level V H), the next stage Output to the signal holding block RSB k + 1 .

Next, the next-stage signal holding block RSB
In k + 1, the output signal OT k at a high level to the input terminal IN is applied, the output signal OT k is taken as the input signal, in the same manner as the operations of the signal holding block RSB k, the signal level of the pulse signal CK2 in the timing but switched from the low level V L to the high level V H, the output signal having a pulse signal CK2 substantially equal signal level (high level V H) OT k + 1 output terminals OUT
Is output to the signal holding block RSB k + 2 at the next stage (signal shift operation).

Here, the output signal OT k + 1 output from the signal holding block RSB k + 1 is supplied as a reset signal to the preceding signal holding block RSB k ,
The transistor T25 is turned on. At this time, MO
The MOS transistor T26 connected in series to the S transistor T25 has the gate terminal to which the output control signal SETB of the high level Vdd is applied, and during the shift operation period,
Since it is always in the ON state, the potential of the contact NC is discharged to the low potential power supply Vss and becomes the low level Vss. This allows
The MOS transistors T22 and T23 are turned off, and M
Since OS transistor T24 is turned on, from the output terminal OUT of the signal holding block RSB k control terminal CT
Output signal OT k of the low level V L in accordance with the signal level of the output control signal SETA supplied (low level Vss) is output to LA (reset operation).

Hereinafter, the same signal shift operation and reset operation are sequentially repeated for each signal holding block in synchronization with the application timing of the pulse signals CK1 and CK2, so that a predetermined signal level from each signal holding block is obtained. Output signals having (high level V H ) are sequentially output.

Although not shown, as in the first embodiment described above, the last-stage signal holding block RSA n
The output signal OT n output from the output terminal OUT of the input to the signal holding block RSA d dummy provided in the next stage, from the dummy signal holding block RSA d in application timing of the pulse signal CK1 (or CK2) The output signal OT d is output, so that the last-stage signal holding block R
SA n is reset.

(Integrated Voltage Adjusting Operation) Next, an integrated voltage adjusting operation by the shift register circuit according to the present embodiment will be described. First, prior to the start of the integrated voltage adjustment operation, as shown in FIG.
B k−1 , RSB k , RSB k + 1 , RSB k + 2.
・ Retains reset status. That is, the contact N
Since the potential of C is set to the low level Vss, the MOS transistors T22 and T23 are kept off, and the potential of the connection node ND is set to the high level Vdd, so that the MOS transistor T24 is kept on. Is done. Further, both the pulse signals CK1 and CK2 are set to the low level VL .

At this time, each signal holding block... RS
B k−1 , RSB k , RSB k + 1 , RSB k + 2.
The potential in the output contact Nout corresponding to the signal level of the output control signal SETA (low level V L) of - is applied from the output terminal OUT, and the output signal of the low level V L ··· OT k-1 , OT k , OT k + 1 , OT k + 2.
・ ・ Is output.

Next, the output control signals SETA and SET
B, the output control signal SETA is set to a signal waveform having an arbitrary high level Va (for example, a high level that satisfies Va ≒ Vdd) and an arbitrary signal width Tw (corresponding to an integrated voltage adjustment operation period). , Output control signal SETB
Is set to a signal waveform having a signal level (low level Vss) and a signal width Tw having an inversion relationship with the output control signal SETA. Further, by controlling the pulse signals CK1 and CK2, both of the pulse signals are output from the output control signal SETA.
And the same signal waveform having a signal width Tw and an arbitrary high level Vb (for example, a high level where Vb ≒ Vdd) corresponding to SETB.

Then, the signal waveform is set as described above.
Output control signals SETA, SETB and pulse signals
No. CK1 and CK2 are optional to start the integrated voltage adjustment operation
, All the signal holding blocks... RS
Bk-1, RSBk, RSB k + 1, RSBk + 2・ ・
Control terminals CTLA, CTLB, and input terminal CL
K are applied simultaneously.

Thus, each signal holding block... R
SBk-1, RSBk, RSBk + 1, RSBk + 2
··· From the output terminal OUT immediately after the above application timing
, The control signal S applied to the control terminal CTLA
Output signal corresponding to ETA signal level OT
k-1, OTk, OTk + 1, OTk + 2... is output
(The first output state), the signal is applied to the input terminal CLK.
Signal level and signal of the extracted pulse signal CK1 or CK2
Output signal having signal waveform corresponding to width ... OT
k-1, OTk, OTk + 1, OTk + 2... are simultaneous
(The second output state).

Here, the switching control of the first and second output states in each signal holding block will be described in detail with reference to the drawings. FIG. 10 is a timing chart showing a detailed voltage change in the integrated voltage adjustment operation of the shift register circuit according to the present embodiment. Here, for convenience of explanation, only the circuit configuration of the signal holding block at the <k> stage will be described.

As described above, in the initial state before the start of the integrated voltage adjustment operation, the potential of the contact NC is at the low level Vss, the MOS transistors T22 and T23 are kept off, and the connection contact ND Is at the high level Vdd, and the MOS transistor T24 is kept on.

Then, as shown in FIG.
At any time to start the adjustment operation, each signal holding block
Hook ... RSBk-1, RSBk, RSBk + 1, R
SB k + 2... high level via the control terminal CTLA
Output control signal SETA having a voltage Va and a control terminal CTL
Output control signal SET having a low level Vss via B
B and a high level Vb via the input terminal CLK.
Pulse signal CK1 (or CK2) to be applied simultaneously
Immediately after the start of the integrated voltage adjustment operation, the MOS transistor
Since the transistor T24 is in the ON state, the control terminal CT
The signal level corresponding to the high level Va of LA is the output contact N
out to high level VHOutput signal OT
k-1, OTk, OTk + 1, OTk + 2... are simultaneous
Is output to At this time, the MOS transistor T
26 is turned off, the potential of the contact NC is discharged.
It will be kept without being done.

Thus, each signal holding block... R
SB k−1 , RSB k , RSB k + 1 , RSB k + 2 ·
The output signal (high level V H ) at the preceding stage is
N, the MOS transistor T21 is turned on, and the potential of the contact NC increases. Here, in FIG. 10, the potential change of the contact point NC is shown by a gentle curve for the sake of explanation, but actually, the potential instantly reaches a predetermined high level.

[0114] In increasing the course of the potential of such a contact NC, the said potential reaches the threshold voltage V t1 of the MOS transistors T22, T23, the MOS transistor T
22 and T23 are turned on, the connection contact ND
Is discharged to the low-potential power supply Vss via the MOS transistor T22 and starts to fall, and the pulse signal C
The signal level of K1 is supplied to the output contact Nout via the MOS transistor T23.

[0115] Then, in descending course of the potential of the connection contacts ND, when the potential reaches below the threshold voltage V t2 of the MOS transistor T24, the MOS transistor T2
4 is turned off, the supply of the output control signal SETA to the output contact Nout is cut off. Here, FIG.
In FIG. 7, the change in the potential of the contact point ND is shown by a gentle curve for convenience of explanation, but in practice, the potential instantaneously reaches a predetermined low level.

That is, in the extremely short period Tth until the operation state of the MOS transistors T22 to T24 switches immediately after the start of the integrated voltage adjustment operation, the control terminal CTL
A high-level Va output control signal S supplied through A
An output signal having a signal level (high level V H ) corresponding to the ETA: OT k−1 , OT k , OT k + 1 , OT
k + 2 ... are each signal holding block ... RS
B k−1 , RSB k , RSB k + 1 , RSB k + 2.
Is output from the output terminal OUT (first output state).

On the other hand, after the elapse of the above-described period Tth, the potential of the contact NC becomes high level,
By holding the potential of D at low level, the MOS
Since the transistors T22 and T23 hold the ON state and the MOS transistor T24 holds the OFF state, the signal level (high level VH ) corresponding to the high-level Vb pulse signal CK1 supplied via the MOS transistor T23. An output signal having
T k−1 , OT k , OT k + 1 , OT k + 2 ... Are signal holding blocks... RSB k−1 , RSB k ,
B k + 1 , RSB k + 2 ... Are output from output terminals OUT (second output state).

As a result, during the integrated voltage adjusting operation period,
Each signal holding block ... RSB k-1, RSBk,
RSBk + 1, RSBk + 2... output signal from ...
・ OTk-1, OTk, OTk + 1, OTk + 2...
Are the output control signal SETA and the pulse signal CK1 (or
CK1) is instantaneously switched and supplied.

Then, at the end of the integrated voltage adjustment operation,
The output control signal SETA changes from the high level Va to the low level VL , the output control signal SETB changes from the low level Vss to the high level Vdd, and the pulse signal CK1 (or CK).
2) is simultaneously switched from the high level Vb to the low level VL , so that each signal holding block... RSB k
-1 , RSB k , RSB k + 1 , RSB k + 2 ... From the output terminal OUT, the pulse signal CK1 (or CK
An output signal having a low level VL based on the signal level of 2): OT k−1 , OT k , OT k + 1 , OT
k + 2 ... are output.

Thus, each signal holding block... R
SB k−1 , RSB k , RSB k + 1 , RSB k + 2 ·
At the point of time, when the electrode of the contact NC is lowered and the MOS transistors T22 and T23 are turned off, and the electrode of the connection contact ND is raised and the MOS transistor T24 is turned on, the supply of the pulse signal CK1 to the output contact Nout is stopped. While being cut off, the output control signal SETA is
t, each signal holding block ... RSB
k-1, RSB k, RSB k + 1, RSB k + 2 ···
OT k−1 , OT k , OT k + 1 , OT k , OT k −1 , OT k , OT k −1 , OT k
k + 2 ... are output.

In this embodiment, similarly to the first embodiment (see FIG. 5), the output signal (adjustment signal) output during the integrated voltage adjustment period is applied during the shift operation period. It is set so as to have a signal waveform (signal level VH and signal width Tw) that can offset or adjust the bias of the polarity of the time integral value of the output signal. Here, the signal level V H of the adjustment signal as a substantially signal level of the pulse signal CK1, CK2 prescribed, when applying a high-level Vdd commonly used in the shift operation,
By controlling the signal width Tw (integrated voltage adjustment period) of the pulse signals CK1 and CK2, a signal waveform that can offset or adjust the bias of the polarity of the time integration value may be set.

As described above, according to the drive control method for the shift register circuit according to the present embodiment, a high-level input signal is applied to the signal holding block of each stage, thereby capturing the signal level. , A shift operation can be performed. According to the configuration of such a shift register circuit (input control unit), a high voltage is applied to the gate electrode of the MOS transistor constituting the input control unit only at the timing when an input signal is applied to each signal holding block in the shift operation. Since the level voltage (gate signal) is applied, it is possible to prevent the gate signal from being repeatedly applied to the gate electrode, and to suppress a change in the threshold characteristic of the MOS transistor.

Further, by the integrated voltage adjustment operation, an adjustment signal having a predetermined signal waveform (signal level VH and signal width Tw) is sent from the gate electrode of the MOS transistor constituting each signal holding block or the shift register circuit. To the gate electrode of a MOS transistor that constitutes a device (for example, a photosensor array) driven by the output signal of (i), to offset the bias of the polarity of the time integral value of the gate signal applied during the shift operation period. It can be adjusted to relax.

[0124] In particular, the MOS transistors T26, during a shift operation, for that the gate is substantially high level Vdd continues, because its drain is always low level Vss, the Vg-Id characteristic curve SP 2 shown in FIG. 26 The characteristic change can be reduced by setting the gate potential to the low level Vss during the integrated voltage adjustment operation.

Further, in the MOS transistor T24,
During the shift operation, while the potential of the gate continues to be substantially close to the high level Vdd, the drain (control terminal CTLA)
26), the low level Vss continues, so that Vg− shown in FIG.
Tended to become Id characteristic curve SP 2, it is possible to relax the characteristic change by the drain potential in the integrated voltage adjustment operation and a high level Va.

Therefore, in the shift register circuit having the configuration according to the present embodiment, fluctuations in the threshold characteristics of the MOS transistors forming each signal holding block can be further suppressed, and malfunction and deterioration of the operation characteristics can be suppressed. A shift register circuit which is unlikely to be generated can be realized.
Further, in a liquid crystal display device or an image reading device in which the shift register circuit according to the present embodiment is applied to a scan driver, voltage fluctuation of a scan signal (output signal from the shift register circuit) is suppressed, so that reliability is improved. A high liquid crystal display device and an image reading device can be provided.

Further, in an image reading apparatus in which the shift register circuit according to the present embodiment is applied to a scanning driver, the voltage is repeatedly applied to a MOS transistor constituting a photosensor of the image reading apparatus during a normal image reading operation. Even when the threshold characteristic fluctuates due to the scanning signal (gate signal), the adjustment signal having the predetermined signal waveform is simultaneously applied to the scanning lines at the same time, so that the threshold Since the characteristics can be temporarily (immediately) improved, it is possible to suppress the deterioration of the element characteristics of the photo sensor, the malfunction of the image reading device, and the deterioration of the reading sensitivity, and to provide a highly reliable image reading device. Can be.

In the above-described embodiment, the output control signal S applied to the control terminals CTLA and CTLB
Although a case has been described where the ETA and SETB are set to signal waveforms having an inversion relationship with each other, the output control signals SETA and SETB may be set to independent signal waveforms.

In this case, as described in the integrated voltage adjusting operation, the output control signal SETA outputs a high-level output signal to each signal holding block of the next stage immediately after the start of the integrated voltage adjusting operation. Then, the potential of the contact NC of each signal holding block of the next stage is set to a high state, and the signal level (high level) of the pulse signal CK1 (or CK2) is set.
Is supplied to the output contact Nout to continuously output an output signal based on the signal level, that is, a function as a so-called trigger.

Therefore, after the function as the trigger has been performed immediately after the start of the integrated voltage adjusting operation, the signal level of the output control signal SETA does not affect the integrated voltage adjusting operation of each signal holding block. The signal waveform of the output control signal SETA may be set to an instantaneous pulse having a very short signal width as shown by a broken line Pa in FIG.

<Third Embodiment> Next, a third embodiment of the shift register circuit according to the present invention will be described with reference to the drawings. FIG. 11 is a circuit configuration diagram showing a specific configuration of a signal holding block applied to the shift register circuit according to the third embodiment. Here, <k
Only the circuit configuration of the signal holding block at the> stage (1 ≦ k ≦ n) will be described.

Further, since the overall configuration of the shift register circuit according to the present embodiment is substantially the same as that of the above-described second embodiment (FIG. 6), FIG. 6 will be appropriately referred to in the following description. At this time, the code R of each signal holding block is used.
SB k−1 , RSB k , RSB k + 1 , RSB
k + 2 is RSC k−1 , RSC k , RS
C k + 1 and RSC k + 2 . Further, for a configuration equivalent to the above-described second embodiment,
The same reference numerals are given, and the description is omitted or simplified.

The shift register circuit according to the present embodiment comprises:
Each signal holding block RSCk-1~ RSCk + 2Is in series
And each signal holding block RSCk-1~ RSC
k + 2Output signal OTk-1~ OTk + 2But each next
Stage signal holding block RSC k~ RSCk + 3Input signal
It is configured to be supplied as a signal. (See FIG. 6).

Each of the signal holding blocks RSC k-1 to RSC k-1 .
Output signals OT k -1 to OT from RSC k + 2
k + 2 is a signal holding block RSC k−2 of each preceding stage.
RRSC k + 1 is provided as a reset signal. Therefore, in the shift register circuit according to the present embodiment, as in the second embodiment described above, the next stage of the signal holding block RSC n of the final stage, a dummy signal holding block is provided, the signal of the dummy the output signal from the holding block is supplied as a reset signal to the reset terminal RST of the signal holding block RSC n of the final stage.

Here, each signal holding block RSC k-1
As shown in FIG. 11, .about.RSC k + 2 has eight MOS transistors T31 to T38 as a basic configuration. Specifically, the input signal (output signal O) from the output signal holding block RSC k-1 at the preceding stage is output.
The source and drain terminals are connected between the input terminal IN to which T k-1 or the start signal is supplied and the contact NE (voltage holding contact), and the gate terminal is connected to the input terminal IN.
Is connected in series between a contact NE and a low-potential power supply Vss (fourth voltage signal), and the next-stage output signal holding block RSC k + 1 is connected to the gate terminal. Output signal OT from
A MOS transistor T36 (sixth transistor) having a gate terminal connected to a MOS transistor T35 (fifth transistor) to which k + 1 is applied and a control terminal CTLB to which an output control signal SETB (sixth voltage signal) is applied. Transistor), a diode-connected MOS transistor T38 connected in series between a high potential power supply Vdd (fifth voltage signal) and a low potential power supply Vss (fourth voltage signal).
(Load) and M having the gate terminal connected to the contact NE.
An OS transistor T32 (second transistor) and a pulse signal CK1 (or CK2;
A third voltage signal) is connected in series between the input terminal CLK to which the third voltage signal is applied and the low potential power supply Vss (fourth voltage signal);
A MOS transistor T33 (third transistor) having a gate terminal connected to the contact NE; a MOS transistor T34 (fourth transistor) having a gate terminal connected to a connection contact NF between the MOS transistors T32 and T38; An output contact Nout provided at a connection contact between T33 and T34 and a high-potential power supply Vdd (fifth
The MOS transistor T37 (the source and drain terminals of which are connected between the voltage signal of the first transistor and the contact NE) and the gate terminal of which is connected to the control terminal CTLC to which the output control signal SETA (the second voltage signal) is applied. (Seventh transistor).

That is, the input control unit according to the present invention uses M
The output control unit according to the present invention includes an OS transistor T31, and includes MOS transistors T32, T33, T
The discharge control unit according to the present invention includes MOS transistors T35 and T36. Here, the MOS transistors T31 to T38 constituting the circuit of the above-described signal holding block are:
As in the first and second embodiments described above, all are constituted by n-channel thin film transistors, and the gate voltage-drain current characteristics of the thin film transistors in the initial state are as follows.
It is assumed that this is equivalent to the characteristic curve SP 0 (solid line) shown in FIG.

Next, a drive control method of a shift register circuit to which the above-described signal holding block is applied will be described. FIG. 12 is a timing chart illustrating the operation of the shift register circuit according to the present embodiment. Here, description will be made with reference to the above-described shift register circuit (see FIG. 6) and the configuration of the signal holding block (FIG. 11) as appropriate.

(Shift Operation) First, prior to the start of the shift operation by the shift register circuit according to the present embodiment,
As shown in FIG. 12, the output control signal SETA is set to the low level Vss, and the output control signal SETB is set to the high level Vdd. As a result, in FIG. 11, the output control signal SETA is applied to the gate terminal.
The OS transistor T37 is turned off, the supply of the high potential power supply Vdd to the contact NE is cut off, and the MOS transistor T36, to which the output control signal SETB is applied to the gate terminal, is turned on, and the contact NE is turned off. Since the discharge of the potential to the low potential power supply Vss depends on the operation state of the MOS transistor T35, the circuit configuration of the shift register circuit (signal holding block) during the shift operation is substantially the second embodiment. 7 is the same as the circuit configuration of the signal holding block (FIG. 7). Therefore, in the shift operation according to the present embodiment, the operation of each MOS transistor (T31 to T38) constituting the signal holding block and each terminal and contact (IN, CLK, NE, NF, CLT)
The relationship between the potentials of C, CTLB, OUT, and RST) is similar to that of the above-described second embodiment (see FIG. 8).

That is, as shown in FIG. 12, the input terminal IN of the signal holding block RSC k of the first stage or the <k> stage is used.
When a high-level input signal (start signal or output signal OT k−1 at the previous stage) is applied to the MOS transistor T31, the MOS transistor T31 is turned on, and the potential of the contact point NE increases.
As a result, the MOS transistors T32 and T33 are turned on, and the MOS transistor T34 is turned off.

Next, when the signal level of the pulse signal CK1 is switched to the high level VH , the potential of the contact point NE further rises due to the bootstrap effect, so that a signal level substantially equal to the pulse signal CK1 (high level VH ). the output signal OT k having is output to the next stage of the signal holding block RSC k + 1.

As a result, the signal holding block RS at the next stage
A high-level output signal OT k is applied to the input terminal IN of C k + 1.
When There is applied, similarly to the operation in the signal holding block RSC k, at the timing when the signal level of the pulse signal CK2 switches to the high level V H, the pulse signal CK
An output signal OT k + 1 having a signal level (high level V H ) substantially equal to that of the second signal holding block RSC
Output to k + 2 (signal shift operation).

Here, the signal holding block RSCk + 1Or
Output signal OT output fromk + 1Is the signal holding block
Rock RSCkIs supplied as a reset signal to
As a result, the MOS transistor T35 is turned on, and the contact N
The potential of E is discharged to the low potential power supply Vss and the low level Vss
become. Thereby, the MOS transistors T32 and T32
33 is turned off, and the MOS transistor T34 is turned on.
The signal holding block RSCkFrom low potential
Low level V according to source VssLOutput signal OT kOutput
(Reset operation).

Hereinafter, the same signal shift operation and reset operation are sequentially repeated for each signal holding block in synchronization with the application timing of the pulse signals CK1 and CK2, so that a predetermined signal level from each signal holding block is obtained. Output signals having (high level V H ) are sequentially output.

(Integrated Voltage Adjusting Operation) Next, an integrated voltage adjusting operation by the shift register circuit according to the present embodiment will be described. First, prior to the start of the integrated voltage adjustment operation, as shown in FIG. 12, the pulse signals CK1 and CK2
Are set to the low level VL . In addition, by the end of the above-described series of shift operations, the signal holding blocks at each stage... RSC k−1 , RSC k , RSC k + 1 , and RSC
.. k hold the reset state. That is, since the potential of the contact NE is set to the low level Vss, the MOS transistors T32 and T33 are kept off, and the potential of the connection contact NF is set to the high level Vdd.
, The MOS transistor T34 is kept on.

At this time, each signal holding block... RS
C k−1 , RSC k , RSC k + 1 , RSC k + 2.
Since a potential corresponding to the low-potential power supply Vss is applied to the output contact Nout, a low level V is applied from the output terminal OUT.
L output signal: OT k− 1 , OT k , OT k + 1 ,
OT k + 2 ... Are output.

Next, the output control signals SETA and SET
B to set the output control signal SETA to a signal waveform having an arbitrary high level V H (for example, ΔVdd) and an arbitrary signal width Tw (corresponding to an integrated voltage adjustment operation period), and SETB is output from the output control signal SE.
It is set to a signal waveform having a signal level (low level Vss) and a signal width Tw that are inversely related to TA. Further, by controlling the pulse signals CK1 and CK2, each of the pulse signals has a signal width Tw corresponding to the output control signals SETA and SETB and an arbitrary high level Vc (for example, Vc ≒).
(The same signal waveform having a high level of Vdd).

Then, the signal waveform is set as described above.
Output control signals SETA, SETB and pulse signals
No. CK1 and CK2 are optional to start the integrated voltage adjustment operation
, All the signal holding blocks... RS
Ck-1, RSCk, RSC k + 1, RSCk + 2・ ・
・ Control terminals CTLC, CTLB and input terminal CL
K are applied simultaneously.

[0148] Thus, firstly, the output control signal SETA high level V H is applied to the control terminal CTLC, MOS transistor T37 is turned on operation, a high potential of the contact NE according to the high-potential power supply Vdd In this state, the MOS transistors T32 and T33 are turned on, and the potential of the connection contact NF is set to a low state.
The OS transistor T34 turns off.

At this time, since the output control signal SETB of the low level Vss is applied to the gate terminal (control terminal CTLB) of the MOS transistor T36 and the MOS transistor T36 is in the off state,
Regardless of the operation state of the MOS transistor T35, the potential of the contact point NE is maintained without being discharged. Also, M
When the OS transistor T34 is turned off, the supply of the low potential power supply Vss to the output contact Nout is cut off.

Therefore, the output contact Nout is connected to the MOS
The signal level of the pulse signal CK1 through the transistor T33 (high level Vc) is supplied, the output signal · · · OT having a high level V H corresponding to the signal level
k-1 , OT k , OT k + 1 , OT k + 2 ... are signal holding blocks... RSC k−1 , RSC k , RSC
k + 1 , RSC k + 2 ... are output from output terminals OUT.

At the end of the integrated voltage adjustment operation,
The output control signal SETA changes from the high level VH to the low level VL , the output control signal SETB changes from the low level Vss to the high level Vdd, and the pulse signal CK1 (or CK).
When 2) is simultaneously switched from the high level Vc to the low level VL , the MOS transistor T37 is turned off to cut off the supply of the high potential power supply Vdd to the contact point NE, and the MOS transistor T36 is turned on, and Next-stage signal holding blocks: RSC k , RSC
k + 1 , RSC k + 2 , RSC k + 3 ... high-level VH output signals OT k−1 , OT k , OT
MOS transistors T by k + 1 , OT k + 2.
35 is in the ON state, the MOS transistor T
35, the potential of the contact NE is set to the low potential power supply Vss through T36.
To a low state.

As a result, the MOS transistor T32,
T33 turns off, the electrode of the connection contact NF rises,
When the MOS transistor T34 is turned on,
Since the supply of the pulse signal CK1 to the output contact Nout is cut off and the low potential power supply Vss is supplied to the output contact Nout, each signal holding block... RSC k−1 , R
From the output terminals OUT of SC k , RSC k + 1 , RSC k + 2 ..., The low level VL based on the low potential power supply Vss is output.
OT k−1 , OT k , OT
k + 1 , OT k + 2 ... are output simultaneously.

At this time, output signals of the next stage having the low level VL ... OT k , OT k + 1 , OT k + 2 , OT
k + 3 ... are each signal holding block ... RS
C k−1 , RSC k , RSC k + 1 , RSC k + 2.
Is supplied as a reset signal, and the MOS transistor T35 is turned off, but the output signal of the preceding stage... OT k−2 , OT k−1 , OT k , OT via the input terminal IN
k + 1 by ...... are incorporated, contact N
The potential of E remains low.

As described above, in the integrated voltage adjustment operation period, each signal holding block... RSC k−1 , R
The pulse signal C applied to the input terminal CLK from the output terminal OUT of SC k , RSC k + 1 , RSC k + 2.
An output signal (adjustment signal) having a signal waveform corresponding to the signal level Vc and the signal width Tw of K1 or CK2 ... OT
k−1 , OT k , OT k + 1 , OT k + 2 ... are output simultaneously.

Therefore, according to the shift register circuit having such a configuration and its drive control method, it is possible to obtain the same operation and effect as those of the above-described second embodiment. In particular, in the MOS transistor T36, during the shift operation, the gate of the MOS transistor T36 substantially remains at the high level Vdd.
Since the drain is always at the low level Vss, FIG.
To indicate tended to become Vg-Id characteristic curve SP 2, the integrated voltage adjusting operation a low level gate potential during Vss
By doing so, the characteristic change can be reduced.

In this embodiment, similarly to the first embodiment (see FIG. 5), the output signal (adjustment signal) output during the integrated voltage adjustment period is applied during the shift operation period. It is set so as to have a signal waveform (signal level VH and signal width Tw) that can offset or adjust the bias of the polarity of the time integration value of the output signal. Here, the pulse signal CK1 which defines a signal level V H of the adjustment signal,
When the high level Vdd normally used in the shift operation is applied as the signal level of CK2, by controlling the signal width Tw (integrated voltage adjustment period) of the pulse signals CK1 and CK2, the polarity of the time integration value is controlled. A signal waveform that can cancel or adjust the bias may be set.

<Fourth Embodiment> Next, a fourth embodiment of the shift register circuit according to the present invention will be described with reference to the drawings. FIG. 13 is a circuit configuration diagram showing a specific configuration of a signal holding block applied to the shift register circuit according to the fourth embodiment. Here, only the circuit configuration of the signal holding block at the <k> stage (1 ≦ k ≦ n) will be described. Note that components equivalent to those of the above-described third embodiment are denoted by the same reference numerals and described.

Further, since the overall configuration of the shift register circuit according to the present embodiment is substantially the same as that of the above-described second embodiment (FIG. 6), FIG. 6 will be appropriately referred to in the following description. At this time, the code R of each signal holding block is used.
SB k−1 , RSB k , RSB k + 1 , RSB
k + 2 is RSD k−1 , RSD k , RS
D k + 1 and RSD k + 2 . Further, for a configuration equivalent to the above-described second embodiment,
The same reference numerals are given, and the description is omitted or simplified.

The shift register circuit according to the present embodiment comprises:
Each signal holding block RSDk-1~ RSDk + 2Is in series
And each signal holding block RSDk-1~ RSD
k + 2Output signal OTk-1~ OTk + 2But each next
Stage signal holding block RSD k~ RSDk + 3Input signal
It is configured to be supplied as a signal. (See FIG. 6).

Each of the signal holding blocks RSD k−1 to RSD k−1 to
Output signals OT k -1 to OT from RSD k + 2
k + 2 is the signal holding block RSD k−2 of each preceding stage.
To RSD k + 1 as a reset signal. Therefore, in the shift register circuit according to the present embodiment, as in the second or third embodiment described above, the next stage of the signal holding block RSD n of the final stage, a dummy signal holding block is provided, this the output signal from the dummy signal holding block is provided as a reset signal to the reset terminal RST of the signal holding block RSD n of the final stage.

Here, each signal holding block RSD k-1
As shown in FIG. 13, RSD k + 2 has eight MOS transistors T41 to T48 as a basic configuration. Specifically, the input signal (output signal O) from the output signal holding block RSD k-1 at the preceding stage is output.
The source and drain terminals are connected between the input terminal IN to which T k-1 or the start signal is supplied and the contact NG (voltage holding contact), and the gate terminal is connected to the input terminal IN.
Is connected in series between the contact NG and the low-potential power supply Vss (fourth voltage signal), and the next-stage output signal holding block RSD k + 1 is connected to the gate terminal of the MOS transistor T41 (first transistor). Output signal OT from
The MOS transistor T46 (the sixth transistor) having a gate terminal connected to the MOS transistor T45 (fifth transistor) to which k + 1 is applied and the control terminal CTLB to which the output control signal SETB (sixth voltage signal) is applied. Transistor), a diode-connected MOS transistor T48 connected in series between a high potential power supply Vdd (fifth voltage signal) and a low potential power supply Vss (fourth voltage signal).
(Load) and M having the gate terminal connected to the contact NG
An OS transistor T42 (second transistor) and a pulse signal CK1 (or CK2;
A third voltage signal) is connected in series between the input terminal CLK to which the third voltage signal is applied and the low potential power supply Vss (fourth voltage signal);
A MOS transistor T43 (third transistor) having a gate terminal connected to the contact NG, a MOS transistor T44 (fourth transistor) having a gate terminal connected to a connection contact NH between the MOS transistors T42 and T48, and a MOS transistor An output contact Nout provided at a connection contact between T43 and T44, and an output control signal SETA;
A MOS in which the source and drain terminals are connected between the control terminal CTLC to which the (second voltage signal) is applied and the contact NG, and the gate terminal is connected to the control terminal CTLC
And a transistor T47 (eighth transistor).

That is, the input control unit according to the present invention uses M
The output control unit according to the present invention includes an OS transistor T41, and includes MOS transistors T42, T43, T
The discharge control unit according to the present invention includes MOS transistors T45 and T46. Here, the MOS transistors T41 to T48 constituting the circuit of the above-described signal holding block are:
As in each of the above-described embodiments, all are configured by n-channel thin film transistors, and the gate voltage thereof is
It is assumed that the drain current characteristic is equivalent to the characteristic curve SP 0 (solid line) shown in FIG. 26 in the initial state.

Next, a driving control method of a shift register circuit to which the above-described signal holding block is applied will be described. Since the drive control method of the shift register circuit according to the present embodiment is substantially the same as that of the above-described third embodiment (FIG. 12), the description thereof will be simplified or omitted with reference to FIG. Further, in the following description, when referring to FIG. 12, the codes RSC k−1 ,
RSC k , RSC k + 1 , RSC k + 2 are represented by RSD
k−1 , RSD k , RSD k + 1 , RSD k + 2 and the contacts NE and NF are read as NG and NH, respectively.

(Shift Operation) First, prior to the start of the shift operation by the shift register circuit according to the present embodiment,
As in the third embodiment (see FIG. 12), the output control signal SETA is set to the low level Vss, and the output control signal SETB is set to the high level Vdd. Thereby, the output control signal SET in FIG.
MOS transistor T47 to which A is applied to the gate terminal
Is turned off, and the contact NG of the output control signal SETA is turned off.
To the gate terminal of the MOS transistor T46, the output control signal SETB is applied to the gate terminal, the MOS transistor T46 is turned on, and the discharging of the potential of the contact NG to the low potential power supply Vss is performed. Therefore, the circuit configuration of the shift register circuit (signal holding block) at the time of the shift operation is the same as that of the third circuit described above.
As in the third embodiment, the circuit configuration is substantially the same as that of the signal holding block (FIG. 7) shown in the second embodiment.

Therefore, the shift operation according to the present embodiment
Are the same as those of the second or third embodiment (see FIG. 12).
Equivalent to the first or <k> stage signal holding block R
SC kHigh level input signal applied to the input terminal IN
Signal is applied to the application timing of the pulse signals CK1 and CK2.
Synchronously, sequentially each signal holding block ... RS
Dk- 1, RSDk, RSDk + 1, RSDk + 2・ ・
· Output signal while being transferred (shifted) to OTk,
OTk + 1, OTk + 2, OTk + 3Output as ...
Is done.

(Integrated Voltage Adjusting Operation) Next, an integrated voltage adjusting operation by the shift register circuit according to the present embodiment will be described. First, prior to the start of the integrated voltage adjustment operation, as in the above-described third embodiment (see FIG. 12),
The pulse signals CK1 and CK2 are both set to the low level VL . Further, upon completion of the above-described series of shift operations, the signal holding blocks at each stage... RSD k−1 , RS
D k , RSD k + 1 , RSD k + 2 ... Hold the reset state. That is, since the potential of the contact NG is set to the low level Vss, the MOS transistor T4
2 and T43 are kept off, and the connection contact N
Since the potential of H is set to the high level Vdd, the MOS transistor T44 is kept on.

At this time, each signal holding block... RS
D k−1 , RSD k , RSD k + 1 , RSD k + 2.
Since a potential corresponding to the low-potential power supply Vss is applied to the output contact Nout, a low level V is applied from the output terminal OUT.
L output signal: OT k− 1 , OT k , OT k + 1 ,
OT k + 2 ... Are output.

Next, the output control signals SETA and SET
B to set the output control signal SETA to a signal waveform having an arbitrary high level V H (for example, ΔVdd) and an arbitrary signal width Tw (corresponding to an integrated voltage adjustment operation period), and SETB is output from the output control signal SE.
It is set to a signal waveform having a signal level (low level Vss) and a signal width Tw that are inversely related to TA. Further, by controlling the pulse signals CK1 and CK2, each of the pulse signals has a signal width Tw corresponding to the output control signals SETA and SETB and an arbitrary high level Vc (for example, Vc ≒).
(The same signal waveform having a high level of Vdd).

Then, the signal waveform is set as described above.
Output control signals SETA, SETB and pulse signals
No. CK1 and CK2 are optional to start the integrated voltage adjustment operation
, All the signal holding blocks... RS
Dk-1, RSDk, RSD k + 1, RSDk + 2・ ・
・ Control terminals CTLC, CTLB and input terminal CL
K are applied simultaneously.

[0170] Thus, firstly, the output control signal SETA high level V H is applied to the control terminal CTLC, MOS transistor T47 is turned on operation, the output control signal SETA signal level (high level V H) When the potential of the contact NG becomes high according to the above, the MOS transistors T42 and T43 are turned on, and the potential of the connection contact NH is turned low and the MOS transistor T44 is turned off.

At this time, since the output control signal SETB of the low level Vss is applied to the gate terminal (control terminal CTLB) of the MOS transistor T46 and the MOS transistor T46 is off,
Regardless of the operation state of the MOS transistor T45, the potential of the contact point NE is maintained without being discharged. Also, M
When the OS transistor T44 is turned off, the supply of the low potential power supply Vss to the output contact Nout is cut off.

Therefore, the output contact Nout is connected to the MOS
The signal level of the pulse signal CK1 through the transistor T43 (high level Vc) is supplied, the output signal · · · OT having a high level V H corresponding to the signal level
k-1 , OT k , OT k + 1 , OT k + 2 ... are signal holding blocks... RSD k−1 , RSD k , RSD
k + 1 , RSD k + 2 ... are output from output terminals OUT.

At the end of the integrated voltage adjustment operation,
Output control signal SETA is at high level VHFrom low level
VLThen, the output control signal SETB is changed from the low level Vss to the high level.
Level Vdd and the pulse signal CK1 (or CK1).
2) from high level Vc to low level VLCut at the same time
As a result, the MOS transistor T47 is turned off.
To cut off the supply of the output control signal SETA to the contact NG
And the MOS transistor T46 is turned on.
And each signal holding block at the next stage ... RSD k,
RSDk + 1, RSDk + 2, RSDk + 3From ...
High level VHOutput signal OTk-1, O
Tk, OTk + 1, OTk + 2... by MOS tiger
Since the transistor T45 is in the ON state, the MOS transistor
The potential of the contact NG is low through the transistors T45 and T46.
The power is discharged to the power supply Vss and becomes low.

As a result, the MOS transistor T42,
T43 turns off, the electrode of the connection contact NH rises,
When the MOS transistor T44 is turned on,
Since the supply of the pulse signal CK1 to the output contact Nout is cut off and the low potential power supply Vss is supplied to the output contact Nout, each signal holding block... RSD k−1 , R
From the output terminals OUT of SD k , RSD k + 1 , RSD k + 2 ..., A low level VL based on the low potential power supply Vss is output.
OT k−1 , OT k , OT
k + 1 , OT k + 2 ... are output simultaneously.

At this time, output signals of the next stage having the low level VL ... OT k , OT k + 1 , OT k + 2 , OT
k + 3 ... are each signal holding block ... RS
D k−1 , RSD k , RSD k + 1 , RSD k + 2.
- to be supplied as a reset signal, but MOS transistor T45 is turned OFF, the output signal of the preceding stage via the input terminal IN ··· OT k-2, OT k-1, OT k, OT
k + 1 by ...... are incorporated, contact N
The potential of G is kept low.

As described above, in the integrated voltage adjustment operation period, each signal holding block... RSD k−1 , R
The pulse signal C applied to the input terminal CLK from the output terminal OUT of SD k , RSD k + 1 , RSD k + 2.
An output signal (adjustment signal) having a signal waveform corresponding to the signal level Vc and the signal width Tw of K1 or CK2 ... OT
k−1 , OT k , OT k + 1 , OT k + 2 ... are output simultaneously.

Therefore, according to the shift register circuit having such a configuration and the drive control method thereof, it is possible to obtain the same operational effects as those of the above-described second embodiment. In particular, in the MOS transistor T46, during the shift operation, the gate of the MOS transistor T46 remains almost at the high level Vdd.
Since the drain is always at the low level Vss, FIG.
To indicate tended to become Vg-Id characteristic curve SP 2, the integrated voltage adjusting operation a low level gate potential during Vss
By doing so, the characteristic change can be reduced.

Next, an application example of the shift register circuit according to the present invention will be specifically described with reference to the drawings. <First Application Example> FIG. 14 is a schematic configuration diagram showing the entire configuration of a liquid crystal display device to which the shift register circuit according to the present invention is applied, and FIG. FIG. 2 is a detailed diagram showing a configuration of the unit. Here, a liquid crystal display device using an active matrix liquid crystal display panel will be described as the liquid crystal display device.

As shown in FIG. 14, the liquid crystal display device according to this application example is roughly classified into a liquid crystal display panel (display means) 1.
0 and source driver (signal driver; display driver)
20, a gate driver (scan driver; display driving device) 30, an LCD controller 40, a system control IC 50, and a digital-analog converter (hereinafter, referred to as a D / A converter) 60. Have been.

Hereinafter, each configuration will be described. As shown in FIG. 15, the liquid crystal display panel 10 has pixel electrodes arranged in a matrix, a common electrode (common electrode; common voltage Vcom) arranged opposite to the pixel electrodes, and a pixel electrode and a common electrode. Liquid crystal capacitance C consisting of liquid crystal filled between
lc, a thin film transistor (hereinafter referred to as “pixel transistor”) TFT having a source connected to the pixel electrode, and a plurality of pixel transistors TF extending in the row direction of the matrix.
A scanning line Lg connected to the gate of the transistor T, and a signal line Ld extending in the column direction of the matrix and connected to the drains of the plurality of pixel transistors TFT. Driver 3
By applying a signal voltage to the pixel electrode selected by 0, the arrangement of the liquid crystal is controlled to display and output predetermined image information. Here, Cs is a storage capacitance, and the liquid crystal capacitance Clc, the storage capacitance Cs, and the pixel transistor TFT are:
The liquid crystal pixels (display pixels) 11 are configured.

The source driver 20 supplies signal voltages corresponding to the image signals R, G, and B to each pixel electrode via a signal line Ld based on a horizontal control signal supplied from an LCD controller 50 described later. Here, as shown in FIG.
A sample and hold circuit 22 to which a B image signal is input;
And a shift register 21 for controlling the sample and hold operation of the sample and hold circuit 22. The sample and hold control signal output from the shift register 21 after being shifted in a certain direction is output to the sample and hold circuit 2.
2 are sequentially applied, so that the applied R, G, B
A signal voltage corresponding to the image signal is transmitted to each signal line Ld of the liquid crystal display panel 10.

On the other hand, based on the vertical control signal supplied from the LCD controller 40, the gate driver 30
A scanning signal is sequentially applied to each scanning line Lg to be in a selected state, and the source driver 20 is applied to a pixel electrode (display pixel) arranged at a position crossing the signal line Ld.
, Line sequential driving for applying (writing) the signal voltage supplied to the signal line Ld is performed. Here, as shown in FIG. 15, the gate driver 30 is generally configured to include a shift register 31 and a buffer 32, and a control signal shifted and output in a certain direction by the shift register 31 is supplied to the gate driver 30. 32, a predetermined gate signal is applied to each scanning line Lg of the liquid crystal display panel 10 to drive and control each pixel transistor TFT, and the source driver 20 applies a signal voltage applied to each signal line Ld. Is applied to each pixel electrode via the pixel transistor TFT.

The LCD controller 40 generates a horizontal control signal and a vertical control signal based on the horizontal synchronizing signal HD, the vertical synchronizing signal VD and the system clock SYSCK supplied from the system control IC 50, and sends them to the data driver 20 and the gate driver 30. By supplying each, a signal voltage is applied to the pixel electrode at a predetermined timing, and control is performed to display desired image information on the liquid crystal display panel 10.

The system control IC 50 supplies the system clock SYSCK to the signal driver 20, the LCD controller 40, the D / A converter 60 and the like, and outputs the horizontal synchronizing signal HD and the vertical synchronizing signal VD synchronized with the system clock SYSCK to the LCD. Controller 4
Supply 0. In addition, the video signal composed of the digital RGB signals is output to the signal driver 20 via the D / A converter 60 as analog RGB signals (image signals R, G, B).

That is, the LCD controller 40 and the system control IC 50 are connected to a liquid crystal display panel 10 via an interface (not shown) based on a video signal supplied from the outside to display desired image information. And generates a control signal for the signal driver 2
0 and a drive control signal generator for outputting to the scanning driver 30.

In the liquid crystal display device having the above configuration, the shift register 21 provided in the source driver 20 and the shift register 31 provided in the gate driver 30 are the shift register according to the first embodiment of the present invention. The circuit (FIG. 1) can be satisfactorily applied, and based on the pulse signals CK1 and CK2 (and the input control signals φ1 and φ2) having a predetermined cycle, sequentially from the above-described signal holding blocks (FIG. 2). The output signal output can be used as the sample-hold control signal or the control signal output to the buffer 32.

Here, in the shift registers 21 and 31, a shift operation (first signal output operation) and an integrated voltage adjustment operation (second shift operation) equivalent to the shift register circuit according to the present invention are performed.
Control signals (input control signals φ1, φ2 and output control signal SE) for selectively executing
T) can be configured to be generated and output by the LCD controller 40, for example. Also, LC
Only the output control signal SET is generated and output by the D controller 40, and the pulse signal CK is generated by a configuration not shown in the source driver 20 and the gate driver 30.
1, the input control signals φ1 and φ2 synchronized with CK2 may be generated.

According to the application of the shift register circuit according to the present invention to a liquid crystal display device, the shift register 2
When the line-sequential driving is performed by performing the shift operation on the input control signals φ 1 and φ 2, the input control units (gate terminals of the MOS transistor T 11) of the signal holding blocks constituting the shift registers 21 and 31 perform the shift operation. Are repeatedly applied, and the operation characteristics of the input control unit (MOS transistor T1
Even if the threshold value (1 threshold characteristic) fluctuates, the input registers (31) of the respective signal holding blocks (31) are adjusted at arbitrary timings or at predetermined intervals by operating the shift registers (21, 31) to perform the integrated voltage adjustment operation. MOS transistor T1
1 gate terminal), an adjustment signal having a signal waveform for canceling or adjusting the bias of the polarity of the time integration value of the applied voltage can be applied simultaneously and collectively. It is possible to provide a liquid crystal display device in which a deterioration in characteristics is suppressed, a favorable shift operation is guaranteed, and a malfunction and deterioration in display characteristics are reduced.

<Second Application> Next, as another application example of the shift register circuit according to the present invention, a case where the shift register circuit according to the present invention is applied to an image reading device (or an imaging device) will be described. This will be specifically described with reference to the drawings. First, a double-gate photosensor will be described as an example of an optimal reading pixel (photosensor) applied to the image reading apparatus according to the application example.

FIG. 16 is a sectional structural view showing a schematic structure of a double gate type photo sensor. As shown in FIG. 16A, the double-gate photosensor 110 has a semiconductor layer (channel layer) of amorphous silicon or the like in which electron-hole pairs are generated when excitation light (for example, visible light) is incident. 111, impurity layers 117 and 118 made of n + silicon provided at both ends of the semiconductor layer 111,
Drain electrode 112 and source electrode 113 opaque to visible light selected from chromium, chromium alloy, aluminum, aluminum alloy, etc. formed on impurity layers 117 and 118
And a transparent conductive film such as ITO formed above the semiconductor layer 111 (above the drawing) with the block insulating film 114 and the upper (top) gate insulating film 115 interposed therebetween, and the top is transparent to visible light. Visible light of chromium, chromium alloy, aluminum, aluminum alloy, or the like formed via a gate electrode (first gate electrode) 121 and a lower (bottom) gate insulating film 116 below (below the drawing) the semiconductor layer 111. Opaque bottom gate electrode (second gate electrode) 1
22. A plurality of double-gate photosensors 110 having such a configuration are formed in a matrix on a transparent insulating substrate 119 such as a glass substrate.

Here, in FIG. 16A, the top gate insulating film 115, the block insulating film 114, the bottom gate insulating film 116, and the protective insulating film 120 provided on the top gate electrode 121 all have the semiconductor layer 111. It is made of a material having a high transmittance to the exciting visible light, for example, silicon nitride or the like, and has a structure for detecting only light incident from above in the drawing. In addition, such a double gate type photo sensor 110 generally has
It is represented by an equivalent circuit as shown in FIG. Here, TG is a top gate terminal, BG is a bottom gate terminal, S is a source terminal, and D is a drain terminal.

Next, a drive control method of the above-described double gate type photo sensor will be described with reference to the drawings. FIG. 17 is a timing chart illustrating an example of a basic drive control operation of the double-gate photosensor,
FIG. 18 is a conceptual diagram illustrating the operation of the double-gate photosensor, and FIG. 19 is a diagram illustrating the optical response characteristics of the output voltage of the double-gate photosensor. Here, description will be made with reference to the configuration of the above-described double-gate photosensor (FIG. 16) as appropriate.

First, in the reset operation (initialization operation, initialization step), as shown in FIGS. 17 and 18 (a), a pulse voltage (hereinafter, referred to as “P”) is applied to the top gate terminal TG of the double gate type photo sensor 110. Reset pulse is applied; for example, Vtg = high level of +15 V) φT is applied to the semiconductor layer 111 and the block insulating film 114.
In this case, carriers (here, holes) accumulated near the interface with the semiconductor layer 111 are released (reset period Trst).

Next, in the light accumulation operation, FIG.
As shown in FIG. 18B, a low-level (for example, Vtg = −15 V) bias voltage φ is applied to the top gate terminal TG.
By applying T, the reset operation ends, and a light accumulation period (charge accumulation operation) Ts by the carrier accumulation operation starts. In the light accumulation period Ts, the semiconductor layer 11 depends on the amount of light incident from the top gate electrode 121 side.
1, an electron-hole pair is generated in the effective incident area, that is, the carrier generation area, and holes are accumulated near the interface between the semiconductor layer 111 and the semiconductor layer 111 in the block insulating film 114, that is, around the channel region. Is done.

In the precharge operation, a predetermined voltage (precharge) is applied to the drain terminal D based on the precharge signal φpg in parallel with the light accumulation period Ts, as shown in FIGS. A voltage) Vpg is applied to cause the drain electrode 112 to hold a charge (precharge period Tprch).

Next, in the read operation, FIG.
7. As shown in FIG. 18D, the precharge period Tpr
After the passage of ch, a high-level (for example, Vbg = + 10 V) bias voltage (read selection signal; hereinafter, referred to as a “read pulse”) φB is applied to the bottom gate terminal BG, whereby the double-gate photosensor 110 is applied.
Is turned on (readout period Tread).

Here, in the reading period Tread,
Carriers (holes) accumulated in the channel region act in a direction to reduce Vtg (−15 V) applied to the top gate terminal TG having the opposite polarity, so that Vbg of the bottom gate terminal BG is reduced.
(+ 15V), an n-channel is formed, and the voltage (drain voltage) VD of the drain terminal D according to the drain current
18 and 19 (a) show a tendency to gradually decrease from the precharge voltage Vpg with the passage of time.

That is, when the light accumulation state in the light accumulation period Ts is dark and no carriers (holes) are accumulated in the channel region, as shown in FIG.
By applying a negative bias to the top gate terminal TG, the positive bias of the bottom gate terminal BG is canceled,
The double-gate photosensor 110 is turned off, and the drain voltage VD is maintained almost as it is regardless of the lapse of time, as shown in FIG.

On the other hand, when the light accumulation state is the bright state, as shown in FIG. 18D, carriers (holes) corresponding to the amount of incident light are trapped in the channel region, so that the top gate terminal TG The double gate photosensor 110 is turned on by the positive bias of the bottom gate terminal BG by the amount of the negative bias.
State. Then, according to the ON resistance corresponding to the amount of incident light, the drain voltage VD gradually decreases over time, as shown in FIG.

Therefore, as shown in FIG. 19A, the change tendency of the drain voltage VD is such that the read pulse is applied to the bottom gate terminal BG from the end of the reset operation by application of the reset pulse φT to the top gate terminal TG. It is closely related to the amount of light received during the time until φB is applied (light accumulation period Ts), and shows a tendency to gradually decrease when the amount of accumulated carriers is small, and when the amount of accumulated carriers is large. Indicates a tendency to decrease sharply.
Therefore, by starting the readout period Tread and detecting the drain voltage VD after a lapse of a predetermined time,
Alternatively, the light amount of the irradiation light is converted by detecting the time required to reach the predetermined threshold voltage.

In the timing chart shown in FIG. 17, after the lapse of precharge period Tprch, FIG.
As shown in (f) and (g), when a state where a low level (for example, Vbg = 0 V) is applied to the bottom gate terminal BG is continued, the double gate photosensor 110 is turned off.
The state is maintained, and as shown in FIG. 4B, the drain voltage VD holds the precharge voltage Vpg. Thus, depending on the state of application of the voltage to the bottom gate terminal BG,
A selection function for selecting the read state of the double gate photosensor 110 is realized.

Next, an image reading apparatus to which the shift register circuit according to the present invention is applied will be described with reference to the drawings. In the following application example, a configuration in which the above-described double-gate photosensor is applied as a read pixel is shown. However, a photosensor used in an image reading apparatus according to an application example of the present invention is a double-gate photosensor. The present invention is not limited to a photosensor, and can be similarly applied to a photosensor system using a photosensor having another configuration such as a photodiode or a thin film transistor (TFT).

FIG. 20 is a schematic configuration diagram showing the overall configuration of an image reading apparatus to which the shift register circuit according to the present invention is applied, and FIG. 21 shows the main configuration of the image reading apparatus according to this application example. FIG. As shown in FIG. 20, the image reading apparatus according to this application example is roughly divided into a photosensor array (image reading unit) 200, a top gate driver (reading drive) 210, and a bottom gate driver 22.
0 (read driving device), a drain driver 230, an analog-digital converter (hereinafter, referred to as an A / D converter) 240, a controller 250, and a storage unit 260.
And is configured. Here, the main configuration of the image reading apparatus including the photo sensor array 200, the top gate driver 210, the bottom gate driver 220, and the drain driver 230 is referred to as a “photo sensor system” for convenience.

Hereinafter, each configuration will be described. As shown in FIG. 21, the photosensor array 200 includes, for example, a plurality of double-gate photosensors 110 arranged on a transparent insulating substrate 119 in a matrix of n rows × m columns.
And a top gate line 201 and a bottom gate line 202 which extend by connecting the top gate terminal TG (top gate electrode 21) and the bottom gate terminal BG (bottom gate electrode 22) of each double gate type photo sensor 110 in the row direction. And each double gate type photo sensor 10
A drain line (data line) 203 having a drain terminal D (drain electrode 12) connected in the column direction and a source terminal S (source electrode 13) connected in the column direction and a source line (common) connected to the ground potential. ) 204 are provided.

The top gate driver 210 sequentially applies reset pulses φT1, φT2,... ΦTi,... ΦTn to the top gate terminal TG of the double-gate photosensor 110 via the top gate line 201. The bottom gate driver 220 is connected to the double gate type photo sensor 110 via the bottom gate line 202.
Read pulses φB1, φB to the bottom gate terminal BG
2,... ΦBn,. Here, the top gate driver 210 and the bottom gate driver 22
Reference numeral 0 generally includes a shift register and a buffer, similarly to the gate driver 30 in the above-described liquid crystal display device (FIG. 14).

The drain driver 230 is connected to the drain line 203, and is connected to the double gate type photo sensor 11
It comprises a column switch 231, a precharge switch 232, and an amplifier 233 for applying a precharge voltage Vpg to 0 and reading drain line voltages VD1, VD2, VD3,.

In FIG. 21, φtg and φbg are:
Reset pulses φT1, φT2,... ΦTi,.
φTn and readout pulses φB1, φB2,.
The control signal for generating i,... φBn, φpg is a precharge signal for controlling the timing of applying the precharge voltage Vpg. The A / D converter 240 converts the drain line voltage (analog signal) read by the drain driver 230 into image data composed of a digital signal.

The controller 250 outputs control signals φtg and φbg to the top gate driver 210 and the bottom gate driver 220, so that each of the top gate driver 210 and the bottom gate driver 220
A predetermined signal voltage (reset pulse φT) is applied to the top gate terminal TG and the bottom gate terminal BG of each of the double gate photo sensors 110 constituting the photo sensor array 200.
i, the reset operation for applying the read pulse φBi) and the read operation are controlled. By outputting the precharge signal φpg to the precharge switch 232,
Drain terminal D of each double gate type photo sensor 110
To control the operation of detecting the drain voltage VD corresponding to the amount of electric charge accumulated in each double-gate photosensor 110 corresponding to the image pattern of the object to be detected by applying the precharge voltage Vpg to the object (precharge operation). I do.

The output voltage Vout read by the drain driver 230 is supplied to the controller 250.
The signal is converted into a digital signal via the A / D converter 240 and input as image data. Controller 250
Is an external functional unit that performs predetermined image processing on this image data, writes and reads data to and from a storage unit 260 such as a RAM, and executes predetermined functional processing such as image data collation and processing. It also has a function as an interface to the 300.

In such a configuration, the top gate driver 210 sends the signal through the top gate line 201
By applying a predetermined voltage to the top gate terminal TG, a photo sensing function is realized, and a predetermined voltage is applied from the bottom gate driver 220 to the bottom gate terminal BG via the bottom gate line 202, and the drain line 203 is connected. The read function is realized by taking the drain voltage of the double-gate photosensor 10 into the column switch 231 and outputting it as the output voltage Vout.

In the image reading apparatus according to this application example, the shift registers provided in the top gate driver 210 and the bottom gate driver 220 as described above have the shift registers according to the first to fourth embodiments of the present invention. It has a configuration to which a register circuit is applied, and has pulse signals CK1 and CK2 (and an input control signal φ) having a predetermined cycle.
1, φ2), the output signals sequentially output from the signal holding blocks (FIG. 2, FIG. 7, FIG. 11, and FIG. 13) of the above-described shift register circuit (FIGS. 1 and 6) via a buffer. Are output to the top gate line 201 and the bottom gate line 202 to be used as signals (reset pulse φTi, read pulse φBi) for driving the photosensor system.

Here, in the shift registers provided in the top gate driver 210 and the bottom gate driver 220, the same shift operation as the shift register circuit according to the present invention (ie, image reading operation; first signal output operation), and An operation control signal (the pulse signal CK1 shown in the first to fourth embodiments of the present invention) for selectively executing the integrated voltage adjustment operation (the second signal output operation);
CK2, input control signals φ1, φ2 and output control signal SE
T, SETA, SETB) are, for example, the controller 2
50 to generate and output. Also, the output control signal S
Generates and outputs only ET, SETA and SETB, and outputs the top gate driver 210 and the bottom gate driver 22
The signal waveforms of the pulse signals CK1 and CK2 may be controlled to change within 0.

Next, an example of a drive control method of the image reading apparatus according to this application example will be described with reference to the drawings. In each operation described below, the signal waveform and application timing of the operation control signal are controlled by the controller 2 described above.
50, and the top gate driver 210
And the shift register provided in the bottom gate driver 220.

FIG. 22 is a timing chart showing an example of the drive control method of the above-described photo sensor system. FIG. 23 shows a top gate line and a bottom gate line in the image reading operation and the integrated voltage adjusting operation of the image reading device. FIG. 3 is a diagram showing a relationship between signal waveforms of signals applied to the multiplexing circuit. Here, a drive control method will be described with reference to the configurations of the above-described image reading apparatus and photosensor system (FIGS. 20 and 21) as appropriate.

(Image Reading Operation) In the image reading operation (first signal output operation) in this application example, as shown in FIG. 22, first, a reset pulse φT1 is applied from the top gate driver 210 to each of the top gate lines 201. , ΦT
2,... ΦTn are sequentially applied to start an initialization operation (reset period Trst) and initialize the double-gate photosensor 110 for each row.

Next, after the reset period Trst has elapsed, the reset pulses φT1, φT2,... ΦTn sequentially fall, and the initialization operation is completed. Thus, the light accumulation operation is started, and a predetermined light accumulation period Ts is set for each row. Charges (holes) are generated and accumulated in the channel region according to the amount of light incident from the top gate electrode side of the double gate type photosensor 10 described above. Here, as shown in FIG. 22, the precharge operation (precharge period Tprch) is performed by applying a precharge voltage Vpg to each of the drain lines 203 from the drain driver 230 in parallel during the light accumulation period Ts. Starting, a predetermined voltage based on the precharge voltage Vpg is held in the drain electrode of the double gate photosensor 110 for each column via the drain line 203.

Next, with respect to the double gate type photosensor 10 after the light accumulation period Ts and the precharge period Tprch have elapsed (the light accumulation operation and the precharge operation have been completed),
The read pulses φB1 and φB1 from the bottom gate driver 220 through the bottom gate line 202 for each row.
, .Phi.Bn are sequentially applied to start a read operation (read period Tread), and changes in drain voltages VD1, VD2, VD3,... VDm corresponding to electric charges accumulated in the double-gate photosensor 110 for each row. To the drain driver 230 via each drain line 203.
At the same time, and read out as an output voltage Vout composed of serial data or parallel data.

Each double gate type photo sensor 11
The method for detecting the amount of incident light at 0
.. VDm of the voltage V.sub.03 are detected by detecting a voltage value after a lapse of a predetermined time (read period Tread) from the start of the read operation, or by a predetermined threshold voltage. , The incident light amount is converted by detecting the time until the voltage value is reached.

(Integrated Voltage Adjustment Operation) Next, the integrated voltage adjustment operation (second signal output operation) in this application example is performed by the controller 250 during the above-mentioned image reading operation period Tv during the above-described image reading operation period Tv. The applied reset pulse φTi (φT1, φT2,.
n) and a time integration value of a read pulse φBi (φB1, φB2,... φBn) applied to each bottom gate line 202, and an adjustment signal having a signal waveform for canceling or adjusting the positive / negative bias. The operation control signals for setting (the pulse signals CK1, CK2, the input control signals φ1, φ2, and the output control signals SET, SETA, SETB shown in the first to fourth embodiments of the present invention) are transmitted to the top gate driver 210. And bottom gate driver 220
Output to each shift register provided in.

More specifically, as shown in FIG.
When the reset pulse φTi is applied to the top gate line 201 during the reset period Trst during the image reading operation period Tv, the average value Vte of the time integration value in the top gate line 201 is determined by setting the high level of the reset pulse φTi to the positive voltage VtgH, Assuming that the level is the negative voltage VtgL, the following expression is obtained based on the above expression (1). Vte = {VtgH × Trst + VtgL × (Tv−Trst)} / Tv (3) Here, since Tv≫Trst and VtgL is a negative voltage, a time integration value during the image reading operation period is obtained. Alternatively, the average value Vte is largely biased toward the negative voltage side.

Further, as shown in FIG. 23B, when the read pulse φBi is applied to the bottom gate line 202 during the image reading operation period Tv during the reading period Tread,
The average value Vbe of the time integration value in the bottom gate line 202 is determined by setting the high level of the read pulse φBi to the positive voltage Vbe.
Assuming that bgH and the low level are the negative voltage VbgL, the following expression is obtained based on the above expression (1). Vbe = {VbgH × Tread + VbgL × (Tv−Tread)} / Tv (4) Here, since Tv≫Tread and VbgL is a negative voltage, a time integration value during an image reading operation period is obtained. Alternatively, the average value Vbe is largely biased toward the negative voltage side, similarly to the case of the reset pulse φTi.

Therefore, the state in which the reset pulse φTi and the read pulse φBi biased to a specific polarity are applied to the top gate terminal TG and the bottom gate terminal BG of each double gate type photosensor is continued. As in the case of the technique (FIG. 26), the transistor characteristics may be deteriorated, and the light receiving sensitivity of the double-gate photosensor may be deteriorated or malfunction may occur.

Therefore, in this application example, the operation control signal ADT for controlling the operation state of the top gate driver 210 is output from the controller 250, and the polarity of the time integration value during the image reading operation period or the average value Vte thereof is obtained. The first gate voltage adjustment operation (first integrated voltage adjustment operation) in which an adjustment signal having a signal waveform (signal level and signal width) represented by the following equation is applied to each top gate line 201 at the same time, Execute. {VtgH × Trst + VtgL × (Tv−Trst)} + VtgH × Twte = 0 .. (5)

Similarly, an operation control signal ADB for controlling the operation state of the bottom gate driver 220 is output from the controller 250, and the time integration value during the image reading operation period or the bias of the polarity of the average value Vbe thereof is adjusted. On the other hand, a bottom gate voltage adjustment operation (second integrated voltage adjustment operation) of simultaneously applying an adjustment signal having a signal waveform (signal level and signal width) as shown in the following equation to each bottom gate line 202 is executed. {VbgH × Tread + VbgL × (Tv−Tread)} + VbgH × Twbe = 0 (6)

Here, the reset pulse φTi and the read pulse φBi are used as signal levels of the adjustment signal.
The case where the signal levels (high levels VtgH, VbgH) used in the above are applied as they are is shown. By setting such signal levels, there is no need to change the configuration of the power supply circuit that sets the signal levels of the reset pulse φTi and the read pulse φBi, and the signal width Twt of the adjustment signal
By using a simple method of controlling only e and Twbe, it is possible to set an adjustment signal that satisfies or approaches the relations of the above equations (5) and (6).

According to such an integrated voltage adjusting operation, the reset pulse φTi and the read pulse φB applied to the double gate type photosensor 110 by the image reading operation.
By applying an adjustment signal having a predetermined signal waveform (signal level and signal width) to the bias of the polarity of the time integration value of i, the bias of the polarity of the time integration value can be canceled or adjusted. Therefore, it is possible to provide a highly reliable image reading apparatus in which the deterioration of the light receiving sensitivity of the double-gate photosensor and the occurrence of a malfunction are suppressed, and the deterioration and the malfunction of the reading sensitivity are suppressed.

Further, by the top gate voltage adjusting operation and the bottom gate voltage adjusting operation, the adjustment signal is simultaneously applied to a plurality of top gate lines or a plurality of bottom gate lines at a predetermined timing and simultaneously. ,
Since the bias of the polarity of the time integration value can be offset or adjusted, deterioration of the element characteristics of the double-gate photosensor can be corrected in a short time, and the image reading function of the image reading device can be favorably maintained. be able to.

In the application example described above, FIG.
As described above, the case where the top gate voltage adjustment operation and the bottom gate voltage adjustment operation are performed at different timings has been described. However, the present invention is not limited to this. Alternatively, they may be executed by overlapping each other.

In the above-described application example, the top gate voltage adjustment operation and the bottom gate voltage adjustment operation are
Although the drive control method executed immediately after the image reading operation has been described, the present invention is not limited to this, and may be executed immediately before the image reading operation, or may be performed at predetermined time intervals. It may be executed. In short, it is only necessary that the deterioration of the element characteristics of the double-gate photosensor is corrected during the image reading operation.

[0230]

According to the present invention, in a shift register circuit provided with a plurality of signal holding means connected in series,
The shift register circuit, via the plurality of signal holding means, the input signal input to the signal holding means of the first stage, while sequentially shifting to the signal holding means of the subsequent stage, the signal holding means of the signal holding means A first signal output operation for sequentially outputting a first output signal from each of the plurality of signal holding units, and a predetermined output control signal is input, so that each of the plurality of signal holding units is output by the first signal output operation. A second signal output operation of simultaneously outputting a second output signal having a predetermined signal level and a signal width for adjusting the bias of the polarity of the time integrated value of the signal level of the first output signal. It is characterized in that it is selectively executed. Here, the second
Is set to have a predetermined signal level and a predetermined signal width for adjusting the bias of the polarity of the time integrated value of the signal level of the first output signal output by the first signal output operation. Have been.

That is, in the first signal output operation, a first output signal (shift signal) having a predetermined signal level is sequentially output from the signal holding means of each stage, and a normal shift operation is realized. . On the other hand, in the second signal output operation, the input of the output control signal is used as a trigger to output a second output signal (adjustment signal) having a predetermined signal waveform (signal level and signal width) from the signal holding means of each stage. ) Are simultaneously output, and an integrated voltage adjustment operation for adjusting the bias of the polarity of the time integration value of the first output signal in the first signal output operation is performed.

By selectively and repeatedly executing such first and second signal output operations, in the shift operation (first signal output operation), the field effect transistors constituting the signal holding means of each stage are used. Even if the threshold characteristics of the field-effect transistor fluctuate due to the application of the gate signal (first output signal) having biased positive and negative polarities to the gate electrode, the integrated voltage adjustment is performed. Operation (second
In the signal output operation, the adjustment signal (second output signal) having a predetermined signal waveform is simultaneously applied to the gate electrodes of the field-effect transistors of the signal holding means in each stage. Of the time integrated value of the signal level (or the time average value of the integrated voltage) to the positive or negative polarity can be offset or adjusted, and the shift register caused by the fluctuation of the threshold characteristic of the field effect transistor Suppress circuit malfunction and deterioration of operating characteristics,
A highly reliable shift register circuit can be provided.

When the shift register circuit having such a configuration is applied to a reading driving device of an image reading device using a photosensor having a field effect transistor structure as image reading means, the first and second shift registers can be used. By selectively and repeatedly executing the signal output operation, in the image reading operation (first signal output operation), when scanning each photosensor, a scanning signal (first signal) having a biased positive and negative polarity is applied to each photosensor. Output signal) is applied, even if the element characteristics of the photosensor fluctuate,
In the integrated voltage adjustment operation (second signal output operation), an adjustment signal (second output signal) having a predetermined signal waveform is
Since the voltage is applied to each photosensor at the same time, it is possible to offset or adjust the bias of the signal integration time level of the scanning signal (or the time average value of the integration voltage) to the positive or negative polarity in the image reading operation. In addition, it is possible to provide a highly reliable image reading device by suppressing a malfunction and a deterioration in reading sensitivity of the image reading device due to a change in the element characteristics of the photosensor.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram showing a first embodiment of a shift register circuit according to the present invention.

FIG. 2 is a circuit configuration diagram showing a specific configuration of a signal holding block applied to the shift register circuit according to the first embodiment.

FIG. 3 is a timing chart illustrating changes in potentials of terminals and contacts of a signal holding block applied to the first embodiment.

FIG. 4 is a timing chart illustrating an operation of the shift register circuit according to the first embodiment.

FIG. 5 is a diagram illustrating a relationship between signal waveforms of output signals in a shift operation and an integrated voltage adjustment operation of the shift register circuit according to the first embodiment.

FIG. 6 is a schematic configuration diagram showing a second embodiment of the shift register circuit according to the present invention.

FIG. 7 is a circuit configuration diagram showing a specific configuration of a signal holding block applied to a shift register circuit according to a second embodiment.

FIG. 8 is a timing chart showing changes in potentials of terminals and contacts of a signal holding block applied to the second embodiment.

FIG. 9 is a timing chart illustrating the operation of the shift register circuit according to the second embodiment.

FIG. 10 is a timing chart showing a detailed voltage change in an integrated voltage adjustment operation of the shift register circuit according to the second embodiment.

FIG. 11 is a circuit configuration diagram showing a specific configuration of a signal holding block applied to a third embodiment of the shift register circuit according to the present invention.

FIG. 12 is a timing chart illustrating an operation of the shift register circuit according to the third embodiment.

FIG. 13 is a circuit configuration diagram showing a specific configuration of a signal holding block applied to a fourth embodiment of the shift register circuit according to the present invention.

FIG. 14 is a schematic configuration diagram illustrating an overall configuration of a liquid crystal display device (first application example) to which the shift register circuit according to the present invention is applied;

FIG. 15 is a detailed diagram illustrating a main configuration of a liquid crystal display device according to a first application example.

FIG. 16 is a sectional structural view showing a schematic configuration of a double-gate photosensor.

FIG. 17 is a timing chart illustrating an example of a basic drive control operation of a double-gate photosensor.

FIG. 18 is a conceptual diagram illustrating an operation of a double gate photosensor.

FIG. 19 is a diagram showing a light response characteristic of an output voltage of a double-gate photosensor.

FIG. 20 is a schematic configuration diagram illustrating an overall configuration of an image reading device (second application example) to which the shift register circuit according to the present invention is applied;

FIG. 21 is a detailed diagram illustrating a main configuration of an image reading apparatus according to a second application example.

FIG. 22 is a timing chart illustrating an example of a drive control method of the photosensor system.

FIG. 23 is a diagram illustrating a relationship between signal waveforms of signals applied to a top gate line and a bottom gate line in an image reading operation and an integrated voltage adjusting operation of the image reading device according to the second application example.

FIG. 24 is a schematic configuration diagram showing a shift register circuit according to a conventional technique.

FIG. 25 is a timing chart showing the operation of the shift register circuit according to the related art.

FIG. 26 shows gate voltage in a field effect transistor.
FIG. 9 is a diagram showing a fluctuation tendency of a drain current characteristic (threshold characteristic).

FIG. 27 is a diagram illustrating a voltage waveform of a pulse applied to a photosensor and a deviation of a time average value of an integrated voltage.

[Explanation of symbols]

RSA k-1 to RSA k + 2 , RSB k-1 to RSB
k + 2 signal holding block T11 to T16, T21 to T27, T31 to T38, T
41 to T48 MOS transistors OT k-1 to OT k + 2 output signal CK1, CK2 pulse signal φ1, φ2 pulse signal SET, SETA, SETB output control signal NA, NC, NE, NG contact NB, ND, NF, NH connection contact Nout output Contact 10 Liquid crystal display panel 20 Source driver 30 Gate driver 21, 31 Shift register 40 LCD controller 110 Double gate photo sensor 200 Photo sensor array 210 Top gate driver 220 Bottom gate driver 230 Drain driver 250 Controller

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H04N 5/335 H04N 5/335 ZE 5/66 102 5/66 102B F-term (Reference) 5C006 AF51 AF52 AF82 BB11 BC03 BC12 BF02 BF03 BF11 BF25 BF31 FA21 5C024 CX00 GX02 GX03 HX02 5C058 AA08 BA35 5C080 AA10 BB05 DD09 JJ02 JJ03 JJ04 JJ05

Claims (24)

[Claims]
1. A shift register circuit comprising a plurality of signal holding units connected in series, wherein the shift register circuit includes an input input to the first stage signal holding unit via the plurality of signal holding units. A first signal output operation of sequentially outputting a first output signal from each of the signal holding units while sequentially shifting a signal to the signal holding unit of a subsequent stage; and inputting a predetermined output control signal. Thus, the predetermined signal level for adjusting the bias of the polarity of the time integrated value of the signal level of the first output signal output by the first signal output operation from each of the plurality of signal holding units. And a second signal output operation of simultaneously outputting a second output signal having a signal width.
2. Each of the plurality of signal holding units fetches the input signal at a first signal timing and holds a signal level based on the input signal, based on the held signal level. An output control unit that outputs the first or second output signal having a predetermined signal level; and a discharge control unit that discharges the held signal level at a second signal timing. The shift register circuit according to claim 1, wherein:
3. The signal holding means according to claim 1, wherein the input signal is taken in at the time of the first signal output operation based on an application timing of an input control signal applied to the input control unit. Item 3. The shift register circuit according to Item 2.
4. The signal holding means according to claim 1, wherein said signal holding means fetches said input signal based on an input timing of said input signal input to said input control section during said first signal output operation. Item 3. The shift register circuit according to Item 2.
5. The signal holding means supplies a first voltage signal periodically having a predetermined high signal level and a second voltage signal whose signal level can be changed at least to the output control unit. Outputting the first output signal having a signal level based on the first voltage signal during the first signal output operation; and outputting the second voltage signal during the second signal output operation. 4. The shift register circuit according to claim 2, wherein the second output signal having an arbitrary signal level based on the second voltage signal is output by being input as the output control signal. 5.
6. The signal holding unit supplies at least a third voltage signal whose signal width can be changed and a second voltage signal whose signal level can be changed to the output control unit, A first signal outputting the second output signal based on the second voltage signal by inputting the second voltage signal as the output control signal during a second signal output operation;
And the second voltage signal based on the third voltage signal.
5. The shift register according to claim 2, wherein the shift register outputs the second output signal having an arbitrary signal level and a signal width by switching between a second output state and a second output state for outputting the output signal. circuit.
7. The signal processing method according to claim 5, wherein the second voltage signal supplied to the output control unit has a predetermined low signal level during the first signal output operation. Or the shift register circuit according to 6.
8. The signal holding unit is configured to supply at least a third voltage signal whose signal width can be changed and a fourth voltage signal having a predetermined low signal level to the output control unit, In the first signal output operation, the first output signal having a first signal width based on the third voltage signal is output. In the second signal output operation, the first output signal is output to the third voltage signal. The shift register circuit according to claim 2, wherein the second output signal having a second signal width based on the second output signal is output.
9. The method according to claim 1, wherein, during the first signal output operation, the first signal is output.
Or the third voltage signal is supplied in a first cycle to the odd-numbered signal holding means of the signal holding means, and is supplied to the even-numbered signal holding means. ,
9. The shift register circuit according to claim 5, wherein the shift register circuit is supplied in a second cycle having an inversion relationship with the first cycle.
10. In each of the plurality of signal holding units, the input control unit turns on at the first signal timing to which the input control signal is applied, and takes in the input signal to a voltage holding contact side. A first transistor, wherein the output control section is turned on based on a signal level of the input signal taken into the voltage holding contact side, and has a predetermined high signal level via a predetermined load. A second transistor for discharging a signal level supplied from the voltage signal of No. 5, and an ON operation based on the signal level of the input signal taken into the voltage holding contact side, and based on the first voltage signal A third transistor that outputs the first output signal; and a high voltage supplied from the fifth voltage signal via the load when the second transistor is turned off. A fourth transistor that is turned on based on a signal level and outputs a first or a second output signal based on the second voltage signal, wherein the discharge control unit includes: 6. A fifth transistor, which is turned on based on the signal level of the first or second output signal output from the means, and discharges the signal level on the voltage holding contact side. 10. The shift register circuit according to claim 7, wherein:
11. In each of the plurality of signal holding units, the input control unit turns on at the first signal timing to which the input signal is applied, and takes in the input signal to a voltage holding contact side. A fifth transistor having a predetermined high signal level via a predetermined load, the transistor being turned on based on a signal level of the input signal taken into the voltage holding contact side. A second transistor that discharges a signal level supplied from the voltage signal of the above, and turns on based on the signal level of the input signal that is taken into the voltage holding contact side, and based on the third voltage signal, A third transistor that outputs a first or second output signal; and a third transistor that is supplied from the fifth voltage signal via the load when the second transistor is turned off. A fourth transistor that is turned on based on a high signal level and outputs a first or a second output signal based on the second voltage signal; A fifth transistor that is turned on based on the signal level of the first or second output signal output from the holding unit and that can discharge the signal level on the voltage holding contact side; And a sixth transistor that is connected in series and that is turned on based on at least a sixth voltage signal whose signal level can be changed, and that discharges the signal level on the voltage holding contact side. The shift register circuit according to claim 6.
12. In each of the plurality of signal holding units, the input control unit turns on at the first signal timing to which the input signal is applied, and takes in the input signal to a voltage holding contact side. The output control unit is turned on based on the signal level of the voltage holding contact side, and is supplied from a fifth voltage signal having a predetermined high signal level via a predetermined load. A second transistor that discharges a signal level; a third transistor that turns on based on the signal level on the voltage holding contact side and outputs the first or second output signal based on the third voltage signal A transistor, when the second transistor is turned off, turns on based on a high signal level supplied from the fifth voltage signal via the load, and the fourth voltage signal A fourth transistor that outputs a first output signal based on the signal, a turn-on operation based on a signal level of the second voltage signal, and a high signal level that is based on the fifth voltage signal. And a seventh transistor that supplies a signal to the first side or the second side. A fifth transistor capable of discharging a signal level on a voltage holding contact side, and a fifth transistor connected in series with the fifth transistor, and turned on based on at least a sixth voltage signal capable of changing a signal level; 10. The shift register circuit according to claim 8, further comprising: a sixth transistor that discharges a signal level on a voltage holding contact side.
13. In each of the plurality of signal holding units, the input control unit turns on at the first signal timing to which the input signal is applied, and takes in the input signal to a voltage holding contact side. The output control unit is turned on based on the signal level of the voltage holding contact side, and is supplied from a fifth voltage signal having a predetermined high signal level via a predetermined load. A second transistor that discharges a signal level; a third transistor that turns on based on the signal level on the voltage holding contact side and outputs the first or second output signal based on the third voltage signal A transistor, when the second transistor is turned off, turns on based on a high signal level supplied from the fifth voltage signal via the load, and the fourth voltage signal A fourth transistor that outputs a first output signal based on the signal, a turn-on operation based on a signal level of the second voltage signal, and a signal level based on the second voltage signal, the voltage holding contact side An eighth transistor for supplying the voltage to the first and second output signals output from the signal holding unit in the next stage. A fifth transistor capable of discharging a signal level on a holding contact side, and a fifth transistor connected in series with the fifth transistor, and turned on based on at least a sixth voltage signal capable of changing a signal level; 10. The shift register circuit according to claim 8, further comprising: a sixth transistor that discharges a signal level on the holding contact side.
14. The shift register circuit according to claim 11, wherein the sixth voltage signal is set to have an inversion relationship with the second voltage signal.
15. The shift register circuit according to claim 10, wherein said transistors constituting said signal holding means are the same channel type field effect transistors.
16. A drive control method for a shift register circuit including a plurality of signal holding units connected in series, the input signal being input to the first stage signal holding unit via the plurality of signal holding units. A first signal output step of sequentially outputting a first output signal from each of the signal holding means while sequentially shifting to the signal holding means in the next and subsequent stages; and by inputting a predetermined output control signal. And a second signal output step of simultaneously outputting a second output signal from each of the plurality of signal holding means in a predetermined order.
17. The second output signal output during the second signal output step is a time integration value of a signal level of the first output signal output by the first signal output step. 17. The drive control method for a shift register circuit according to claim 16, wherein the shift register circuit is set to have a predetermined signal level and a predetermined signal width for adjusting the bias of the polarity of the shift register circuit.
18. A display drive device comprising a shift register circuit for sequentially outputting a drive signal for displaying a desired image to a display means in which a plurality of display pixels are arranged in a matrix, wherein the shift register circuit is A plurality of signal holding units connected in series, and, via the plurality of signal holding units, sequentially shift an input signal input to the signal holding unit of the first stage to the signal holding unit of a subsequent stage. A first signal output operation for sequentially outputting a first output signal from each of the signal holding units to select the display pixels for each row of the matrix, and inputting a predetermined output control signal. By doing so, a second output signal is simultaneously output from each of the plurality of signal holding units, and the second output signal is collectively input to each of the plurality of signal holding units as the input signal. And a signal output operation of the display driving device.
19. The second output signal is a predetermined signal level for adjusting a bias of a polarity of a time integration value of a signal level of the first output signal output by the first signal output operation. 19. The display driving device according to claim 18, wherein the display driving device has a signal width and a signal width.
20. Each of the plurality of signal holding units constituting the shift register circuit, receives the input signal at a first signal timing, and holds an input signal based on the input signal; An output controller that outputs the first or second output signal having a predetermined signal level based on the held signal level; and a discharge controller that discharges the held signal level at a second signal timing. 21. The display driving device according to claim 18, further comprising:
21. A read driving device comprising a shift register circuit for sequentially outputting a drive signal for reading a desired image to image reading means in which a plurality of read pixels are arranged in a matrix, for each row of the matrix. In the above, the shift register circuit includes a plurality of signal holding units connected in series, via the plurality of signal holding units, an input signal input to the first stage of the signal holding unit, sequentially to a next stage and subsequent stages. A first signal output operation for sequentially outputting a first output signal from each of the signal holding units while shifting to the signal holding unit, and setting the read pixels for each row of the matrix to a selected state; By inputting a predetermined output control signal, a second output signal is simultaneously output from each of the plurality of signal holding units, and the readout pixels for each row of the matrix are collectively output. And a second signal output operation of selectively applying the read drive signal.
22. The second output signal, wherein the first signal output operation adjusts a bias of a polarity of a time integrated value of a signal level applied to the read pixel for each row of the matrix by the first signal output operation. 22. The read driving device according to claim 21, having a signal level and a signal width.
23. Each of the plurality of signal holding units constituting the shift register circuit, the input control unit fetching the input signal at a first signal timing, and holding a signal level based on the input signal; An output controller that outputs the first or second output signal having a predetermined signal level based on the held signal level; and a discharge controller that discharges the held signal level at a second signal timing. 23. The reading drive device according to claim 21, further comprising:
24. Each of the read pixels constituting the image reading means includes: a semiconductor layer that generates carriers by excitation light; a source electrode and a drain electrode formed with a channel region including the semiconductor layer interposed therebetween; A first gate electrode formed above the channel region via a first gate insulating film; and a second gate electrode provided below the channel region via a second gate insulating film. The read driving device is configured to output a reset pulse based on the first output signal output by the first signal output operation of the shift register circuit to a first gate electrode of the read pixel for each row of the matrix. And an initializing operation for initializing the read pixel by sequentially applying the first and second readouts to the first and second readouts based on the first output signal output by the first signal output operation. A pulse is sequentially applied to the second gate electrode of the read pixel for each row of the matrix, and is accumulated in the channel region during a charge accumulation period from the end of the initialization to the application of the read pulse. A voltage readout operation for outputting a voltage corresponding to the stored electric charge; and a first adjustment signal based on the second output signal output by the second signal output operation by the shift register circuit. The bias is applied simultaneously to the first gate electrodes of all of the read pixels that constitute the pixel at the same time, and the polarity of the time integral of the signal level applied to the first gate electrode is biased by the initialization operation. A second integrated signal based on the second output signal output by the first integrated voltage adjusting operation for adjusting the second output signal and the second signal output operation by the shift register circuit. And simultaneously applying the voltage to the second gate electrodes of all of the read pixels constituting the image reading means at the same time and applying the voltage read operation to the signal level applied to the second gate electrodes. 24. The reading drive device according to claim 21, wherein the second integrated voltage adjusting operation for adjusting the bias of the polarity of the integrated value is performed in a predetermined order.
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