CN215220225U

CN215220225U - Display panel and display device

Info

Publication number: CN215220225U
Application number: CN202120722553.3U
Authority: CN
Inventors: 廖燕平; 缪应蒙; 李承珉; 邵喜斌; 姚树林; 张银龙; 苏秋杰; 王聪; 陈东川; 刘建涛
Original assignee: BOE Technology Group Co Ltd; Beijing BOE Display Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Beijing BOE Display Technology Co Ltd
Priority date: 2021-04-09
Filing date: 2021-04-09
Publication date: 2021-12-17
Anticipated expiration: 2031-04-09

Abstract

A display panel and a display device. The display panel comprises a grid driving circuit, wherein the grid driving circuit comprises sequentially arranged multi-stage shift registers which are combined into N groups of grid driving sub-circuits, and the shift registers in the N groups of grid driving sub-circuits are respectively cascaded; the m-th group of gate driving sub-circuits in the N groups of gate driving sub-circuits comprises an m-th stage shift register and an m + L-N stage shift register which are cascaded, wherein m is an integer which is greater than or equal to 1 and less than or equal to N, L is an integer which is greater than or equal to 1, and N is an even number which is greater than or equal to 2. The display panel can realize clear display of H-1Line pictures, has no serial problem, meets the test standard of industrial CM value, and improves the performance of display products.

Description

Display panel and display device

Technical Field

Embodiments of the present disclosure relate to a display panel and a display device.

Background

In the field of display technology, a pixel array, such as a liquid crystal display panel or an Organic Light Emitting Diode (OLED) display panel, generally includes a plurality of rows of gate scan signal lines and a plurality of columns of data lines interleaved with the gate scan signal lines. The driving of the gate scan signal lines may be implemented by a bonded integrated driving circuit. In recent years, with the continuous improvement of the manufacturing process of the amorphous silicon thin film transistor or the oxide thin film transistor, the gate scanning signal line driving circuit may be directly integrated On the thin film transistor array substrate to form a goa (gate driver On array) to drive the gate scanning signal line. For example, the GOA including a plurality of cascaded shift register units can be used to provide switching state voltage signals (scan signals) to a plurality of rows of gate scan signal lines of a pixel array, so as to control the plurality of rows of gate scan signal lines to be turned on sequentially, and simultaneously provide data signals to corresponding rows of pixel units in the pixel array from data lines, so as to form gray voltages required for displaying gray scales of an image in each pixel unit, thereby displaying a frame of image.

SUMMERY OF THE UTILITY MODEL

The display panel provided by at least one embodiment of the disclosure can realize clear display of H-1Line pictures, has no serial problem, meets the test standard of industry CM value, and improves the performance of display products.

At least one embodiment of the present disclosure provides a display panel including a gate driving circuit; the grid driving circuit comprises sequentially arranged multi-stage shift registers, the sequentially arranged multi-stage shift registers are combined into N groups of grid driving sub-circuits, and the shift registers in the N groups of grid driving sub-circuits are respectively cascaded; the m-th group of gate driving sub-circuits in the N groups of gate driving sub-circuits comprise an m-th stage shift register and an m + L N-th stage shift register which are cascaded, m is an integer which is greater than or equal to 1 and less than or equal to N, L is an integer which is greater than or equal to 1, and N is an even number which is greater than or equal to 2.

For example, the display panel provided by at least one embodiment of the present disclosure further includes N trigger signal lines respectively connected to the N groups of gate driving sub-circuits, and an mth trigger signal line of the N trigger signal lines is connected to an input terminal of the mth stage shift register.

For example, the display panel provided in at least one embodiment of the present disclosure further includes 4K clock signal lines, where the 4K clock signal lines include a first clock signal line to a 4K clock signal line, and are respectively connected to the clock signal terminals of the multi-stage shift register to provide clock signals, and K is an integer greater than or equal to 1.

For example, in a display panel provided in at least one embodiment of the present disclosure, when K is 1, the 4K clock signal lines include a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line, and the first clock signal line is connected to a clock signal terminal of a 4n-3 th stage shift register; the second clock signal line is connected with a clock signal end of the 4n-2 th-stage shift register; the third clock signal line is connected with a clock signal end of the 4n-1 th-stage shift register; the fourth clock signal line is connected with a clock signal end of the 4 nth stage shift register; n is an integer of 1 or more.

For example, in a display panel provided in at least one embodiment of the present disclosure, when K is 3, the 4K clock signal lines include a first clock signal line, a second clock signal line, a third clock signal line, a fourth clock signal line, a fifth clock signal line, a sixth clock signal line, a seventh clock signal line, an eighth clock signal line, a ninth clock signal line, a tenth clock signal line, an eleventh clock signal line, and a twelfth clock signal line, and the first clock signal line is connected to a clock signal terminal of a shift register of 12n-11 th stage; the second clock signal line is connected with a clock signal end of the 12n-10 th stage shift register; the third clock signal line is connected with a clock signal end of the 12n-9 th stage shift register; the fourth clock signal line is connected with a clock signal end of the 12n-8 th-stage shift register; the fifth clock signal line is connected with a clock signal end of the 12n-7 th stage shift register; the sixth clock signal line is connected with a clock signal end of the 12n-6 th stage shift register; the seventh clock signal line is connected with a clock signal end of the 12n-5 th stage shift register; the eighth clock signal line is connected with a clock signal end of the 12n-4 th-stage shift register; the ninth clock signal line is connected with a clock signal end of the 12n-3 th stage shift register; the tenth clock signal line is connected with a clock signal end of the 12n-2 th stage shift register; the eleventh clock signal line is connected with a clock signal end of the 12n-1 stage shift register; the twelfth clock signal line is connected with a clock signal end of the 12 nth stage shift register; n is an integer of 1 or more.

For example, in a display panel provided in at least one embodiment of the present disclosure, when N is 2, the N trigger signal lines include a first trigger signal line and a second trigger signal line, the first trigger signal line is connected to input terminals of the first K odd-numbered shift registers to provide a first trigger signal, and input terminals of the remaining odd-numbered shift registers are connected to output terminals of the upper-numbered shift registers that are spaced apart from the first odd-numbered shift registers by K-1 odd-numbered shift registers; the second trigger signal line is connected with the input ends of the first K even-level shift registers to provide a second trigger signal, and the input ends of the rest even-level shift registers are connected with the output ends of the superior shift registers which are separated from the rest even-level shift registers by K-1 even-level.

For example, at least one embodiment of the present disclosure provides a display panel, further including a clock controller connected to the 4K clock signal lines and configured to: when a clock signal is supplied to the clock signal lines connected to the odd-numbered groups of gate drive sub-circuits of the N groups of gate drive sub-circuits, the clock signal is not supplied to the clock signal lines connected to the even-numbered groups of gate drive sub-circuits of the N groups of gate drive sub-circuits or an invalid clock signal is supplied to the clock signal lines connected to the even-numbered groups of gate drive sub-circuits; when the clock signal is supplied to the clock signal line connected to the even-numbered group of gate drive sub-circuits, the clock signal is not supplied to the clock signal line connected to the odd-numbered group of gate drive sub-circuits or the invalid clock signal is supplied to the clock signal line connected to the odd-numbered group of gate drive sub-circuits.

For example, in the display panel provided in at least one embodiment of the present disclosure, a time difference between clock signals received by two adjacent clock signal lines connected to the odd-numbered gate driving sub-circuits is 2T, a time difference between clock signals received by two adjacent clock signal lines connected to the even-numbered gate driving sub-circuits is 2T, and T is a charging time of the sub-pixels in 1 row.

For example, in a display panel provided in at least one embodiment of the present disclosure, the clock controller is further connected to the N trigger signal lines, and configured to: when an effective trigger signal is provided for the trigger signal line connected with the odd-numbered group of gate drive sub-circuits, an invalid trigger signal is provided or the effective trigger signal is not provided for the trigger signal line connected with the even-numbered group of gate drive sub-circuits; and when the effective trigger signal is provided for the trigger signal line connected with the even group of gate drive sub-circuits, providing the invalid trigger signal or not providing the effective trigger signal for the trigger signal line connected with the odd group of gate drive sub-circuits.

For example, the display panel provided by at least one embodiment of the present disclosure further includes a pixel array connected to the gate driving circuit; the pixel array comprises a plurality of rows and a plurality of columns of sub-pixels; odd-numbered groups of grid driving sub-circuits in the N groups of grid driving sub-circuits are respectively connected with odd-numbered row sub-pixels, and even-numbered groups of grid driving sub-circuits in the N groups of grid driving sub-circuits are respectively connected with even-numbered row sub-pixels.

For example, the display panel provided by at least one embodiment of the present disclosure further includes a data driving circuit and a plurality of data lines; the data lines are electrically connected with the sub-pixels in the multiple columns and are configured to transmit data signals provided by the data driving circuit to the sub-pixels in the multiple columns; the data driving circuit is configured to: when the pixel array is driven to display the x frame picture, providing a data signal with a first level to the data lines; when the pixel array is driven to display the x +1 th frame picture, providing a data signal with a second level to the plurality of data lines; x is an integer of 1 or more.

For example, in a display panel provided in at least one embodiment of the present disclosure, the gate driving circuit is located at one side of the pixel array.

For example, in the display panel provided by at least one embodiment of the present disclosure, the gate driving circuits are located at two sides of the pixel array, and the shift registers located at the same stage in the gate driving circuits located at the two sides are used for driving the sub-pixels in the same row.

For example, in a display panel provided in at least one embodiment of the present disclosure, the sequentially arranged multiple shift registers include multiple redundant shift registers, and input terminals of N redundant shift registers of the multiple redundant shift registers are respectively connected to the N trigger signal lines to receive trigger signals.

At least one embodiment of the present disclosure further provides a display device including the display panel provided in any one of the embodiments of the present disclosure.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly described below, and it is apparent that the drawings in the following description only relate to some embodiments of the present invention and are not limiting on the present invention.

FIG. 1A is a timing diagram of an H-1 Line;

FIG. 1B is a schematic serial timing diagram of H-1 Line;

FIG. 1C is a schematic diagram of a display screen of H-1Line in an ideal state;

FIG. 1D is a schematic diagram of display screen serials of H-1Line in an actual state;

fig. 2 is a schematic diagram of a display panel according to at least one embodiment of the present disclosure;

fig. 3A is a schematic diagram of a gate driving circuit according to at least one embodiment of the present disclosure;

fig. 3B is a schematic diagram of another gate driving circuit according to at least one embodiment of the present disclosure;

fig. 4 is a schematic diagram of a display panel including 4CLK (K ═ 1) according to at least one embodiment of the present disclosure;

fig. 5 is a schematic diagram of a display panel including 8CLK (K-2) according to at least one embodiment of the present disclosure;

fig. 6A is a schematic diagram of a display panel including 12CLK (K-3) according to at least one embodiment of the present disclosure;

fig. 6B is a schematic diagram of a display panel including 16CLK (K-4) according to at least one embodiment of the present disclosure;

fig. 7A is a timing diagram corresponding to an xth frame display screen according to at least one embodiment of the present disclosure;

fig. 7B is a schematic diagram of an xth frame display according to at least one embodiment of the present disclosure;

fig. 8A is a timing diagram of an x +1 th frame of a display image according to at least one embodiment of the disclosure;

fig. 8B is a schematic diagram of an x +1 th frame display according to at least one embodiment of the present disclosure;

fig. 9A is a schematic diagram illustrating a position relationship of a gate driving circuit according to at least one embodiment of the present disclosure;

fig. 9B is a schematic diagram of a position relationship of another gate driving circuit provided in at least one embodiment of the present disclosure;

fig. 9C is a schematic view of a display image with a combination of bright and dark lines according to at least one embodiment of the present disclosure;

fig. 10 is a schematic view of a display device according to at least one embodiment of the present disclosure; and

fig. 11 is a flowchart of a driving method of a display panel according to at least one embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the drawings of the embodiments of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the invention without any inventive step, are within the scope of protection of the invention.

Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "coupled" or "connected," and the like, are not restricted to physical or mechanical couplings, but may include electrical couplings, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

The present disclosure is illustrated by the following specific examples. Detailed descriptions of known functions and known components may be omitted in order to keep the following description of the embodiments of the present invention clear and concise. When any element of an embodiment of the present invention appears in more than one drawing, that element is identified by the same reference numeral in each drawing.

The 8K resolution +5G communication has become a hot topic of current technological development, and each television manufacturer has a product with 8K resolution (hereinafter, referred to as "8K product") to come on the market, and each panel factory also responds to market demands quickly, and invests manpower quickly to research and develop. Products with 8K resolution, as high-end display products, require a higher refresh frequency in addition to requiring high pixels. Products with 8K resolution coupled with a refresh rate of 120 hertz (Hz) (hereinafter referred to as "8K, 120Hz products") have become standard for high-end display products. However, for 8K and 120Hz products, the charging time of the pixels in 1 row is only 1/120Hz/4500 rows-1.85 μ s (microseconds), so the delay of the gate scan signal and the delay of the data signal may greatly affect the charging time of the pixels. And according to the energy efficiency standard requirement of household appliances, the transmittance of 8K and 120Hz products is the same as that of products with the refresh frequency of 60Hz, so that the energy consumption requirement can be met. Therefore, the gate scan signal lines and the data lines of the 8K, 120Hz product cannot reduce the load by increasing the line width. Therefore, when displaying an H-1line picture (Pattern), the delay of the gate scan signal is large for 8K, 120Hz products, and the row of the data signal 1 is inverted once, which may cause the occurrence of the serial problem.

For the serial problem, the industry has universal test standards. For example, the test is performed by a CM (Contrast Modulation, abbreviated as a luminance Modulation ratio) value. The CM value refers to the brightness difference value of black and white lines between different phases on a display picture under H-1Line and V-1Line modes. For example, the customer can judge the performance of the display product according to the CM value of H-1Line or V-1Line, for example, the higher the CM value, i.e., the larger the difference in brightness of the black and white lines (as shown in FIG. 1C), the better the performance of the display product. For example, ICDM (International Committee for Display Metrology, International Display measurement Commission) requires that the CM for 8K products be greater than 50%.

For example, the CM value may be expressed by the following expression:

wherein Lw represents the light emission luminance of the white line; lk represents the light emission luminance of the black line.

For example, for 8K products, V-1Line does not have the serial problem, H-1Line has high and low jump of data signals due to the particularity of pictures, when the delay of grid scanning signals is large, the level of the grid scanning signals is not timely converted, so that data writing transistors in pixel circuits are not timely turned off, and the data signals are already inverted, so that the H-1Line is in serial.

FIG. 1A is a timing diagram of an H-1 Line; FIG. 1B is a schematic serial timing diagram of H-1 Line; FIG. 1C is a schematic diagram of a display screen of H-1Line in an ideal state; FIG. 1D is a schematic diagram of the display screen series of H-1Line in an actual state.

For example, the level settings in FIG. 1A are shown in the following table:

STV/Gn	H＝Vgh	L＝Vgl
			Datan	H＝Vdh	L＝Vdl≈VCOM

for example, as shown in fig. 1A and 1B, the level of the data signal Datan is inverted (e.g., from a high level to a low level) once per charged 1 row of subpixels. For example, when the data signal Datan corresponding to the current row of sub-pixels (e.g., the 1 st row R1) is at a high level, the data signal Datan corresponding to the next row of sub-pixels (e.g., the 2 nd row R2) is at a low level. After the current row sub-pixel Vpixel is charged by the current row data signal Datan (for example, high level H), since the falling edge delay of the gate scan signal Gn is large, the gate scan signal is still at an active level, so that the data writing transistor in the pixel circuit is not turned off, and the data signal (for example, low level L) of the next row sub-pixel is input to the current sub-pixel for charging, so that the current row sub-pixel Vpixel is charged with the data signal (low level L) of the next row data, therefore, the charging level of the current row sub-pixel Vpixel is shifted from an ideal state to an actual state, for example, from a dotted Line to a solid Line in fig. 1B, so as to generate a serial Line, so that the displayed picture of the display product is, for example, the picture of which the black Line is not enough black and the white Line is not enough white as shown in fig. 1D, but is not the displayed picture of H-1Line in the ideal state (for example, the black Line is only black as shown in fig. 1C, white lines show only white pictures), and therefore, H-1Line pictures produce serials. When the seriousness is serious, the H-1line picture is seen to be all lines bright.

At least one embodiment of the present disclosure provides a display panel, including a gate driving circuit, where the gate driving circuit includes sequentially arranged multiple shift registers, the sequentially arranged multiple shift registers are combined into N groups of gate driving sub-circuits, and the shift registers in the N groups of gate driving sub-circuits are respectively cascaded; the m-th group of gate driving sub-circuits in the N groups of gate driving sub-circuits comprises an m-th stage shift register and an m + L-N stage shift register which are cascaded, wherein m is an integer which is greater than or equal to 1 and less than or equal to N, L is an integer which is greater than or equal to 1, and N is an even number which is greater than or equal to 2.

The display panel of the embodiment of the disclosure enables the odd frames to display the odd lines in cooperation with the data signals and the even frames to display the even lines in cooperation with the data signals by detecting the H-1Line pictures of the display product, so that the clear display of the H-1Line pictures can be realized, the problem of serial connection is avoided, the test standard of industrial CM values is met, and the performance of the display product is improved.

Embodiments of the present disclosure and some examples thereof are described in detail below with reference to the accompanying drawings.

Fig. 2 is a schematic diagram of a display panel according to at least one embodiment of the present disclosure. For example, the display panel may be a display panel with a resolution of 8K and a refresh frequency of 120Hz, and may also be a display panel with other resolutions or refresh frequencies, which is not limited in this embodiment of the disclosure. For example, as shown in fig. 2, in some examples, the display panel 1 includes a gate driving circuit 10. For example, as shown in fig. 2, in other examples, the display panel 1 further includes a display area 40, the display area 40 includes a pixel array connected to the gate driving circuit 10, and the pixel array includes a plurality of rows and a plurality of columns of sub-pixels 410. For example, in other examples, the display panel 1 may further include a data driving circuit 30 and a plurality of data lines DL. The plurality of data lines DL are electrically connected to the plurality of columns of sub-pixels 410 and configured to transmit data signals provided by the data driving circuit 30 to the plurality of columns of sub-pixels 410.

For example, the data driving circuit 30 is used to supply data signals to the pixel array; the gate driving circuit 10 is used to provide gate scanning signals to the pixel array. The data driving circuit 30 is electrically connected to the sub-pixel 410 through the data line DL, and the gate driving circuit 10 is electrically connected to the sub-pixel 410 through the gate scanning signal line GL.

For example, the gate driving circuit is used to drive a display panel such as a liquid crystal display panel or an organic light emitting diode display panel, and sequentially provides scan signals to a plurality of gate scan signal lines of the display panel, so as to perform progressive or interlaced scanning while the display panel displays one frame of picture.

Fig. 3A is a schematic diagram of a gate driving circuit according to at least one embodiment of the present disclosure; fig. 3B is a schematic diagram of another gate driving circuit according to at least one embodiment of the disclosure. The gate driving circuit provided by the embodiment of the present disclosure is described in detail below with reference to fig. 3A and 3B.

For example, as shown in fig. 3A and 3B, the gate driving circuit 10 includes a plurality of shift registers arranged in series. For example, as shown in fig. 3A and 3B, the sequentially arranged multi-stage shift register includes a1 st stage shift register GOA1, a2 nd stage shift register GOA2, a3 rd stage shift register GOA3 … …, and the like, which are sequentially cascaded. For example, for a display panel with 8K resolution, the sequentially arranged multiple shift registers include a shift register GOA1 of level 1, a shift register GOA2 of level 2, shift registers GOA3, … … of level 3, a shift register of level 4320, a shift register of level 4322, a shift register of level 4324, or more shift registers, which are sequentially cascaded, and the embodiments of the present disclosure are not limited thereto.

It should be noted that, for clarity and simplicity of representation, fig. 3A only shows a shift register with 12 stages arranged sequentially, and fig. 3B only shows a shift register with 16 stages arranged sequentially, and of course, a plurality of shift register units cascaded sequentially may also be included. The number of stages of the shift register is merely exemplary, which may be determined according to practical situations, and the embodiment of the disclosure is not limited thereto.

For example, the sequentially arranged multiple stages of shift registers are combined into N groups of gate driving sub-circuits, and the shift registers in the N groups of gate driving sub-circuits are respectively cascaded. For example, in some examples, as shown in fig. 3A, the sequentially arranged multi-stage shift registers are combined into 2(N ═ 2) groups of gate driving sub-circuits, i.e., a1 st group of gate driving sub-circuits and a2 nd group of gate driving sub-circuits. For example, in other examples, as shown in fig. 3B, the sequentially arranged multi-stage shift registers are combined into 4(N ═ 4) sets of gate driving sub-circuits, i.e., the 1 st, 2 nd, 3 rd and 4 th sets of gate driving sub-circuits.

For example, the mth group of gate driving sub-circuits in the N groups of gate driving sub-circuits includes an mth stage shift register and an m + L × N stage shift register, which are cascaded, where m is an integer greater than or equal to 1 and less than or equal to N, L is an integer greater than or equal to 1, and N is an even number greater than or equal to 2.

The gate driving circuits shown in fig. 3A and 3B are taken as examples, that is, N-2 (including 2 groups of gate driving sub-circuits) and N-4 (including 4 groups of gate driving sub-circuits) are taken as examples, and the embodiments of the present disclosure are not limited thereto.

For example, as shown in fig. 3A, when N is 2, the 1 st group of gate driver sub-circuits (i.e., when m is 1) includes cascaded odd-numbered stage shift registers, for example, the cascaded odd-numbered stage shift registers (the white rectangular frame shown in fig. 3A) include cascaded 1 st (m), 3 st (L is 1, m + L is N is 3), 5 st (L is 2, m + L is N is 5), 7 st (L is 3, m + L is N is 7), 9 st (L is 4, m + L is N is 9), 11 st (L is 5, m + L is N is 11) … … stage shift registers GOA1, GOA3, GOA5, GOA7, GOA9, and GOA11 … …; the 2 nd group of gate driver sub-circuits (i.e., when m is 2) includes cascaded even-numbered stage shift registers, for example, the cascaded even-numbered stage shift registers (the shaded rectangular frame shown in fig. 3A) include cascaded 2 nd (m), 4 th (L is 1, m + L is 4), 6 th (L is 2, m + L is N is 6), 8 th (L is 3, m + L is N is 8), 10 th (L is 4, m + L is N is 10), 12 th (L is 5, m + L is N is 12) … … stages of shift registers GOA2, GOA4, GOA6, GOA8, GOA10, and GOA12 … …, which the disclosed embodiment is not limited thereto.

For example, as shown in fig. 3B, when N is 4, the 1 st group of gate driving sub-circuits (i.e., when m is 1) includes cascaded odd-numbered stage shift registers, for example, the cascaded odd-numbered stage shift registers include cascaded 1 st, 5 th, 9 th, 13 … … stage shift registers, GOA1, GOA5, GOA9, GOA13 … …; the group 2 gate driving sub-circuits (i.e., when m is 2) include cascaded even-numbered stage shift registers, for example, the cascaded even-numbered stage shift registers include cascaded 2 nd, 6 th, 10 th, 14 … … th stage shift registers, i.e., GOA2, i.e., GOA6, i.e., GOA10, i.e., GOA14 … …; the 3 rd group of gate driving sub-circuits (i.e., when m is 3) includes cascaded odd-numbered stage shift registers, for example, the cascaded odd-numbered stage shift registers include cascaded 3 rd, 7 th, 11 th, and 15 … … th stage shift registers, i.e., GOA3, i.e., GOA7, i.e., GOA11, i.e., GOA15 … …; the 4 th group of gate driving sub-circuits (i.e., when m is 4) includes cascaded even-numbered stage shift registers, for example, the cascaded even-numbered stage shift registers include cascaded 4 th, 8 th, 12 th, and 16 … … th stage shift registers, i.e., GOA4, GOA8, GOA12, and GOA16 … …, which are not limited by the embodiments of the present disclosure.

For example, as described above, the odd-numbered group of gate drive sub-circuits (e.g., the 1 st group of gate drive sub-circuits as shown in fig. 3A or the 1 st and 3 rd groups of gate drive sub-circuits as shown in fig. 3B include cascaded odd-numbered stage shift registers) each include cascaded odd-numbered stage shift registers; the even group of gate drive sub-circuits (e.g., the 2 nd group of gate drive sub-circuits as shown in fig. 3A or the 2 nd and 4 th group of gate drive sub-circuits as shown in fig. 3B include cascaded odd-numbered stage shift registers) each include cascaded even-numbered stage shift registers. For example, the shift registers in each group of gate driving sub-circuits are respectively cascaded and form an independent cascade relationship, and the gate driving sub-circuits in each group are not cascaded with each other, so that the independent driving of the sub-pixels in odd rows during odd frame display or the independent driving of the sub-pixels in even rows during even frame display can be realized.

For example, the display panel 1 further includes N trigger signal lines respectively connected to the N groups of gate driving sub-circuits.

For example, in some examples, as shown in fig. 3A, when sequentially arranged multi-stage shift registers are combined into 2 groups of gate driving sub-circuits (i.e., a1 st group of gate driving sub-circuits and a2 nd group of gate driving sub-circuits), the display panel includes 2 trigger signal lines respectively connected to the 2 groups of gate driving sub-circuits. For example, in other examples, as shown in fig. 3B, when the sequentially arranged multi-stage shift registers are combined into 4 sets of gate driving sub-circuits (i.e., the 1 st set of gate driving sub-circuits, the 2 nd set of gate driving sub-circuits, the 3 rd set of gate driving sub-circuits, and the 4 th set of gate driving sub-circuits), the display panel includes 4 trigger signal lines respectively connected to the 4 sets of gate driving sub-circuits.

For example, the mth trigger signal line of the N trigger signal lines is connected to the Input terminal Input of the mth stage shift register. That is, the 1 st trigger signal line STV1 is connected to the Input terminal Input of the 1 st stage shift register in the 1 st group of gate driving sub-circuits; the 2 nd trigger signal line STV2 is connected to the Input terminal Input of the 2 nd stage shift register (i.e., the 1 st shift register of the 2 nd group of gate drive sub-circuits); the 3 rd trigger signal line is connected with the Input end Input of the 3 rd stage shift register (namely the 1 st shift register of the 3 rd group of grid drive sub-circuits); the 4 th trigger signal line is connected to the Input terminal Input of the 4 th shift register (i.e., the 1 st shift register of the 4 th group of gate driver sub-circuits).

It should be noted that each trigger signal line may be connected to other stages of shift registers besides the 1 st stage shift register of each group of gate driving sub-circuits, which may be determined according to actual situations, specifically, may be set according to the number of clock signal lines, and the specific connection relationship may refer to the design in the art, and will not be described herein again.

The following description will be made by taking the display panel including 2 groups of gate driving sub-circuits and 2 trigger signal lines (the 1 st trigger signal line STV1 and the 2 nd trigger signal line STV2), which is not limited in this respect by the embodiments of the present disclosure. The connection relationships of the gate driving sub-circuits of other groups are similar to that of the gate driving sub-circuits, and are not described in detail herein.

For example, in some examples, the display panel further includes 4K clock signal lines. For example, the 4K clock signal lines include a first clock signal line to a 4K clock signal line, and are respectively connected to the clock signal terminals CLK of the multi-stage shift register to provide clock signals, K is an integer greater than or equal to 1, and 4K is less than or equal to the number of stages of the multi-stage shift register. For example, K may be equal to 1, 2, 3, 4, 5, etc. For example, the number of clock signal lines is an integer multiple of 4, such as 4CLK (4 clock signal lines, K is 1), 8CLK (8 clock signal lines, K is 2), 12CLK (12 clock signal lines, K is 3), 16CLK (16 clock signal lines, K is 4), and the like, which is not limited in the embodiments of the present disclosure.

Fig. 4 is a schematic diagram of a display panel including 4CLK (K ═ 1) according to at least one embodiment of the present disclosure; fig. 5 is a schematic diagram of a display panel including 8CLK (K-2) according to at least one embodiment of the present disclosure; fig. 6A is a schematic diagram of a display panel including 12CLK (K-3) according to at least one embodiment of the present disclosure; fig. 6B is a schematic diagram of a display panel including 16CLK (K-4) according to at least one embodiment of the present disclosure.

For example, when K is 1, as shown in fig. 4, the 4K clock signal lines include a first clock signal line CLK1, a second clock signal line CLK2, a third clock signal line CLK3, and a fourth clock signal line CLK 4.

For example, as shown in fig. 4, a first clock signal line CLK1 is connected to a clock signal terminal CLK of a 4n-3(n is an integer of 1 or more) th stage shift register; the second clock signal line CLK2 is connected to the clock signal terminal CLK of the 4n-2 th stage shift register; the third clock signal line CLK3 is connected to the clock signal terminal CLK of the 4n-1 th stage shift register; the fourth clock signal line CLK4 is connected to the clock signal terminal CLK of the 4 nth stage shift register.

For example, when K is 3, as shown in fig. 6A, the 4K clock signal lines include a first clock signal line CLK1, a second clock signal line CLK2, a third clock signal line CLK3, a fourth clock signal line CLK4, a fifth clock signal line CLK5, a sixth clock signal line CLK6, a seventh clock signal line CLK7, an eighth clock signal line CLK8, a ninth clock signal line CLK9, a tenth clock signal line CLK10, an eleventh clock signal line CLK11, and a twelfth clock signal line CLK 12.

For example, as shown in fig. 6A, a first clock signal line CLK1 is connected to a clock signal terminal of the 12n-11 th stage shift register; the second clock signal line CLK2 is connected with the clock signal end of the shift register of the 12n-10 th stage; the third clock signal line CLK3 is connected with the clock signal end of the shift register of the 12n-9 th stage; the fourth clock signal line CLK4 is connected to the clock signal terminal of the 12n-8 th stage shift register; a fifth clock signal line CLK5 is connected to the clock signal terminal of the 12n-7 th stage shift register; a sixth clock signal line CLK6 is connected to the clock signal terminal of the 12n-6 th stage shift register; the seventh clock signal line CLK7 is connected to the clock signal terminal of the 12n-5 th stage shift register; an eighth clock signal line CLK8 is connected to the clock signal terminal of the 12n-4 th stage shift register; a ninth clock signal line CLK9 is connected to the clock signal terminal of the 12n-3 th stage shift register; a tenth clock signal line CLK10 is connected to a clock signal terminal of the 12n-2 th stage shift register; an eleventh clock signal line CLK11 is connected to the clock signal terminal of the 12n-1 th stage shift register; a twelfth clock signal line CLK12 is connected to a clock signal terminal of the 12 nth stage shift register; n is an integer of 1 or more.

It should be noted that the connection manner of the other number of clock signal lines and the shift register units is similar to that in fig. 4 and 6A, and is not described herein again, and other connection manners may also be adopted, which is not limited in this embodiment of the disclosure.

For example, as shown in fig. 4-6B, when N is 2, the N trigger signal lines include a first trigger signal line STV1 and a second trigger signal line STV 2.

For example, the first trigger signal line STV1 is connected to the Input terminals Input of the first K odd-numbered stage shift registers to supply the first trigger signal, and the Input terminals Input of the remaining respective odd-numbered stage shift registers are connected to the output terminals OUT of the upper-numbered shift registers which are separated therefrom by K-1 odd-numbered stages or to the output terminals OUT of the upper-numbered shift registers which are separated therefrom by 2K-1 stages; the second trigger line STV2 is connected to the Input terminals Input of the first K even-numbered stage shift registers to supply the second trigger signal, and the Input terminals Input of the remaining respective even-numbered stage shift registers are connected to the output terminals OUT of the upper-numbered stage shift registers which are spaced apart from the Input terminals by K-1 even-numbered stages or to the output terminals OUT of the upper-numbered stage shift registers which are spaced apart from the Input terminals by 2K-1 stages.

For example, as shown in fig. 4, when 4 (K ═ 1) clock signal lines are included, for the 1 st group of gate drive sub-circuits, the first trigger signal line STV1 is connected to the Input terminal Input of the first 1 odd-numbered stage shift register (i.e., the 1 st stage shift register a1) of the gate drive circuit to supply the first trigger signal, and the Input terminals Input of the remaining respective odd-numbered stage shift registers are connected to the output terminals OUT of the upper-numbered stage shift registers which are 0 odd-numbered stages apart therefrom (i.e., to the output terminals OUT of the upper-numbered stage odd-numbered stage shift registers adjacent thereto), or to the output terminals OUT of the upper-numbered stage shift registers which are 1 stage apart therefrom. For example, the remaining odd-numbered shift registers are illustrated by taking the 3 rd shift register as an example, and the embodiment of the disclosure is not limited thereto. For example, the Input terminal Input of the 3 rd stage shift register A3 is connected to the output terminal OUT of the upper stage odd-numbered stage shift register adjacent thereto (i.e., the 1 st stage shift register a1), or connected to the output terminal OUT of the upper stage shift register 1 th stage apart therefrom (i.e., the 2 nd stage shift register a2) (i.e., the 1 st stage shift register a 1).

For example, as shown in fig. 4, when 4 (K ═ 1) clock signal lines are included, for the group 2 gate drive sub-circuits, the second trigger line STV2 is connected to the Input terminals Input of the first 1 even-numbered stage shift registers (i.e., the 2 nd stage shift register a2) to supply the second trigger signal, and the Input terminals Input of the remaining respective even-numbered stage shift registers are connected to the output terminals OUT of the upper-numbered stage shift registers which are separated by 0 even-numbered stages (i.e., to the output terminals OUT of the upper-numbered stage shift registers which are adjacent thereto), or to the output terminals OUT of the upper-numbered stage shift registers which are separated by 1 stage. For example, the remaining even-numbered shift registers are illustrated by taking the 4 th shift register as an example, and the embodiment of the disclosure is not limited thereto. For example, the Input terminal Input of the 4 th stage shift register a4 is connected to the output terminal OUT of the upper stage even-numbered stage shift register adjacent thereto (i.e., the 2 nd stage shift register a2), or connected to the output terminal OUT of the upper stage shift register 1 stage apart therefrom (i.e., 3 rd stage shift register A3 apart therefrom (i.e., the 2 nd stage shift register a 2).

For example, as shown in fig. 5, when 8 (K ═ 2) clock signal lines are included, for the 1 st group of gate drive sub-circuits, the first trigger signal line STV1 is connected to the Input terminals Input of the first 2 odd-numbered stage shift registers (i.e., the 1 st stage shift register a1 and the 3 rd stage shift register A3) of the gate drive circuit to supply the first trigger signal, and the Input terminals Input of the remaining respective odd-numbered stage shift registers are connected to the output terminals OUT of the upper-numbered stage shift registers which are separated by 1 odd-numbered stage or to the output terminals OUT of the upper-numbered stage shift registers which are separated by 3 stages. For example, the remaining odd-numbered shift registers are illustrated by taking the 5 th shift register as an example, and the embodiments of the disclosure are not limited thereto. For example, the Input terminal Input of the 5 th-stage shift register a5 is connected to the output terminal OUT of the upper-stage shift register (i.e., the 1 st-stage shift register a1) that is separated from it by 1 odd-numbered stage (i.e., the 3 rd-stage shift register A3), or to the output terminal OUT of the upper-stage shift register (i.e., the 1 st-stage shift register a1) that is separated from it by 3 stages (i.e., the 2 nd-stage shift register a2, the 3 rd-stage shift register A3, the 4 th-stage shift register a 4).

For example, as shown in fig. 5, when 8 (K ═ 2) clock signal lines are included, for the group 2 gate drive sub-circuits, the second trigger line STV2 is connected to the Input terminals Input of the first 2 even-numbered stage shift registers (i.e., the 2 nd stage shift register a2 and the 4 th stage shift register a4) to supply the second trigger signal, and the Input terminals Input of the remaining respective even-numbered stage shift registers are connected to the output terminals OUT of the upper-numbered stage shift registers which are separated by 1 even-numbered stage or to the output terminals OUT of the upper-numbered stage shift registers which are separated by 3 stages. For example, the remaining even-numbered stage shift registers are illustrated by taking the 6 th stage shift register as an example, and the embodiment of the disclosure is not limited thereto. For example, the Input terminal Input of the 6 th-stage shift register a6 is connected to the output terminal OUT of the upper-stage shift register (i.e., the 2 nd-stage shift register a2) that is separated from it by 1 even-numbered stage (i.e., by the 4 th-stage shift register a4), or to the output terminal OUT of the upper-stage shift register (i.e., the 2 nd-stage shift register a2) that is separated from it by 3 stages (i.e., by the 3 rd-stage shift register A3, the 4 th-stage shift register a4, the 5 th-stage shift register a 5).

For example, as shown in fig. 6A, when 12 (K-3) clock signal lines are included, for the 1 st group of gate drive sub-circuits, the first trigger signal line STV1 and the Input terminals Input of the first 3 odd-numbered shift registers of the gate drive circuit (i.e., the 1 st shift register a1, the 3 rd shift register A3, and the 5 th shift register a5) are connected to provide a first trigger signal, and the Input terminals Input of the remaining respective odd-numbered shift registers are connected to the output terminals OUT of the upper-numbered shift registers spaced apart therefrom by 2 (K-1-2) odd-numbered stages or to the output terminals OUT of the upper-numbered shift registers spaced apart therefrom by 5 (2K-1-5) stages. For example, the remaining odd-numbered shift registers are illustrated by taking the 7 th shift register as an example, and the embodiments of the disclosure are not limited thereto. For example, the Input terminal Input of the 7 th-stage shift register a7 is connected to the output terminal OUT of the upper-stage shift register (i.e., the 1 st-stage shift register a1) that is separated from it by 3 odd-numbered stages (i.e., the 3 rd-stage shift register A3 and the 5 th-stage shift register a5), or to the output terminal OUT of the upper-stage shift register (i.e., the 1 st-stage shift register a1) that is separated from it by 5 stages (i.e., the 2 nd-stage shift register a2 to the 6 th-stage shift register a 6).

For example, as shown in fig. 6A, when 12 (K ═ 3) clock signal lines are included, for the group 2 gate drive sub-circuits, the second trigger line STV2 is connected to the Input terminals Input of the first 3 even-numbered stage shift registers (i.e., the 2 nd stage shift register a2, the 4 th stage shift register a4, and the 6 th stage shift register a6) to supply the second trigger signal, and the Input terminals Input of the remaining respective even-numbered stage shift registers are connected to the output terminals OUT of the upper-numbered shift registers which are spaced by 2 even-numbered stages or to the output terminals OUT of the upper-numbered shift registers which are spaced by 5 stages. For example, the remaining even-numbered stage shift registers are illustrated by taking the 8 th stage shift register as an example, and the embodiment of the disclosure is not limited thereto. For example, the Input terminal Input of the 8 th stage shift register A8 is connected to the output terminal OUT of the upper stage shift register (i.e., the 2 nd stage shift register a2) which is separated by 2 even stages (i.e., the 4 th stage shift register a4 and the 6 th stage shift register a6), or to the output terminal OUT of the upper stage shift register (i.e., the 2 nd stage shift register a2) which is separated by 5 stages (i.e., the 3 rd stage shift register A3 to the 7 th stage shift register a 7).

For example, as shown in fig. 6B, when 16 (K ═ 4) clock signal lines are included, for the 1 st group of gate drive sub-circuits, the first trigger signal line STV1 is connected to the Input terminals Input of the first 4 odd-numbered shift registers of the gate drive circuit (i.e., the 1 st shift register a1, the 3 rd shift register A3, the 5 th shift register a5, and the 7 th shift register a7) to supply the first trigger signal, and the Input terminals Input of the remaining respective odd-numbered shift registers are connected to the output terminals OUT of the upper-numbered shift registers which are 3 odd-numbered stages apart therefrom or to the output terminals OUT of the upper-numbered shift registers which are 7 stages apart therefrom. For example, the remaining odd-numbered shift registers are illustrated by taking the 9 th shift register as an example, and the embodiment of the disclosure is not limited thereto. For example, the Input terminal Input of the 9 th-stage shift register a9 is connected to the output terminal OUT of the upper-stage shift register (i.e., the 1 st-stage shift register a1) that is separated from it by 3 odd-numbered stages (i.e., the 3 rd-stage shift register A3, the 5 th-stage shift register a5, and the 7 th-stage shift register a7), or to the output terminal OUT of the upper-stage shift register (i.e., the 1 st-stage shift register a1) that is separated from it by 7 stages (i.e., the 2 nd-stage shift register a2 to the 8 th-stage shift register A8).

For example, as shown in fig. 6B, when 16 (K ═ 4) clock signal lines are included, for the group 2 gate drive sub-circuits, the second trigger line STV2 is connected to the Input terminals Input of the first 4 even-numbered stage shift registers (i.e., the 2 nd stage shift register a2, the 4 th stage shift register a4, the 6 th stage shift register a6, and the 8 th stage shift register a8) to supply the second trigger signal, and the Input terminals Input of the remaining respective even-numbered stage shift registers are connected to the output terminals OUT of the upper-numbered stage shift registers which are 3 even-numbered stages apart therefrom, or to the output terminals OUT of the upper-numbered shift registers which are 7 stages apart therefrom. For example, the remaining even-numbered shift registers are illustrated by taking the 10 th shift register as an example, and the embodiment of the disclosure is not limited thereto. For example, the Input terminal Input of the 10 th stage shift register a10 is connected to the output terminal OUT of the upper stage shift register (i.e., the 2 nd stage shift register a2) which is separated from it by 3 even stages (i.e., the 4 th stage shift register a4, the 6 th stage shift register a6, and the 8 th stage shift register A8), or to the output terminal OUT of the upper stage shift register (i.e., the 2 nd stage shift register a2) which is separated from it by 7 stages (i.e., the 3 rd stage shift register A3 to the 9 th stage shift register a 9).

For example, in the examples shown in fig. 4 and 5, when K is 1 or 2, the Reset terminal Reset of each of the odd-numbered stage shift registers except the last K odd-numbered stage shift registers is connected to the output terminal OUT of the lower-stage shift register which is spaced apart from it by 2K-2 odd-numbered stage shift registers, or to the output terminal OUT of the lower-stage shift register which is spaced apart from it by 4K-3 stages; except the last K even-numbered shift registers, the Reset terminals Reset of the other even-numbered shift registers are connected with the output terminals OUT of the next-level shift registers which are separated by 2K-2 even-numbered shift registers, or connected with the output terminals OUT of the next-level shift registers which are separated by 4K-3 even-numbered shift registers.

For example, as shown in fig. 4, when 4 (K ═ 1) clock signal lines are included, the Reset terminals Reset of the respective odd-numbered shift registers except for the last 1 odd-numbered shift register are connected to the output terminals OUT of the lower-numbered shift registers which are 0 odd-numbered shift registers apart therefrom, or to the output terminals OUT of the lower-numbered shift registers which are 1 odd-numbered apart therefrom. For example, the remaining odd-numbered stage shift registers are illustrated by taking the 1 st stage shift register as an example, and the embodiment of the disclosure is not limited thereto. For example, the Reset terminal Reset of the 1 st stage shift register a1 is connected to the output terminal OUT of the lower stage shift register (i.e., the 3 rd stage shift register A3) which is separated from it by 0 odd-numbered stages of shift registers, or to the output terminal OUT of the lower stage shift register (i.e., the 3 rd stage shift register A3) which is separated from it by 1 stage (i.e., the 2 nd stage shift register a 2).

For example, as shown in fig. 4, when 4 (K ═ 1) clock signal lines are included, the Reset terminals Reset of the respective even-numbered stage shift registers except for the last 1 even-numbered stage shift register are connected to the output terminals OUT of the lower-stage shift registers which are 0 even-numbered stage apart therefrom, or to the output terminals OUT of the lower-stage shift registers which are 1 stage apart therefrom. For example, the remaining even-numbered shift registers are illustrated by taking the 2 nd-level shift register as an example, and the embodiment of the disclosure is not limited thereto. For example, the Reset terminal Reset of the 2 nd stage shift register a2 is connected to the output terminal OUT of the lower stage shift register (i.e., the 4 th stage shift register a4) which is separated from it by 0 even-numbered stages of shift registers, or to the output terminal OUT of the lower stage shift register (i.e., the 4 th stage shift register a4) which is separated from it by 1 stage (i.e., the 3 rd stage shift register A3).

For example, as shown in fig. 5, when 8 (K ═ 2) clock signal lines are included, the Reset terminals Reset of the respective odd-numbered shift registers except the last 2 odd-numbered shift registers are connected to the output terminals OUT of the lower-level shift registers which are spaced apart by 2 odd-numbered shift registers, or to the output terminals OUT of the lower-level shift registers which are spaced apart by 5 levels. For example, the remaining odd-numbered stage shift registers are illustrated by taking the 1 st stage shift register as an example, and the embodiment of the disclosure is not limited thereto. For example, the Reset terminal Reset of the 1 st stage shift register a1 is connected to the output terminal OUT of the lower stage shift register (i.e., the 7 th stage shift register a7) which is separated from it by 2 odd-numbered stages (i.e., the 3 rd stage shift register A3 and the 5 th stage shift register a5), or to the output terminal OUT of the lower stage shift register (i.e., the 7 th stage shift register a7) which is separated from it by 5 stages (i.e., the 2 nd stage shift register a2 to the 6 th stage shift register a 6).

For example, as shown in fig. 5, when 8 (K ═ 2) clock signal lines are included, the Reset terminals Reset of the respective even-numbered stage shift registers except for the last 2 even-numbered stage shift registers are connected to the output terminals OUT of the lower-stage shift registers which are spaced apart by 2 even-numbered stage shift registers, or to the output terminals OUT of the lower-stage shift registers which are spaced apart by 5 stages. For example, the remaining even-numbered shift registers are illustrated by taking the 2 nd-level shift register as an example, and the embodiment of the disclosure is not limited thereto. For example, the Reset terminal Reset of the 2 nd stage shift register a2 is connected to the output terminal OUT of the lower stage shift register (i.e., the 8 th stage shift register A8) which is separated from it by 2 even-numbered stages (i.e., the 4 th stage shift register a4 and the 6 th stage shift register a6), or to the output terminal OUT of the lower stage shift register (i.e., the 8 th stage shift register A8) which is separated from it by 5 stages (i.e., the 3 rd stage shift register A3 to the 7 th stage shift register a 7).

For example, in other examples, when K is 3 (i.e., 12 clock signal lines are included as shown in fig. 6A) or 4 (i.e., 16 clock signal lines are included as shown in fig. 6B), for example, in the example shown in fig. 6A, the Reset terminals Reset of the respective odd-numbered shift registers except for the last K odd-numbered shift registers are connected to the output terminals OUT of the lower-numbered shift registers which are separated by K odd-numbered shift registers or to the output terminals OUT of the lower-numbered shift registers which are separated by 2K +1 stages; except the last K even-level shift registers, the Reset ends Reset of the rest even-level shift registers are connected with the output ends OUT of the lower-level shift registers which are separated from the last even-level shift registers by K even-level shift registers, or connected with the output ends OUT of the lower-level shift registers which are separated from the last even-level shift registers by 2K +1 levels; for example, in the example shown in fig. 6B, the Reset terminals Reset of the remaining respective odd-numbered stage shift registers except for the last K odd-numbered stage shift registers are connected to the output terminals OUT of the lower-stage shift registers which are K odd-numbered stage apart therefrom, or to the output terminals OUT of the lower-stage shift registers which are 2K +1 stage apart therefrom; the Reset terminals Reset of the even-numbered shift registers except the last K even-numbered shift registers are connected to the output terminals OUT of the next-level shift registers which are separated from the last K even-numbered shift registers by K even-numbered shift registers, or connected to the output terminals OUT of the next-level shift registers which are separated from the last K +1 even-numbered shift registers.

For example, as shown in fig. 6A, when 12 (K ═ 3) clock signal lines are included, the Reset terminals Reset of the respective odd-numbered shift registers except the last 3 odd-numbered shift registers are connected to the output terminals OUT of the lower-level shift registers which are 3(K ═ 3) odd-numbered shift registers apart therefrom, or to the output terminals OUT of the lower-level shift registers which are 7(2K +1 ═ 7) levels apart therefrom. For example, the remaining odd-numbered stage shift registers are illustrated by taking the 1 st stage shift register as an example, and the embodiment of the disclosure is not limited thereto. For example, the Reset terminal Reset of the 1 st stage shift register a1 is connected to the output terminal OUT of the lower stage shift register (i.e., the 9 th stage shift register a9) which is separated from it by 4 odd-numbered stages (i.e., the 3 rd stage shift register A3, the 5 th stage shift register a5, the 7 th stage shift register a7), or to the output terminal OUT of the lower stage shift register (i.e., the 9 th stage shift register a9) which is separated from it by 7 stages (i.e., the 2 nd stage shift register a2 to the 8 th stage shift register A8).

For example, as shown in fig. 6A, when 12 (K ═ 3) clock signal lines are included, the Reset terminals Reset of the respective even-numbered stage shift registers except the last 3 even-numbered stage shift registers are connected to the output terminals OUT of the lower-stage shift registers which are 3 even-numbered stages apart therefrom, or to the output terminals OUT of the lower-stage shift registers which are 7 stages apart therefrom. For example, the remaining even-numbered shift registers are illustrated by taking the 2 nd-level shift register as an example, and the embodiment of the disclosure is not limited thereto. For example, the Reset terminal Reset of the 2 nd stage shift register a2 is connected to the output terminal OUT of the lower stage shift register (i.e., the 10 th stage shift register a10) which is separated from it by 3 even stages (i.e., the 4 th stage shift register a4, the 6 th stage shift register a6, the 8 th stage shift register A8), or to the output terminal OUT of the lower stage shift register (i.e., the 10 th stage shift register a10) which is separated from it by 7 stages (i.e., the 3 rd stage shift register A3 to the 9 th stage shift register a 9).

For example, as shown in fig. 6B, when 16 (K ═ 4) clock signal lines are included, the Reset terminals Reset of the respective odd-numbered shift registers except for the last 4 odd-numbered shift registers are connected to the output terminals OUT of the lower-level shift registers which are separated by 4 odd-numbered shift registers, or to the output terminals OUT of the lower-level shift registers which are separated by 9 levels. For example, the remaining odd-numbered stage shift registers are illustrated by taking the 1 st stage shift register as an example, and the embodiment of the disclosure is not limited thereto. For example, the Reset terminal Reset of the 1 st stage shift register a1 is connected to the output terminal OUT of the shift register (i.e., 11 th stage shift register a11) of the next stage which is separated from it by 4 odd stages (i.e., 3 rd stage shift register A3, 5 th stage shift register a5, 7 th stage shift register a7, 9 th stage shift register a9), or to the output terminal OUT of the shift register (i.e., 11 th stage shift register a11) of the next stage which is separated from it by 9 stages (i.e., 2 nd stage shift register a2 to 10 th stage shift register a 10).

For example, as shown in fig. 6B, when 16 (K ═ 4) clock signal lines are included, the Reset terminals Reset of the respective even-numbered stage shift registers except for the last 4 even-numbered stage shift registers are connected to the output terminals OUT of the lower-stage shift registers which are separated by 4 even-numbered stages or to the output terminals OUT of the lower-stage shift registers which are separated by 9 stages. For example, the remaining even-numbered shift registers are illustrated by taking the 2 nd-level shift register as an example, and the embodiment of the disclosure is not limited thereto. For example, the Reset terminal Reset of the 2 nd stage shift register a2 is connected to the output terminal OUT of the shift register (i.e., the 12 th stage shift register a12) of the next stage which is separated from it by 4 even stages (i.e., the shift register a4 of the 4 th stage, the shift register a6 of the 6 th stage, the shift register A8 of the 8 th stage, and the shift register a10 of the 10 th stage), or to the output terminal OUT of the shift register (i.e., the shift register a12 of the 12 th stage) of the next stage which is separated from it by 9 stages (i.e., the shift register A3 of the 3 rd stage to the shift register a11 of the 11 th stage).

For example, the Reset terminals Reset of the last K (i.e., K stages) odd-numbered stage shift registers are connected to a Reset signal line (not shown in the figure) to receive a Reset signal.

For example, the sequentially arranged multi-stage shift register includes a plurality of redundant (dummy) shift registers, and input terminals of N redundant shift registers among the plurality of redundant shift registers are connected to N trigger signal lines to receive the trigger signals.

Due to factors such as the output of the shift register unit directly connected to the trigger signal line may not be stable enough, the shift register connected to the trigger signal line may be provided as a redundant (dummy) shift register, for example, not connected to a sub-pixel or connected to a redundant sub-pixel, for example, not used for light emission, i.e., not written with a data signal.

For example, in the example of fig. 4, an 8K-resolution display may include 4320 rows of sub-pixels and 4322 stages of shift registers connected to the 4320 rows of sub-pixels, wherein the 1 st stage shift register a1 connected to the first trigger signal line STV1 and the 2 nd stage shift register a2 connected to the second trigger signal line STV2 are not connected to the sub-pixels as redundant shift registers; or an 8K resolution display may include 4322 rows of sub-pixels and a shift register connected to the 4322 rows of sub-pixels, wherein the 4320 rows (e.g., 3 rd to 4320 th rows) of sub-pixels are used for display, and the sub-pixels (connected to the 1 st to 2 nd stages of redundant shift registers) disposed in the remaining 2 rows (e.g., 1 st and 2 nd rows) are not used for display (e.g., no data signal is input) as redundant sub-pixels.

For example, in the example shown in fig. 5, an 8K-resolution display may include 4320 rows of sub-pixels and 4324 stages of shift registers connected to the 4320 rows of sub-pixels, wherein the 1 st and 3 rd stages of shift registers a1 and A3 connected to the first trigger signal line STV1 and the 2 nd and 4 th stages of shift registers a2 and a4 connected to the second trigger signal line STV2 are not connected to the sub-pixels as redundant shift registers; or the 8K resolution display may include 4324 rows of sub-pixels and a shift register connected to the 4324 rows of sub-pixels, wherein the 4320 rows (e.g., 3 rd to 4320 th rows) of sub-pixels are used for display, and the sub-pixels (connected to the 1 st to 4 th stage redundant shift registers) disposed in the remaining 4 rows (e.g., 1 st to 4 th rows) are not used for display (e.g., no data signal is input) as redundant sub-pixels.

For example, in the example shown in fig. 6A, an 8K-resolution display may include 4320 rows of sub-pixels and 4326 stages of shift registers connected to the 4320 rows of sub-pixels, wherein the 1 st, 3 rd, and 5 th stage shift registers a1, A3, and a5 connected to the first trigger signal line STV1, and the 2 nd, 4 th, and 6 th stage shift registers a2, a4, and a6 th stage shift register connected to the second trigger signal line STV2 are not connected to the sub-pixels as redundant shift registers; or the 8K resolution display may include 4326 rows of sub-pixels and a shift register connected to the 4326 rows of sub-pixels, wherein the 4320 rows (e.g., 7 th to 4320 th rows) of sub-pixels are used for display, and the sub-pixels (connected to the 1 st to 6 th stage redundant shift registers) disposed in the remaining 6 rows (e.g., 1 st to 6 th rows) are not used for display (e.g., no data signal is input) as redundant sub-pixels.

Fig. 6B is similar to fig. 6A, and the redundant shift registers included in the 8K-resolution display are level 1 shift registers to level 8 shift registers, or the redundant sub-pixels included in the 8K-resolution display are row 1 to row 8, which is not described herein again.

It should be noted that the number of redundant shift registers and the number of redundant sub-pixel rows may include more or less according to actual needs, and fig. 4 to 6B are only schematic illustrations of the corresponding numbers, and the embodiment of the present disclosure is not limited thereto.

The following description is given by taking as an example that the redundant shift register and the redundant sub-pixels are not provided (i.e., the plurality of rows of sub-pixels connected thereto are driven for display by the gate scan signals output from the plurality of stages of shift registers connected to the trigger signal line), and the embodiment of the present disclosure is not limited thereto.

For example, as shown in fig. 4 to 6B, the display panel 1 further includes a clock controller 300 connected to the 4K clock signal lines and configured to: when the clock signal is provided for the clock signal lines connected with the odd-numbered gate drive sub-circuits in the N groups of gate drive sub-circuits, the clock signal is not provided for the clock signal lines connected with the even-numbered gate drive sub-circuits in the N groups of gate drive sub-circuits or the invalid clock signal is provided for the clock signal lines connected with the even-numbered gate drive sub-circuits; when a clock signal is supplied to the clock signal line connected to the even-numbered group of gate drive sub-circuits, no clock signal is supplied to the clock signal line connected to the odd-numbered group of gate drive sub-circuits or an invalid clock signal is supplied to the clock signal line connected to the odd-numbered group of gate drive sub-circuits.

fig. 7B is a schematic diagram of an xth frame display according to at least one embodiment of the present disclosure; fig. 8A is a timing diagram of an x +1 th frame of a display image according to at least one embodiment of the disclosure; fig. 8B is a schematic diagram of an x +1 th frame display screen according to at least one embodiment of the present disclosure. Fig. 7A and 8A are signal timing diagrams corresponding to the gate driving circuits shown in fig. 4, and the signal timing of the remaining gate driving circuits can refer to the descriptions of fig. 7A and 7B, which are not repeated herein.

For example, when the x-th frame (x is an integer of 1 or more) is an odd frame, the x + 1-th frame is an even frame; when the x-th frame is an even frame, the x + 1-th frame is an odd frame. In the following, the x-th frame is an odd frame, and the x + 1-th frame is an even frame, which are not limited in the embodiments of the present disclosure.

For example, STV1 represents both the first trigger signal line and the first trigger signal; STV2 represents both the second trigger signal line and the second trigger signal; CLK1 represents both the first clock signal line and the first clock signal; CLK2 represents both the second clock signal line and the second clock signal; CLK3 represents both the third clock signal line and the third clock signal; CLK4 represents both the fourth clock signal line and the fourth clock signal; G1-Gn represents both gate scanning signal lines connected to the sequentially arranged multiple stages of shift registers and gate scanning signals; datan represents a data signal; h represents an active level; l represents an inactive level.

For example, as shown in fig. 7A, when the pixel array is driven to display an x-th frame picture, clock signals are supplied to clock signal lines (e.g., a first clock signal CLK1 and a third clock signal line CLK3) connected to the odd-numbered group (e.g., group 1) of gate driving sub-circuits to cause odd-numbered gate scanning signal lines G1, G3 of the plurality of gate scanning signal lines to output gate scanning signals, e.g., to output an active level H; the clock signal lines (e.g., the second clock signal CLK2 and the fourth clock signal line CLK4) connected to the even-numbered group (e.g., the 2 nd group) gate drive sub-circuits are not supplied with the clock signal or the clock signal lines connected to the even-numbered group gate drive sub-circuits are supplied with the inactive clock signal (e.g., the low-level L signal), so that even-numbered gate scanning signal lines G2, G4 of the plurality of gate scanning signal lines output an inactive gate scanning signal (e.g., output an inactive level L) or do not output the gate scanning signal, thereby causing the data transistors in the sub-pixels connected to the odd row gate scanning signal lines G1 and G3 to be turned on in response to the active level H of the gate scanning signal, to enable writing of the data signal Datan (e.g., having a high level) so that the even-numbered rows of subpixels in the x +1 th frame picture are displayed as full white.

For example, as shown in fig. 8A, when the pixel array is driven to display an x +1 th frame picture, clock signals are supplied to clock signal lines (e.g., the second clock signal CLK2 and the fourth clock signal line CLK4) connected to even-numbered group (e.g., the 2 nd group) gate drive sub-circuits so that the even-numbered row gate scan signal lines G2, G4 output gate scan signals, for example, output an active level H; the clock signal lines (e.g., the first clock signal CLK1 and the third clock signal line CLK3) connected to the odd-numbered group (e.g., group 1) gate drive sub-circuits are not supplied with a clock signal or the clock signal lines connected to the odd-numbered group gate drive sub-circuits are supplied with an inactive clock signal to cause the odd-numbered row gate scan signal lines to output an inactive gate scan signal or not to output a gate scan signal, e.g., to output an inactive level L, so that the data transistors in the even-numbered row gate scan signal lines G2 and G4 are turned on in response to the active level H of the gate scan signal to effect writing of the data signal Datan (e.g., having a low level) to cause the even-numbered row sub-pixels in the x +1 frame to be displayed in full black.

For example, the inactive level is a signal to make the transistor non-conductive, and the active level is a signal to make the transistor conductive.

For example, as shown in fig. 7A, the time difference between the clock signals (e.g., the first clock signal CLK1 and the third clock signal CLK3) received by the adjacent two clock signal lines connected to the odd-numbered group gate drive sub-circuits is 2T (T ═ T1 or T2), and for example, as shown in fig. 8A, the time difference between the clock signals (e.g., the second clock signal CLK2 and the fourth clock signal CLK4) received by the adjacent two clock signal lines connected to the even-numbered group gate drive sub-circuits is 2T. For example, T is the charging time of the sub-pixels of 1 row.

For example, as shown in fig. 4-6B, the clock controller 300 is further connected to the N trigger signal lines and configured to: when an active trigger signal is supplied to a trigger signal line (e.g., the first trigger signal line STV1) connected to the odd-numbered group of gate drive sub-circuits, an inactive trigger signal or no active trigger signal is supplied to a trigger signal line (e.g., the second trigger signal line STV2) connected to the even-numbered group of gate drive sub-circuits; when the active trigger signal is supplied to the trigger signal line (e.g., the second trigger signal line STV2) connected to the even-numbered group of gate drive sub-circuits, the inactive trigger signal or no active trigger signal is supplied to the trigger signal line (e.g., the first trigger signal line STV1) connected to the odd-numbered group of gate drive sub-circuits.

For example, as shown in fig. 7A, when the pixel array is driven to display the x-th frame picture, an active trigger signal is supplied to the first trigger signal line STV1 to make the 1 st group of gate driving sub-circuits start outputting gate scan signals by odd rows, and an inactive trigger signal or no active trigger signal is supplied to the second trigger signal line STV2 to make the 2 nd group of gate driving sub-circuits inactive, i.e., not outputting gate scan signals.

For example, as shown in fig. 8A, when the pixel array is driven to display an x +1 th frame, an active trigger signal is supplied to the second trigger signal line STV2 to cause the 2 nd group of gate driving sub-circuits to start outputting gate scan signals by even rows, and an inactive trigger signal or no active trigger signal is supplied to the first trigger signal line STV1 to cause the 1 st group of gate driving sub-circuits to be inactive, i.e., not to output gate scan signals.

For example, in some examples, in red, odd groups of gate drive sub-circuits (e.g., group 1 gate drive sub-circuit in fig. 3A or group 1 and group 2 gate drive sub-circuits in fig. 3B) of the N groups of gate drive sub-circuits are respectively connected to odd row sub-pixels to provide gate scan signals to the odd row sub-pixels, and even groups of gate drive sub-circuits (e.g., group 2 gate drive sub-circuit in fig. 3A or group 2 and group 4 gate drive sub-circuits in fig. 3B) of the N groups of gate drive sub-circuits are respectively connected to even row sub-pixels to provide gate scan signals to the even row sub-pixels.

For example, in some examples, the data driving circuitry 30 is configured to: when the pixel array is driven to display the x frame picture, providing a data signal with a first level to a plurality of data lines; when the pixel array is driven to display the (x + 1) th frame of picture, the data signals with the second level are supplied to the plurality of data lines.

For example, as shown in fig. 7A, when the driving pixel array displays an x-th frame picture, a data signal having a first level (e.g., a high level) is supplied to the plurality of data lines such that the odd row sub-pixels are charged in response to the odd row gate driving signals (e.g., G1, G3, etc.), the data signal having the first level is written so that full white is displayed at the odd row sub-pixels (e.g., the 1 st row sub-pixel R1 and the 3 rd row sub-pixel R3), and a specific display picture is, for example, as shown in fig. 7B.

For example, as shown in fig. 8A, when the driving pixel array displays an x +1 th frame picture, a data signal having a second level (e.g., a low level) is supplied to the plurality of data lines such that the even-row sub-pixels are charged in response to the even-row gate driving signals (e.g., G2, G4, etc.), the data signal having the second level is written so that full black is displayed at the even-row sub-pixels (e.g., the 2 nd row sub-pixel R2 and the 4 th row sub-pixel R4), and a specific display picture is, for example, as shown in fig. 8B.

It should be noted that when the driving pixel array displays the x-th frame picture, the data signal having the second level (e.g., low level) may be further supplied to the plurality of data lines so that the odd row sub-pixels are charged in response to the odd row gate driving signals (e.g., G1, G3, etc.), the data signal having the second level is written so that full black is displayed at the odd row sub-pixels (e.g., the 1 st row sub-pixel R1 and the 3 rd row sub-pixel R3), and a specific display picture is, for example, as shown in fig. 8B; when the driving pixel array displays the (x + 1) th frame, the data signal having the first level (e.g., high level) is provided to the plurality of data lines, so that the even-numbered rows of sub-pixels are charged in response to the even-numbered row gate driving signals (e.g., G2, G4, etc.), and the data signal having the first level is written, so that full white is displayed at the even-numbered rows of sub-pixels (e.g., the 2 nd row sub-pixel R2 and the 4 th row sub-pixel R4), as shown in fig. 7B for example, a specific display screen may be determined in real time, as long as the odd-numbered rows and the even-numbered rows of the two adjacent frame display screens are displayed as black and white display screens, which the embodiment of the present disclosure does not limit.

For example, based on the above-described driving, an x-th frame display screen in which odd-row sub-pixels display full white and an x + 1-th frame display screen in which even-row sub-pixels display full black can be obtained; of course, the even-row sub-pixels may display the x-th frame display screen of full white and the odd-row sub-pixels may display the x + 1-th frame display screen of full black.

According to the visual retention effect of people, based on the fact that the odd-Line sub-pixels shown in the figure 7B display the x-th frame display picture which is completely white and the even-Line sub-pixels shown in the figure 8B display the x + 1-th frame display picture which is completely black, human eyes can see the clear H-1Line picture shown in the figure 1C, so that the odd-Line frame is matched with the data signals to display the odd-Line and the even-Line frame is matched with the data signals to display the even-Line, clear display of the H-1Line picture can be achieved, no serial problem exists, the test standard of industrial CM values is met, and the performance of display products is improved.

For example, in the embodiment of the present disclosure, the H-1Line is implemented to the white/black picture in cooperation with the level of the data signal Datan when the odd/even row gate scan signal is output. For example, odd frames: the first trigger signal line STV1+ odd-row gate scanning signal output + first level of data signal Datan to the white picture, realize that the odd-row sub-pixel displays white, the even-row sub-pixel is in the data state before keeping after this frame finishes; even frames: the second trigger signal line STV2+ the even-row gate scan signal output + the second level of the data signal Datan to the black frame, so that the even-row sub-pixels display black, and after the frame is finished, the odd-row sub-pixels are in the previous data holding state. After the even frame and the odd frame are combined, the sub-pixels can display a clear H-1line picture as shown in FIG. 1C.

Fig. 9A is a schematic diagram illustrating a position relationship of a gate driving circuit according to at least one embodiment of the present disclosure; fig. 9B is a schematic diagram of a position relationship of another gate driving circuit according to at least one embodiment of the present disclosure.

For example, in some examples, as shown in fig. 9A, the gate driving circuit 10 is located at one side of the pixel array (e.g., located in the display area 40), and each stage of the shift register unit is connected to 1 row of sub-pixels respectively to drive the row of sub-pixels to operate (e.g., write data signals).

For example, in other examples, as shown in fig. 9B, the gate driving circuit 10 is located on two sides of the pixel array to implement bilateral driving, and the embodiment of the disclosure does not limit the arrangement manner of the gate driving circuit 10. For example, the shift registers at the same stage in the gate driving circuits at both sides are used for driving the sub-pixels in the same row. For example, as shown in fig. 9B, the gate driving circuits on both sides have the same structure and operation principle, and the shift registers on the same level are used for driving the sub-pixels on the same row. For example, the 1 st-stage shift register units GOA1 on both sides are connected to the 1 st row sub-pixels for driving the 1 st row sub-pixels to operate, and the 2 nd-stage shift register units GOA1 on both sides are connected to the 2 nd row sub-pixels for driving the 2 nd row sub-pixels to operate, and so on, so as to reduce the driving load of the gate scanning signal lines and improve the driving capability of the gate driving circuit.

For example, the structures and the operating principles of the shift register and the sub-pixels may adopt the design in the art, for example, the sub-pixels include a pixel driving circuit and a light emitting element, the pixel driving circuit may be 4T1C, 4T2C, 7T1C, and the light emitting element may be an organic light emitting diode or a quantum dot light emitting diode, and the details are not described herein. Embodiments of the present disclosure are not limited in this regard.

In the embodiment of the present disclosure, the odd group of trigger signal lines (e.g., the 1 st trigger signal line STV1) work in conjunction with the odd group of gate driving sub-circuit connection clock signal lines (e.g., the first clock signal line CLK1 or the third clock signal line CLK3) to turn off the even row shift register in conjunction with the first level or the second level of the data signal Datan so that the odd rows of the entire frame are displayed in full black or full white, the even group of trigger signal lines (e.g., the 2 nd trigger signal line STV2) work in conjunction with the even group of gate driving sub-circuit connection clock signal lines (e.g., the second clock signal line CLK2 or the fourth clock signal line CLK4) to turn off the odd row shift register in conjunction with the second level or the first level of the data signal Datan so that the even rows of the entire frame are displayed in full white or full black, that is, the odd frame is opposite to the high and low levels of the data signal Datan corresponding to the even frame, the CM value of the display picture of the H-1Line can be approximately equal to 100 percent, and the industrial test standard is met. The data signal framing display technology enables odd frames to display odd rows and even frames to display even rows, and therefore the serial problem of display pictures formed by combining bright lines and dark lines is solved.

It should be noted that the display panel provided by the embodiment of the present disclosure adopts a frame dividing driving technique (for example, the above-mentioned odd frame displays odd lines, and even frame displays even lines), is not limited to solve the problem of serial display of H-1Line, and can also be used to solve the problem of display of all bright and dark Line combinations (as shown in fig. 9C), and as long as a Line-like display is detected, performs frame dividing by blanking (for example, blanking even lines in the case of odd frame, and blanking odd lines in the case of even frame), so as to double the pixel charging time, thereby solving the serial problem; meanwhile, the resolution of the display panel can be reduced, and the refreshing frequency of the display panel is improved; for example, with the frame display, when 2 groups of gate driving sub-circuits are included, in each frame of display image driving process, in response to the trigger signals of 2 trigger signal lines, two gate scanning signal lines output the gate scanning signals simultaneously for driving the sub-pixels of 2 rows, so that the refresh frequency of the display panel can be increased, and the resolution of the display panel can be decreased, for example, the resolution of the display panel is decreased from 8K to 4K, and the refresh frequency is increased from 120Hz to 240Hz, so that the frame division technique is adopted, i.e., the data signal Datan (e.g., high level shown in fig. 7A) of the odd rows is displayed as the odd frame, the data signal Datan (e.g., low level shown in fig. 8A) of the even rows is displayed as the even frame, and the H-1line series problem of products with shorter charging time T of the sub-pixels of 1 row, such as 8K resolution, 120Hz refresh frequency, 4K, and 240Hz, can be solved, the application scene of the display panel is improved.

Fig. 9C is a schematic view of a display image with a combination of bright and dark lines according to at least one embodiment of the present disclosure. For example, as shown in fig. 9C, the original picture can be obtained by combining the display frames of the odd frames and the display frames of the even frames, and the specific driving timing is similar to the driving timing provided in fig. 7A and fig. 8A, and is not described herein again.

For example, at least one embodiment of the present disclosure further provides a display device. Fig. 10 is a schematic view of a display device according to at least one embodiment of the present disclosure. For example, as shown in fig. 10, the display device 100 includes the display panel 1 provided in any embodiment of the present disclosure.

Note that, the display device 100 in this embodiment may be: the display device comprises any product or component with a display function, such as a liquid crystal panel, a liquid crystal television, a display, an OLED panel, an OLED television, an electronic paper display device, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigator and the like. The display device 100 may further include other conventional components such as a display panel, which is not limited in this respect by the embodiments of the present disclosure.

Technical effects of the display device 100 provided by the embodiments of the present disclosure can refer to corresponding descriptions about the display panel in the above embodiments, and are not described herein again.

It should be noted that the entire structure of the display device 100 is not shown for clarity and conciseness. In order to implement the necessary functions of the display device, those skilled in the art may set other structures not shown according to the specific application scenarios, and the embodiment of the present disclosure is not limited thereto.

At least one embodiment of the present disclosure further provides a driving method of a display panel, for example, the display panel may be the display panel shown in fig. 2, or may be another display panel in the art, which is not limited in this respect.

The following description will be made by taking the driving method of the display panel shown in fig. 2 as an example, and the driving method of the display panel having other structure is similar to this and will not be described again.

For example, as shown in fig. 2, the display panel 1 includes a pixel array (e.g., located in the display region 40) including a plurality of rows and a plurality of columns of sub-pixels 410, and a plurality of gate scanning signal lines GL and a plurality of rows of sub-pixel connections 410.

Fig. 11 is a flowchart of a driving method of a display panel according to at least one embodiment of the present disclosure. For example, as shown in fig. 11, the driving method includes step S110 and step S120.

Step S110: when the pixel array is driven to display the x-th frame of picture, odd-numbered grid scanning signal lines in the plurality of grid scanning signal lines output grid scanning signals, and even-numbered grid scanning signal lines in the plurality of grid scanning signal lines output invalid grid scanning signals or do not output the grid scanning signals.

For example, in some examples, as shown in fig. 4-6B, for example, the odd row gate scan signal lines (e.g., gate scan signal lines G1, G3, G5, etc.) are also connected to the odd group gate drive sub-circuits (e.g., group 1 gate drive sub-circuits), and the even row gate scan signal lines (e.g., gate scan signal lines G2, G4, G6, etc.) are also connected to the even group gate drive sub-circuits (e.g., group 2 gate drive sub-circuits).

For example, as shown in fig. 7A, when the pixel array is driven to display an x-th frame picture, clock signals are supplied to clock signal lines (e.g., a first clock signal CLK1 and a third clock signal line CLK3) connected to the odd-numbered group (e.g., group 1) of gate driving sub-circuits to cause odd-numbered gate scanning signal lines G1, G3 of the plurality of gate scanning signal lines to output gate scanning signals, e.g., to output an active level H; the clock signal lines (e.g., the second clock signal CLK2 and the fourth clock signal CLK4) connected to the even group (e.g., group 2) gate drive sub-circuits are not supplied with a clock signal or an invalid clock signal (e.g., a low level L signal) is supplied to the clock signal lines connected to the even group gate drive sub-circuits, so that the even-numbered row gate scanning signal lines G2, G4 of the plurality of gate scanning signal lines output an invalid gate scanning signal (e.g., output an invalid level L) or do not output the gate scanning signal, thereby causing the data transistors in the sub-pixels connected to the odd-numbered row gate scanning signal lines G1, G3 to be turned on in response to the valid level H of the gate scanning signal to enable writing of the data signal Datan (e.g., having a high level), thereby causing the odd-numbered row sub-pixels in the x-th frame screen to be displayed in full white.

For example, as shown in fig. 7A, when the pixel array is driven to display the x-th frame picture, the time difference between the clock signals (e.g., the first clock signal CLK1 and the third clock signal CLK3) supplied by the adjacent two clock signal lines connected to the odd-numbered group gate driving sub-circuits is 2T (T1 or T2), for example, T is the charging time of 1 row of sub-pixels.

For example, as shown in fig. 7A, the display driving method further includes: when the pixel array is driven to display the x-th frame, an active trigger signal is supplied to a trigger signal line (e.g., the first trigger signal line STV1) connected to the odd-numbered group of gate drive sub-circuits, and an inactive trigger signal or no active trigger signal is supplied to a trigger signal line (e.g., the second trigger signal line STV2) connected to the even-numbered group of gate drive sub-circuits.

For example, as shown in fig. 7A, when the pixel array is driven to display the x-th frame picture, an active trigger signal is supplied to the first trigger signal line STV1 to cause the 1 st group gate driving sub-circuit to start outputting gate scan signals (e.g., 1 st row G1, 3 rd row G3) by odd rows, and an inactive trigger signal or no active trigger signal is supplied to the second trigger signal line STV2 to cause the 2 nd group gate driving sub-circuit to be inactive, i.e., not output gate scan signals.

For example, in the case that the display panel 1 further includes data lines electrically connected to the plurality of columns of sub-pixels, the driving method further includes: when the pixel array is driven to display the x-th frame picture, a first level is supplied to the plurality of data lines. For example, as shown in fig. 7A, when the driving pixel array displays an x-th frame picture, a data signal having a first level (e.g., a high level) is supplied to the plurality of data lines such that the odd row sub-pixels are charged in response to the odd row gate driving signals (e.g., G1, G3, etc.), the data signal having the first level is written so that full white is displayed at the odd row sub-pixels (e.g., the 1 st row sub-pixel R1 and the 3 rd row sub-pixel R3), and a specific display picture is, for example, as shown in fig. 7B.

Step S120: when the pixel array is driven to display the (x + 1) th frame, the even-row grid scanning signal lines output grid scanning signals, and the odd-row grid scanning signal lines output invalid grid scanning signals or do not output grid scanning signals.

For example, as shown in fig. 8A, when the pixel array is driven to display an x +1 th frame picture, a time difference between clock signals (e.g., the second clock signal CLK2 and the fourth clock signal CLK4) supplied from adjacent two clock signal lines connected to the even group gate drive sub-circuits is 2T.

For example, as shown in fig. 8A, the display driving method further includes: when the pixel array is driven to display an x +1 th frame, an active trigger signal is supplied to a trigger signal line (e.g., the second trigger signal line STV2) connected to the even-numbered group of gate drive sub-circuits, and an inactive trigger signal or no active trigger signal is supplied to a trigger signal line (e.g., the first trigger signal line STV1) connected to the odd-numbered group of gate drive sub-circuits.

For example, as shown in fig. 8A, when the pixel array is driven to display an x +1 th frame, an active trigger signal is supplied to the second trigger signal line STV2 to cause the 2 nd group gate driving sub-circuit to start outputting gate scan signals (e.g., 2 nd row G2, 4 th row G4) by even rows, and an inactive trigger signal or no active trigger signal is supplied to the first trigger signal line STV1 to cause the 1 st group gate driving sub-circuit to be inactive, i.e., not output gate scan signals.

For example, in the case that the display panel 1 further includes data lines electrically connected to the plurality of columns of sub-pixels, the driving method further includes: when the pixel array is driven to display the (x + 1) th frame of picture, a second level is supplied to the plurality of data lines.

For example, based on the above-described driving, an x-th frame display screen in which odd-row sub-pixels display full white and an x + 1-th frame display screen in which even-row sub-pixels display full black can be obtained; of course, even-row sub-pixels may display an x-th frame display picture that is all white and odd-row sub-pixels may display an x + 1-th frame display picture that is all black, and it is determined in real time that the odd-row and even-row display pictures of two adjacent frames are black and white display pictures, and the embodiment of the disclosure is not limited thereto.

Technical effects and working principles of the driving method of the display panel provided by the embodiment of the present disclosure may refer to corresponding descriptions about the display panel in the above embodiments, and are not described herein again.

The following points need to be explained:

(1) the drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to the common design.

(2) Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.

The above description is intended to be exemplary of the present disclosure, and not to limit the scope of the present disclosure, which is defined by the claims appended hereto.

Claims

1. A display panel includes a gate driving circuit, wherein,

the grid driving circuit comprises sequentially arranged multi-stage shift registers, the sequentially arranged multi-stage shift registers are combined into N groups of grid driving sub-circuits, and the shift registers in the N groups of grid driving sub-circuits are respectively cascaded;

the mth group of gate drive sub-circuits in the N groups of gate drive sub-circuits comprise an mth stage shift register and an m + LxN stage shift register which are cascaded,

wherein m is an integer of 1 or more and N or less, L is an integer of 1 or more, and N is an even number of 2 or more.

2. The display panel according to claim 1, further comprising N trigger signal lines respectively connected to the N groups of gate driving sub-circuits,

and the mth trigger signal line in the N trigger signal lines is connected with the input end of the mth-stage shift register.

3. The display panel according to claim 2, further comprising 4K clock signal lines,

wherein the 4K clock signal lines include a first clock signal line to a 4K clock signal line, and are respectively connected with the clock signal terminals of the multi-stage shift register to provide clock signals,

wherein K is an integer of 1 or more.

4. The display panel according to claim 3, wherein when K is 1, the 4K clock signal lines include a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line,

the first clock signal line is connected with a clock signal end of the 4n-3 th-stage shift register; the second clock signal line is connected with a clock signal end of the 4n-2 th-stage shift register; the third clock signal line is connected with a clock signal end of the 4n-1 th-stage shift register; the fourth clock signal line is connected with a clock signal end of the 4 nth stage shift register;

wherein n is an integer of 1 or more.

5. The display panel according to claim 3, wherein when K is 3, the 4K clock signal lines include a first clock signal line, a second clock signal line, a third clock signal line, a fourth clock signal line, a fifth clock signal line, a sixth clock signal line, a seventh clock signal line, an eighth clock signal line, a ninth clock signal line, a tenth clock signal line, an eleventh clock signal line, a twelfth clock signal line,

the first clock signal line is connected with a clock signal end of the 12n-11 th stage shift register; the second clock signal line is connected with a clock signal end of the 12n-10 th stage shift register; the third clock signal line is connected with a clock signal end of the 12n-9 th stage shift register; the fourth clock signal line is connected with a clock signal end of the 12n-8 th-stage shift register; the fifth clock signal line is connected with a clock signal end of the 12n-7 th stage shift register; the sixth clock signal line is connected with a clock signal end of the 12n-6 th stage shift register; the seventh clock signal line is connected with a clock signal end of the 12n-5 th stage shift register; the eighth clock signal line is connected with a clock signal end of the 12n-4 th-stage shift register; the ninth clock signal line is connected with a clock signal end of the 12n-3 th stage shift register; the tenth clock signal line is connected with a clock signal end of the 12n-2 th stage shift register; the eleventh clock signal line is connected with a clock signal end of the 12n-1 stage shift register; the twelfth clock signal line is connected with a clock signal end of the 12 nth stage shift register;

wherein n is an integer of 1 or more.

6. The display panel according to any one of claims 3 to 5, wherein when N is 2, the N trigger signal lines include a first trigger signal line and a second trigger signal line,

the first trigger signal line is connected with the input ends of the first K odd-numbered shift registers to provide a first trigger signal, and the input ends of the rest odd-numbered shift registers are connected with the output ends of the upper-level shift registers which are separated from the first odd-numbered shift registers by K-1 odd-numbered shift registers;

the second trigger signal line is connected with the input ends of the first K even-level shift registers to provide a second trigger signal, and the input ends of the rest even-level shift registers are connected with the output ends of the superior shift registers which are separated from the rest even-level shift registers by K-1 even-level.

7. The display panel of claim 6, further comprising a clock controller connected to the 4K clock signal lines and configured to:

when a clock signal is supplied to the clock signal lines connected to the odd-numbered groups of gate drive sub-circuits of the N groups of gate drive sub-circuits, the clock signal is not supplied to the clock signal lines connected to the even-numbered groups of gate drive sub-circuits of the N groups of gate drive sub-circuits or an invalid clock signal is supplied to the clock signal lines connected to the even-numbered groups of gate drive sub-circuits;

when the clock signal is supplied to the clock signal line connected to the even-numbered group of gate drive sub-circuits, the clock signal is not supplied to the clock signal line connected to the odd-numbered group of gate drive sub-circuits or the invalid clock signal is supplied to the clock signal line connected to the odd-numbered group of gate drive sub-circuits.

8. The display panel according to claim 7, wherein the time difference between the clock signals received by two adjacent clock signal lines connected to the odd-numbered group of gate drive sub-circuits is 2T,

the time difference between the clock signals received by the two adjacent clock signal lines connected with the even group of gate drive sub-circuits is 2T,

wherein T is the charging time of the sub-pixels of 1 row.

9. The display panel of claim 7, wherein the clock controller is further connected to the N trigger signal lines and configured to:

when an effective trigger signal is provided for the trigger signal line connected with the odd-numbered group of gate drive sub-circuits, an invalid trigger signal is provided or the effective trigger signal is not provided for the trigger signal line connected with the even-numbered group of gate drive sub-circuits;

and when the effective trigger signal is provided for the trigger signal line connected with the even group of gate drive sub-circuits, providing the invalid trigger signal or not providing the effective trigger signal for the trigger signal line connected with the odd group of gate drive sub-circuits.

10. The display panel according to any one of claims 1 to 5, further comprising a pixel array connected to the gate driving circuit,

the pixel array comprises a plurality of rows and a plurality of columns of sub-pixels;

odd-numbered gate drive sub-circuits in the N groups of gate drive sub-circuits are respectively connected with odd-numbered row sub-pixels,

and even groups of gate drive sub-circuits in the N groups of gate drive sub-circuits are respectively connected with even-row sub-pixels.

11. The display panel according to claim 10, further comprising a data driving circuit and a plurality of data lines,

the data driving circuit is configured to drive the data driving circuit to provide data signals to the plurality of columns of sub-pixels;

the data driving circuit is configured to:

when the pixel array is driven to display the x frame picture, providing a data signal with a first level to the data lines;

when the pixel array is driven to display the x +1 th frame picture, providing a data signal with a second level to the plurality of data lines;

wherein x is an integer of 1 or more.

12. The display panel according to claim 10, wherein the gate driving circuit is located at one side of the pixel array.

13. The display panel according to claim 10, wherein the gate driving circuits are located at two sides of the pixel array, and the shift registers located at the same stage in the gate driving circuits located at the two sides are used for driving the sub-pixels in the same row.

14. The display panel according to any one of claims 2 to 5, wherein the sequentially arranged multi-stage shift register comprises a plurality of redundant shift registers, and input terminals of N-stage redundant shift registers of the plurality of redundant shift registers are respectively connected to the N trigger signal lines to receive trigger signals.

15. A display device comprising the display panel according to any one of claims 1 to 14.