CN110189724B - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
- Publication number
- CN110189724B CN110189724B CN201910570642.8A CN201910570642A CN110189724B CN 110189724 B CN110189724 B CN 110189724B CN 201910570642 A CN201910570642 A CN 201910570642A CN 110189724 B CN110189724 B CN 110189724B
- Authority
- CN
- China
- Prior art keywords
- clock signal
- circuit
- signal line
- effective
- shift register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The embodiment of the invention provides a display panel and a display device, relates to the technical field of display, and can reduce the delay difference between an output signal of an effective GOA unit and an output signal of a Dummy GOA unit; in the display panel, the gate driving circuit includes: the shift register comprises a plurality of stages of effective shift registers which are arranged in sequence, and a virtual shift register which is positioned behind the last stage of effective shift register; the multistage effective shift register is connected with a plurality of grid lines; the clock signal line in the display panel includes: an active clock signal line and a dummy clock signal line; the effective clock signal line is connected with the virtual clock signal through the connection control circuit; the connection control circuit is configured to: before the scanning signal is output by the last stage of effective shift register, the effective clock signal line and the virtual clock signal line are controlled to be disconnected; and the effective clock signal line is controlled to be electrically connected with the virtual clock signal line under the control of the scanning signal output by the last stage of effective shift register.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display panel and a display device.
Background
In the display apparatus, the gate driving circuit functions to sequentially output on-state voltages (i.e., scan signals) of the tft (thin Film transistor) devices line by line to scan a plurality of gate lines in the display panel line by line.
The Gate driving circuit may be a Gate Driver on Array (GOA) circuit, that is, the Gate driving circuit 01 is directly integrated in the Array substrate of the display panel 001. In this case, in some GOA circuits, a plurality of cascaded stages of effective GOA units (also referred to as effective shift registers) and Dummy GOA units (i.e., Dummy GOA units, also referred to as Dummy shift registers) are included; the effective GOA unit is connected with the grid line positioned in the display area, and the Dummy GOA unit is not connected with the grid line, so that the loads of the effective GOA unit and the Dummy GOA unit are different, the difference between the Delay (Delay) of the output signal of the effective GOA unit and the Delay (Delay) of the output signal of the Dummy GOA unit is larger, and the problem of poor display pictures is easily caused during display.
Disclosure of Invention
Embodiments of the present invention provide a display panel and a display device, which can reduce a delay difference between an output signal of an effective GOA unit and an output signal of a Dummy GOA unit, and improve display uniformity.
In order to achieve the above purpose, the embodiment of the invention adopts the following technical scheme:
the embodiment of the invention provides a display panel, which comprises a plurality of grid lines and a grid driving circuit; the gate driving circuit includes: a plurality of stages of shift registers arranged in sequence; wherein, the multistage shift register includes: the shift register comprises a plurality of stages of effective shift registers which are arranged in sequence, and a virtual shift register which is positioned behind the last stage of effective shift register; the multistage effective shift register is respectively connected with the grid lines in a one-to-one correspondence manner; the display panel is also provided with a clock signal line; the clock signal line includes: an effective clock signal line connected to the multi-stage effective shift register, and a virtual clock signal line connected to the virtual shift register; the effective clock signal line is connected with the virtual clock signal through a connection control circuit; the connection control circuit is configured to: in an image display frame, before the signal output end of the last stage effective shift register outputs a scanning signal, the effective clock signal line and the virtual clock signal line are controlled to be disconnected; and under the control of the scanning signal output by the signal output end of the last stage of effective shift register, the effective clock signal line and the virtual clock signal line are controlled to be electrically connected and maintain the next image display frame.
In some embodiments, the connection control circuit comprises: the circuit comprises a first control sub-circuit, a second control sub-circuit, an energy storage sub-circuit and a connecting sub-circuit; the first control sub-circuit is connected with the signal output end, the first voltage end and the first node of the last stage effective shift register; the second control sub-circuit is connected with a control signal end, a second voltage end, the first node and a second node; the tank subcircuit is connected with the first node and the second node; the connection sub-circuit is connected with the second node, the effective clock signal line and the virtual clock signal line; before an image display frame is started, the second control sub-circuit outputs the voltage of the second voltage end to the first node and the second node under the control of the voltage of the control signal end so as to release the charges in the energy storage sub-circuit, and the connection sub-circuit disconnects the effective clock signal line from the virtual clock signal line under the control of the voltage of the second node; the first control sub-circuit outputs the voltage of the first voltage end to the first node under the control of the scanning signal output by the signal output end of the last stage effective shift register; under the control of the voltage of the first node, the energy storage sub-circuit is charged, and the voltage of the second node is controlled; the connection sub-circuit electrically connects the effective clock signal line and the virtual clock signal line under the control of the voltage of the second node and maintains the connection until the next image display frame is started.
In some embodiments, the control signal terminal is connected to a start signal terminal of the image display frame.
In some embodiments, the connection sub-circuit comprises a first transistor; the gate of the first transistor is connected to the second node, the first pole is connected to the active clock signal line, and the second pole is connected to the virtual clock signal line.
In some embodiments, the tank sub-circuit comprises a first capacitor; a first pole of the first capacitor is connected to the first node, and a second pole of the first capacitor is connected to the second node.
In some embodiments, the first control sub-circuit comprises a second transistor; the grid electrode of the second transistor is connected with the signal output end of the last stage of effective shift register, the first electrode of the second transistor is connected with the first voltage end, and the second electrode of the second transistor is connected with the first node.
In some embodiments, the second control sub-circuit comprises a third transistor and a fourth transistor; a grid electrode of the third transistor is connected with the control signal end, a first pole of the third transistor is connected with the second voltage end, and a second pole of the third transistor is connected with the first node; and the grid electrode of the fourth transistor is connected with the control signal end, the first pole of the fourth transistor is connected with the second voltage end, and the second pole of the fourth transistor is connected with the second node.
In some embodiments, a plurality of the clock signal lines are provided in the display panel; the plurality of clock signal lines are periodically connected with a plurality of stages of shift registers sequentially arranged in the gate driving circuit.
In some embodiments, the gate driving circuit is a GOA circuit.
An embodiment of the invention provides a display device, which includes the display panel.
The embodiment of the invention provides a display panel and a display device, wherein the display panel comprises a plurality of grid lines and a grid drive circuit; the gate driving circuit includes: a plurality of stages of shift registers arranged in sequence; wherein, the multistage shift register includes: the shift register comprises a plurality of stages of effective shift registers which are arranged in sequence, and a virtual shift register which is positioned behind the last stage of effective shift register; the multistage effective shift register is respectively connected with the plurality of grid lines in a one-to-one correspondence manner; the display panel is also provided with a clock signal line; the clock signal line includes: an effective clock signal line connected to the multi-stage effective shift register, and a virtual clock signal line connected to the virtual shift register; the virtual clock signal line is connected with the virtual clock signal through the connection control circuit; the connection control circuit is configured to: in an image display frame, before the signal output end of the last stage of effective shift register outputs a scanning signal, the effective clock signal line and the virtual clock signal line are controlled to be disconnected; and under the control of the scanning signal output by the signal output end of the last stage of effective shift register, the effective clock signal line and the virtual clock signal line are controlled to be electrically connected and maintained until the next image display frame comes.
In summary, in the display panel of the present invention, in the process of outputting the scanning signal to the plurality of gate lines line by the effective shift register, the connection control circuit controls the effective clock signal line and the virtual clock signal line to be disconnected from each other, and after the signal output terminal of the last stage effective shift register outputs the scanning signal, the connection control circuit controls the effective clock signal line and the virtual clock signal line to be electrically connected to each other; therefore, in the driving process, the effective shift register does not need to load a virtual clock signal line part, so that the delay of the output signal of the effective shift register is reduced, although the virtual shift register does not need to load a grid line, the effective clock signal line part needs to be loaded, which is equivalent to increasing the delay of the output signal of the virtual shift register, so that the delay difference between the output signal of the effective shift register (effective GOA unit) and the output signal of the virtual shift register (Dummy GOA unit) is reduced, the relative uniformity of the reset signal of each level of shift register in the gate driving circuit (GOA circuit) is improved, and the picture quality of the display panel is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 4 is a schematic partial structure diagram of a GOA circuit according to an embodiment of the present invention;
FIG. 5 is a timing control diagram of a GOA unit according to an embodiment of the present invention;
FIG. 6 is a waveform diagram of an ideal Gate signal and Data signal;
FIG. 7 is a waveform diagram of a Gate signal and a Data signal in practice;
FIG. 8 is a waveform diagram of a Gate signal and a Data signal in practice;
FIG. 9 is a waveform diagram of a Gate signal and a Data signal in practice;
fig. 10 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 11 is a schematic structural diagram of a connection control circuit according to an embodiment of the present invention;
fig. 12 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 13 is a schematic timing control diagram of a connection control circuit according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Unless otherwise defined, technical or scientific terms used in the embodiments of the present application should have the ordinary meaning as understood by those having ordinary skill in the art to which the present invention belongs. The use of "first," "second," and similar language in the embodiments of the present invention does not denote any order, quantity, or importance, but rather the terms "first," "second," and similar language are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
Further, in the present application, directional terms such as "upper," "lower," "left," "right," "horizontal" and "vertical" are defined with respect to the schematically-disposed orientation of components in the drawings, and it is to be understood that these directional terms are relative concepts that are used for descriptive and clarity purposes and that will vary accordingly depending on the orientation in which the components are disposed in the drawings.
An embodiment of the present invention provides a display device, which may be a television, a mobile phone, a computer, a notebook computer, a tablet computer, a Personal Digital Assistant (PDA), a vehicle-mounted computer, or the like. The display device comprises a frame, a display panel arranged in the frame, a circuit board, a display driving IC and other electronic accessories.
The display panel may be: a Liquid Crystal Display (LCD), an Organic Light Emitting Diode (OLED), a Quantum Dot Light Emitting Diode (QLED), a Micro Light Emitting Diode (Micro LED), and so on, which are not limited in this invention.
The following embodiments of the present invention are all described by taking the above-described display panel as an example of a liquid crystal display panel.
As shown in fig. 1, the display panel 001 includes: a display area 1 (AA, AA area for short; also called effective display area) and a peripheral area 2 arranged around the display area 1.
The display panel 001 includes a plurality of color sub-pixels (sub-pixels) P in the display area 1, the plurality of color sub-pixels including at least a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel, the first color, the second color, and the third color being three primary colors (e.g., red, green, and blue).
For convenience of description, the plurality of sub-pixels P are described as an example in a matrix arrangement. In this case, the subpixels P arranged in one row in the horizontal direction X are referred to as same row subpixels; the subpixels P arranged in one row in the vertical direction Y are referred to as the same column of subpixels.
As shown in fig. 2, in the display panel 001, a pixel circuit S including a transistor T and a liquid crystal capacitor C is provided in each sub-pixel P. The two electrode plates of the liquid crystal capacitor C are respectively composed of a pixel electrode and a common electrode. The gates of the transistors T of the pixel circuits S in the same row are connected to the same Gate Line (Gate Line) GL, and the gates (for example, the sources) of the transistors T of the pixel circuits S in the same column are connected to the same Data Line (Data Line) DL.
Referring to fig. 1 or 2, the display panel 001 is further provided with a gate driving circuit 01 connected to the gate lines GL and a data driving circuit 02 connected to the data lines DL in the peripheral region 2. In some embodiments, the gate driving circuit 01 may be disposed at a side in an extending direction of the gate line GL, and the data driving circuit 02 may be disposed at a side in an extending direction of the data line DL; the pixel circuit S in the display panel 001 is driven to display an image.
In some embodiments, in order to reduce the manufacturing cost of the display panel and narrow the frame width of the display device, the Gate driving circuit 01 may be a Gate Driver on Array (GOA) circuit, that is, the Gate driving circuit 01 is directly integrated in the Array substrate of the display panel 001. In the following embodiments, the gate driving circuit 01 is used as a GOA circuit as an example.
It should be noted that fig. 1 and 2 are only schematic, and the display panel 001 is described by taking, as an example, a case where the GOA circuit (01) is provided on one side of the peripheral region 2, and the gate lines GL are sequentially driven from one side row by row, that is, one-side driving. In other embodiments, the display panel 001 may be configured to separately provide the GOA circuits (01) along two sides of the extending direction of the gate lines GL in the peripheral region 2, and sequentially drive the gate lines GL from two sides line by line at the same time through two gate driving circuits, that is, simultaneously drive the gate lines GL from two sides. In other embodiments, the display panel 001 may be provided with the GOA circuits (01) respectively along two sides of the extending direction of the gate lines GL in the peripheral region 2, and the gate lines GL are sequentially driven by the two GOA circuits (01) alternately from two sides row by row, that is, double-sided cross driving. The following examples of the present invention are all described by taking a single-side drive as an example.
On this basis, as shown in fig. 3, a plurality of gate lines GL are provided in the display region 1 of the display panel 001; in the drawings and the following, N gate lines are taken as examples, and the N gate lines GL are respectively denoted as G1, G2 … … G (N). In addition, the GOA circuit (i.e., the gate driving circuit 01) in the peripheral region 2 of the display panel 001 includes N +2 shift registers RS (which may also be referred to as GOA cells) sequentially disposed, where the N +2 shift registers RS are respectively denoted as RS1, RS2 … … RS (N), RS (N +1), and RS (N + 2).
The N +2 stage shift registers (RS1, RS2 … … RS (N), RS (N +1), RS (N +2)) include: the N stages of effective shift registers 11 (i.e., effective GOA units), i.e., RS1 and RS2 … … RS (N), are sequentially arranged, and the N stages of effective shift registers (RS1 and RS2 … … RS (N)) are respectively connected to the N gate lines (G1 and G2 … … G (N)) in the display region 1 in a one-to-one correspondence.
The N +2 stage shift register (RS1, RS2 … … RS (N), RS (N +1), RS (N +2)) further includes: the Dummy shift register 12 (also referred to as Dummy GOA unit, Dummy GOA unit) located after the last stage of the effective shift register 11 (i.e. RS (N)), namely RS (N), RS (N + 1).
It should be noted that fig. 3 is only schematic, and the example that the dummy shift register 12 includes two shift registers (RS (N), RS (N +1)) is taken for illustration, the present invention is not limited thereto, and in some embodiments, the dummy shift register 12 may also include one-stage, three-stage, and four-stage shift registers.
On this basis, as can be understood by those skilled in the art, referring to fig. 3, for the shift register (GOA unit) in the above-mentioned GOA circuit (01), a clock signal terminal CK is provided inside; the display panel 001 is provided with a clock signal line CLK at the side where the GOA circuit (01) is provided in the peripheral region 2; the clock signal terminal CK of the shift register is connected to a clock signal line CLK. The scanning signal output by the shift register is provided by a clock signal input by a clock signal line CLK. In the peripheral region 2, the display panel 001 is further provided with other related signal lines, such as a high-level voltage signal line VGH, a low-level voltage signal line VGL, a start signal line STV, and the like shown in fig. 3, at a side where the GOA circuit (01) is provided. In addition, for the sake of clarity of the present invention, the high level voltage terminal, the low level voltage terminal, and the start signal terminal are respectively denoted as VGH, VGL, and STV hereinafter, and should not be construed as unclear.
Of course, in some embodiments, the display panel 001 may also be provided with a clock signal line CLK of another control class, that is, the clock signal provided by the clock signal line CLK is not used for providing the scan signal, and the clock signal line CLK of the control class provides the clock signal of the relevant control class to the shift register; that is, the clock signal line according to the present invention is not limited to the clock signal line for supplying the scanning signal, and may include a clock signal line CLK for controlling the clock signal line connected to the GOA circuit (01).
In addition, the number of the clock signal lines CLK connected to the shift register in the GOA circuit (01) is not limited in the present invention, and may be one or a plurality of. For example, in some embodiments, as shown in fig. 3, in the display panel 001, one GOA circuit (01) is connected to two clock signal lines CLK; the two clock signal lines CLK are respectively represented as: a first clock signal line CLK1 and a second clock signal line CLK 2. In this case, as shown in fig. 3, the clock signal terminal CK of the shift registers sequentially arranged in the GOA circuit (01) is periodically connected to the first clock signal line CLK1 and the second clock signal line CLK 2.
In addition, as shown in fig. 3, in the shift register of the GOA circuit (01), a signal Input terminal Input (hereinafter, abbreviated as Iput in the drawings), a signal Output terminal Output (hereinafter, abbreviated as Oput in the drawings), and a Reset signal terminal Reset (hereinafter, abbreviated as RST in the drawings) are further provided, and the circuit structures of the shift registers of the respective stages in the GOA circuit (01) are the same. For example, the arrangement of the signal terminals (Oput, RST, CK, VGL) in the local circuit of the shift register shown in fig. 4 may be referred to, but of course, the arrangement of the local circuit of fig. 4 is not shown for the other relevant signal terminals (Iput, VGH), and the like.
On this basis, for the cascade connection condition between the shift registers of the respective stages in the GOA circuit (01), referring to fig. 3, except that the signal input terminal Iput (exemplarily shown as RS1 in fig. 3) of the shift register of the previous stage or the plurality of stages is connected to the start signal terminal STV (also referred to as a start voltage terminal), except for the shift register (e.g. RS (1) in fig. 3) connected to the start signal terminal STV, the signal input terminal Iput of any one of the shift registers of the other stages is connected to the signal output terminal Oput of the shift register located at the previous stage (which may or may not be adjacent); the reset signal end RST of the last stage or multi-stage shift register is independently arranged or connected with the initial signal end STV; except for the last stage or stages of shift register, the reset signal terminal RST of any stage of shift register is connected to the signal output terminal Oput of the shift register located at the subsequent stage (which may or may not be adjacent).
Illustratively, as shown in fig. 3 (corresponding to the timing control signal referring to fig. 5), the signal input terminal Iput of the first stage shift register RS1 is connected to the start signal terminal STV, and the signal input terminal Iput of any stage shift register except the first shift register RS1 is connected to the signal output terminal Oput of the shift register located at the stage before it; except for the last stage of shift register RS (N +2), the reset signal end RST of any stage of shift register is connected with the signal output end Oput of the shift register at the next stage; the reset signal terminal RST of the last stage shift register RS (N +2) is connected through the reset control circuit 20. The reset control circuit 20 is configured to generate a reset signal of the last stage shift register RS (N + 2).
For example, in some embodiments, as shown in fig. 3, the reset control circuit 20 may include a control transistor M ', and a gate of the control transistor M' is connected to the start signal terminal STV, a first pole of the control transistor M 'is connected to the low level voltage terminal VGL, and a second pole of the control transistor M' is connected to the reset signal terminal RST of the last stage shift register RS (N +2), so that the voltage of the low level voltage terminal VGL is output as the reset signal to the reset signal terminal RST of the last stage shift register RS (N +2) under the control of the start signal terminal STV.
On the basis, referring to fig. 2 and 3, in the process of displaying on the display panel 001, the effective shift registers (RS1, RS2 … … RS (n)) of the GOA circuit (01) output scanning signals (which may also be referred to as Gate signals) to the Gate lines GL (G1, G2 … … G (n)) located in the display area 1 line by line through the signal output terminals Oput, and when scanning to one of the Gate lines GL, the Data driving circuit 02 inputs pixel Data voltages (i.e., Data signals) to the pixel driving circuits S connected to the one of the Gate lines GL, so as to charge the pixel Data voltages. However, since the dummy shift registers (RS (N), RS (N +1)) are not connected to the gate lines GL, the dummy shift registers (RS (N), RS (N +1)) do not need to output the scanning signal to the gate lines GL, and only need to output the reset signal to the reset signal terminals RST of the effective shift registers (RS (N-1), RS (N)) located at the preceding stage and connected thereto during the scanning.
In this case, taking the example that the Data signal writing time is 1H and the Gate signal pulse width is 1H, the ideal waveform timing for the Data signal and the Gate signal is as shown in fig. 6, and the Data signal is written while the Gate signal is output. However, in practice, as shown in fig. 7, there is a certain Delay (Delay) between the Gate signal and the Data signal, and the falling Delay time Tf of the Gate signal has a Delay time t with respect to the effective Data signal (i.e., the Data signal with the largest amplitude), and when the Delay time t is large, the Data signal may charge the pixel driving circuit S of the next row, so that the risk of mischarging is likely to occur. In this case, as shown in fig. 8, in the related art, a delay time t1 (the delay time t1 may also be referred to as GOE time, that is, Gate Output Enable time) of the Data signal relative to the Gate signal may be artificially set to ensure that the Data signal is input to the pixel driving circuit S of the row for charging when the Gate signal scans to the Gate line of the row, so as to reduce the risk of mis-charging.
Based on this, referring to fig. 10, in the GOA circuit (01) of the related art, the effective shift register 11(RS1, RS2 … … RS (N)) is connected to the gate line GL (G1, G2 … … G (N)) located in the display area 1, and the dummy shift register 12(RS (N +1), RS (N +2)) is not connected to the gate line GL; the effective shift registers 11(RS1, RS2 … … RS (N)) and the dummy shift registers 12(RS (N), RS (N +1)) are connected to a clock signal line CLK of an integral structure, wherein the output signals of the effective shift registers 11 and the dummy shift registers 12 are substantially identical in signal delay caused by a load clock signal line, and the output signal of the effective shift register 11 needs an additional load gate line GL, so that the load of the effective shift register 11 is larger than the load of the dummy shift register 12, that is, the falling delay time Tf of the output signal of the dummy shift register 12 is smaller than the falling delay time Tf of the output signal of the effective shift register 11, in which case, the preceding effective shift register (RS (N-1) ("Oput") connected to the signal output terminals Oput of the dummy shift registers (RS (N +1), RS (N +2)) is connected to the signal output terminals of the dummy shift registers (RS (, The falling delay time Tf of the reset signal received by the reset signal terminal RST of rs (n)) is shorter than the falling delay time Tf of the reset signal received by the reset signal terminals RST of the other active shift registers (i.e., the Gate signal is turned off rapidly). In this case, referring to fig. 9, the Gate signals output from the preceding effective shift registers (RS (N-1) and RS (N)) connected to the signal output terminals Oput of the dummy shift registers (RS (N +1) and RS (N +2)) are turned off earlier than the corresponding Data signals by a longer time (t2), so that the Gate lines connected to the preceding effective shift registers (RS (N-1) and RS (N)) are turned on for a short time, and the pixel driving circuit S connected thereto is short in charging time, thereby causing a problem of poor image quality.
In contrast, in the display panel 001 according to the embodiment of the present invention, as shown in fig. 3, the clock signal line CLK connected to the shift register in the GOA circuit (01) is configured as an independent two-part structure; one part of the method is as follows: the effective clock signal line 21 connected to the multi-stage effective shift register 11 has, in the other part: a virtual clock signal line 22 connected to the virtual shift register 12; and an active clock signal line 21 in the clock signal line CLK is connected to a dummy clock signal 22 through the connection control circuit 10.
The above-described connection control circuit 10 is configured to: in an image display Frame (Frame), before the signal output terminal Oput of the last stage effective shift register RS (N) outputs a scanning signal, the effective clock signal line 21 and the virtual clock signal line 22 are controlled to be disconnected; and under the control of the scanning signal of RS (N) output by the signal output end of the last stage effective shift register RS (N), the effective clock signal line 21 and the virtual clock signal line 22 are controlled to be electrically connected and maintained until the next image display frame arrives.
As can be seen from the above, in the display panel of the present invention, in the process of outputting the scan signals to the gate lines (G1, G2 … … G (n)) row by the effective shift registers (RS1, RS2 … … RS (n)), the connection control circuit 10 controls the effective clock signal line 21 and the dummy clock signal line 22 to be disconnected from each other, and after outputting the scan signal at the signal output terminal of the last stage of effective shift register RS (n), the connection control circuit 10 controls the effective clock signal line 21 and the dummy clock signal line 22 to be electrically connected to each other, so that in the display driving process, the effective shift register 11 does not need to load the dummy clock signal line 22, which is equivalent to reducing the delay of the output gate line signal of the effective shift register 11, and the dummy shift register 12 does not need to load GL, but needs to load the effective clock signal line 21, which is equivalent to increasing the delay of the output signal of the dummy shift register 12, therefore, the delay difference between the output signal of the effective shift register 11 (effective GOA unit) and the output signal of the Dummy shift register 12(Dummy GOA unit) is reduced, so that the relative uniformity of the reset signals of the shift registers in the gate driver circuit 01(GOA circuit) is improved, and the picture quality of the display panel is improved.
The specific configuration of the connection control circuit 10 will be further described below.
In some embodiments, as shown in fig. 11, the connection control circuit 10 may include: a connection sub-circuit 101, a first control sub-circuit 102, a second control sub-circuit 103, a tank sub-circuit 104.
The connection sub-circuit 101 is connected to the second node P2, the active clock signal line 21, and the dummy clock signal line 22; of course, the effective clock signal line 21 and the dummy clock signal line 22 are two portions independently provided in the same clock signal line CLK.
For example, in some implementations, as shown in fig. 11, the connection sub-circuit 101 may include a first transistor M1. The gate of the first transistor M1 is connected to the second node P2, the first pole of the first transistor M1 is connected to the active clock signal line 21, and the second pole of the first transistor M1 is connected to the dummy clock signal line 22.
The first control sub-circuit 102 is connected to a signal output terminal (hereinafter referred to as "oput (n)" in fig. 11) of the last stage of the effective shift register rs (n), a first voltage terminal V1, and a first node P1.
For example, in some embodiments, as shown in fig. 11, the first control sub-circuit 102 may include a second transistor M2. The gate of the second transistor M2 is connected to the signal output terminal oput (n) of the last stage of the effective shift register rs (n), the first pole of the second transistor M2 is connected to the first voltage terminal V1, and the second pole of the second transistor M2 is connected to the first node P1.
In some embodiments, referring to fig. 11, the first voltage terminal V1 is a high voltage terminal VGH. In this case, referring to fig. 12, the first voltage terminal V1 may be connected to the aforementioned high level voltage signal line (VGH).
The second control sub-circuit 103 is connected to a control signal terminal R1, a second voltage terminal V2, a first node P1, and a second node P2.
For example, the second control sub-circuit 103 may include a third transistor M3 and a fourth transistor M4. The gate of the third transistor M3 is connected to the control signal terminal R1, the first pole of the third transistor M3 is connected to the second voltage terminal V2, and the second pole of the third transistor M3 is connected to the first node P1. A gate of the fourth transistor M4 is connected to the control signal terminal R1, a first pole of the fourth transistor M4 is connected to the second voltage terminal V2, and a second pole of the fourth transistor M4 is connected to the second node P2.
In some embodiments, referring to fig. 11, the second voltage terminal V2 is a low voltage terminal VGL. In this case, the second voltage terminal V2 may be connected to the aforementioned low level voltage signal line (VGL) with reference to fig. 12.
In some embodiments, referring to fig. 11 and 12, the control signal terminal R1 is connected to the start signal terminal STV of the image display frame, so that the second control sub-circuit 103 is controlled by the start voltage of the start signal terminal STV. For example, the third and fourth transistors M3 and M4 are turned on under the control of the start voltage of the start signal terminal STV, and the voltage (e.g., a low level voltage) of the second voltage terminal V2 is output to the first and second nodes P1 and P2.
The energy storage sub-circuit 104 is connected to a first node P1 and a second node P2.
For example, in some embodiments, as shown in fig. 11, the energy storage sub-circuit 104 may include a first capacitor C1. The first pole of the first capacitor C1 is connected to the first node P1, and the second pole of the first capacitor C1 is connected to the second node P2.
Based on this, before an image display frame is turned on, the second control sub-circuit 103 outputs the voltage of the second voltage terminal V2 to the first node P1 and the second node P2 under the control of the voltage of the control signal terminal R1 to discharge the charge in the tank sub-circuit 104, and the connection sub-circuit 101 disconnects the active clock signal line 21 from the virtual clock signal line 22 under the control of the voltage of the second node P2. When the signal output terminal oput (n) of the last stage of the effective shift register rs (n) outputs the scan signal, the first control sub-circuit 102 outputs the voltage of the first voltage terminal V1 to the first node P1 under the control of the scan signal; the tank sub-circuit 104 charges under the control of the voltage at the first node P1 and controls the voltage at the second node P2; the connection sub-circuit electrically connects the active clock signal line 21 and the dummy clock signal line 22 under the control of the voltage at the second node P2, and maintains the connection until the next image display frame is turned on.
That is, in an image display frame, before the scan signal is outputted from the signal output terminal oput (n) of the last stage of the effective shift register rs (n), the effective clock signal line 21 and the dummy clock signal line 22 are disconnected under the control of the second control sub-circuit 103, the energy storage sub-circuit 104, and the connection sub-circuit 101, and after the scan signal is outputted from the signal output terminal oput (n) of the last stage of the effective shift register rs (n), the effective clock signal line 21 and the dummy clock signal line 22 are electrically connected under the control of the first control sub-circuit 102, the energy storage sub-circuit 104, and the connection sub-circuit 101.
The following describes a method of driving the connection control circuit 10 with reference to a transistor and a capacitor, with reference to the timing charts of the connection control circuit 10 and fig. 13 shown in fig. 11.
Before an image display frame F is turned on, the third transistor M3 and the fourth transistor M4 are turned on under the control of a start signal terminal STV, a low level Voltage (VGL) of a second voltage terminal V2 is outputted to the first node P1 and the second node P2 to discharge charges in the first capacitor C1, and the first transistor M1 is turned off under the control of a low level Voltage (VGL) of a second node P2, so that the effective clock signal line 21 and the virtual clock signal line 22 are disconnected from each other and maintained until the signal output terminal oput (n) of the last stage effective shift register rs (n) outputs a scan signal; that is, in the Display phase of an image Display frame F, before the signal output terminal oput (n) of the last stage of the effective shift register rs (n) outputs the scan signal (during the period T1 in fig. 13), the effective clock signal line 21 and the dummy clock signal line 22 are kept disconnected from each other, and they are not electrically connected.
When the signal output terminal oput (n) of the last stage of the effective shift register rs (n) outputs the scan signal, under the control of the scan signal, the second transistor M2 is turned on, the high level Voltage (VGH) of the first voltage terminal V1 is output to the first node P1, and under the control of the high level Voltage (VGH) of the first node P1, the first capacitor C1 charges, and under the bootstrap coupling action of the first capacitor C1, the voltage of the second node P2 is raised to the high level voltage; under the control of the high-level voltage of the second node P2, the first transistor M1 is turned on, so that the effective clock signal line 21 and the dummy clock signal line 22 are electrically connected and maintained through the first capacitor C1 until the next image display frame F is turned on; that is, in the non-display period Blanking of one image display frame F, the electric connection state is maintained between the effective clock signal line 21 and the dummy clock signal line 22.
The transistor in the invention may be an enhancement transistor or a depletion transistor; the first electrode of the transistor may be a source and the second electrode may be a drain, or the first electrode of the transistor may be a drain and the second electrode may be a source, which is not limited in the present invention.
In the above embodiments of the present invention, the turning-on and turning-off (conducting and turning-off) processes of the transistors are described by taking all transistors as N-type transistors as an example; in the embodiment of the invention, the transistors can also be of a P type, and when all the transistors are of the P type, all the control signals need to be inverted.
Those of ordinary skill in the art will understand that: all or part of the steps for implementing the method embodiments may be implemented by hardware related to program instructions, and the program may be stored in a computer readable storage medium, and when executed, the program performs the steps including the method embodiments; and the aforementioned storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (10)
1. A display panel comprises a plurality of grid lines and a grid drive circuit;
the gate driving circuit includes: a plurality of stages of shift registers arranged in sequence; wherein, the multistage shift register includes: the shift register comprises a plurality of stages of effective shift registers which are arranged in sequence, and a virtual shift register which is positioned behind the last stage of effective shift register;
the multistage effective shift register is respectively connected with the grid lines in a one-to-one correspondence manner;
the display panel is also provided with a clock signal line; the clock signal line includes: an effective clock signal line connected to the multi-stage effective shift register, and a virtual clock signal line connected to the virtual shift register; the effective clock signal line is connected with the virtual clock signal through a connection control circuit;
the connection control circuit is configured to: in an image display frame, before the signal output end of the last stage effective shift register outputs a scanning signal, the effective clock signal line and the virtual clock signal line are controlled to be disconnected; and under the control of the scanning signal output by the signal output end of the last stage of effective shift register, the effective clock signal line and the virtual clock signal line are controlled to be electrically connected and maintain the next image display frame.
2. The display panel according to claim 1, wherein the connection control circuit comprises: the circuit comprises a first control sub-circuit, a second control sub-circuit, an energy storage sub-circuit and a connecting sub-circuit;
the first control sub-circuit is connected with the signal output end, the first voltage end and the first node of the last stage effective shift register;
the second control sub-circuit is connected with a control signal end, a second voltage end, the first node and a second node;
the tank subcircuit is connected with the first node and the second node;
the connection sub-circuit is connected with the second node, the effective clock signal line and the virtual clock signal line;
before an image display frame is started, the second control sub-circuit outputs the voltage of the second voltage end to the first node and the second node under the control of the voltage of the control signal end so as to release the charges in the energy storage sub-circuit, and the connection sub-circuit disconnects the effective clock signal line from the virtual clock signal line under the control of the voltage of the second node;
the first control sub-circuit outputs the voltage of the first voltage end to the first node under the control of the scanning signal output by the signal output end of the last stage effective shift register; under the control of the voltage of the first node, the energy storage sub-circuit is charged, and the voltage of the second node is controlled; the connection sub-circuit electrically connects the effective clock signal line and the virtual clock signal line under the control of the voltage of the second node and maintains the connection until the next image display frame is started.
3. The display panel according to claim 2,
and the control signal end is connected with the initial signal end of the image display frame.
4. The display panel according to claim 2, wherein the connection sub-circuit includes a first transistor; the gate of the first transistor is connected to the second node, the first pole is connected to the active clock signal line, and the second pole is connected to the virtual clock signal line.
5. The display panel according to claim 2,
the energy storage sub-circuit comprises a first capacitor; a first pole of the first capacitor is connected to the first node, and a second pole of the first capacitor is connected to the second node.
6. The display panel according to claim 2,
the first control sub-circuit comprises a second transistor; the grid electrode of the second transistor is connected with the signal output end of the last stage of effective shift register, the first electrode of the second transistor is connected with the first voltage end, and the second electrode of the second transistor is connected with the first node.
7. The display panel according to claim 2,
the second control sub-circuit comprises a third transistor and a fourth transistor;
a grid electrode of the third transistor is connected with the control signal end, a first pole of the third transistor is connected with the second voltage end, and a second pole of the third transistor is connected with the first node; and the grid electrode of the fourth transistor is connected with the control signal end, the first pole of the fourth transistor is connected with the second voltage end, and the second pole of the fourth transistor is connected with the second node.
8. The display panel according to any one of claims 1 to 7,
a plurality of clock signal lines are arranged in the display panel;
the plurality of clock signal lines are periodically connected with a plurality of stages of shift registers sequentially arranged in the gate driving circuit.
9. The display panel according to any one of claims 1 to 7, wherein the gate driving circuit is a GOA circuit.
10. A display device characterized by comprising the display panel according to any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910570642.8A CN110189724B (en) | 2019-06-27 | 2019-06-27 | Display panel and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910570642.8A CN110189724B (en) | 2019-06-27 | 2019-06-27 | Display panel and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110189724A CN110189724A (en) | 2019-08-30 |
| CN110189724B true CN110189724B (en) | 2021-01-26 |
Family
ID=67723942
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910570642.8A Active CN110189724B (en) | 2019-06-27 | 2019-06-27 | Display panel and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110189724B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110503921B (en) * | 2019-09-18 | 2020-11-10 | 京东方科技集团股份有限公司 | Gate drive circuit, drive method thereof and display device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100428319C (en) * | 2002-04-08 | 2008-10-22 | 三星电子株式会社 | Liquid crystal display device |
| WO2003104879A2 (en) * | 2002-06-01 | 2003-12-18 | Samsung Electronics Co., Ltd. | Shift register, liquid crystal display device having the shift register and method of driving scan lines using the same |
| CN105448259B (en) * | 2015-12-25 | 2018-03-30 | 上海中航光电子有限公司 | Gate drivers and display panel |
-
2019
- 2019-06-27 CN CN201910570642.8A patent/CN110189724B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN110189724A (en) | 2019-08-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11315471B2 (en) | Shift register unit, driving device, display device and driving method | |
| CN110060645B (en) | Shifting register and driving method thereof, grid driving circuit and display device | |
| US10930360B2 (en) | Shift register, driving method thereof, gate driving circuit, and display device | |
| US11308872B2 (en) | OLED display panel for minimizing area of internalconnection line part for connecting GIP dirving circuit located in active area and OLED display device comprising the same | |
| EP3828875A1 (en) | Shift register unit and driving method therefor, gate driving circuit and display apparatus | |
| EP3571691B1 (en) | Shift register unit, gate drive circuit and method of driving the same | |
| CN110415664B (en) | Shift register and driving method thereof, gate drive circuit and display device | |
| US7839374B2 (en) | Liquid crystal display device and method of driving the same | |
| KR101108172B1 (en) | Scan driver and organic light emitting display | |
| US20100315403A1 (en) | Display device, method for driving the display device, and scan signal line driving circuit | |
| US20160372078A1 (en) | Goa circuit and a driving method thereof, a display panel and a display apparatus | |
| EP3229226A1 (en) | Shift register unit, driving method therefor, gate drive circuit, and display device | |
| US20210358362A1 (en) | Shift register unit and driving method thereof, gate drive circuit and display device | |
| US20220036788A1 (en) | Shift register and method for driving the same, gate driving circuit, and display apparatus | |
| US10998068B2 (en) | Shift register circuit and driving method therefor, and gate drive circuit and display device | |
| US10796780B2 (en) | Shift register unit and driving method thereof, gate driving circuit and display apparatus | |
| CN111223449B (en) | Display panel, driving method thereof and display device | |
| WO2019227947A1 (en) | Array substrate, display panel, and display device | |
| CN109817182B (en) | Display panel and display device | |
| CN109166542B (en) | Shifting register unit, driving method, grid driving circuit and display device | |
| CN109377948B (en) | Shift register and driving method thereof, grid driving circuit and display device | |
| CN113192551A (en) | Shift register and driving method thereof, gate drive circuit and display device | |
| CN111610676A (en) | Display panel, driving method thereof and display device | |
| CN110189724B (en) | Display panel and display device | |
| CN109903718B (en) | Shifting register and driving method thereof, grid driving circuit and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |