CN111610676A - Display panel, driving method thereof and display device - Google Patents
Display panel, driving method thereof and display device Download PDFInfo
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- CN111610676A CN111610676A CN202010568237.5A CN202010568237A CN111610676A CN 111610676 A CN111610676 A CN 111610676A CN 202010568237 A CN202010568237 A CN 202010568237A CN 111610676 A CN111610676 A CN 111610676A
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- 239000003990 capacitor Substances 0.000 claims abstract description 7
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- 230000008569 process Effects 0.000 description 9
- 230000005669 field effect Effects 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
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- 239000010409 thin film Substances 0.000 description 3
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- 230000005540 biological transmission Effects 0.000 description 1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- Engineering & Computer Science (AREA)
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- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Nonlinear Science (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- Optics & Photonics (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention provides a display panel, a driving method thereof and a display device, wherein the display panel comprises: the display area is provided with a through hole, and the non-display area surrounds the display area; the display area comprises data lines and grid lines which are arranged in a crossed manner; the non-display area comprises a control switch and a driving chip electrically connected with each data line; the data line with part of the data lines disconnected by the through holes is electrically connected with the data line with part of the data lines not disconnected by the through holes through the control switches, all the control switches are electrically connected with the driving chip, the control switches are used for storing first data signals provided by the driving chip in parasitic capacitors of the data lines with part of the data lines disconnected by the through holes when in an on state, the driving chip is used for providing second data signals to the data lines with part of the data lines not disconnected by the through holes when the control switches are in an off state, and the parasitic capacitors are used for maintaining the data lines with part of the data lines disconnected by the through holes at the first data signals.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a display panel, a driving method thereof, and a display device.
Background
At present, display devices such as mobile phones and tablet computers often need to reserve space for electronic devices such as commonly used front cameras, mechanical keys and fingerprint modules. In order to increase the screen occupation ratio, a transparent non-display area (i.e., a pixel blank area) without pixels can be formed in the display area of the display panel to accommodate the electronic device.
In the prior art, as shown in fig. 1, a schematic structural diagram of a display device often needs to arrange a large number of data lines V around a blank area W of a pixel to provide data signals for pixels px in an area U of the blank area W away from a driving IC, however, the frame of the blank area W is wider due to the large number of data lines, which affects the display quality of the display device.
Therefore, how to improve the display quality of the display device is an extremely important technical problem.
Disclosure of Invention
The invention provides a display panel, a driving method thereof and a display device, which are used for improving the display quality of the display device.
In a first aspect, an embodiment of the present invention provides a display panel, including:
the display device comprises a display area provided with a through hole and a non-display area surrounding the display area;
the display area comprises data lines and grid lines which are arranged in a crossed manner;
the non-display area comprises a control switch and a driving chip electrically connected with each data line;
wherein a part of the data lines are disconnected by the via holes, a part of the data lines which are disconnected by the via holes and a part of the data lines which are not disconnected by the via holes are electrically connected through the control switches, and all the control switches are electrically connected with the driving chip, the control switches are used for storing a first data signal provided by the driving chip in a parasitic capacitance of the data lines which are partially disconnected by the via holes when in an on state, the driving chip is used for providing a second data signal to the data lines which are partially not disconnected by the via holes when in an off state, the parasitic capacitance is used for maintaining the data lines which are partially disconnected by the via holes at the first data signal, and the first data signal is used for driving a first pixel on the data lines which are partially disconnected by the via holes, the second data signal is used for driving a second pixel on the data line, a part of which is not disconnected by the through hole.
In one possible implementation manner, the data line partially disconnected by the through hole is electrically connected with the data line partially not disconnected by the through hole through the control switch.
In a possible implementation manner, the non-display area includes shift registers respectively disposed at two sides of each row of the gate lines, one shift register is electrically connected to one gate line, and when the shift registers at two sides of the gate lines electrically connected to the first pixel and the second pixel are in an on state, the shift registers charge the first pixel according to the first data signal and charge the second pixel according to the second data signal.
In a possible implementation manner, in a charging period, a charging duration of a gate line where the first pixel and the second pixel are located is a first duration, where the first duration at least includes an on duration of the control switch and an on duration of the shift register, and the on duration of the shift register is less than the first duration.
In a possible implementation manner, the shift registers on both sides of the gate line where each pixel on the data line is located on a part of the data line disconnected by the through hole are electrically connected to a redundant shift register, and the redundant shift register is used for transmitting a row scanning signal required by the gate line on a current row to the shift register electrically connected to the gate line on the current row.
In a possible implementation manner, in one charging period, the charging time of the shift register to the first pixel and the charging time of the shift register to the second pixel are both the first time length.
In a second aspect, an embodiment of the present invention provides a method for driving a display panel, including:
outputting, by the driving chip, the first data signal for driving the first pixel on the data line partially disconnected by the via hole;
controlling the switch to be in the conducting state through the driving chip, and storing the first data signal in a parasitic capacitance of the data line, wherein part of the parasitic capacitance is disconnected by the through hole;
and controlling the switch to be in the cut-off state through the driving chip, outputting the second data signal for driving part of the second pixels on the data line which is not disconnected by the through hole, and maintaining the part of the data line which is disconnected by the through hole at the first data signal through the parasitic capacitor.
In one possible implementation, the method further includes:
and when the shift registers at two sides of the grid line electrically connected with the first pixel and the second pixel are in an open state, charging the first pixel according to the first data signal through the shift registers, and charging the second pixel according to the second data signal.
In a possible implementation manner, the charging, by the shift register, the first pixel according to the first data signal and the second pixel according to the second data signal includes:
and in a charging period, charging the first pixel and the second pixel for a second time length through the shift register, wherein the second time length is less than a first time length, and the first time length at least comprises the starting time length of the control switch and the starting time length of the shift register.
In a third aspect, an embodiment of the present invention provides a display device, including:
such as the display panel described above.
The invention has the following beneficial effects:
the embodiment of the invention provides a display panel, a driving method thereof and a display device, wherein the display panel comprises: the display device comprises a display area provided with through holes and a non-display area surrounding the display area, wherein the display area comprises data lines and grid lines which are arranged in a crossed manner, the non-display area comprises control switches and driving chips which are electrically connected with each data line, part of the data lines which are disconnected by the through holes are electrically connected with part of the data lines which are not disconnected by the through holes through the control switches, all the control switches are electrically connected with the driving chips, the control switches are used for storing first data signals provided by the driving chips in parasitic capacitors of the data lines which are partially disconnected by the through holes in an on state, the driving chips are used for providing second data signals to the part of the data lines which are not disconnected by the through holes in an off state, and at the moment, the parasitic capacitors are used for maintaining the data lines which are partially disconnected by the through holes in first data signals, namely, pixels on the data lines which are partially disconnected by the through holes and the data lines which are partially disconnected by the through holes are realized by the control switches arranged in the non On one hand, the control switch is arranged in the non-display area, and the data lines with parts disconnected by the through holes and the data lines with parts not disconnected by the through holes are electrically connected through the control switch, so that the narrow frame design of a pixel blank area is ensured.
Drawings
FIG. 1 is a schematic diagram of a display device according to the related art;
FIG. 2 is a schematic diagram of a display device according to the related art;
FIG. 3 is a schematic diagram of a display device according to the related art;
fig. 4 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
FIG. 8 is a timing diagram of the control switch of FIG. 7 being a P-channel FET;
FIG. 9 is a timing diagram of the control switch of FIG. 7 in the form of an N-channel FET;
fig. 10 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
FIG. 11 is a timing diagram of the control switch of FIG. 10 corresponding to a P-channel FET;
fig. 12 is a flowchart of a method for driving a display panel according to an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the drawings of the embodiments of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. And the embodiments and features of the embodiments may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the invention without any inventive step, are within the scope of protection of the invention.
Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of the word "comprise" or "comprises", and the like, in the context of this application, is intended to mean that the elements or items listed before that word, in addition to those listed after that word, do not exclude other elements or items.
It should be noted that the sizes and shapes of the figures in the drawings are not to be considered true scale, but are merely intended to schematically illustrate the present invention. And the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.
In the prior art, the structure design shown in fig. 2 and 3 may be adopted to ensure the narrow frame design of the pixel blank area a, specifically, as shown in fig. 2, the Gate control signals of each row of pixels in the area U on the side of the pixel blank area W departing from the driving IC are controlled by an independent Gate Driver on Array (GOA), the routing of each independent GOA must pass through the display area X, and when the number of rows of pixels on each row on the side of the pixel blank area W departing from the driving IC is large, the routing of each independent GOA is increased, so that the difference exists between the area U on the side of the pixel blank area W departing from the driving IC and other areas except the area U in the display area X during display, and the display quality is poor.
In addition, specifically referring to fig. 3, each row of pixels in the area U on the side of the pixel blank area W away from the driving IC is electrically connected to other data lines other than the data lines in the display area X, and each row of data lines is electrically connected to the driving IC through the frames on the two sides of the display panel, when there are more pixel rows in the area U on the side of the pixel blank area W away from the driving IC, the frame is wider due to the data lines introduced into the frame, and in addition, the data lines introduced from each row of pixels in the area U on the side of the pixel blank area W away from the driving IC are too long compared to the data lines in other areas in the display area X except the area U, which increases the voltage drop of the corresponding row of data lines, and further leads to poor display quality of the area C on the side of the pixel blank area a away from the driving IC.
In view of this, embodiments of the present invention provide a display panel, a driving method thereof and a display device, which are used to improve the display quality of the display device.
Fig. 4 is a schematic structural diagram of a display panel according to an embodiment of the present invention, specifically, the display panel includes:
the display area X is provided with a through hole H, and the non-display area E surrounds the display area X;
the display area X comprises data lines d and grid lines g which are arranged in a crossed mode;
the non-display area E includes a control switch 10 and a driving chip 20 electrically connected to each data line d;
wherein part of the data line d is disconnected by the via H, the data line d1 partially disconnected by the via H and the data line d2 partially not disconnected by the via H are electrically connected by the control switch 10, and all the control switches 10 are electrically connected to the driving chip 20, the control switches 10 are used for storing the first data signal provided by the driving chip 20 in the parasitic capacitance of the data line d1 partially disconnected by the via hole H in the on state, when the control switch 10 is in the off state, the driving chip 20 is configured to provide a second data signal to the data line d2 partially not disconnected by the via H, the parasitic capacitance is configured to maintain the data line d1 partially disconnected by the via H at the first data signal, the first data signal is configured to drive the first pixel PX1 on the data line d1 partially disconnected by the via H, and the second data signal is configured to drive the second pixel PX2 on the data line d2 partially disconnected by the via H.
In the embodiment of the present invention, the data lines d in the display region X are often multiple, and the gate lines g are also often multiple, wherein a part of the data lines in the multiple data lines are disconnected by the through holes H, and a part of the data lines are not disconnected by the through holes H. In the specific implementation process, the data line d1 with a part being disconnected by the via H and the data line d2 with a part not being disconnected by the via H are electrically connected through the control switch 10, so that it is not necessary to arrange related data lines for the pixel columns with a part being disconnected by the via H around the via H, thereby ensuring the narrow frame design around the via H.
In the embodiment of the present invention, the data line d1 partially disconnected by the via H and the data line d2 partially not disconnected by the via H are electrically connected through the control switch 10, specifically, one of the data lines d1 partially disconnected by the via H and one of the data lines d2 partially disconnected by the via H are electrically connected in a one-to-one correspondence by a control switch 10, specifically, the source and the drain of the control switch 10 are electrically connected to the two data lines, respectively, and accordingly, the gate of the control switch 10 is electrically connected to the driving chip 20. When there are a plurality of data lines d1 partially disconnected by the via H, each data line is electrically connected to a portion of the data lines d2 partially not disconnected by the via H through a control switch 10. For example, when there are four data lines d1 partially disconnected by the via H, the four data lines are electrically connected to four data lines d2 partially not disconnected by the via H by four control switches 10. Fig. 4 is a schematic diagram showing one of the two control switches 10 when there are two data lines d1 partially disconnected by the via H. Of course, the skilled person can set the control switch 10 according to the actual setting of the data line d1 partially disconnected by the via H, which is not limited herein.
In the embodiment of the present invention, the control switch 10 is used to store the first data signal provided by the driving chip 20 in the parasitic capacitance of the data line d1 partially disconnected by the via H when in the on state, wherein the first data signal is used to drive the first pixel PX1 on the data line d1 partially disconnected by the via H. The parasitic capacitance belongs to the capacitance of the corresponding data line, and as long as the data line is arranged, the parasitic capacitance exists on the data line correspondingly. When the control switch 10 is in the off state, the driving chip 20 is configured to provide a second data signal to the data line d2, which is partially not disconnected by the via H, wherein the second data signal is used to drive the second pixel PX2 on the data line d2, which is partially not disconnected by the via H, and at this time, the parasitic capacitance maintains the data line d2, which is partially not disconnected by the via H, at the first data signal, that is, the data line d2, which is partially not disconnected by the via H, maintains its potential at the same potential as the first data signal by virtue of the parasitic capacitance thereon. Thus, by controlling the on and off of the control switch 10 disposed in the non-display area E, independent control of data signals required for pixels on the data line d1 partially disconnected by the via H and the data line d2 partially not disconnected by the via H is achieved.
In a specific implementation process, the control switch 10 may be a thin film transistor, and may also be a field effect transistor, and specifically may be an N-channel type thin film transistor, and may also be a P-channel type thin film transistor, and may also be an N-channel type field effect transistor, and may also be a P-channel type field effect transistor, which is not limited herein. When the control switch 10 is a P-channel type field effect transistor, the control switch 10 is turned on when the gate signal Ctrl supplied to the control switch 10 by the driver chip 20 is at a low potential, and the control switch 10 is turned off when the gate signal Ctrl supplied to the control switch 10 by the driver chip 20 is at a high potential. When the control switch 10 is an N-channel fet, when the gate signal Ctrl provided by the driving chip 20 to the control switch 10 is at a high potential, the control switch 10 is in a conducting state, and when the gate signal Ctrl provided by the driving chip 20 to the control switch 10 is at a low potential, the control switch 10 is in a blocking state.
In the embodiment of the present invention, since the control switch 10 is disposed in the non-display area E, and the data line d1 partially disconnected by the via H and the data line d2 partially not disconnected by the via H are electrically connected by the control switch 10, a narrow bezel design around the via H is ensured. In addition, when the subsequent GOA performs line scanning to output line scanning signals, since data signals required for the first pixel PX1 and the second pixel PX2 in the same scanning line can be independently controlled, the first pixel PX1 and the second pixel PX2 in the same scanning line can perform data writing according to the respective required data signals, thereby ensuring the display quality of the display device.
In the embodiment of the present invention, as shown in fig. 5 and 6, which are schematic structural diagrams of the display panel in the embodiment of the present invention, specifically, the data line d1 partially disconnected by the via H is electrically connected to the adjacent data line d2 partially not disconnected by the via H through the control switch 10. In this way, the data line d1 partially disconnected by the via hole H can be electrically connected with the adjacent data line d2 partially not disconnected by the via hole H through the control switch 10 without long routing, and the overall resistance is small, so that the display effect of each pixel on the electrically connected data line is ensured. Fig. 5 is a schematic structural diagram of one of the two control switches 10 when there are two data lines d1 partially disconnected by the through hole H. Fig. 6 is a schematic diagram showing one of four control switches 10 when there are four data lines d1 partially broken by the through hole H.
In the embodiment of the present invention, as shown in fig. 7, one of the structural diagrams of the display panel in the embodiment of the present invention is shown, specifically, the non-display region E includes shift registers 30 respectively disposed at both sides of each row of gate lines, one shift register 30 is electrically connected to one gate line, and when the shift registers 40 at both sides of the gate lines electrically connected to the first pixel PX1 and the second pixel PX2 are in an on state, the shift registers 40 charges the first pixel PX1 according to the first data signal and charges the second pixel PX2 according to the second data signal. In a specific implementation, when the control switch 10 is in the off state, the driving chip 20 supplies the second data signal to the data line d2, the portion of which is not disconnected by the via H, the parasitic capacitance maintains the data line d2, the portion of which is not disconnected by the via H, at the first data signal, and then the shift register 40 on both sides of the gate line where the first pixel PX1 and the second pixel PX2 are located is turned on, the first pixel PX1 is charged according to the first data signal through the shift register 30, and the second pixel PX2 is charged according to the second data signal, that is, the shift register 40 performs data writing according to voltages required by the first pixel PX1 and the second pixel PX2, respectively. After a certain period of time, the shift register 40 is turned off, and the first pixel PX1 and the second pixel PX2 are completely charged, thereby ensuring the writing of the required data signals to the first pixel PX1 and the second pixel PX 2.
In the embodiment of the present invention, in one charging period, the charging period of the gate line of the row where the first pixel PX1 and the second pixel PX2 are located at least includes the on-period of the control switch 10 and the on-period of the shift register 30, wherein the on-period of the shift register 30 is less than the first period, since in one charging period, data writing of voltages required for the first pixel PX1 and the second pixel PX2, that is, writing of data signals required for the first pixel PX1 and the second pixel PX2, is achieved through the shift register 40.
In a specific implementation process, in combination with the display panel shown in fig. 5 and the timing diagram shown in fig. 8, fig. 8 is a timing diagram of a case where the control switch 10 is a P-channel fet, for example, the first pixel PX1 is a pixel a located on a data line data (n), the second pixel PX2 is a pixel a located on a data line data (n), and a pixel B, a pixel C, a pixel D, and the like are further disposed on the data line data (n), where the pixel a and the pixel a are located on an (n-1) th row gate line, the pixel B and the pixel B are located on an nth row gate line, and n is an integer greater than 1. A pixel a, a pixel B, a pixel C, a pixel D, and the like are sequentially disposed on the data line data (m) adjacent to the data line data (n). For the data line data (m), the driving chip 20 sequentially supplies driving voltages to the pixel a, the pixel B, the pixel C, and the pixel D on the data line according to the scanning frequency of the shift register 40. For the pixels on the grid line of the (n-1) th row, taking the pixel a and the pixel A as an example, the data line data (n) needs to provide a driving voltage for the pixel a and a driving voltage for the pixel A. Specifically, when the driving chip 20 outputs a first data signal required by the pixel a, and the driving chip 20 adjusts the gate signal Ctrl of the control switch 10 to a low level, the control switch 10 is turned on at this time, so that the first data signal is stored in the parasitic capacitance on the data (n), and then the driving chip 20 adjusts the gate signal Ctrl of the control switch 10 to a high level, the control switch 10 is turned off at this time, the data line d1 disconnected by the via-hole H where the pixel a is located maintains a potential corresponding to the first data signal by the parasitic capacitance, and then the driving chip 20 outputs a second data signal required by the pixel a, and then the shift register 40 connected to the (n-1) th row gate line is turned on, that is, G (n-1) is turned on, at this time, the pixel a is written according to the first data signal, the pixel a is written according to the second data signal, that is, the pixel a and the pixel a respectively perform data writing according to the respective required voltages, after a period of time, G (n-1) is turned off, the (n-1) th row gate line charging period ends, as shown in fig. 8, in a charging period of the (n-1) th row, a charging duration 1H of the (n-1) th row includes an on duration of the Ctrl signal, an on duration of the shift register 30, and a partial time interval, where the charging duration is 1H as indicated by an arrow in fig. 8. In addition, in one charging period of the (n-1) th row, the charging periods for the pixel a and the pixel a are both the on periods of the shift register 30.
In a specific implementation process, for the pixel B and the pixel B on the gate line of the nth row, signal writing to the corresponding pixels can be implemented by using the same implementation manner as described above, and will not be described in detail herein. Since the pixels on the data line d1 disconnected by the via H and the pixels on the data line d2 not disconnected by the via H can perform data writing according to required voltages, respectively, the display quality of the corresponding pixels is ensured.
In the implementation process, when the control switch 10 in fig. 7 is an N-channel fet, the timing chart adopted is different from that in fig. 8, and specifically may be as shown in fig. 9, and the detailed description of the specific charging process is omitted here.
In the embodiment of the present invention, as shown in fig. 10, a structural diagram of a display panel according to an embodiment of the present invention is provided, specifically, the shift register 30 on both sides of a row gate line on which each pixel on a data line d1, which is partially disconnected by a via H, is electrically connected to a redundant shift register 40, and the redundant shift register 40 is used to transmit a required row scanning signal of a current row gate line to the shift register 30 electrically connected to the current row gate line. In a specific implementation process, on a side of the through hole H away from the driving chip 20, the pixels d1 on the data line disconnected by the through hole H are respectively located on two adjacent rows of gate lines, as shown in fig. 10, respectively located on the (n-1) th row of gate lines and the nth row of gate lines, and two sides of each gate line are provided with a redundant shift register 40. In a specific implementation process, the redundant shift register 40 may adopt a circuit structure identical to that of a shift register in the prior art, and the specific implementation may refer to that in the prior art, which is not described herein again. In addition, each of the redundant shift registers 40 only participates in the transmission of the scanning signal of the current row, and does not directly provide the gate control signal for the pixels on the gate line of the current row. In this way, the interval duration between the gate control signals for driving the pixels on the gate lines of each row on the data line d1, which is partially disconnected by the through hole H, can be relatively extended, so that the on duration of the gate control signals is extended, and the display uniformity of the display panel is ensured.
In the embodiment of the present invention, as shown in fig. 11, it is a timing chart corresponding to the control switch 10 in the display panel shown in fig. 10 being a P-channel field effect transistor, specifically, in one charging period, the charging time duration of the shift register 40 for the first pixel PX1 and the second pixel PX2 is a first time duration. Still taking the control switch 10 as a P-channel fet as an example, compared with fig. 8, after the redundant shift register 40 is added, the charging time of the grid line of the row where the first pixel PX1 and the second pixel PX2 are located may be 2 times of the first time 1H, and the shift register 30 may charge both the pixel a and the pixel a for the first time 1H, which further increases the on-time of G (n-1) compared with fig. 8, thereby ensuring the display quality of the display panel.
Based on the same inventive concept, as shown in fig. 12, an embodiment of the present invention further provides a driving method of a display panel, including:
s101: outputting, by the driving chip, the first data signal for driving the first pixel on the data line partially disconnected by the via hole;
s102: controlling the switch to be in the conducting state through the driving chip, and storing the first data signal in a parasitic capacitance of the data line, wherein part of the parasitic capacitance is disconnected by the through hole;
s103: and controlling the switch to be in the cut-off state through the driving chip, outputting the second data signal for driving part of the second pixels on the data line which is not disconnected by the through hole, and maintaining the part of the data line which is disconnected by the through hole at the first data signal through the parasitic capacitor.
Since the principle of the driving method for a display panel according to the embodiment of the present invention to solve the problem is similar to that of the display panel, the implementation of the driving method can be referred to the implementation of the display panel, and repeated details are not repeated.
In an embodiment of the present invention, the method further comprises:
and when the shift registers at two sides of the grid line electrically connected with the first pixel and the second pixel are in an open state, charging the first pixel according to the first data signal through the shift registers, and charging the second pixel according to the second data signal.
In an embodiment of the present invention, the charging, by the shift register, the first pixel according to the first data signal and the second pixel according to the second data signal includes:
and in a charging period, charging the first pixel and the second pixel for a second time length through the shift register, wherein the second time length is less than a first time length, and the first time length at least comprises the starting time length of the control switch and the starting time length of the shift register. The embodiment of the invention also provides a display device, and the principle of the display device for solving the problems is similar to that of the display panel, so the implementation of the display device can be referred to that of the display panel, and repeated parts are not repeated.
In a specific implementation process, the display device provided in the embodiment of the present invention may be a Liquid Crystal Display (LCD) display, an Organic Light-Emitting semiconductor (OLED) display, specifically a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and any product or component with a display function. Other essential components of the display device are understood by those skilled in the art, and are not described herein nor should they be construed as limiting the present invention.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.
Claims (10)
1. A display panel, comprising:
the display device comprises a display area provided with a through hole and a non-display area surrounding the display area;
the display area comprises data lines and grid lines which are arranged in a crossed manner;
the non-display area comprises a control switch and a driving chip electrically connected with each data line;
wherein a part of the data lines are disconnected by the via holes, a part of the data lines which are disconnected by the via holes and a part of the data lines which are not disconnected by the via holes are electrically connected through the control switches, and all the control switches are electrically connected with the driving chip, the control switches are used for storing a first data signal provided by the driving chip in a parasitic capacitance of the data lines which are partially disconnected by the via holes when in an on state, the driving chip is used for providing a second data signal to the data lines which are partially not disconnected by the via holes when in an off state, the parasitic capacitance is used for maintaining the data lines which are partially disconnected by the via holes at the first data signal, and the first data signal is used for driving a first pixel on the data lines which are partially disconnected by the via holes, the second data signal is used for driving a second pixel on the data line, a part of which is not disconnected by the through hole.
2. The display panel according to claim 1, wherein the data line partially disconnected by the via hole and the data line adjacent to the data line partially not disconnected by the via hole are electrically connected through the control switch.
3. The display panel according to claim 1, wherein the non-display region includes shift registers respectively disposed at both sides of each row of the gate lines, one of the shift registers being electrically connected to one of the gate lines, and wherein the shift registers charge the first pixels according to the first data signals and charge the second pixels according to the second data signals when the shift registers at both sides of the gate lines electrically connected to the first pixels and the second pixels are in an on state.
4. The display panel according to claim 3, wherein a charging period of the row gate line where the first pixel and the second pixel are located in one charging period is a first period, the first period at least includes an on period of the control switch and an on period of the shift register, and the on period of the shift register is less than the first period.
5. The display panel according to claim 4, wherein the shift register at two sides of the gate line of the row where each pixel on the data line is partially disconnected by the through hole is electrically connected to a redundant shift register, and the redundant shift register is used for transmitting a required row scanning signal of the gate line in a current row to the shift register electrically connected to the gate line in the current row.
6. The display panel according to claim 5, wherein a charging period of the shift register to the first pixel and the second pixel is the first period in one charging period.
7. A driving method of the display panel according to any one of claims 1 to 6, comprising:
outputting, by the driving chip, the first data signal for driving the first pixel on the data line partially disconnected by the via hole;
controlling the switch to be in the conducting state through the driving chip, and storing the first data signal in a parasitic capacitance of the data line, wherein part of the parasitic capacitance is disconnected by the through hole;
and controlling the switch to be in the cut-off state through the driving chip, outputting the second data signal for driving part of the second pixels on the data line which is not disconnected by the through hole, and maintaining the part of the data line which is disconnected by the through hole at the first data signal through the parasitic capacitor.
8. The driving method according to claim 7, characterized in that the method further comprises:
and when the shift registers at two sides of the grid line electrically connected with the first pixel and the second pixel are in an open state, charging the first pixel according to the first data signal through the shift registers, and charging the second pixel according to the second data signal.
9. The driving method according to claim 8, wherein the charging the first pixel in accordance with the first data signal and the charging the second pixel in accordance with the second data signal by the shift register includes:
and in a charging period, charging the first pixel and the second pixel for a second time length through the shift register, wherein the second time length is less than a first time length, and the first time length at least comprises the starting time length of the control switch and the starting time length of the shift register.
10. A display device, comprising:
the display panel of any one of claims 1-6.
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