KR102218386B1 - Gate driver circuit and liquid crystal display comprising the same - Google Patents

Abstract

The present invention provides a gate driver for preventing deterioration in display quality of an image, and a liquid crystal display including the same, in a gate driver including a plurality of shift registers sequentially outputting output signals according to a start signal, the plurality of Each of the shift registers includes a first transistor connected between a first start signal input terminal and a Q node and a second transistor connected between the Q node, a third output signal input terminal, and a low potential voltage input terminal, and a first clock signal input terminal, A third transistor and a third clock signal input terminal connected between the Q node and the first output signal output terminal, the fourth transistor connected between the low potential voltage input terminal and the source terminal of the third transistor and the drain of the third transistor A fifth transistor connected between the terminal and the first output signal output terminal, a capacitor connected between the Q node and the source terminal of the third transistor, and a sixth transistor connected between the first clock signal input terminal and the QB node, A gate driver including a seventh transistor connected between the QB node, the low potential voltage input terminal, and the first output signal output terminal, and an eighth transistor connected between the Q node, the QB node and the low potential voltage input terminal to provide.

Description

Gate driver and liquid crystal display device including the same {GATE DRIVER CIRCUIT AND LIQUID CRYSTAL DISPLAY COMPRISING THE SAME}

The present invention relates to a gate driving unit and a liquid crystal display device including the same, and more particularly, to a gate driving unit for preventing image display quality from deteriorating and a liquid crystal display device including the same.

A liquid crystal display includes a liquid crystal panel, a data driver for supplying data to a data line of the liquid crystal panel, a gate driver for supplying a gate pulse to a gate line of the liquid crystal panel, and a timing controller for controlling the data driver and the gate driver It is equipped with.

Such a liquid crystal display device is generally used by forming a gate and a data driver in the form of an integrated circuit and attaching it to a liquid crystal panel such as a TCP or COF.

As a result, the number of component elements increases, and the process cost increases due to the increase in the number of component elements, which is a problem in reducing the weight and size of the liquid crystal display. Thus, GIP (Gate In Panel, which forms the gate driver on the liquid crystal display panel) ) Type liquid crystal display device was proposed.

In the display area of a liquid crystal panel of a GIP-type liquid crystal display device, a plurality of gates and data lines defining a liquid crystal cell are formed by crossing each other, and a GIP-type gate driver composed of a plurality of thin film transistors (hereinafter , A built-in gate driver) is provided.

1 is a diagram showing a detailed circuit configuration of a shift register provided in a conventional built-in gate driver.

In a gate driver including a plurality of shift registers sequentially outputting an output signal according to a start signal, as shown in FIG. 1, a first shift register SR1 includes a control unit 10 for controlling a Q node, An output unit 20 for outputting the first clock signal CLK1 according to the Q node is provided.

The controller 10 controls the Q node and outputs the first clock signal CLK1 through the third transistor T3 of the output unit 20.

Accordingly, the outputted first clock signal CLK1 is supplied to the first gate line as the first output signal Vg1 in a high state.

To this end, the control unit 10 includes a first transistor T1 connected between the first start signal Vst1 input terminal and the Q node, a Q node, a third output signal Vg3 input terminal and a low potential voltage (VSS) input terminal. And a second transistor T2 connected therebetween.

The first transistor T1 has a diode function by connecting a drain terminal and a gate terminal. That is, the voltage of the drain terminal of the first transistor T1 is applied to the source terminal, but the voltage of the source terminal is not applied to the drain terminal.

Accordingly, the first transistor T1 charges the first start signal Vst1 to the Q node, and prevents the voltage charged at the Q node from being discharged to the outside through the first transistor T1.

The second transistor T2 initializes the Q node, and charges the low potential voltage VSS in the Q node when turned on by the third output signal Vg3.

Accordingly, the first start signal Vst1 in a high state can be charged in the Q node in the next frame.

The output unit 20 outputs the high-state first clock signal CLK1 to the first gate line according to the voltage state of the Q node, and discharges the first output signal Vg1 output through the first gate line. .

To this end, the output unit 20 includes a first clock signal CLK1 input terminal, a third transistor T3 connected between the Q node and the first output signal Vg1 output terminal, and a third clock signal CLK3 input terminal, The fourth transistor (T4) connected between the low potential voltage (VSS) input terminal and the source terminal of the third transistor (T3), and the drain terminal of the third transistor (T3) and the output terminal of the first output signal (Vg1). A fifth transistor T5 and a capacitor C connected between the Q node and the source terminal of the third transistor are provided.

The third transistor T3 is turned on by the high-state voltage charged in the Q node, and outputs the high-state first clock signal CLK1 to the output terminal of the first output signal Vg1.

Meanwhile, although not shown in the drawing, the second shift register is initiated by the second start signal, and the second output signal is output to the second gate line through the same process as the first shift register SR1.

Also, the first output signal Vg1 is input as a start signal of the third shift register. Accordingly, the third output signal Vg3 is output to the third gate line from the third shift register.

In addition, the third output signal Vg3 is supplied to the input terminal of the third output signal Vg3 of the first shift register SR1, and the second transistor T2 is turned on by the third output signal Vg3. The low potential voltage (VSS) in the low state is charged to the Q node.

The fifth transistor T5 has a diode function by connecting the source terminal and the gate terminal. Therefore, when the first clock signal CLK1 in the high state is applied to the gate terminal of the fifth transistor T5, it is turned on to output the first output signal Vg1, and the gate terminal of the fifth transistor T5 When the low potential voltage VSS in the low state is applied to the device, it is turned off to prevent the first clock signal CLK1 in the high state from being output.

When the first start signal Vst1 in a high state is input to the gate terminal of the first transistor T1 and the first transistor T1 is turned on, the capacitor C reaches the voltage level of the first start signal Vst1. Is charged.

Thereafter, when the capacitor C is charged above the threshold voltage between the gate terminal and the source terminal of the third transistor T3, and when the first clock signal CLK1 goes high, a bootstrapping phenomenon occurs. The node is charged with a voltage greater than the voltage level of the first start signal Vst1 and is in a certain high state, and accordingly, the third transistor T3 is turned on.

The fourth transistor T4 is turned on by the third clock signal CLK3 to apply the low-state low-potential voltage VSS to the output terminal of the first output signal Vg1.

At this time, the low potential voltage VSS in the low state is charged to the Q node by the second transistor T2 turned on by the third output signal Vg3, and the third transistor T3 is turned off and initialized. Is made.

This process is repeatedly performed for each frame.

FIG. 2 is a diagram showing a waveform of an output signal of a shift register provided in a conventional built-in gate driver.

As shown in the drawing, the first output signal is divided into a high state section (H) and a low state section (L).

At this time, the low potential voltage VSS in the low state is charged to the Q node by the second transistor T2 turned on by the third output signal Vg3 in the low state period L. 3 When a ripple phenomenon in which the waveform is distorted occurs in the output signal Vg3, stress is applied to the second transistor T2, and accordingly, the low potential voltage VSS charged to the Q node is also distorted. 1 The waveform of the output signal is also affected by this, causing a ripple phenomenon.

A shift register provided in a conventional built-in gate driver has a problem of deteriorating the display quality of an image due to such ripple phenomenon.

The present invention has been conceived to solve the above problems, and provides a gate driver capable of preventing a distortion ripple phenomenon of a waveform of an output signal output from the gate driver, and a liquid crystal display device including the same. For that purpose.

The present invention is a gate driver including a plurality of shift registers sequentially outputting an output signal by a start signal in order to achieve the above object, each of the plurality of shift registers, a first start signal input terminal and The first transistor connected between the Q nodes and the Q node, the second transistor connected between the third output signal input terminal and the low potential voltage input terminal and the first clock signal input terminal, and the connection between the Q node and the first output signal output terminal A fourth transistor connected between the third transistor and the third clock signal input terminal, the low potential voltage input terminal, and the source terminal of the third transistor, and the drain terminal of the third transistor and the first output signal output terminal. The fifth transistor, the capacitor connected between the Q node and the source terminal of the third transistor, the sixth transistor and the QB node connected between the first clock signal input terminal and the QB node, the low potential voltage input terminal, and the third transistor A gate driver including a seventh transistor connected between one output signal output terminal and an eighth transistor connected between the Q node, the QB node, and the low potential voltage input terminal is provided.

Further, a gate terminal and a drain terminal of each of the first and sixth transistors are connected, and a gate terminal and a source terminal of the fifth transistor are connected.

In addition, the first, fifth and sixth transistors have a diode function that passes a voltage in only one direction.

Further, the first start signal is a voltage in a high state, and the low potential voltage is a voltage in a low state.

Also, the seventh transistor is turned on by the voltage of the QB node.

Also, the seventh transistor is turned off by the eighth transistor in a high state period of the second output signal.

In addition, a liquid crystal panel for displaying an image in a pixel region defined by a gate wiring receiving the first output signal from the gate driver and the gate driver, and a data wiring perpendicular to the gate wiring, and the data wiring are driven. A liquid crystal display device including a data driver and a timing controller for controlling the gate driver and the data driver is provided.

The gate driver of the present invention and a liquid crystal display including the same stabilize the waveform of the output signal output from the gate driver, especially the output waveform of the gate low voltage, thereby preventing a ripple phenomenon in which the output waveform is distorted. have.

1 is a diagram showing a detailed circuit configuration of a shift register provided in a conventional built-in gate driver.
FIG. 2 is a diagram showing a waveform of an output signal of a shift register provided in a conventional built-in gate driver.
3 is a diagram showing a detailed circuit configuration of a shift register provided in a built-in gate driver according to an embodiment of the present invention.
FIG. 4 is a diagram showing a start signal, a clock signal, a voltage of a Q node, a waveform of an output signal, and an on/off period of the thin film transistor of FIG. 3.
5 is a diagram showing an output signal waveform of a shift register provided in a built-in gate driver according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

3 is a diagram showing a detailed circuit configuration of a shift register provided in a built-in gate driver according to an embodiment of the present invention.

In a gate driver including a plurality of shift registers sequentially outputting an output signal according to a start signal, as shown in FIG. 3, a first shift register SR1 includes a control unit 100 for controlling a Q node, Compensation for outputting the first output signal Vg1 according to the Q node, and for outputting a stable first output signal Vg1 from the output unit 200 when the voltage level of the Q node is low It has a part 300.

The control unit 100 controls the Q node to output the first clock signal CLK1 through the third transistor T3 of the output unit 200.

Accordingly, the outputted first clock signal CLK1 is supplied to the first gate line as the first output signal Vg1 in a high state.

To this end, the control unit 100 includes a first transistor T1 connected between the first start signal Vst1 input terminal and the Q node, a Q node, a third output signal Vg3 input terminal and a low potential voltage VSS input terminal. And a second transistor T2 connected therebetween.

The first transistor T1 has a diode function by connecting a drain terminal and a gate terminal. That is, the voltage of the source terminal of the first transistor T1 is applied to the drain terminal, but the voltage of the drain terminal is not applied to the source terminal.

Accordingly, the first transistor T1 charges the first start signal Vst1 to the Q node, and prevents the voltage charged at the Q node from being discharged to the outside through the first transistor T1.

The second transistor T2 initializes the Q node, and charges the low potential voltage VSS in the Q node when turned on by the third output signal Vg3.

Accordingly, the first start signal Vst1 in a high state can be charged in the Q node in the next frame.

The output unit 200 outputs the high-state first clock signal CLK1 to the first gate line according to the voltage state of the Q node, and discharges the first output signal Vg1 output through the first gate line. .

To this end, the output unit 200 includes a first clock signal CLK1 input terminal, a third transistor T3 connected between the Q node and the first output signal Vg1 output terminal, and a third clock signal CLK3 input terminal, The fourth transistor (T4) connected between the low potential voltage (VSS) input terminal and the source terminal of the third transistor (T3), and the drain terminal of the third transistor (T3) and the output terminal of the first output signal (Vg1). A fifth transistor (T5) and a capacitor (C) connected between the Q node and the source terminal of the third transistor (T3) are provided.

The third transistor T3 is turned on by the high-state voltage charged in the Q node, and outputs the high-state first clock signal CLK1 to the output terminal of the first output signal Vg1.

Meanwhile, although not shown in the drawing, the second shift register is initiated by the second start signal, and the second output signal is output to the second gate line through the same process as the first shift register SR1.

Also, the first output signal Vg1 is input as a start signal of the third shift register. Accordingly, the third output signal Vg3 is output to the third gate line from the third shift register.

In addition, the third output signal Vg3 is supplied to the input terminal of the third output signal Vg3 of the first shift register SR1, and the second transistor T2 is turned on by the third output signal Vg3. The low potential voltage (VSS) in the low state is charged to the Q node.

The fifth transistor T5 has a diode function by connecting the source terminal and the gate terminal. Therefore, when the first clock signal CLK1 in the high state is applied to the gate terminal of the fifth transistor T5, it is turned on to output the first output signal Vg1, and the gate terminal of the fifth transistor T5 When the low potential voltage VSS in the low state is applied to the device, it is turned off to prevent the first clock signal CLK1 in the high state from being output.

When the first start signal Vst1 in a high state is input to the gate terminal of the first transistor T1 and the first transistor T1 is turned on, the capacitor C reaches the voltage level of the first start signal Vst1. Is charged.

Thereafter, when the capacitor C is charged above the threshold voltage between the gate terminal and the source terminal of the third transistor T3, and when the first clock signal CLK1 goes high, a bootstrapping phenomenon occurs. The node is charged with a voltage greater than the voltage level of the first start signal Vst1 and is in a certain high state, and accordingly, the third transistor T3 is turned on.

The fourth transistor T4 is turned on by the third clock signal CLK3 to apply the low-state low-potential voltage VSS to the output terminal of the first output signal Vg1.

At this time, the low potential voltage VSS in the low state is charged to the Q node by the second transistor T2 turned on by the third output signal Vg3 to turn off the third transistor T3.

When the voltage level of the Q node is in a low state, the compensation unit 300 causes the output unit 200 to output a stable first output signal Vg1.

To this end, the compensation unit 300 includes a sixth transistor T6 connected between the input terminal of the first clock signal CLK1 and the QB node, the input terminal of the QB node and the low potential voltage (VSS), and the first output signal Vg1. A seventh transistor T7 is connected between the output terminals, and an eighth transistor T8 is connected between the Q node, the QB node, and the low potential voltage (VSS) input terminal.

Specifically, the source electrode of the sixth transistor T6 is connected to the QB node, and the gate terminal and the source terminal are connected to the input terminal of the first clock signal CLK1, thereby having a diode function. That is, in the sixth transistor T6, the voltage at the drain terminal is applied to the source terminal, but the voltage at the source terminal is not applied to the drain terminal.

Accordingly, the sixth transistor T6 prevents the first clock signal CLK1 from being discharged to the outside through the sixth transistor T6, instead of charging the QB node with the voltage charged in the QB node.

In addition, the gate terminal of the seventh transistor T7 is connected to the QB node, the source terminal is connected to the low potential voltage (VSS) input terminal, and the drain terminal is connected to the output terminal of the first output signal (Vg1). The low potential voltage VSS in the low state is applied to the output terminal of the first output signal Vg1 by being turned on by the high-state first clock signal CLK1 applied through T6.

Further, although not shown in the drawing, a separate high-state voltage stabilization signal may be applied to the sixth transistor T6, and accordingly, the sixth transistor T6 is turned on and the low-potential voltage VSS ) May be applied to the output terminal of the first output signal Vg1.

At this time, the seventh transistor T7 is turned on by the voltage of the QB node.

Meanwhile, in the high state period of the first output signal Vg1 by the eighth transistor T8 to be described later, the seventh transistor T7 is turned off.

The gate terminal of the eighth transistor T8 is connected to the Q node, the drain terminal is connected to the QB node, and the source terminal is connected to the low potential voltage (VSS) input terminal.

At this time, when the voltage at the Q node is charged to a high state, the eighth transistor T8 is turned on, and the first clock signal CLK1 applied through the sixth transistor T6 is applied to the seventh transistor T7. The seventh transistor T7 is turned off because it is not supplied to the gate terminal but is supplied to the low potential voltage VSS input terminal.

That is, in the high state period of the first output signal Vg1, the seventh transistor T7 is turned off.

Accordingly, during the initial driving, in the low state period of the first output signal Vg1, the second transistor T2 turned on by the third output signal Vg3, whose waveform is distorted, reduces the charge to the Q node. A ripple phenomenon of the first output signal, which is caused by distortion of the potential voltage VSS, may also be prevented.

In addition, it is possible to prevent deterioration of the display quality of an image due to such a ripple phenomenon.

Meanwhile, the above-described operation process of the shift register is repeatedly performed for each frame.

FIG. 4 is a diagram showing a start signal, a clock signal, a voltage of a Q node, a waveform of an output signal, and an on/off period of the thin film transistor of FIG. 3.

An operation of the first shift register SR1 according to an embodiment of the present invention will be described with reference to FIG. 4.

First, when the first start signal Vst1 in the high state is input, the start signal Vst in the high state is charged to the Q node via the first transistor T1.

Accordingly, the third transistor T3 connected to the Q node is gradually turned on. At this time, the third transistor T3 is not completely turned on, so that the first clock signal CLK1 in a high state Does not pass through the third transistor T3.

Accordingly, the first output signal Vg1 in a low state is output to the first gate line.

Thereafter, when the first clock signal CLK1 in the high state is applied instead of the first start signal Vst1 falling to the low state, it is booted by the capacitor C formed between the gate terminal and the source terminal of the third transistor T3. A bootstrapping phenomenon occurs, and a voltage higher than the voltage level of the first start signal Vst1 is charged to the Q node, thereby becoming a certain high state.

Accordingly, the third transistor T3 is completely turned on, and the first clock signal CLK1 in a high state is output as the first gate line as the first output signal Vg1.

Thereafter, the third output signal Vg3 output from the third shift register is applied to the second transistor T2 of the first shift register SR1.

Accordingly, the second transistor T2 is turned on by the third output signal, so that the low potential voltage VSS in the low state is charged to the Q node.

In addition, the third transistor T3 connected to the Q node is turned off, and the fourth transistor is turned on by the third clock signal, so that the low potential voltage VSS in the low state becomes the first output signal Vg1. It is supplied to the output stage.

Meanwhile, a ripple phenomenon may occur in the waveform of the first output signal Vg1 here. To prevent this, the seventh transistor T7 is the first clock signal in the high state applied through the sixth transistor T6. It is turned on by CLK1) and outputs the low potential voltage VSS to the output terminal of the first output signal Vg1.

In addition, in the high state period of the first output signal Vg1 by the eighth transistor T8, the seventh transistor T7 is turned off and the first clock signal CLK1 in the high state is transmitted to the first output signal Vg1. ) Output to the output terminal.

Accordingly, during initial driving, in the low state period of the first output signal Vg1, the low potential voltage VSS charged to the Q node is also distorted, thereby preventing the ripple of the first output signal. have.

In addition, it is possible to prevent deterioration of the display quality of an image due to such a ripple phenomenon.

The remaining shift registers are also operated in the same manner as described above. Accordingly, output signals in the high state are sequentially output to the corresponding gate lines.

That is, output signals in a high state are sequentially output by shift registers connected to each gate line during one frame, and this process is repeatedly operated for each frame.

5 is a diagram showing an output signal waveform of a shift register provided in a built-in gate driver according to an embodiment of the present invention.

As shown in the drawing, the first output signal is divided into a high state section (H) and a low state section (L).

In the low state period L of the first output signal Vg1 when initially driven through the compensation unit 300 described above, the low potential voltage VSS charged to the Q node is also distorted. Ripple phenomenon can be prevented.

In addition, it is possible to prevent deterioration of the display quality of the image due to the ripple phenomenon.

Further, although not shown in the drawings, the liquid crystal display device according to the exemplary embodiment of the present invention further includes a liquid crystal panel, a data driver, and a timing controller in the gate driver described above.

In this case, the liquid crystal panel displays an image in a pixel region defined by a gate wiring receiving an output signal from the gate driver and a data wiring perpendicular to the gate wiring.

In addition, the data driver drives the data line, and the timing controller controls the data driver and the gate driver.

The present invention is not limited to the above embodiments, and various modifications may be made without departing from the scope of the present invention.

Vst1: First start signal
T1 to T8: first to eighth transistors
C: capacitor
VSS: low potential voltage
CLK1 to CLK4: first to fourth clock signals
Vg1, Vg3: 1st and 3rd output signals

Claims (8)

In the gate driver including a plurality of shift registers sequentially outputting an output signal according to a start signal,
Each of the plurality of shift registers,
A first transistor connected between the first start signal input terminal and the Q node;
A second transistor connected between the Q node, a third output signal input terminal, and a low potential voltage input terminal;
A first clock signal input terminal, a third transistor connected between the Q node and the first output signal output terminal;
A fourth transistor connected between a third clock signal input terminal, the low potential voltage input terminal, and a source terminal of the third transistor;
A fifth transistor connected between the drain terminal of the third transistor and the output terminal of the first output signal;
A capacitor connected between the Q node and the source terminal of the third transistor;
A sixth transistor connected between the first clock signal input terminal and a QB node;
A seventh transistor connected between the QB node, the low potential voltage input terminal, and the first output signal output terminal; And
An eighth transistor connected between the Q node, the QB node, and the low potential voltage input terminal
Gate driver comprising a.
The method of claim 1,
A gate terminal and a drain terminal of each of the first and sixth transistors are connected, and a gate terminal and a source terminal of the fifth transistor are connected.
The method of claim 2,
The first, fifth and sixth transistors have a diode function to pass a voltage in only one direction.
The method of claim 1,
The first start signal is a voltage in a high state and the low potential voltage is in a low state.
The method of claim 4,
The seventh transistor is turned on by the voltage of the QB node.
The method of claim 5,
The seventh transistor is turned off by the eighth transistor in a high state period of the first output signal.
The method of claim 6,
The sixth transistor is turned on by a high-state first clock signal or a high-state voltage stabilization signal applied from the first clock signal input terminal.
The gate driver of claim 1;
A liquid crystal panel configured to display an image in a pixel area defined by a gate line to which the first output signal is applied from the gate driver and a data line perpendicular to the gate line;
A data driver driving the data line; And
A timing controller that controls the gate driver and the data driver
Liquid crystal display device comprising a.

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