JP2008276849A - Image display device and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image display device which achieves bidirectional scan without causing increase of circuit scale of shift register circuit and a circuit area and deterioration of operating margin, and to provide a semiconductor device to be used for a driving circuit of a scan line of the image display device. <P>SOLUTION: The image display device is equipped with: a pixel array 3 of which scan line is driven by shift register circuits 1 and 2; a source driver 5 which writes image data in a pixel transistor 4 which constitutes a pixel array 3; a power source circuit 6 which supplies power supply voltage to shift register circuits 1 and 2; a timing generation circuit 7 which generates timing required for a source driver 5 or shift register circuits 1 and 2 based on a vertical synchronization signal, a horizontal synchronization signal, image data, dot clock or the like; and a control signal switching circuit 8 which controls switching of shift register circuits 1 and 2 based on a logic of the scan direction switching signal (DIR). <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an image display device and a semiconductor device used as a scanning line driving circuit of the image display device.

  In an image display device such as a liquid crystal display device, as a gate line driving circuit (scanning line driving circuit) for scanning a display panel, a shift register circuit that performs a shift operation that makes a round in one frame period of a display signal is used. it can. The shift register circuit is preferably composed of only the field effect transistors of the same conductivity type in order to reduce the number of steps in the manufacturing process of the display device.

  A display device in which a shift register circuit of a gate line driving circuit is composed of an amorphous silicon thin film transistor (hereinafter referred to as “a-Si transistor”) is easy to increase in area and has high productivity. Widely used in large screen display devices.

  On the other hand, it is known that the a-Si transistor has a characteristic that the threshold voltage shifts when the gate electrode is continuously (DC) biased.

  When the threshold voltage is shifted, there is a problem that the operation margin of the shift register circuit is reduced or the operation is not performed in some cases.

  Such a problem becomes more significant as the circuit scale becomes larger, and it becomes difficult to grasp the reliability of the entire circuit by shifting the threshold voltage.

  For example, in Patent Document 1, in the block diagram of the shift register circuit shown in FIG. 2, the output of the (N−1) th stage is used as the input of the Nth stage, and the output of the (N + 1) th stage is used as the Nth stage. Used to reset the stage output.

  In general, in order to realize display by bidirectional scanning, a function of switching the shift direction of each stage of the shift register circuit in the gate driver circuit is provided, or the output stage of each shift register circuit or the gate pulse output stage (shift It is necessary to physically switch the connection between the gate line and the output stage having a low impedance so that the gate line can be driven based on the output signal of the register circuit.

  In order to switch the connection wiring between the stages, or to physically switch the connection between the output stage of each shift register circuit or the gate pulse output stage and the gate line, it is necessary to provide a switching circuit in each stage. is there.

  When such a configuration is applied to the shift register circuit of FIG. 2 in Patent Document 1, for example, a positive bias or a negative bias is applied to a switch (thin film transistor: TFT) for switching the scan direction in a direct current. When a certain amount of time elapses, the threshold voltage (Vth) of the TFT used for the switch shifts, and the operation margin of the shift register circuit decreases or does not operate in some cases. Such a threshold voltage shift of the TFT due to the application of the DC bias is particularly remarkable in the a-Si transistor.

  The shift of the threshold voltage is also described in paragraphs 0018 to 0021 of Patent Document 1.

  Thus, even if the shift register circuit disclosed in Patent Document 1 is added with a configuration for physically switching the connection with the gate line, it is difficult to realize display by bidirectional scanning. A threshold voltage compensation circuit that compensates for the threshold voltage shift of the TFT is required. In this case, a compensation circuit is required for each of a plurality of stages constituting the shift register circuit. There arises a problem that the scale and circuit area are significantly increased.

  In general, in an image display device, an electronic circuit for display is arranged around the display panel. Therefore, when the circuit scale of the shift register circuit increases, the frame size of the display panel increases.

  As a method of realizing display by bidirectional scanning, there are methods other than those described above. For example, in FIG. 20 of Patent Document 2, switching of the scan signal is performed by switching the polarity of the external power supply voltage according to the scanning direction. A possible configuration is disclosed.

  Here, in FIG. 20 of Patent Document 2, in order to secure the same circuit margin when the scan operation is reversed as in the case where the scan operation is not reversed, a charging transistor for charging the gate node of the output transistor is provided. The driving capability of the discharging transistor that discharges the gate node of the output transistor needs to be the same.

  On the other hand, in a shift register circuit that performs scanning in only a single direction, the driving capability of the discharging transistor is smaller than that of the charging transistor, and the transistor size is about half or less.

  As described above, in the method of switching the polarity of the external power supply voltage in accordance with the scan direction, the total capacity of the discharge transistor and the charge transistor is increased as compared with the shift register circuit that scans only in a single direction. Accordingly, in order to make the operation margin of the shift register circuit comparable to that of the shift register circuit that performs scanning in only one direction, the output transistor connected to the gate node of the charging transistor and discharging transistor in the next stage It is necessary to increase the transistor size.

  On the other hand, increasing the transistor size of the output transistor means that the transistor size of the charging transistor and the discharging transistor that drive the output transistor must also be increased, and the circuit must be increased one after another. . Therefore, it is difficult to obtain a shift register circuit that performs bidirectional scanning that is driven with the same operation margin as a shift register circuit that performs scanning in only one direction without increasing the circuit area.

  Conversely, if the circuit area is about the same as that of a shift register circuit that performs scanning in only one direction, the operation margin of the shift register circuit that performs bidirectional scanning may decrease or become inoperable. is there.

Japanese Patent Laying-Open No. 2004-246358 (FIG. 2) Japanese Patent Laying-Open No. 2001-3504388 (FIG. 20)

  As described above, when a shift register circuit is configured with an a-Si transistor, in order to realize display by bidirectional scanning, a switch circuit for switching the scanning direction and a threshold voltage compensation circuit are provided at each stage. Therefore, there arises a problem that the circuit scale and circuit area of the shift register circuit are significantly increased. In addition, there is a problem that the operation margin of the shift register circuit is lower than that of a shift register circuit that performs scanning in only one direction.

  The present invention has been made to solve the above problems, and an image display device that realizes bidirectional scanning without increasing the circuit scale and circuit area of the shift register circuit and reducing the operation margin. Another object of the present invention is to provide a semiconductor device used in a scanning line driving circuit of the image display device.

  The semiconductor device according to claim 1 of the present invention includes first and second shift register circuits having a plurality of unit shift registers connected in cascade, and the plurality of unit shift registers of the first shift register circuit. Are connected to the output nodes of the plurality of unit shift registers of the second shift register circuit in a one-to-one relationship, and one of the first and second shift register circuits performs a shift operation. The other is controlled to be in a non-operating state by fixing the power supply voltage to the reference voltage and controlled to fix the gate node of each output transistor of the plurality of unit shift registers to the reference voltage. The

  According to the semiconductor device of the first aspect of the present invention, when one of the first and second shift register circuits is performing the shift operation, the other is not operating with the power supply voltage fixed at the reference voltage. Since the control is performed so that the gate node of the output transistor of each of the plurality of unit shift registers is fixed to the reference voltage, the shift directions of the first and second shift register circuits are different and bidirectional. When controlled to perform scanning, a switch circuit for switching the scan direction and a threshold voltage compensation circuit are not required, and the circuit scale and circuit area of the shift register circuit are reduced in order to realize bidirectional scanning. It can be prevented from becoming significantly large. In addition, a problem that the operation margin of the shift register circuit is reduced as compared with a shift register circuit that performs scanning in only one direction can be prevented.

<A. Embodiment 1>
<A-1. Configuration of Shift Register Circuit>
<A-1-1. Overall configuration>
First, the overall configuration of an image display apparatus 100 that realizes bidirectional scanning according to the present invention will be described with reference to FIG. The image display device 100 is premised on a liquid crystal display device.

  As shown in FIG. 1, the image display device 100 includes shift register circuits 1 and 2 having a multi-stage structure in which a plurality of shift registers are connected in cascade (cascade connection). In this specification, each of the shift registers of each stage constituting the multistage structure is referred to as a “unit shift register”.

  The shift register circuit 1 has n unit shift registers D1 to Dn connected in cascade, and the shift register circuit 2 has n unit shift registers U1 to Un connected in cascade.

  In addition, the image display device 100 includes a pixel array 3 in which scanning lines are driven by the shift register circuits 1 and 2, a source driver 5 that writes image data to the pixel transistors 4 that constitute the pixel array 3, and the shift register circuit 1. And a power supply circuit 6 that supplies a power supply voltage to 2 and 2, and a timing generation that generates a necessary timing for the source driver 5 and the shift register circuits 1 and 2 based on a vertical synchronization signal, a horizontal synchronization signal, image data, a dot clock, and the like A circuit 7 and a control signal switching circuit 8 that controls switching of the shift register circuits 1 and 2 based on the logic of the scan direction switching signal (DIR) are provided.

  The shift register circuit 1 outputs output signals OD1 to ODn from output terminals OUT of unit shift registers D1 to Dn (hereinafter, unit shift registers D1 to Dn are collectively referred to as “unit shift register D”), In the pixel array 3 in which the transistors 4 are arranged in m columns × n rows, the first row gate line G1 on the upper display side is applied to the last gate line Gn on the lower display side. Therefore, the shift register circuit 1 can be referred to as a gate driver circuit that scans in a direction (first direction) in which the gate line G1 is the start row and the gate line Gn is the last row.

  The shift register circuit 2 outputs output signals OU1 to OUn from output terminals OUT of unit shift registers U1 to Un (hereinafter, the unit shift registers U1 to Un are collectively referred to as “unit shift register U”). The pixel array 3 is supplied from the gate line Gn in the last row on the lower display side to the gate line G1 in the first row on the upper display side. Therefore, the shift register circuit 2 can be referred to as a gate driver circuit that scans in a direction (second direction) in which the gate line Gn is the start row and the gate line G1 is the last row.

  As described above, the output terminal OUT of the unit shift register D1 constituting the first stage of the shift register circuit 1 is connected to the output terminal OUT of the unit shift register Un constituting the nth stage of the shift register circuit 2, and hereinafter, It can be seen that the stages of the shift register circuit 1 and the stages of the shift register circuit 2 are connected to each other so that the order of the stage numbers is reversed.

  In FIG. 1, for the sake of convenience, the shift register circuits 1 and 2 are arranged on the left and right with the pixel array 3 interposed therebetween. However, if the connection relationship with each gate line can be the same, They may be arranged at positions opposite to the left and right, may be arranged on either the left or right side, or may be arranged on either the upper or lower side or the upper or lower side with the pixel array 3 interposed therebetween.

  1 is premised on a liquid crystal display device, the application of the present invention is not limited to the liquid crystal display device, and any organic display device can be used as long as it sequentially scans gate lines. The present invention can also be applied to an EL display device and other display devices.

<A-1-2. Configuration of Shift Register Circuit 1>
As shown in FIG. 1, the input terminal IN of each unit shift register D constituting the shift register circuit 1 is connected to the output terminal OUT of the unit shift register D in the preceding stage. A predetermined start pulse STV1 is input to the input terminal IN of the shift register D1. Further, one of the clock signals CLKA1 and CLKB1 is input to the clock terminal CK of each unit shift register D so that clock signals having phases different from those of the unit shift registers D adjacent to each other are input.

  The output terminal OUT of the next unit shift register D is connected to the reset terminal RST of each unit shift register D. The reset terminal RST of the unit shift register Dn, which is the nth stage, is connected to a predetermined terminal. A start pulse STV1 is input. A configuration in which a dedicated reset pulse is given instead of the start pulse STV1 may be adopted.

  Further, a select signal (not shown) of each unit shift register D is supplied with a select signal SEL1, and when the select signal SEL1 becomes significant, the shift register circuit 1 is selected and the first direction is selected. It becomes possible to perform a gate scan.

  Further, a first power supply terminal (not shown) of each unit shift register D is supplied with a low potential side power supply potential (VSS1) which is a circuit reference voltage, and is supplied to a second power supply terminal (not shown). Is supplied with the high potential side power supply potential (VDD1).

  The select signal SEL1, the start pulse STV1, the clock signals CLKA1 and CLKB1 are supplied by the control signal switching circuit 8, and the low potential side power supply potential (VSS1) and the high potential side power supply potential (VDD1) are supplied by the power supply circuit 6. .

<A-1-3. Configuration of Shift Register Circuit 2>
As shown in FIG. 1, the input terminal IN of each unit shift register U constituting the shift register circuit 2 is connected to the output terminal OUT of the unit shift register U in the preceding stage. A predetermined start pulse STV2 is input to the input terminal IN of the shift register U1. In addition, one of the clock signals CLKA2 and CLKB2 is input to the clock terminal CK of each unit shift register U so that clock signals having phases different from those of the unit shift registers U adjacent to each other are input.

  The reset terminal RST of each unit shift register U is connected to the output terminal OUT of the next unit shift register U. The reset terminal RST of the unit shift register Un, which is the nth stage, is connected to a predetermined terminal. A start pulse STV2 is input. A configuration in which a dedicated reset pulse is given instead of the start pulse STV1 may be adopted.

  The select signal (not shown) of each unit shift register U is supplied with a select signal SEL2. When the select signal SEL2 becomes significant, the shift register circuit 2 is selected and the second direction is selected. It becomes possible to perform a gate scan.

  Further, a first power supply terminal (not shown) of each unit shift register U is supplied with a low potential side power supply potential (VSS2) that is a reference voltage of the circuit, and is supplied to a second power supply terminal (not shown). Is supplied with the high potential side power supply potential (VDD2).

  The select signal SEL2, the start pulse STV2, and the clock signals CLKA2 and CLKB2 are given by the control signal switching circuit 8, and the low potential side power supply potential (VSS2) and the high potential side power supply potential (VDD2) are given by the power supply circuit 6. .

<A-1-4. Configuration of Pixel Array 3>
In the pixel array 3, as described above, the pixel transistors 4 are arranged in m columns × n rows, and the gates of the plurality of pixel transistors 4 constituting each row are commonly connected to one gate line. The lines G1 to Gn are connected to the shift register circuits 1 and 2.

  The sources of the plurality of pixel transistors 4 constituting each column are commonly connected to one source line, and the m source lines SL1 to SLm are connected to the source driver 5.

<A-2. Operation of shift register circuit>
Next, the operation of the shift register circuits 1 and 2 will be described with reference to FIG. 1 and FIG. 2 and FIG.

  First, as a specific example of the unit shift registers D and U, the configuration of the unit shift register 10 is shown in FIG.

  Here, the unit shift register 10 will be described as a unit shift register of the k-th stage of the shift register circuit 1 or 2.

  As shown in FIG. 2, the unit shift register 10 has an input terminal IN, an output terminal OUT, a clock terminal CK, and a reset terminal RST. Further, the unit shift register 10 is supplied with the low-potential-side power supply potential VSS (in accordance with FIG. 1, VSS1 is supplied to the shift register circuit 1 and VSS2 is supplied to the shift register circuit 2 through the first power supply terminal S1. VSS is supplied, and the high potential side power supply potential VDD (VDD1 is supplied to the shift register circuit 1 according to FIG. 1, and VDD2 is supplied to the shift register circuit 2 through the second power supply terminal S2). Are referred to as VDD for convenience).

  In FIG. 2, the output stage of the unit shift register 10 includes a transistor Q1 connected between the output terminal OUT and the clock terminal CK, and a transistor Q2 connected between the output terminal OUT and the first power supply terminal S1. It is configured. That is, the transistor Q1 has a clock signal CLKA inputted to the clock terminal CK (according to FIG. 1, CLKA1 is given to the shift register circuit 1 and CLKA2 is given to the shift register circuit 2, but CLKA is used for convenience) or This is a transistor (first transistor) that supplies CLKB (CLKB1 is given to the shift register circuit 1 and CLKB2 is given to the shift register circuit 2 according to FIG. 1 to CLKB for convenience) to the output terminal OUT. The transistor Q2 is a transistor (second transistor) that discharges the output terminal OUT. Hereinafter, a node to which the gate (control electrode) of the transistor Q1 is connected is defined as “node N1”, and a node to which the gate of the transistor Q2 is connected is defined as “node N2”.

  A capacitive element C1 is provided between the gate and source of the transistor Q1 (that is, between the node N1 and the output terminal OUT). The capacitive element C1 is an element (bootstrap capacitance) that capacitively couples the output terminal OUT and the node N1 and boosts the potential of the node N1 in response to a rise in the potential of the output terminal OUT. However, the capacitance element C1 can be omitted if the gate-channel capacitance of the transistor Q1 is sufficiently large, and can be omitted in such a case.

  A transistor Q3 having a gate connected to the input terminal IN is connected between the node N1 and the second power supply terminal S2. A transistor Q4 whose gate is connected to the reset terminal RST is connected between the node N1 and the first power supply terminal S1. That is, the transistor Q3 constitutes a charging circuit that charges the node N1 according to a signal input to the input terminal IN, and the transistor Q4 discharges the node N1 according to a signal input to the reset terminal RST. (First discharge circuit) is configured. Note that the gate (node N2) of the transistor Q2 is also connected to the reset terminal RST.

  Further, a transistor Q13 having a gate connected to the select terminal SS is connected between the node N1 and the first power supply terminal S1, and a select signal SEL (according to FIG. 1) input to the select terminal SS. SEL1 is given to the shift register circuit 1 and SEL2 is given to the shift register circuit 2, but it is SEL for convenience, and a discharge circuit (second discharge circuit) for discharging the node N1 is configured. .

  Here, if the unit shift register 10 is a unit shift register of the k-th stage of the shift register circuit 1 or 2, the unit shift register 10 of the preceding stage (k-1) stage is connected to the input terminal IN of the unit shift register 10. The output signal K-1 is supplied to the input terminal IN of the unit shift register 10 of the first stage. A predetermined start pulse STV (STV1 is applied to the shift register circuit 1 according to FIG. 2 is given STV2 but is referred to as STV for convenience.

  The reset signal RST of the unit shift register 10 of the next stage (k + 1) stage is given to the reset terminal RST of the unit shift register 10, but the reset terminal RST of the unit shift register 10 of the final stage is given to A predetermined start pulse STV is input. A configuration in which a dedicated reset pulse is given instead of the start pulse STV may be adopted.

  The transistor Q3 has been described as being connected between the node N1 and the second power supply terminal S2, but the output output from the output terminal OUT of the preceding unit shift register instead of the second power supply terminal S2. It may be configured to connect to a terminal to which the signal K-1 is applied. Thereby, the effective use of electric power can be aimed at.

  Next, the operation of the shift register circuit 1 when the unit shift register 10 shown in FIG. 2 is applied as the unit shift register of each stage of the shift register circuits 1 and 2 will be described with reference to the timing chart shown in FIG. To do.

  Here, the high level (H level) potential of the clock signals CLKA1 and CLKB1 is VDD (high potential side power supply potential), and the low level (L level) potential is VSS (low potential side power supply potential). To do. The threshold voltage of each transistor constituting the unit shift register 10 is represented as Vth.

  As shown in FIG. 3, first, as an initial state of the unit shift register 10, it is assumed that the node N1 is at the L level, and hereinafter, the state where the node N1 is at the L level is referred to as a “reset state”.

  The input terminal IN and the clock terminal CK (clock signal CLKA1 or CLKB1) are both at L level. At this time, since the transistors Q1 and Q2 are both off, the output terminal OUT is in a high impedance state (floating state). In the initial state, the output terminal OUT is also at L level.

  When the clock signal CLKA1 changes to the L level and the clock signal CLKB1 changes to the H level from the state at time t1, and the start pulse STV1 is input to the input terminal IN of the unit shift register 10 which is the first stage, the transistor Q3 is turned on, and the node N1 is charged and becomes H level (hereinafter, the state where the node N1 is at H level is referred to as “set state”).

  At this time, if the H level of the start pulse STV1 is the same level as VDD (high potential side power supply potential), the transistor Q3 operates in the saturation region, so that the node N1 is equal to the threshold voltage (Vth) of the transistor Q3 from VDD. It rises to the lowered potential (VDD-Vth).

  At time t2, when the start pulse STV1 falls and the clock signal CLKB1 changes to the L level and the clock signal CLKA1 changes to the H level, the potential of the node N1 becomes the overlap capacitance between the drain and gate of the transistor Q1 and the bootstrap. The voltage (VDD) of the clock signal CLKA1 is boosted by the capacitor (C1), and the voltage amplitude (VDD) of the clock signal CLKA1 is increased to the potential (VDD−Vth) of the node N1 before the clock signal CLKA1 is input. Addition results in a potential of 2 × VDD−Vth.

  As a result, the voltage between the gate (node N1) and the drain (output terminal OUT) of the transistor Q1 is kept large even while the output signal of this stage is at the H level. That is, since the on-resistance of the transistor Q1 is kept low, the output signal of the unit shift register 10 rises at high speed following the clock signal CLKA1 and becomes H level.

  At this time, since the transistor Q1 operates in a linear region (non-saturated region), the potential of the output signal OD1 rises to the same VDD as the amplitude of the clock signal CLKA1.

  Further, at time t3, when the clock signal CLKB1 changes to H level and the clock signal CLKA1 changes to L level, the on-resistance of the transistor Q1 is kept low, and the output signal OD1 follows the clock signal CLKA1 and falls at high speed. Return to L level.

  Since the output signal OD1 of the first stage unit shift register 10 is input to the input terminal IN of the second stage unit shift register 10, the transistor Q3 of the second stage unit shift register 10 is turned on. Thus, the node N1 is charged, and the potential of the node N1 is raised to the potential of 2 × VDD−Vth by the clock signal CLKB1 whose phase is shifted from the clock signal CLKA1, and at time t3, the unit of the second stage The output signal OD2 of the shift register 10 becomes H level.

  The output signal OD2 is supplied to the reset terminal RST of the unit shift register 10 in the first stage, and the transistors Q2 and Q4 are turned on. As a result, the output terminal OUT is sufficiently discharged through the transistor Q2, and is surely at L level (VSS). Node N1 is discharged to low level by transistor Q4. That is, the unit shift register 10 of the first stage is in a reset state.

  At time t4, after the output signal OD2 of the unit shift register 10 of the second stage returns to the L level, the unit shift register 10 of the first stage is maintained in the reset state, and the output signal OD1 becomes the L level. Kept.

  By repeating this operation, after the output signal ODn of the nth stage unit shift register 10 returns to L level at time t, the start pulse STV1 is applied to the reset terminal RST of the nth stage unit shift register 10. Thus, the unit shift register 10 in the nth stage is in a reset state.

  To summarize the above operations, the unit shift register 10 is in a reset state during the period when the signal (start pulse STV1 or the previous stage output signal K-1 is not input) is input to the input terminal IN, and the transistor Q1 maintains the OFF state. The signal K is maintained at the L level (VSS), and when the signal is input to the input terminal IN, the unit shift register 10 is switched to the set state, and the transistor Q1 is turned on in the set state, so that the clock terminal CK While the signal (clock signal CLKA1 or CLKB1) is at the H level, the output signal K is at the H level, and then when the signal (the output signal K + 1 or the start pulse STV1 at the next stage) is input to the reset terminal RST. Return to the original reset state.

  According to the shift register circuit 1 including the plurality of unit shift registers 10 operating in this way, when the start pulse ST is input to the unit shift register 10 of the first stage, the output signal Are shifted at a timing synchronized with the clock signals CLKA1 and CLKB1, and output signals from each unit shift register are output from OD1, OD2, OD3... ODn-3, ODn-2, ODn-1 as shown in FIG. , ODn.

  In the image display device 100, the output signals output in this order are used as horizontal (or vertical) scanning signals for the display panel. Hereinafter, a period during which a specific unit shift register outputs an output signal is referred to as a “selection period” of the unit shift register.

  In the final stage unit shift register 10, by applying a start pulse STV1 (or a dedicated reset pulse) to the reset terminal RST, the transistors Q2 and Q4 are turned on to discharge the output terminal OUT and discharge the node N1. As a result, the operation of the shift register circuit 1 is completed.

  Further, the shift register circuit 2 can be operated by setting the scan direction switching signal DIR to the H level. Since the configuration of the shift register circuit 2 is the same as that of the shift register circuit 1 and the operation is the same except that the scanning direction is opposite, description thereof is omitted.

  Note that the shift register circuits 1 and 2 can be arbitrarily operated by selecting the scan direction switching signal DIR, and the scan direction is arbitrary depending on whether the shift register circuit 1 is selected or the shift register circuit 2 is selected. You can switch to

  In addition, the image display device 100 illustrated in FIG. 1 has the configuration including the two shift register circuits 1 and 2 having different scan directions, but the shift register circuit is not limited to two, It is not necessary that the scanning directions are different from each other, and all the shift register circuits may scan in the same direction.

  For example, the shift register circuit 2 is divided into two to be an upper shift register circuit and a lower shift register circuit, and each is configured to operate independently, so that only the shift register circuit 1 operates, the upper shift register Operation patterns such as operation of only the circuit, operation of only the lower shift register circuit, and operation of only the upper and lower shift register circuits are possible, and variations in image display can be increased.

  Next, the overall operation of the image display apparatus 100 including the operation of the shift register circuit 2 will be described with reference to FIG. 1 and FIG. 4 showing a timing chart.

  As shown in FIG. 4, the shift register circuit 1 is supplied with the start pulse STV1 and the clock signals CLKA1 and CLKB1 when the scan direction switching signal DIR applied to the control signal switching circuit 8 (FIG. 1) is at the L level. Thus, the high potential side power supply potential VDD1 becomes H level.

  Further, during the period in which the scan direction switching signal DIR is at the L level, the select signal SEL1 is maintained at the L level, so that the shift register circuit 1 is operated, and the image is scanned sequentially from the gate line G1. An image corresponding to the data signal is displayed on the display.

  On the other hand, the start pulse STV2 and the clock signals CLKA2 and CLKB2 are not supplied to the shift register circuit 2 while the scan direction switching signal DIR is at the L level, and the high potential side power supply potential VDD2 is also fixed at the L level. Here, during the period in which the scan direction switching signal DIR is at the L level, the shift register circuit 2 does not operate by controlling the select signal SEL2 to maintain the H level.

  Here, select signals SEL1 and SEL2 applied to shift register circuits 1 and 2, respectively, are signals for discharging node N1 of unit shift register 10 constituting the non-operating side shift register circuit via transistor Q13. In the period during which the shift register circuit 1 is performing the shift operation, the select signal SEL1 is fixed to the L level, while the select signal SEL2 is fixed to the H level, so that the unit shift register constituting the shift register circuit 2 is provided. The potential of the ten nodes N1 is fixed to the L level.

  When the shift register circuit 2 is non-operating and the potential of the node N1 of the unit shift register 10 constituting the shift register circuit 2 is not fixed at the L level, when the gate line is selected by the shift register circuit 1, The potential of the node N1 of the unit shift register 10 constituting the shift register circuit 2 commonly connected to the gate line is increased by the coupling due to the gate-drain overlap capacitance, and the transistor Q1 is turned on. . In the case where the bootstrap capacitor C1 is provided, the potential of the node N1 rises due to coupling due to the bootstrap capacitor and the gate-drain overlap capacitor. In this case, since the high-potential side power supply potential VDD2 of the non-operating shift register circuit 2 is fixed at the L level, the potential of the gate line selected by the shift register circuit 1 is lowered, and the circuit operation margin is lowered. become.

  The transistor Q13 is a transistor for fixing the potential of the node N1 of the non-operating unit shift register 10 to the L level. By including this, the above-described reduction in the circuit operation margin can be prevented.

  On the other hand, as shown in FIG. 4, when the scan direction switching signal DIR is at the H level, the shift register circuit 2 is supplied with the start pulse STV2 and the clock signals CLKA2 and CLKB2, and the high potential side power supply potential VDD2 is set to H. Become a level.

  Further, during the period when the scan direction switching signal DIR is at the H level, the select signal SEL2 is maintained at the L level, so that the shift register circuit 2 is operated, and the image is scanned sequentially from the gate line Gn. An image corresponding to the data signal is displayed on the display. Therefore, when the shift register circuit 1 is operated, an inverted image is displayed on the display. By switching the operations of the shift register circuit 1 and the shift register circuit 2, a vertically inverted image can be arbitrarily set. It can be displayed.

  In this case, since the start pulse STV1 and the clock signals CLKA1 and CLKB1 are not applied, the high-potential power supply potential VDD1 is also fixed to the L level, and the select signal SEL1 is set to the H level, the shift register circuit 1 does not operate.

  In the image display apparatus 100 described above, an example is shown in which the two-phase clocks of the clock signals CLKA1 and CLKB1 (CLKA2 and CLKB2) are used as the shift clock. There is no limit to the number of clock phases.

<A-3. Effect>
In the image display device 100 described above, the shift register circuits 1 and 2 capable of scanning the gate lines only in a single direction are prepared, and the shift register circuit is assigned for each scan direction, thereby switching the scan direction. Since the switch circuit and the threshold voltage compensation circuit are not required, and bidirectional scanning is realized, it is possible to prevent the circuit scale and circuit area of the shift register circuit from being significantly increased. In addition, a problem that the operation margin of the shift register circuit is reduced as compared with a shift register circuit that performs scanning in only one direction can be prevented.

<A-4. Modification 1>
The unit shift registers D and U constituting the shift register circuits 1 and 2 shown in FIG. 1 are not limited to the unit shift register 10 described with reference to FIG. 2, but for example, the unit shift register shown in FIG. The register 10A may be adopted. In the unit shift register 10A, the same components as those in the unit shift register 10 shown in FIG. 2 are denoted by the same reference numerals, and redundant description is omitted.

  Here, the unit shift register 10A will be described as the k-th stage unit shift register of the shift register circuit 1. In the unit shift register 10A, the capacitor C1 is not provided between the output terminal OUT and the node N1, the gate (node N2) of the transistor Q2 is not connected to the reset terminal RST, and the node N2 and the second power supply A transistor Q5 that is diode-connected to the terminal S2, and an inverter that includes a transistor Q6 that is connected between the node N2 and the first power supply terminal S1 and that has a gate connected to the node N1; Q6 is set to have a sufficiently smaller on-resistance than the transistor Q5.

  When the node N1 is at L level, the transistor Q6 is turned off, so that the node N2 is at H level (VDD-Vth (Q5)). Conversely, when the node N1 is at the H level, the transistors Q5 and Q6 are both turned on, but the node N2 is at the L level of the potential (≈0V) determined by the ratio of the on resistances of the transistors Q5 and Q6. That is, the inverter is a so-called “ratio inverter”.

  Here, the unit shift register 10A is connected to the unit shift register 10A in a period other than the selection period (for example, 50 μsec) for scanning the gate line (this is referred to as “non-selection period”, for example, 16.6 msec-50 μsec). The gate line thus formed needs to maintain the L level. Therefore, it is desirable that the transistor Q2 for pulling down the output is always on during the non-selection period.

  The ratio type inverter is suitable for realizing such an operation, and while the node N1 is at the L level, the inverter composed of the transistors Q5 and Q6 maintains the node N2 at the H level, so that the non-selection period During this time, transistor Q2 is kept on. That is, since the output terminal OUT in the non-selection period is fixed at the L level with low impedance, the operation is stabilized.

  In the selection period of the unit shift register 10A, the transistor Q6 is turned on so that the potential of the gate (node N2) of the transistor Q2 is lowered to L level so that the transistor Q2 is not turned on.

  Further, as shown in FIG. 5, a transistor Q13 having a gate connected to the select terminal SS is connected between the node N1 and the first power supply terminal S1, and the node N2 and the first power supply terminal are connected. A transistor Q14 having a gate connected to the select terminal SS is connected to S1, and is activated in response to a select signal SEL input to the select terminal SS, and discharges the nodes N1 and N2. Is configured.

  By adopting such a configuration, the potentials of the nodes N1 and N2 of the unit shift register 10A can be fixed to the L level in the non-operation side shift register circuit. Therefore, even when the gate line connected to the unit shift register 10A is selected by the shift register circuit on the operating side, the potential of the node N1 of the unit shift register 10A on the non-operating side is between the gate and the drain of the transistor Q1. The transistor Q1 can be prevented from being turned on due to the coupling due to the overlap capacitance, and the potential of the node N2 is raised due to the coupling due to the overlap capacitance between the gate and the drain of the transistor Q2, and the transistor Q2 is turned on. Can be prevented. For this reason, it is possible to prevent the potential of the gate line selected by the shift register circuit on the operation side from being lowered and the circuit operation margin from being lowered.

<A-5. Modification 2>
In contrast to the unit shift register 10A shown in FIG. 5, as shown in FIG. 6, a unit shift register in which a transistor Q7 whose gate is connected to the node N2 is provided between the node N1 and the first power supply terminal S1. 10B may be adopted. In the unit shift register 10B, the same components as those of the unit shift register 10A shown in FIG.

  Here, the unit shift register 10B will be described as the kth stage unit shift register of the shift register circuit 1. In the unit shift register 10A shown in FIG. 5, when the output signal of the next stage unit shift register 10A becomes H level (next stage selection period), the transistor Q4 is turned on to discharge the node N1. During the non-selection period when the select signal SS is not at the H level, the node N1 is at the L level with high impedance (floating state). Therefore, if charge is supplied to the node N1 due to noise or leakage current during the non-selection period, the potential of the node N1 may rise. In this case, the transistor Q1 is turned on, and the output signal is output as an erroneous signal. A malfunction of being output occurs.

  The transistor Q7 is a transistor that fixes the node N1 to the L level during the non-selection period when the select signal SS is not at the H level. In combination with the presence of the transistor Q13, the node N1 has a low impedance and the L level during all the non-selection periods. It will be fixed to. Therefore, the increase in the level of the node N1 is suppressed in all non-selection periods, and the occurrence of the malfunction is prevented.

<B. Second Embodiment>
In the first embodiment according to the present invention, in the unit shift registers 10, 10A, and 10B described with reference to FIGS. 2, 5, and 6, the gate (node N2) of the transistor Q2 continues during the non-selection period. As a result, the output terminal OUT can be set to L level with low impedance. However, when the gate of the a-Si transistor is continuously positively biased with respect to the source, the threshold voltage shifts in the positive direction. When the threshold voltage of the transistor Q2 shifts in the positive direction, the on-resistance of the transistor Q2 increases, and the output terminal OUT may not be able to have a sufficiently low impedance.

  In the second embodiment of the present invention, the configuration of a unit shift register that reduces the possibility as described above will be described.

<B-1. Device configuration>
FIG. 7 shows a configuration of the unit shift register 20 according to the second embodiment. In the unit shift register 20, transistors Q2A and Q2B are connected in parallel between the output terminal OUT and the first power supply terminal S1 as transistors for discharging the output terminal OUT. The same components as those of the unit shift register 10 shown in FIG.

  Here, the unit shift register 20 will be described as a kth stage unit shift register of the shift register circuit 1. First, nodes to which the gates of transistors Q2A and Q2B are connected are defined as “node N2A” and “node N2B”, respectively.

  A transistor Q3 having a gate connected to the input terminal IN is connected between the node N1 and the second power supply terminal S2, and a gate is connected to the reset terminal between the node N1 and the first power supply terminal S1. A transistor Q4 connected to RST is connected.

  Further, a transistor Q13 having a gate connected to the select terminal SS is connected between the node N1 and the first power supply terminal S1, and is activated according to a select signal SEL input to the select terminal SS. A discharge circuit for discharging the node N1 is configured.

  Transistors Q14a and Q14b are connected between the node N2A and the first power supply terminal S1, and between the node N2B and the first power supply terminal S1, respectively, and the respective gates are connected to the select terminal SS. ing. Transistors Q14a and Q14b are activated according to a select signal SEL input to select terminal SS, and constitute a discharge circuit that discharges nodes N2A and N2B, respectively.

  A transistor Q7A having a gate connected to the node N2A and a transistor Q7B having a gate connected to the node N2B are connected in parallel between the node N1 and the first power supply terminal S1. Transistors Q7A and Q7B are transistors that discharge node N1.

  Further, it has a ratio type inverter composed of transistors Q5 and Q6 connected in series between the second power supply terminal S2 and the first power supply terminal S1, and the gate of the transistor Q5 is the second power supply terminal S2. The transistor Q6 has a gate connected to the node N1.

  A transistor Q9A is connected between the output terminal of the ratio type inverter and the node N2A, and a transistor Q9B is connected between the output terminal of the inverter and the node N2B. The gate of the transistor Q9A is connected to the first control terminal TA, and the gate of the transistor Q9B is connected to the second control terminal TB.

  The transistor Q8A is connected between the first control terminal TA and the node N2A, the transistor Q8B is connected between the second control terminal TB and the node N2B, and the gate of the transistor Q8A is connected to the node N2B. The gate of the transistor Q8B is connected to the node N2A. That is, the transistor Q8A and the transistor Q8B have one main electrode (drain in this case) connected to each other's control electrode (gate) so as to form a so-called flip-flop circuit.

  Here, in FIG. 8, the control signals VFR1 and xVFR1 are supplied from the control signal switching circuit 8 to each shift register circuit of the shift register circuit 1, and the control signal switching circuit 8 is supplied to each shift register circuit of the shift register circuit 2. 2 shows the configuration of the image display device 200 to which the control signals VFR2 and xVFR2 are applied.

<B-2. Device operation>
The unit shift register 20 is supplied with a first control signal VFR (according to FIG. 8, VFR1 is given to the shift register circuit 1 and VFR2 is given to the shift register circuit 2 but VFR for convenience). The second control terminal TA and the control signal xVFR (according to FIG. 8, xVFR1 is given to the shift register circuit 1 and xVFR2 is given to the shift register circuit 2 but for convenience xxFRR). A terminal TB is provided. The control signals VFR and xVFR are complementary signals.

  The control signals VFR and xVFR are signals whose levels are switched at a constant cycle. In driving the gate line, it is desirable to control the level to switch (alternate) during the blanking period between frames of the display image. For example, the level is controlled to switch for each frame of the display image.

  Since the transistor Q9A is turned on and the transistor Q9B is turned off while the control signal VFR is at the H level and the control signal x number VFR is at the L level, the output terminal of the inverter composed of the transistors Q5 and Q6 is connected to the node N2A Is done. At this time, the transistor Q8B is turned on, and the node N2A becomes L level. That is, during that period, the transistor Q2A is driven, and the transistor Q2B is in a dormant state.

  Conversely, during the period when the control signal VFR is at L level and the control signal xVFR is at H level, the transistor Q9A is turned off and the transistor Q9B is turned on, so that the output terminal of the inverter constituted by the transistors Q5 and Q6 is connected to the node N2B. Connected. At this time, the transistor Q8A is turned on, and the node N2B becomes L level. That is, during that period, the transistor Q2B is driven, and the transistor Q2A is in a resting state.

  Thus, the transistors Q9A and Q9B function as a switching circuit that alternately connects the output terminal of the ratio type inverter to the node N2A and the node N2B based on the control signals VFR and xVFR.

<B-3. Effect>
Thus, in the unit shift register 20, each time the control signals VFR and xVFR are inverted, the pair of the transistors Q2A and Q8A and the pair of the transistors Q2B and Q8B are alternately in a dormant state. Continuous biasing can be prevented. Therefore, malfunction due to a positive shift of the threshold value of the a-Si transistor can be prevented, and the operation reliability is improved.

  The transistors Q7A and Q7B are transistors that fix the node N1 to the L level during the non-selection period in which the select signal SS is not at the H level. During the period in which the transistor Q9A is on, the transistor Q7A is on and the node N1 Is fixed at the L level, and during the period when the transistor Q9B is on, the transistor Q7B is turned on and the node N1 is fixed at the L level. Therefore, the node N1 is fixed at the L level regardless of the control signals VFR and xVFR. In combination with the presence of the transistor Q13, the node N1 is fixed to the L level with low impedance in all non-selection periods. Therefore, the increase in the level of the node N1 is suppressed in all non-selection periods, and the occurrence of malfunction is prevented.

  Since the transistors Q14a and Q14b can fix the potentials of the nodes N2A and N2B to the L level during the period in which the select signal SS is at the H level, the gate line connected to the unit shift register 20 is connected to the operation side. Even when selected by the shift register circuit, the potential of the node N2 of the unit shift register 20 on the non-operating side rises due to the coupling due to the overlap capacitance between the gates and drains of the transistors Q2A and Q2B, and the transistors Q2A and Q2B It can be prevented from turning on. For this reason, it is possible to prevent the potential of the gate line selected by the shift register circuit on the operation side from being lowered and the circuit operation margin from being lowered.

<C. Embodiment 3>
<C-1. Device configuration>
FIG. 9 shows the configuration of the unit shift register 30 according to the third embodiment of the present invention. The same components as those of the unit shift register 10 shown in FIG. In the unit shift register 30, any one of the clock signals CLKA, CLKB, and CLKC is input to the clock terminal CK (one of the clock signals CLKA, CLKB, and CLKC is input to the shift register circuit 2). It has become.

  The unit shift register 30 has two input terminals, a first input terminal IN1 and a second input terminal IN2. The first input terminal IN1 is connected to the output terminal OUT at the preceding stage, The second input terminal IN2 is connected to the previous output terminal OUT. The start pulses STV11 (or STV21) and STV1 (or STV2) are input to the first input terminal IN1 and the second input terminal IN2 of the unit shift register 30 in the first stage, respectively. The start pulses STV11 and STV1 are activated (become H level) at different timings, and the start pulse STV1 is activated after the start pulse STV11.

  In the unit shift register 30, the configuration for charging the node N1 of the transistor Q3 is different from that of the unit shift register 10, and the transistor Q10 that charges the gate node (defined as “node N4”) of the transistor Q3, The capacitor C2 that boosts N4 and the transistor Q4 that discharges the node N4 are provided.

  As shown in FIG. 9, the transistor Q10 is connected between the node N4 and the second power supply terminal S2, and the gate is connected to the first input terminal IN1. The capacitive element C2 is connected between the node N4 and the second input terminal IN2, the transistor Q4 is connected between the node N4 and the first power supply terminal S1, and the gate thereof is connected to the reset terminal RST. It is connected.

  The unit shift register 30 includes a ratio type inverter (configured by transistors Q5 and Q6) having the node N4 as an input terminal, and the gates of the transistors Q2 and Q7 (node N2) that discharge the output terminal OUT and the node N1, respectively. ) Are both connected to the output terminal of the inverter. A transistor Q11 is connected in parallel with the transistor Q4 between the node N4 and the first power supply terminal S1, and its gate is connected to the node N2.

  A transistor Q13 having a gate connected to the select terminal SS is connected between the node N1 and the first power supply terminal S1, and a gate is connected between the node N2 and the first power supply terminal S1. Is connected to the select terminal SS, is activated in response to a select signal SEL input to the select terminal SS, and constitutes a discharge circuit that discharges the nodes N1 and N2.

  Here, FIG. 10 shows the configuration of the image display device 300 including the shift register circuits 1 and 2 each including a plurality of unit shift registers 30, and each unit shift register 30 of the shift register circuits 1 and 2 is shown. The connection relationship of the signals given to the first input terminals IN1 and IN2 is shown. In FIG. 10, the unit shift register 30 is configured to perform a shift operation with a three-phase clock of clock signals CLKA1, CLKB1, and CLKC1 (CLKA2, CLKB2, and CLKC2) as a shift clock.

  Further, the start pulse STV1 (or STV2) or STV11 (or STV11) is input to the reset terminal RST of the unit shift register 30 at the final stage depending on the number of stages of the unit shift register 30. That is, in the shift register circuit 1, when the clock signal CLKA1 is applied to the last unit shift register 30, the start pulse STV11 is applied. In the shift register circuit 2, the clock signal is applied to the last unit shift register 30. When CLKA2 is given, a start pulse STV21 is given.

<C-2. Device operation>
The unit shift register 30 is characterized in that the gate of the transistor Q3 that charges the node N1 is charged and boosted using the output signals of the previous stage and the previous stage.

  Here, the unit shift register 30 will be described as the kth stage unit shift register of the shift register circuit 1. That is, in the unit shift register 30, the gate of the transistor Q3 (node N4) is pre-set to the level of VDD-Vth (Q10) by the transistor Q10 when the output signal K-2 of the preceding stage is at the H level. Charged. Next, when the output signal K-1 at the previous stage becomes the H level, the node N4 is boosted to about 2 × VDD−Vth (10) by the capacitive element C2. That is, the gate potential of the transistor Q3 is about VDD higher than that of the unit shift register of FIG. 2, and the transistor Q3 can charge the node N1 not by the source follower mode but by the operation in the non-saturated region. Therefore, since the node N1 is charged at high speed and becomes H level (VDD), the operation of the shift register circuit can be speeded up.

  In the unit shift register 30, since the gate (node N4) of the transistor Q3 is in a floating state during the selection period, the transistor Q4 controlled by the output signal K + 1 in the next stage is used for discharging the node N4. . This is different from the unit shift register 10 shown in FIG. 2 in which the transistor Q4 is used as the discharge transistor of the node N1.

  When the transistor Q4 sets the node N4 to the L level, the node N2 is set to the H level by the ratio type inverter constituted by the transistors Q5 and Q6, and accordingly the transistor Q7 is turned on to discharge the node N1. That is, in the unit shift register 30, the transistor Q7 plays a role of discharging the node N1 in accordance with a signal input to the reset terminal RST (that is, the role of the transistor Q4 in FIG. 2).

  The transistor Q11 operates to maintain the node N4 at the low impedance L level while the node N2 is at the H level (non-selection period), thereby preventing the unit shift register from malfunctioning. Is done.

<C-3. Effect>
As described above, in the shift register circuit on the non-operating side, the potentials of the nodes N1 and N2 of the unit shift register 30 can be fixed to the L level, so that the gate line connected to the unit shift register 30 Even when selected by the shift register circuit on the operating side, the potential of the node N1 of the unit shift register 30 on the non-operating side rises due to the coupling due to the overlap capacitance between the gate and drain of the transistor Q1, and the transistor Q1 is turned on. Can be prevented. Further, it is possible to prevent the transistor Q2 from being turned on by the potential of the node N2 rising due to the coupling due to the overlap capacitance between the gate and the drain of the transistor Q2. For this reason, it is possible to prevent the potential of the gate line selected by the shift register circuit on the operation side from being lowered and the circuit operation margin from being lowered.

<D. Embodiment 4>
<D-1. Device configuration>
FIG. 11 shows the configuration of the unit shift register 40 according to the fourth embodiment of the present invention. The same components as those of the unit shift register 10 shown in FIG.

  The unit shift register 40 has two clock terminals. In other words, in addition to the first clock terminal CK1 to which the drain of the transistor Q1 is connected, a second clock terminal CK2 to which a clock signal having a phase different from that inputted thereto is input.

  A transistor Q12 whose gate is connected to the first clock terminal CK1 is provided between the node N1 and the output terminal OUT. And it has a ratio type inverter constituted by transistors Q5 and Q6A connected in series between the second clock terminal CK2 and the first power supply terminal S1, and the gate of the transistor Q5 is the second clock terminal CK2 The transistor Q6A has its gate connected to the node N1. That is, the clock signal input to the second clock terminal CK2 serves as a power source for the inverter.

  A transistor Q6B having a gate connected to the first clock terminal CK1 is provided between the output terminal of the ratio type inverter (defined as “node N5”) and the first power supply terminal S1.

  Further, a transistor Q7 whose gate is connected to the node N5 is connected between the node N1 and the first power supply terminal S1. In the unit shift register 40, the gate of the transistor Q2 connected between the output terminal OUT and the first power supply terminal S1 is connected to the second clock terminal CK2.

<D-2. Device operation>
The basic operation of the unit shift register 40 is almost the same as that of the unit shift register 10 shown in FIG. 2, except that the inverter formed of the transistors Q5 and Q6A receives a clock signal input to the second clock terminal CK2. It is characterized in that it is activated when power is supplied by, and its output is forcibly fixed to the L level by the transistor Q6B.

  Here, the operation will be described with the unit shift register 40 as the k-th stage unit shift register of the shift register circuit 1. For simplicity, in the unit shift register 40, the clock signal CLKA is input to the first clock terminal CK1, and the clock signal CLKB is input to the second clock terminal CK2. In the k-th stage unit shift register 40, when the clock signal CLKA is input to the first clock terminal CK1 and the clock signal CLKB is input to the second clock terminal CK2, the unit of the next stage (k + 1 stage). In the shift register 40, the clock signal CLKB is input to the first clock terminal CK1, and the clock signal CLKA is input to the second clock terminal CK2. As described above, the clock signals CLKA and CLKB are alternately input to the first clock terminal CK1 and the second clock terminal CK2 for each stage of the plurality of unit shift registers 40 connected in cascade. Needless to say.

  First, the operation of the unit shift register 40 during the non-selection period will be described. Since node N1 is at L level during the non-selection period, node N5 attains H level when the inverter formed of transistors Q5 and Q6A is activated by clock signal CLKB. When the inverter is inactivated, transistor Q6B is turned on by clock signal CLKA, so that node N5 is at L level. That is, in the non-selection period, the level of the node N5 changes almost in the same manner as the clock signal CLKB. Therefore, the transistor Q7 sets the node N1 to the low impedance L level at the timing when the clock signal CLKB becomes the H level.

  The transistor Q7 is turned off when the clock signal CLKB is at the L level. During this period, the clock signal CLKA turns on the transistor Q12, so that the charge at the node N1 is discharged to the output terminal OUT by the transistor Q12. In general, since a capacitive load (a gate line of the pixel array) is connected to the output terminal OUT, the output terminal OUT does not become H level with the charge that is discharged to the output terminal OUT.

<D-3. Effect>
Thus, during the non-selection period of the unit shift register 40, the transistor Q7 and the transistor Q12 operate so as to alternately discharge the node N1, thereby preventing the level of the node N1 from rising. Since the gates of transistors Q7 and Q12 are not continuously positively biased, the positive shift of their threshold voltages is suppressed.

  Further, the transistor Q2 is turned on when the clock signal CLKB becomes H level, and sets the output terminal OUT to L level with low impedance. That is, since the gate of the transistor Q2 is not continuously positively biased, the positive shift of the threshold voltage is also suppressed.

  Further, when the output signal K-1 at the previous stage becomes H level and the selection period of the unit shift register 40 is reached, the node N1 becomes H level. In the meantime, even if the inverter composed of transistors Q5 and Q6A is activated by clock signal CLKB, node N5 is at L level, so transistor Q7 is turned off and the H level of node N1 is maintained. When the clock signal CLKA becomes H level, the gate of the transistor Q12 becomes H level. At the same time, the output terminal OUT (output signal K) also becomes H level. Therefore, the transistor Q12 is not turned on and the node N1 is in a floating state. And maintained at the H level (stepped up by the clock signal CLKA). Therefore, the unit shift register 40 can output the output signal K normally.

  When the shift register circuit 1 is not operating, the node N1 of the unit shift register 40 is discharged through the transistor Q13, so that the potential of the node N1 of the unit shift register 40 is overlapped between the gate and the drain. It is possible to prevent the transistor Q1 from being turned on due to coupling due to the capacitance, and to prevent the circuit operation margin of the operating shift register circuit 2 from being lowered.

<D-4. Modification>
In the above description, the source of the transistor Q2 is connected to the first power supply terminal S1, but it may be connected to the first clock terminal CK1. In that case, when the clock signal CLKB input to the gate of the transistor Q2 becomes L level and the transistor Q2 is turned off, the clock signal CLKA input to the source becomes H level, so that the gate of the transistor Q2 Is equivalent to being negatively biased with respect to the source. As a result, the threshold voltage shifted in the positive direction returns and recovers in the negative direction, so that the reduction in the driving capability of the transistor Q2 is reduced, and the operation life of the circuit is extended.

<E. Embodiment 5>
<E-1. Device configuration>
FIG. 12 shows the configuration of the unit shift register 50 according to the fifth embodiment of the present invention. The same components as those of the unit shift register 10 shown in FIG.

  The unit shift register 50 also includes a first clock terminal CK1 to which the drain of the transistor Q1 is connected, and a second clock terminal CK2 to which a clock signal having a phase different from that input thereto is input.

  In the unit shift register 50, transistors Q2A and Q2B are connected in parallel between the output terminal OUT and the first power supply terminal S1 as transistors for discharging the output terminal OUT.

  Here, the unit shift register 50 will be described as a kth stage unit shift register of the shift register circuit 1. First, a node to which the gate of the transistor Q2A is connected is defined as “node N2”.

  A transistor Q3 having a gate connected to the input terminal IN is connected between the node N1 and the second power supply terminal S2, and a gate is connected to the reset terminal between the node N1 and the first power supply terminal S1. A transistor Q4 connected to RST is connected. Further, a transistor Q7 whose gate is connected to the node N2 is connected between the node N1 and the first power supply terminal S1. The transistor Q3 has been described as being connected between the node N1 and the second power supply terminal S2, but the output output from the output terminal OUT of the preceding unit shift register instead of the second power supply terminal S2. It may be configured to connect to a terminal to which the signal K-1 is applied.

  An inverter is provided between the first clock terminal CK1 and the first power supply terminal S1. The inverter includes a capacitive element C3 and a transistor Q6 whose gate is connected to the node N1. Yes. The inverter circuit is a capacitive load type inverter having a gate node (node N1) of the transistor Q1 as an input terminal, a gate node (node N2) of the transistor Q2A as an output terminal, and a capacitive element C3 as a load element.

  The inverter is different from a normal inverter in that a clock signal input to the first clock terminal CK1 serves as a power source. That is, the capacitive element C3 connected between the node N2 which is the output terminal of the inverter and the first clock terminal CK1 is a load element of the inverter and is a combination of the first clock terminal CK1 and the node N2. It also functions as a capacity.

  Further, in the unit shift register 50, a transistor Q2B is connected in parallel with the transistor Q2A whose gate is connected to the output terminal of the inverter. The gate of the transistor Q2B is connected to the second clock terminal CK2.

  A transistor Q13 having a gate connected to the select terminal SS is connected between the node N1 and the first power supply terminal S1, and a gate is selected between the node N2 and the first power supply terminal S1. A transistor Q14 connected to the terminal SS is connected, and is activated in accordance with a select signal SEL input to the select terminal SS to constitute a discharge circuit that discharges the nodes N1 and N2.

<E-2. Device operation>
The basic operation of the unit shift register 50 is substantially the same as that of the unit shift register 10 shown in FIG. 2, but an inverter composed of a capacitive element C3 and a transistor Q6 is input to the first clock terminal CK1. It is characterized in that it is activated when power is supplied by the clock signal.

  Here, the operation will be described using the unit shift register 50 as the kth unit shift register of the shift register circuit 1. For simplicity, in the unit shift register 50, the clock signal CLKA is input to the first clock terminal CK1, and the clock signal CLKB is input to the second clock terminal CK2.

  First, the operation of the unit shift register 50 during the non-selection period will be described. In the non-selection period, the node N1 is at the L level, so that the node N2 is set to the H level when the inverter formed of the capacitor C3 and the transistor Q6 is activated by the clock signal CLKA. When the inverter becomes inactive, the node N2 becomes L level in response to the fall of the clock signal CLKA because of coupling through the capacitive element C3. That is, in the non-selection period, the level of the node N2 changes almost in the same manner as the clock signal CLKA. Therefore, the transistor Q7 sets the node N1 to L level with low impedance at the timing when the clock signal CLKA becomes H level.

  Similarly to the transistor Q7, the transistor Q2A is turned on at a timing synchronized with the clock signal CLKA, thereby setting the output terminal OUT to the L level of low impedance. When the clock signal CLKA is at L level, the transistor Q2A is turned off. At this time, the transistor Q2B is turned on by the clock signal CLKB, and the output terminal OUT is set to L level with low impedance.

<E-3. Effect>
Thus, during the non-selection period of the unit shift register 50, the level of the node N1 is prevented from increasing by the transistor Q7 operating so as to discharge the node N1 at a timing synchronized with the clock signal CLKA. Further, the transistor Q2A and the transistor Q2B alternately discharge the output terminal OUT, thereby preventing the output signal K as an erroneous signal from being generated. Since the gate electrodes of these transistors Q2A, Q2B and Q7 are not continuously positively biased, the positive shift of their threshold voltages is suppressed.

  When the output signal K-1 at the previous stage becomes H level and the selection period of the unit shift register 50 is reached, the transistor Q3 of the unit shift register 50 is turned on, so that the node N1 becomes H level. At that time, the inverter formed of the capacitive element C3 and the transistor Q6 is inactive, and the node N2 is at the L level. When the clock signal CLKA becomes H level, the inverter is activated. However, since the transistor Q6 is turned on, the node N2 maintains L level. Therefore, the transistor Q7 is kept off during the selection period, and the node N1 is kept at the H level in a floating state (boosted by the clock signal CLKA). Therefore, the unit shift register 50 can output the output signal K normally.

  When shift register circuit 1 is not operating, nodes N1 and N2 of unit shift register 50 are discharged through transistors Q13 and Q14, so that the potentials of nodes N1 and N2 can be fixed at the L level. it can.

  Therefore, even when the gate line connected to the unit shift register 50 is selected by the shift register circuit on the operation side, the potential of the node N1 of the unit shift register 50 on the non-operation side is over the gate-drain of the transistor Q1. The transistor Q1 can be prevented from being turned on due to the coupling due to the wrap capacitance, and the potential of the node N2 is increased due to the coupling due to the overlap capacitance between the gate and drain of the transistors Q2A and Q2B, and the transistors Q2A and Q2B Can be prevented from turning on. For this reason, it is possible to prevent the potential of the gate line selected by the shift register circuit on the operation side from being lowered and the circuit operation margin from being lowered.

<F. About Embodiment 6>
In the unit shift register described in the first to fifth embodiments, the configuration in which the potential of the gate node of the transistor constituting the output stage is forcibly fixed to the L level according to the select signal SEL is shown. It is also possible to fix the potential without using.

  Hereinafter, as a sixth embodiment according to the present invention, a configuration in which the potential is fixed without using the select signal SEL for each of the unit shift registers shown in the respective embodiments will be described.

<F-1. Application to Unit Shift Register 10A>
<F-1-1. First application example>
FIG. 13 shows a configuration of a unit shift register 10A1 in which a configuration in which the potential is fixed without using the select signal SEL is applied to the unit shift register 10A shown in FIG. Note that the same components as those of the unit shift register 10A shown in FIG.

  As shown in FIG. 13, in the unit shift register 10A1, the source of the transistor Q13 is connected to the second power supply terminal S2, and the gates of the transistors Q13 and Q14 are connected to the output terminal OUT. The select signal SEL is not used.

  When such a configuration is adopted, when the gate line connected to the unit shift register 10A1 of the non-operating side shift register circuit is selected by the unit shift register 10A1 of the operating side shift register circuit, the potential of the gate line The transistors Q13 and Q14 of the unit shift register 10A1 of the non-operating shift register circuit are turned on. However, as described with reference to FIG. 4, in the non-operating shift register circuit, the high-potential power supply potential VDD is also at the L level. Therefore, the potentials of nodes N1 and N2 are fixed at the L level.

  On the other hand, in the unit shift register 10A1 of the operation-side shift register circuit, the gate potential of the transistor Q13 rises to the high-potential power supply potential VDD due to the selection of the gate line, but since the source potential is the high-potential power supply potential VDD, the transistor Q13 is not turned on and does not affect the operation of the shift register circuit. Further, although the transistor Q14 is also turned on, the transistor Q2 for pulling down the output is fixed in the off state, so that the operation of the shift register circuit is not affected.

  Therefore, according to the unit shift register 10A1, it is possible to prevent the potential of the selected gate line from being lowered and the circuit operation margin from being lowered, and it is not necessary to supply the select signal SEL from the outside. Become.

<F-1-2. Second application example>
FIG. 14 shows a configuration of a unit shift register 10A2 in which a configuration in which the potential is fixed without using the select signal SEL is applied to the unit shift register 10A shown in FIG. Note that the same components as those of the unit shift register 10A shown in FIG.

  As shown in FIG. 14, in the unit shift register 10A2, the source of the transistor Q13 is connected to the clock terminal CK, and the gates of the transistors Q13 and Q14 are connected to the output terminal OUT. The configuration is not used.

  When such a configuration is adopted, when the gate line connected to the unit shift register 10A2 of the non-operating side shift register circuit is selected by the unit shift register 10A2 of the operating side shift register circuit, the potential of the gate line is Although the transistors Q13 and Q14 of the unit shift register 10A2 of the non-operating shift register circuit are turned on, as described with reference to FIG. 4, in the non-operating shift register circuit, the clock signals CLKA and CLKB are set to the L level. Since it is fixed, the potentials of nodes N1 and N2 are fixed to the L level.

  On the other hand, in the unit shift register 10A2 of the operation side shift register circuit, the gate potential of the transistor Q13 rises to the high potential side power supply potential VDD by the selection of the gate line, but the potential of the clock signal CLKA (or CLKB) applied to the source. Is the high potential side power supply potential VDD, the transistor Q13 is not turned on and does not affect the operation of the shift register circuit. Further, although the transistor Q14 is also turned on, the transistor Q2 for pulling down the output is fixed in the off state, so that the operation of the shift register circuit is not affected.

  Therefore, according to the unit shift register 10A2, it is possible to prevent the potential of the selected gate line from being lowered and the circuit operation margin from being lowered, and it is not necessary to supply the select signal SEL from the outside. Become.

<F-1-3. Third application example>
FIG. 15 shows a configuration of a unit shift register 10A3 in which a configuration in which the potential is fixed without using the select signal SEL is applied to the unit shift register 10A shown in FIG. Note that the same components as those of the unit shift register 10A shown in FIG.

  As shown in FIG. 15, the unit shift register 10A3 has transistors Q13a and Q13b connected in series between the clock terminal CK and the node N1, instead of the transistor Q13 in the unit shift register 10A of FIG. ing. The gates of the transistors Q13a and Q13b are connected to the output terminal OUT together with the gate of the transistor Q14, and the selection signal SEL is not used. A configuration in which the gates of transistors connected in series like the transistors Q13a and Q13b are connected to each other is referred to as a “dual gate transistor”.

  When such a configuration is adopted, when the gate line connected to the unit shift register 10A3 of the non-operating side shift register circuit is selected by the unit shift register 10A3 of the operating side shift register circuit, the potential of the gate line The transistors Q13a, Q13b, and Q14 of the unit shift register 10A3 of the non-operating shift register circuit are turned on. However, as described with reference to FIG. 4, in the non-operating shift register circuit, the clock signals CLKA and CLKB are L Since it is fixed at the level, the potentials of nodes N1 and N2 are fixed at the L level.

  On the other hand, in the unit shift register 10A3 of the shift register circuit on the operation side, the gate potential of the transistors Q13a and Q13b rises to the high potential side power supply potential VDD by the selection of the gate line, but the clock signal CLKA (or CLKB) applied to the source The transistor Q13a and Q13b are not turned on because the potential at the high-potential side power supply potential VDD is not affected. Further, although the transistor Q14 is also turned on, the transistor Q2 for pulling down the output is fixed in the off state, so that the operation of the shift register circuit is not affected.

  Therefore, according to the unit shift register 10A3, it is possible to prevent the potential of the selected gate line from being lowered and the circuit operation margin from being lowered, and it is not necessary to supply the select signal SEL from the outside. Become.

  In addition, by configuring the potential fixing transistor of the node N1 as a dual gate transistor, a negative shift of the threshold voltage occurs in the potential fixing transistor of the node N1 during the gate line non-selection period. This can be suppressed.

  That is, in each of transistors Q13a and Q13b connected in series, a potential state in which both the source and the drain are at the H level and the gate is at the L level is prevented, so that the threshold voltage of the transistor shifts in the negative direction. It is prevented. Therefore, current can be prevented from flowing through the dual gate transistor during the non-selection period and the level of the node N1 can be prevented, and malfunction can be prevented and reliability of the shift register circuit can be improved.

<F-2. Application to Unit Shift Register 10B>
<F-2-1. First application example>
FIG. 16 shows a configuration of the unit shift register 10B1 in which a configuration in which the potential is fixed without using the select signal SEL is applied to the unit shift register 10B shown in FIG. Note that the same components as those of the unit shift register 10B shown in FIG. 6 are denoted by the same reference numerals, and redundant description is omitted.

  As shown in FIG. 16, in the unit shift register 10B1, the source of the transistor Q13 is connected to the second power supply terminal S2, and the gates of the transistors Q13 and Q14 are connected to the output terminal OUT. The select signal SEL is not used.

  Also in the case of adopting such a configuration, the same effect as the unit shift register 10A1 shown in FIG. 13 can be obtained, the potential of the selected gate line can be prevented from being lowered, and the circuit operation margin can be prevented from being lowered. Since it is not necessary to supply the select signal SEL from, the circuit configuration is simplified.

<F-2-2. Second application example>
FIG. 17 illustrates a configuration of a unit shift register 10B2 in which a configuration in which the potential is fixed without using the select signal SEL is applied to the unit shift register 10B illustrated in FIG. Note that the same components as those of the unit shift register 10B shown in FIG. 6 are denoted by the same reference numerals, and redundant description is omitted.

  As shown in FIG. 17, in the unit shift register 10B2, the source of the transistor Q13 is connected to the clock terminal CK, the gates of the transistors Q13 and Q14 are connected to the output terminal OUT, and the select signal SEL The configuration is not used.

  Also in the case of adopting such a configuration, the same effect as that of the unit shift register 10A2 shown in FIG. 14 can be obtained, the potential of the selected gate line can be prevented from being lowered, and the circuit operation margin can be prevented from being lowered. Since it is not necessary to supply the select signal SEL from, the circuit configuration is simplified.

<F-2-3. Third application example>
FIG. 18 shows a configuration of a unit shift register 10B3 in which a configuration in which the potential is fixed without using the select signal SEL is applied to the unit shift register 10B shown in FIG. Note that the same components as those of the unit shift register 10B shown in FIG. 6 are denoted by the same reference numerals, and redundant description is omitted.

  As shown in FIG. 18, the unit shift register 10B3 has transistors Q13a and Q13b connected in series between the clock terminal CK and the node N1, instead of the transistor Q13 in the unit shift register 10B of FIG. ing. The gates of the transistors Q13a and Q13b are connected to the output terminal OUT together with the gate of the transistor Q14, and the selection signal SEL is not used.

  Also in the case of adopting such a configuration, the same effect as the unit shift register 10A3 shown in FIG. 15 can be obtained, the potential of the selected gate line can be prevented from being lowered, and the circuit operation margin can be prevented from being lowered. Since it is not necessary to supply the select signal SEL from, the circuit configuration is simplified.

  In addition, by configuring the potential fixing transistor of the node N1 as a dual gate transistor, a negative shift of the threshold voltage occurs in the potential fixing transistor of the node N1 during the gate line non-selection period. This can be suppressed. Therefore, current can be prevented from flowing through the dual gate transistor during the non-selection period and the level of the node N1 can be prevented, and malfunction can be prevented and reliability of the shift register circuit can be improved.

<F-3. Application to Unit Shift Register 20>
<F-3-1. First application example>
FIG. 19 shows the configuration of a unit shift register 201 in which the unit shift register 20 shown in FIG. 7 is applied with a configuration in which the potential is fixed without using the select signal SEL. Note that the same components as those of the unit shift register 20 shown in FIG.

  As shown in FIG. 19, in the unit shift register 201, the source of the transistor Q13 is connected to the second power supply terminal S2, and the gates of the transistors Q13, Q14a, and Q14b are connected to the output terminal OUT. Therefore, the select signal SEL is not used.

  When such a configuration is adopted, when the gate line connected to the unit shift register 201 of the non-operating side shift register circuit is selected by the unit shift register 201 of the operating side shift register circuit, the potential of the gate line The transistors Q13, Q14a, and Q14b of the unit shift register 201 of the non-operating shift register circuit are turned on. However, as described with reference to FIG. Since it is fixed at L level, the potentials of nodes N1, N2A and N2B are fixed at L level.

  On the other hand, in the unit shift register 201 of the operation side shift register circuit, the gate potential of the transistor Q13 rises to the high potential side power supply potential VDD by the selection of the gate line, but the source potential is the high potential side power supply potential VDD. Q13 is not turned on and does not affect the operation of the shift register circuit. The transistors Q14a and Q14b are also turned on, but the transistors Q2A and Q2B that pull down the output are fixed in the off state, so that the operation of the shift register circuit is not affected.

  Therefore, according to the unit shift register 201, it is possible to prevent the potential of the selected gate line from being lowered and the circuit operation margin from being lowered, and it is not necessary to supply the select signal SEL from the outside. Become.

<F-3-2. Second application example>
FIG. 20 shows a configuration of a unit shift register 202 in which the unit shift register 20 shown in FIG. 7 is applied with a configuration in which the potential is fixed without using the select signal SEL. Note that the same components as those of the unit shift register 20 shown in FIG.

  As shown in FIG. 20, in the unit shift register 202, the source of the transistor Q13 is connected to the clock terminal CK, and the gates of the transistors Q13, Q14a, and Q14b are connected to the output terminal OUT. The signal SEL is not used.

  When such a configuration is adopted, when the gate line connected to the unit shift register 202 of the non-operating side shift register circuit is selected by the unit shift register 202 of the operating side shift register circuit, the potential of the gate line is used. The transistors Q13, Q14a and Q14b of the unit shift register 202 of the non-operating shift register circuit are turned on. However, as described with reference to FIG. 4, in the non-operating shift register circuit, the clock signals CLKA and CLKB are L Since it is fixed at the level, the potentials of nodes N1, N2A and N2B are fixed at the L level.

  On the other hand, in the unit shift register 202 of the shift register circuit on the operating side, the gate potential of the transistor Q13 rises to the high potential side power supply potential VDD by the selection of the gate line, but the potential of the clock signal CLKA (or CLKB) applied to the source. Is the high potential side power supply potential VDD, the transistor Q13 is not turned on and does not affect the operation of the shift register circuit. The transistors Q14a and Q14b are also turned on, but the transistors Q2A and Q2B that pull down the output are fixed in the off state, so that the operation of the shift register circuit is not affected.

  Therefore, according to the unit shift register 202, it is possible to prevent the potential of the selected gate line from being lowered and the circuit operation margin from being lowered, and it is not necessary to supply the select signal SEL from the outside. Become.

<F-3-3. Third application example>
FIG. 21 shows a configuration of the unit shift register 203 in which the unit shift register 20 shown in FIG. 7 is applied with a configuration in which the potential is fixed without using the select signal SEL. Note that the same components as those of the unit shift register 20 shown in FIG.

  As shown in FIG. 21, unit shift register 203 has transistors Q13a and Q13b connected in series between clock terminal CK and node N1, instead of transistor Q13 in unit shift register 20 of FIG. ing. The gates of the transistors Q13a and Q13b are connected to the output terminal OUT together with the gates of the transistors Q14a and Q14b, and the selection signal SEL is not used.

  When such a configuration is adopted, when the gate line connected to the unit shift register 203 of the shift register circuit on the non-operation side is selected by the unit shift register 203 of the shift register circuit on the operation side, the potential of the gate line The transistors Q13a and Q13b, Q14a and Q14b of the unit shift register 203 of the non-operating shift register circuit are turned on. However, as described with reference to FIG. Is fixed at the L level, the potentials of the nodes N1 and N2 are fixed at the L level.

  On the other hand, in the unit shift register 202 of the shift register circuit on the operation side, the gate potential of the transistors Q13a and Q13b rises to the high potential side power supply potential VDD by the selection of the gate line, but the clock signal CLKA (or CLKB) applied to the source The transistor Q13a and Q13b are not turned on because the potential at the high-potential side power supply potential VDD is not affected. The transistors Q14a and Q14b are also turned on, but the transistors Q2A and Q2B that pull down the output are fixed in the off state, so that the operation of the shift register circuit is not affected.

  Therefore, according to the unit shift register 203, it is possible to prevent the potential of the selected gate line from being lowered and the circuit operation margin from being lowered, and it is not necessary to supply the select signal SEL from the outside. Become.

  In addition, by configuring the potential fixing transistor of the node N1 as a dual gate transistor, a negative shift of the threshold voltage occurs in the potential fixing transistor of the node N1 during the gate line non-selection period. This can be suppressed. Therefore, current can be prevented from flowing through the dual gate transistor during the non-selection period and the level of the node N1 can be prevented, and malfunction can be prevented and reliability of the shift register circuit can be improved.

<F-4. Application to Unit Shift Register 30>
<F-4-1. First application example>
FIG. 22 shows a configuration of a unit shift register 301 in which the unit shift register 30 shown in FIG. 9 is applied with a configuration in which the potential is fixed without using the select signal SEL. Note that the same components as those of the unit shift register 30 shown in FIG.

  As shown in FIG. 22, in the unit shift register 301, the source of the transistor Q13 is connected to the second power supply terminal S2, and the gates of the transistors Q13 and Q14 are connected to the output terminal OUT. The select signal SEL is not used.

  Also in the case of adopting such a configuration, the same effect as the unit shift register 10A1 shown in FIG. 13 can be obtained, the potential of the selected gate line can be prevented from being lowered, and the circuit operation margin can be prevented from being lowered. Since it is not necessary to supply the select signal SEL from, the circuit configuration is simplified.

<F-4-2. Second application example>
FIG. 23 shows a configuration of a unit shift register 302 in which the unit shift register 30 shown in FIG. 9 is applied with a configuration in which the potential is fixed without using the select signal SEL. Note that the same components as those of the unit shift register 30 shown in FIG.

  As shown in FIG. 23, in the unit shift register 302, the source of the transistor Q13 is connected to the clock terminal CK, and the gates of the transistors Q13 and Q14 are connected to the output terminal OUT. The configuration is not used.

  Also in the case of adopting such a configuration, the same effect as that of the unit shift register 10A2 shown in FIG. 14 can be obtained, the potential of the selected gate line can be prevented from being lowered, and the circuit operation margin can be prevented from being lowered. Since it is not necessary to supply the select signal SEL from, the circuit configuration is simplified.

<F-4-3. Third application example>
FIG. 24 shows a configuration of the unit shift register 303 in which the unit shift register 30 shown in FIG. 9 is applied with a configuration in which the potential is fixed without using the select signal SEL. Note that the same components as those of the unit shift register 30 shown in FIG. 9 are denoted by the same reference numerals, and redundant description is omitted.

  As shown in FIG. 24, unit shift register 303 has transistors Q13a and Q13b connected in series between clock terminal CK and node N1, instead of transistor Q13 in unit shift register 30 of FIG. ing. The gates of the transistors Q13a and Q13b are connected to the output terminal OUT together with the gate of the transistor Q14, and the selection signal SEL is not used.

  Also in the case of adopting such a configuration, the same effect as the unit shift register 10A3 shown in FIG. 15 can be obtained, the potential of the selected gate line can be prevented from being lowered, and the circuit operation margin can be prevented from being lowered. Since it is not necessary to supply the select signal SEL from, the circuit configuration is simplified.

  In addition, by configuring the potential fixing transistor of the node N1 as a dual gate transistor, a negative shift of the threshold voltage occurs in the potential fixing transistor of the node N1 during the gate line non-selection period. This can be suppressed. Therefore, current can be prevented from flowing through the dual gate transistor during the non-selection period and the level of the node N1 can be prevented, and malfunction can be prevented and reliability of the shift register circuit can be improved.

<F-5. Application to Unit Shift Register 40>
<F-5-1. First application example>
FIG. 25 shows a configuration of the unit shift register 401 in which the unit shift register 40 shown in FIG. 11 is applied with a configuration in which the potential is fixed without using the select signal SEL. Note that the same components as those of the unit shift register 40 shown in FIG.

  As shown in FIG. 25, in the unit shift register 401, the source of the transistor Q13 is connected to the second power supply terminal S2, and the gate of the transistor Q13 is connected to the output terminal OUT. The SEL is not used.

  When such a configuration is adopted, when the gate line connected to the unit shift register 401 of the non-operating side shift register circuit is selected by the unit shift register 401 of the operating side shift register circuit, the potential of the gate line is The transistor Q13 of the unit shift register 401 of the non-operating shift register circuit is turned on. However, as described with reference to FIG. 4, in the non-operating shift register circuit, the high-potential power supply potential VDD is also fixed to the L level. Therefore, the potential of the node N1 is fixed at the L level.

  On the other hand, in the unit shift register 401 of the shift register circuit on the operation side, the gate potential of the transistor Q13 rises to the high-potential-side power supply potential VDD by the selection of the gate line. Q13 is not turned on and does not affect the operation of the shift register circuit.

  Therefore, according to the unit shift register 401, it is possible to prevent the potential of the selected gate line from being lowered and the circuit operation margin from being lowered, and it is not necessary to supply the select signal SEL from the outside. Become.

<F-5-2. Second application example>
FIG. 26 shows a configuration of a unit shift register 402 in which the unit shift register 40 shown in FIG. 11 is applied with a configuration in which the potential is fixed without using the select signal SEL. Note that the same components as those of the unit shift register 40 shown in FIG. 11 are denoted by the same reference numerals, and redundant description is omitted. The transistor Q3 may be connected to a terminal to which the output signal K-1 output from the output terminal OUT of the previous unit shift register is applied instead of the second power supply terminal S2.

  As shown in FIG. 26, in the unit shift register 402, the source of the transistor Q13 is connected to the clock terminal CK, and the gate of the transistor Q13 is connected to the output terminal OUT, and the select signal SEL is used. It has a configuration that does not.

  When such a configuration is adopted, when the gate line connected to the unit shift register 402 of the non-operating side shift register circuit is selected by the unit shift register 402 of the operating side shift register circuit, the potential of the gate line Although the transistor Q13 of the unit shift register 402 of the non-operating shift register circuit is turned on, as described with reference to FIG. 4, in the non-operating shift register circuit, the clock signals CLKA and CLKB are fixed at the L level. Therefore, the potential of the node N1 is fixed at the L level.

  On the other hand, in the unit shift register 402 of the shift register circuit on the operating side, the gate potential of the transistor Q13 rises to the high potential side power supply potential VDD by the selection of the gate line, but the potential of the clock signal CLKA (or CLKB) applied to the source. Is the high potential side power supply potential VDD, the transistor Q13 is not turned on and does not affect the operation of the shift register circuit.

  Therefore, according to the unit shift register 202, it is possible to prevent the potential of the selected gate line from being lowered and the circuit operation margin from being lowered, and it is not necessary to supply the select signal SEL from the outside. Become.

<F-5-3. Third application example>
FIG. 27 shows a configuration of a unit shift register 403 in which the unit shift register 40 shown in FIG. 11 is applied with a configuration in which the potential is fixed without using the select signal SEL. Note that the same components as those of the unit shift register 40 shown in FIG. The transistor Q3 may be connected to a terminal to which the output signal K-1 output from the output terminal OUT of the previous unit shift register is applied instead of the second power supply terminal S2.

  As shown in FIG. 27, unit shift register 403 has transistors Q13a and Q13b connected in series between clock terminal CK and node N1, instead of transistor Q13 in unit shift register 40 of FIG. ing. The gates of the transistors Q13a and Q13b are connected to the output terminal OUT and do not use the select signal SEL.

  When such a configuration is adopted, when the gate line connected to the unit shift register 403 of the non-operating side shift register circuit is selected by the unit shift register 403 of the operating side shift register circuit, the potential of the gate line is The transistor Q13 of the unit shift register 403 of the non-operating shift register circuit is turned on. However, as described with reference to FIG. 4, in the non-operating shift register circuit, the clock signals CLKA and CLKB are fixed at the L level. Therefore, the potential of the node N1 is fixed at the L level.

  On the other hand, in the unit shift register 402 of the shift register circuit on the operation side, the gate potential of the transistors Q13a and Q13b rises to the high potential side power supply potential VDD by the selection of the gate line, but the clock signal CLKA (or CLKB) applied to the source The transistor Q13a and Q13b are not turned on because the potential at the high-potential side power supply potential VDD is not affected.

  Therefore, according to the unit shift register 403, it is possible to prevent the potential of the selected gate line from being lowered and the circuit operation margin from being lowered, and it is not necessary to supply the select signal SEL from the outside. Become.

  In addition, by configuring the potential fixing transistor of the node N1 as a dual gate transistor, a negative shift of the threshold voltage occurs in the potential fixing transistor of the node N1 during the gate line non-selection period. This can be suppressed. Therefore, current can be prevented from flowing through the dual gate transistor during the non-selection period and the level of the node N1 can be prevented, and malfunction can be prevented and reliability of the shift register circuit can be improved.

<F-6. Application to Unit Shift Register 50>
<F-6-1. First application example>
FIG. 28 shows a configuration of the unit shift register 501 in which the unit shift register 50 shown in FIG. 12 is applied with a configuration in which the potential is fixed without using the select signal SEL. Note that the same components as those of the unit shift register 50 shown in FIG.

  As shown in FIG. 28, in the unit shift register 501, the source of the transistor Q13 is connected to the second power supply terminal S2, and the gates of the transistors Q13 and Q14 are connected to the output terminal OUT. The select signal SEL is not used.

  Also in the case of adopting such a configuration, the same effect as the unit shift register 10A1 shown in FIG. 13 can be obtained, the potential of the selected gate line can be prevented from being lowered, and the circuit operation margin can be prevented from being lowered. Since it is not necessary to supply the select signal SEL from, the circuit configuration is simplified.

<F-6-2. Second application example>
FIG. 29 shows a configuration of a unit shift register 502 in which the unit shift register 50 shown in FIG. 12 is applied with a configuration in which the potential is fixed without using the select signal SEL. Note that the same components as those of the unit shift register 50 shown in FIG. The transistor Q3 may be connected to a terminal to which the output signal K-1 output from the output terminal OUT of the previous unit shift register is applied instead of the second power supply terminal S2.

  As shown in FIG. 29, in the unit shift register 502, the source of the transistor Q13 is connected to the clock terminal CK, and the gates of the transistors Q13 and Q14 are connected to the output terminal OUT. The configuration is not used.

  Also in the case of adopting such a configuration, the same effect as that of the unit shift register 10A2 shown in FIG. 14 can be obtained, the potential of the selected gate line can be prevented from being lowered, and the circuit operation margin can be prevented from being lowered. Since it is not necessary to supply the select signal SEL from, the circuit configuration is simplified.

<F-6-3. Third application example>
30 shows a configuration of a unit shift register 503 in which the unit shift register 50 shown in FIG. 12 is applied with a configuration in which the potential is fixed without using the select signal SEL. Note that the same components as those of the unit shift register 50 shown in FIG. The transistor Q3 may be connected to a terminal to which the output signal K-1 output from the output terminal OUT of the previous unit shift register is applied instead of the second power supply terminal S2.

  As shown in FIG. 30, unit shift register 503 has transistors Q13a and Q13b connected in series between clock terminal CK and node N1, instead of transistor Q13 in unit shift register 50 of FIG. ing. The gates of the transistors Q13a and Q13b are connected to the output terminal OUT together with the gate of the transistor Q14, and the selection signal SEL is not used.

  Also in the case of adopting such a configuration, the same effect as the unit shift register 10A3 shown in FIG. 15 can be obtained, the potential of the selected gate line can be prevented from being lowered, and the circuit operation margin can be prevented from being lowered. Since it is not necessary to supply the select signal SEL from, the circuit configuration is simplified.

  In addition, by configuring the potential fixing transistor of the node N1 as a dual gate transistor, a negative shift of the threshold voltage occurs in the potential fixing transistor of the node N1 during the gate line non-selection period. This can be suppressed. Therefore, current can be prevented from flowing through the dual gate transistor during the non-selection period and the level of the node N1 can be prevented, and malfunction can be prevented and reliability of the shift register circuit can be improved.

It is a figure which shows the whole structure of the image display apparatus which implement | achieves bidirectional scanning. It is a figure which shows the structure of the unit shift register of Embodiment 1 which concerns on this invention. 5 is a timing chart for explaining the operation of the shift register circuit configured by the unit shift register according to the first embodiment of the present invention. It is a timing chart explaining operation | movement of the image display apparatus which implement | achieves bidirectional scanning. It is a figure which shows the structure of the modification 1 of the unit shift register of Embodiment 1 which concerns on this invention. It is a figure which shows the structure of the modification 1 of the unit shift register of Embodiment 1 which concerns on this invention. It is a figure which shows the structure of the unit shift register of Embodiment 2 which concerns on this invention. 5 is a timing chart for explaining the operation of the shift register circuit configured by the unit shift register according to the first embodiment of the present invention. It is a figure which shows the structure of the unit shift register of Embodiment 3 which concerns on this invention. It is a figure which shows the connection relation of the signal of the shift register circuit comprised by the unit shift register of Embodiment 3 which concerns on this invention. It is a figure which shows the structure of the unit shift register of Embodiment 4 which concerns on this invention. It is a figure which shows the structure of the unit shift register of Embodiment 5 which concerns on this invention. It is a figure which shows the structure of the unit shift register of Embodiment 6 which concerns on this invention. It is a figure which shows the structure of the unit shift register of Embodiment 6 which concerns on this invention. It is a figure which shows the structure of the unit shift register of Embodiment 6 which concerns on this invention. It is a figure which shows the structure of the unit shift register of Embodiment 6 which concerns on this invention. It is a figure which shows the structure of the unit shift register of Embodiment 6 which concerns on this invention. It is a figure which shows the structure of the unit shift register of Embodiment 6 which concerns on this invention. It is a figure which shows the structure of the unit shift register of Embodiment 6 which concerns on this invention. It is a figure which shows the structure of the unit shift register of Embodiment 6 which concerns on this invention. It is a figure which shows the structure of the unit shift register of Embodiment 6 which concerns on this invention. It is a figure which shows the structure of the unit shift register of Embodiment 6 which concerns on this invention. It is a figure which shows the structure of the unit shift register of Embodiment 6 which concerns on this invention. It is a figure which shows the structure of the unit shift register of Embodiment 6 which concerns on this invention. It is a figure which shows the structure of the unit shift register of Embodiment 6 which concerns on this invention. It is a figure which shows the structure of the unit shift register of Embodiment 6 which concerns on this invention. It is a figure which shows the structure of the unit shift register of Embodiment 6 which concerns on this invention. It is a figure which shows the structure of the unit shift register of Embodiment 6 which concerns on this invention. It is a figure which shows the structure of the unit shift register of Embodiment 6 which concerns on this invention. It is a figure which shows the structure of the unit shift register of Embodiment 6 which concerns on this invention.

Explanation of symbols

  1, 2 shift register circuit, 3 pixel array, D1-Dn, U1-Un unit shift register.

Claims (22)

First and second shift register circuits having a plurality of unit shift registers connected in cascade;
Each of the output nodes of the plurality of unit shift registers of the first shift register circuit is connected to the output nodes of the plurality of unit shift registers of the second shift register circuit in a one-to-one relationship.
The first and second shift register circuits include:
When one side is performing a shift operation, the other is controlled to a non-operating state by fixing the power supply voltage to a reference voltage, and the gate node of each output transistor of the plurality of unit shift registers is set to the reference voltage. A semiconductor device controlled to be fixed. Each of the plurality of unit shift registers is
An input terminal, an output terminal, a first clock terminal, a select terminal, a first power supply terminal for supplying the reference voltage, a second power supply terminal for supplying the power supply voltage, and a reset terminal;
A first transistor for supplying a first clock signal input to the first clock terminal to the output terminal;
A second transistor for discharging the output terminal;
A charging circuit for charging a first node connected to the gate of the first transistor in response to an input signal input to the input terminal;
A first discharge circuit for discharging the first node in response to a reset signal input to the reset terminal;
A second discharge circuit connected between the first node and the first power supply terminal and discharging the first node according to a select signal input to the select terminal;
The first transistor corresponds to the output transistor;
The gate node corresponds to the first node;
The output terminal corresponds to an output node;
The semiconductor device according to claim 1, wherein the second discharge circuit is activated when the plurality of unit shift registers are controlled to the non-operating state.   The semiconductor device according to claim 2, wherein a gate of the second transistor is connected to the reset terminal. An inverter having the first node as an input terminal and a second node connected to the gate of the second transistor as an output terminal;
3. The semiconductor device according to claim 2, further comprising: a third discharge circuit connected between the second node and the first power supply terminal and discharging the second node in response to the select signal. .   A third node connected between the first node and the first power supply terminal, a gate connected to the second node, and discharging the first node according to a potential of the second node. The semiconductor device according to claim 4, further comprising: The second transistor is
Including two transistors connected in parallel,
The gates of each of the two transistors are connected to the second and third nodes, and the two transistors are alternately driven based on a predetermined control signal,
The control signal is
First and second control signals complementary to each other;
Each of the plurality of unit shift registers is
First and second control terminals to which the first and second control signals are respectively input;
A third transistor connected between the first control terminal and the second node;
A fourth transistor connected between the second control terminal and the third node;
Driving means for alternately driving the two second transistors;
A fifth transistor having a gate connected to the second node and discharging the first node;
A sixth transistor having a gate connected to the third node and discharging the first node;
A third discharge circuit connected between the second and third nodes and the first power supply terminal and discharging the second and third nodes in response to the select signal; ,
The third and fourth transistors are:
One of the main electrodes is connected to the gates of each other
The driving means includes
An inverter having the first node as an input end;
The semiconductor device according to claim 2, further comprising: a switching circuit that alternately connects an output terminal of the inverter to the second and third nodes based on the control signal. A second clock terminal to which a second clock signal having a phase different from that of the first clock signal is input;
A third transistor having a gate connected to the first clock terminal and connected between the first node and the output terminal;
An inverter having the first node as an input and being activated by the second clock signal;
A fourth transistor having a gate connected to the first clock terminal and discharging an output terminal of the inverter;
A fifth transistor having a gate connected to the output terminal of the inverter and discharging the first node;
The semiconductor device according to claim 2, wherein a gate of the second transistor is connected to the second clock terminal.   The semiconductor device according to claim 7, wherein the second transistor is connected between the output terminal and the first clock terminal. Each of the plurality of unit shift registers is
First and second input terminals, output terminals, clock terminals, select terminals, a first power supply terminal for supplying the reference voltage, a second power supply terminal for supplying the power supply voltage, and a reset terminal;
A first transistor for supplying a clock signal input to the first clock terminal to the output terminal;
A second transistor for discharging the output terminal;
A first charging circuit for charging a first node connected to the gate of the first transistor;
A first discharge circuit for discharging the first node in response to a reset signal input to the reset terminal;
A second discharge circuit connected between the first node and the first power supply terminal and discharging the first node according to a select signal input to the select terminal;
The first charging circuit includes:
A third transistor connected between the first node and the second power supply terminal and having a gate connected to a predetermined second node;
A second charging circuit that charges the second node in response to a first input signal input to the first input terminal;
A booster circuit that boosts the second node in response to a second input signal input to the second input terminal;
A third discharge circuit for discharging the second node in response to the reset signal;
The first transistor corresponds to the output transistor;
The gate node corresponds to the first node;
The output terminal corresponds to an output node;
The semiconductor device according to claim 1, wherein the second discharge circuit is activated when the plurality of unit shift registers are controlled to the non-operating state. An inverter having the second node as an input end;
A fourth transistor having a gate connected to the output terminal of the inverter and discharging the second node;
A fourth discharge circuit connected between the third node connected to the gate of the second transistor and the first power supply terminal and discharging the third node in response to the select signal; Further comprising
The first discharge circuit includes:
A gate connected to the output terminal of the inverter and including a fifth transistor for discharging the first node;
The booster circuit includes:
A capacitive element connected between the second input terminal and the second node;
The semiconductor device according to claim 9, wherein the third node is connected to the output terminal of the inverter. Each of the plurality of unit shift registers is
An input terminal, an output terminal, a first clock terminal, a first power supply terminal for supplying the reference voltage, a second power supply terminal for supplying the power supply voltage, and a reset terminal;
A first transistor for supplying a first clock signal input to the first clock terminal to the output terminal;
A second transistor for discharging the output terminal;
A charging circuit for charging a first node connected to the gate of the first transistor in response to an input signal input to the input terminal;
A first discharge circuit for discharging the first node in response to a reset signal input to the reset terminal;
A second discharge circuit for discharging the first node according to a signal of the output terminal,
The first transistor corresponds to the output transistor;
The gate node corresponds to the first node;
The output terminal corresponds to an output node;
The semiconductor device according to claim 1, wherein the second discharge circuit is activated when the plurality of unit shift registers are controlled to the non-operating state. An inverter having the first node as an input terminal and a second node connected to the gate of the second transistor as an output terminal;
12. A third discharge circuit connected between the second node and the first power supply terminal and discharging the second node in accordance with a signal of the output terminal, according to claim 11. Semiconductor device.   A third node connected between the first node and the first power supply terminal, a gate connected to the second node, and discharging the first node according to a potential of the second node. The semiconductor device according to claim 12, further comprising: The second transistor is
Including two transistors connected in parallel,
The gates of each of the two transistors are connected to the second and third nodes, and the two transistors are alternately driven based on a predetermined control signal,
The control signal is
First and second control signals complementary to each other;
Each of the plurality of unit shift registers is
First and second control terminals to which the first and second control signals are respectively input;
A third transistor connected between the first control terminal and the second node;
A fourth transistor connected between the second control terminal and the third node;
Driving means for alternately driving the two second transistors;
A fifth transistor having a gate connected to the second node and discharging the first node;
A sixth transistor having a gate connected to the third node and discharging the first node;
A third discharge circuit connected between the second and third nodes and the first power supply terminal and discharging the second and third nodes in response to a signal of the output terminal; Have
The third and fourth transistors are:
One of the main electrodes is connected to the gates of each other
The driving means includes
An inverter having the first node as an input end;
The semiconductor device according to claim 11, further comprising: a switching circuit that alternately connects output terminals of the inverter to the second and third nodes based on the control signal. A second clock terminal to which a second clock signal having a phase different from that of the first clock signal is input;
A third transistor having a gate connected to the first clock terminal and connected between the first node and the output terminal;
An inverter having the first node as an input and being activated by the second clock signal;
A fourth transistor having a gate connected to the first clock terminal and discharging an output terminal of the inverter;
A fifth transistor having a gate connected to the output terminal of the inverter and discharging the first node;
The semiconductor device according to claim 11, wherein a gate of the second transistor is connected to the second clock terminal. Each of the plurality of unit shift registers is
First and second input terminals, output terminals, clock terminals, a first power supply terminal for supplying the reference voltage, a second power supply terminal for supplying the power supply voltage, and a reset terminal;
A first transistor for supplying a clock signal input to the first clock terminal to the output terminal;
A second transistor for discharging the output terminal;
A first charging circuit for charging a first node connected to the gate of the first transistor;
A first discharge circuit for discharging the first node in response to a reset signal input to the reset terminal;
A second discharge circuit for discharging the first node according to a signal of the output terminal,
The first charging circuit includes:
A third transistor connected between the first node and the second power supply terminal and having a gate connected to a predetermined second node;
A second charging circuit that charges the second node in response to a first input signal input to the first input terminal;
A booster circuit that boosts the second node in response to a second input signal input to the second input terminal;
A third discharge circuit for discharging the second node in response to the reset signal;
The first transistor corresponds to the output transistor;
The gate node corresponds to the first node;
The output terminal corresponds to an output node;
The semiconductor device according to claim 1, wherein the second discharge circuit is activated when the plurality of unit shift registers are controlled to the non-operating state. An inverter having the second node as an input end;
A fourth transistor having a gate connected to the output terminal of the inverter and discharging the second node;
A fourth discharge circuit connected between the third node connected to the gate of the second transistor and the first power supply terminal and discharging the third node in accordance with the signal of the output terminal And
The first discharge circuit includes:
A gate connected to the output terminal of the inverter and including a fifth transistor for discharging the first node;
The booster circuit includes:
A capacitive element connected between the second input terminal and the second node;
The semiconductor device according to claim 16, wherein the third node is connected to the output terminal of the inverter. The second discharge circuit includes:
The semiconductor device according to claim 12, wherein the semiconductor device is connected between the first node and the second power supply terminal. The second discharge circuit includes:
The semiconductor device according to claim 12, wherein the semiconductor device is connected between the first node and the first clock terminal. The second discharge circuit includes:
The plurality of transistors connected in series between the first node and the first clock terminal, wherein the gates of the plurality of transistors are commonly connected to the output terminal. Semiconductor device. The charging circuit is
4. A third transistor connected between the first node and the second power supply terminal or the output terminal of the previous unit shift register and having a gate connected to the second node is provided. A semiconductor device according to any one of claims 6, 7, 12, 14, and 15.   2. An image display device, wherein the first and second shift register circuits of the semiconductor device according to claim 1 are gate line driving circuits.

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