JP2010250029A - Display - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display capable of obtaining a desired display luminance, while attaining narrow framing. <P>SOLUTION: In both-side power supply driving, one side is supplied from the same shift register circuit similar to conventional system, and the other side is provided with an auxiliary shift register circuit 201 fewer in the number of Trs (transistors) and control signals. The auxiliary shift register circuit 201 includes a voltage input terminal for inputting VGH; an output terminal connected to an output terminal of the shift register circuit via a scanning line; a clock terminal for inputting a clock signal CK; a start terminal for inputting a start signal ST (Gn-1); the Tr(MS2) for supplying the clock signal CK to the output terminal; the Tr(MS1) for supplying VGH voltage to a gate node of the Tr(MS2) by the start signal ST(Gn-1); the Tr(MS3) for discharging the gate node of the TR(MS2) to the output terminal by the clock signal CK; and capacity CS1, which ic to be connected between the output terminal and the gate node of the Tr(MS2). <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an active matrix display device using TFT liquid crystal or the like, and in particular, in a scanning line driving circuit of a driving device for a display device, a rising speed and a falling speed of a scanning signal output from the scanning line driving circuit are high. The present invention relates to a drive circuit for achieving the above.

  In general, a plurality of scanning lines, a plurality of data lines, pixel electrodes arranged in a matrix, a switching transistor (hereinafter referred to as TFT) in the pixel electrode, and a display element connected to the source terminal of the TFT And an active matrix display having a storage capacitor Cst that reduces charge loss at the source terminal, a common common electrode disposed on the opposite side of the display element and the storage capacitor Cst, and a parasitic capacitance Cgs between the source terminal and the scanning line. In the apparatus, a scanning voltage indicating a selected state is applied to the scanning line line by line for every scanning period, a data voltage corresponding to display data is applied to the data line, and a common voltage corresponding to the polarity is applied to the common electrode. The difference between the data voltage and the common voltage at the scanning line in the selected state becomes the applied voltage of the display element, and the display brightness of the display device is adjusted according to the value of the applied voltage. Are your. In recent years, the above-described display devices have been developed with higher definition and higher resolution, and time-division SW for RGB time-division driving that applies a data voltage for each RGB line, and less photo (less photolithography process). A scanning line driving circuit or the like composed only of a field effect transistor (hereinafter referred to as Tr) of the same conductivity type using aSi or the like is built in, thereby reducing the cost of the entire display device driving device. However, since the scanning line driving circuit built in the display device uses a small number of aSi Tr or the like as described above, since the charge mobility is low, the rising and falling speeds of the scanning signal (hereinafter referred to as convergence characteristics). The display device is slow and the load capacity of the scanning line increases with the increase in definition and resolution, resulting in insufficient writing of the data voltage to the source terminal and the display luminance being different from the desired display luminance. There has been a problem that image quality degradation due to. In addition, the conventional shift register circuit includes a transistor Tr1 that supplies the clock signal CLK to the output terminal OUT (Gn) and a transistor Tr2 that discharges the output terminal OUT (Gn), and is output from the output terminal OUT (Gn). Since the scanning signal is supplied to the scanning line of the own line and also used as a start pulse of the shift register circuit of the next stage, the Tr1 and Tr2 drive the load capacitance of the scanning line of the own line, and The load capacity of the shift register circuit is also driven, which is one of the causes that deteriorate the convergence characteristic of the scanning signal.

JP 2008-112550 A

  As a method for improving the convergence characteristic of the scanning signal, there is a method of increasing the driving capability by widening the channel width of the output Tr in the scanning line driving circuit. However, since the normal scanning line driving circuit is built in the frame portion of the display device, and recently mobile devices and the like have been narrowed (to narrow the frame portion of the display device), the channel of the output Tr The width cannot be widened easily.

  As another method for improving the convergence characteristic of the scanning signal, for example, a scanning line driving circuit disclosed in Patent Document 1 can be cited. The scanning line driving circuit disclosed in Patent Document 1 is provided with transistors QD1 and QD2 that supply start pulse signals for the next-stage shift register circuit in addition to Tr1 and Tr2 that supply scanning signals to the scanning lines. The load on Tr1 and Tr2 is reduced, and the convergence characteristic of the scanning signal is improved. However, in a high-definition and high-resolution display device, the scanning line load capacity (Cg) per line and the load capacity (Cs) of the next-stage shift register circuit have a relationship of Cg >> Cs, The effect of improving the convergence characteristics is small.

  As another method for improving the convergence characteristic of the scanning signal, there is a double-sided power feeding drive in which scanning line driving circuits are provided at both ends of the scanning line and the scanning signal is supplied from both ends of the scanning line. If the channel width of the output Tr of the shift register circuit in the scanning line driving circuit provided at both ends is the same, the time constant (CR) of the scanning line is theoretically halved, so that the convergence characteristic of the scanning signal can be improved. However, when the both-side power feeding drive is used, the scanning line driving circuit is simply doubled and the circuit scale is increased, and the control signal for the scanning line driving circuit is also doubled. It becomes difficult to make a frame.

  An object of the present invention is to provide a display drive device that improves the convergence characteristics of a scanning signal with a small circuit scale and control signal during the above-described double-side power feeding drive.

  In order to achieve the above object, according to the present invention, in both-side feed driving, one side is supplied from a shift register circuit in a scanning line driving circuit similar to the conventional one, and the other side has a smaller Tr number and control signal than the conventional shift register circuit. By providing the auxiliary shift register circuit configured by the number, it is possible to improve the convergence characteristic of the scanning signal and to narrow the frame of the display device.

  According to the present invention, both-side power feeding driving is performed in the conventional shift register circuit and the auxiliary shift register circuit configured with a smaller number of Trs and the number of control signals than the conventional shift register circuit. Since the convergence characteristics are improved, it is possible to obtain a desired display luminance while narrowing the frame in a high-definition and high-resolution display device.

It is a circuit block diagram of the display apparatus and drive device explaining Example 1 of this invention. FIG. 2 is a circuit configuration diagram in an odd-numbered scan line drive circuit and an even-numbered scan line drive circuit according to the first exemplary embodiment of the present invention. 1 is a circuit configuration diagram and operation timing of a conventional shift register circuit according to a first embodiment of the present invention. 1 is a circuit configuration diagram and operation timings of an auxiliary shift register circuit according to a first embodiment of the present invention. It is a circuit block diagram in the drive circuit for odd scanning lines and the drive circuit for even scanning lines of Example 2 of this invention. FIG. 6 is a circuit configuration diagram and operation timing of an auxiliary shift register circuit according to a second embodiment of the present invention.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS The best mode for carrying out the present invention will be described below in detail with reference to the drawings of the examples.

  The configuration and operation of the first embodiment of the present invention will be described below with reference to FIG. 1 is a block diagram of a display device driving apparatus according to an embodiment of the present invention, in which 100 is a CPU, 101 is a driving circuit, 102 is a system interface unit, 103 is a register unit, 104 is a memory control unit, 105 Is a display memory unit, 106 is a timing generation unit, 107 is a latch circuit unit, 108 is a data voltage generation unit, 109 is a reference voltage generation unit, 110 is a data voltage selection unit, 111 is an operational amplifier unit, and 112 is for a scanning line driver circuit. A control signal generation unit, 113 is a common signal generation unit, 114 is a display unit, 115 is a pixel unit, 116 is an odd scanning line driving circuit, and 117 is an even scanning line driving circuit.

  The drive circuit 101 is a so-called display memory built-in controller / driver, and includes means for realizing the present embodiment. Here, the drive circuit 101 of the present embodiment is not limited to a display memory built-in type, and can be applied to a type without a built-in memory. Hereinafter, the configuration and operation of the internal block of the drive circuit 101 will be described.

  The system interface unit 102 receives display data and instructions output from the CPU 100 and outputs them to the register unit 103. Here, the instruction is information for determining the internal operation of the drive circuit 101, and includes various parameters such as a frame frequency, the number of drive lines, and a drive voltage. It is also assumed that information regarding the operation timing of the scanning signal, which is a feature of the present embodiment, is also included.

  The register unit 103 is a block that stores instruction data and outputs the data to each block. For example, the instructions regarding the frame frequency, the number of drive lines, and the data voltage switching timing are output to the timing generator 106, and the instructions regarding the drive voltage are output to the reference voltage generator 109. The display data is also temporarily stored in the register unit 103, and is output to the memory control unit 104 together with instructions for indicating the display position. The memory control unit 104 is a block that performs the write and read operations of the display memory unit 105. First, during a write operation, a signal for selecting an address of the display memory unit 105 is output based on the display position instruction transferred from the register unit 103. At the same time, the display data is transferred to the display memory unit 105. With this operation, display data can be written to a predetermined address in the display memory unit 105. On the other hand, during the read operation, the operation of sequentially selecting a predetermined word line group one by one in the display memory unit 105 is repeated. With this operation, the display data on the selected word lines can be read all at once via the bit lines. It should be noted that setting of the range of the word line to be read, one selection period (equivalent to one scanning period), selection operation repetition period (equivalent to one frame period), and the like are instructed by the instruction. The display memory unit 105 includes word lines and bit lines corresponding to the scanning lines and data lines of the display unit 114, and performs the above-described display data write operation and read operation. Note that the read display data is output to the latch circuit unit 107.

  The timing generation unit 106 self-generates and outputs a signal group indicating one scanning period or one frame period based on a reference clock generated by a built-in oscillator and outputs the signal group to the scanning line drive circuit control signal generation unit 112. To do. Based on the signal output from the timing generation unit 106, the latch circuit unit 107 latches the display data input from the display memory unit 105 and outputs the latched display data to the data voltage selection unit 110. The reference voltage generation unit 109 generates a voltage level required in the drive circuit 101 from the input power supply voltage Vci. The data voltage generation unit 108 divides the voltage input from the reference voltage generation unit 109. For example, if 24-bit display data is output from the CPU 100, the data voltage generation unit 108 generates a 256-level data voltage and generates a data voltage selection unit. To 110. The data voltage selection unit 110 selects one level from 256 levels of data voltage according to the value of the display data output from the latch circuit unit 107, and outputs the selected data voltage. The operational amplifier unit 111 is a buffer for impedance conversion of the output of the data voltage selection unit 110, and is configured by a voltage follower circuit. The scanning line drive circuit control signal generator 112 generates and outputs a control signal used when driving an odd scan line drive circuit 116 and an even scan line drive circuit 117 incorporated in a display unit 114 to be described later. It is a block to do. The output timing will be described later. The common signal generation unit 113 switches the common high voltage (VcomH) and the common low voltage (VcomL) generated by the reference voltage generation unit 109 based on the timing signal output from the timing generation unit 106, and displays the common signal as a common signal. Is output to the common common electrode on the opposite side. The display unit 114 is a so-called active matrix type flat panel in which a switching transistor is arranged in each pixel unit 115 located at an intersection of a data line and a scanning line. The pixel portion 115 is connected to the drain terminal of a switching transistor (hereinafter referred to as TFT) via the data line to the output of the operational amplifier 111, and the gate terminal of the scanning line driving circuits 116 and 117 via the scanning line. Connected to output. Further, the source terminal of the TFT is connected to the display element Cpix and the storage capacitor Cst that reduces the loss of electric charge of the source terminal. A common common electrode is connected to the opposite side of the display element Cpix and the storage capacitor Cst, and the common signal generated by the common signal generation unit 113 is output to the common electrode. Therefore, in the scanning line in the selected state, the difference between the data voltage and the common voltage is the voltage applied to the display element Cpix. The type of display element is typically liquid crystal or the like, but scanning pulses are sequentially applied every scanning period, and a data voltage corresponding to display data on the selected scanning line is applied to the data line. Other elements may be used as long as the display luminance can be controlled. The odd scanning line driving circuit 116 and the even scanning line driving circuit 117 output scanning signals to the scanning lines of the display unit 114 based on the control signals output from the scanning line driving circuit control signal generation unit 112.

  Next, circuit configurations and operations of the odd-number scan line drive circuit 116 and the even-number scan line drive circuit 117 according to the embodiment of the present invention will be described with reference to FIGS. FIG. 2 is a block diagram of the odd-numbered scanning line driving circuit 116 and the even-numbered scanning line driving circuit 117 when 8-phase clock driving described later is used. The odd scanning line driving circuit 116 and the even scanning line driving circuit 117 are composed of a shift register circuit 200 and an auxiliary shift register circuit 201 described later. In FIG. 2, a block indicated by a thick line is the auxiliary shift register circuit 201, and a block not shown by the thick line is the shift register circuit 200. The shift register circuit 200 and the auxiliary shift register circuit 201 are arranged alternately. In the odd scan driving circuit 116, the shift register circuit 200 is arranged on the odd line, and the auxiliary shift register circuit 201 is arranged on the even line. In the even-scan driving circuit 117, the shift register circuit 200 is disposed on the even line and the auxiliary shift register circuit 201 is disposed on the odd line.

  Control signals CK, V1, V3, V5, and V7, which will be described later, and voltage sources VGH and VGL are input to the odd-numbered scan line driving circuit 116, and control signals CKB and V2 to be described later are input to the even-numbered scan line drive circuit 117. , V4, V6, V8 and VGH and VGL which are voltage sources are input. Note that the VST signal generated by the scanning line drive circuit control signal generation unit 112 is input as a start signal to the shift register circuit 200 and the auxiliary shift register circuit 201 on the first line, and the shift register circuits on and after the second line. As the start signal to 200 and the auxiliary shift register circuit 201, the preceding scanning signal (Gn-1) is input. Further, the next stage scanning signal (Gn + 1) is input as the reset signal of the shift register circuit 200. Note that the VGH voltage and the VGL voltage have a relationship of VGH> VGL, and a voltage at which the TFT in the pixel portion 115 can be turned on (scanning voltage indicating a selected state) is set as a VGH voltage, and a voltage at which the TFT can be turned off (non-selected) A non-scanning voltage indicating a state) is defined as a VGL voltage.

  Next, the circuit configuration and operation of the conventional shift register circuit 200 will be described with reference to FIGS. FIG. 3A shows a circuit configuration of a conventional shift register circuit 200. The shift register circuit 200 includes four Trs (M1 to M4) and one capacitor (C1). As control signals, a start signal ST (Gn-1), a reset signal RST (Gn + 1), and an input clock signal CK ( V1 to V8), and VGL is input as a voltage source. That is, the shift register circuit 200 includes a voltage input terminal that inputs a VGL voltage (a non-scanning voltage indicating a non-selected state), an output terminal that outputs a scanning signal Gn to the scanning line of the display portion, and a clock signal CK (V1 to V1). V8), a start terminal for inputting a start signal ST (Gn-1), and a reset terminal for inputting a reset signal RST (Gn + 1). Note that all of the input control signals are VGH for the high voltage and VGL for the low voltage.

  The circuit operation of the shift register circuit 200 will be described with reference to FIG. FIG. 3B shows the shift register circuit 200 on the first line as an example. First, in the period T1, when a start signal ST (VST) is input, M3 is turned on, and the internal node N1 (gate line of M1) of the shift register circuit 200 changes from the VGL potential to the VGH potential, and M1 Is turned on. At this time, the capacitor C1 is also charged. Next, when the clock signal CK (V1) is input in the period T2, the clock signal CK (V1) is output from the M1 to the scanning line Gn (G0). Since the internal node N1 has a potential of VGH × 2 due to the coupling of the capacitor C1, the gate voltage of M1 is supplied with a potential twice that of the normal time (VGH). The charge mobility is increased and the convergence characteristic of the scanning signal is improved. Next, in the period T3, the reset signal RST (G0) is input, so that M2 and M4 are turned on, the potential of the scanning line Gn (G0) is discharged to VGL, and the potential of the internal node N1 is similarly changed to VGL. Thereafter, M1 keeps the off state (Gn = VGL). Although V1 to V8 are input as clock signals of the shift register circuit 200, V1 to V8 are signals that are output in a pulse with an 8H cycle as shown in FIG. By using this low duty clock signal, the power consumed by the shift register circuit 200 (mainly M1) can be reduced. Such a driving method using eight clock signals is called 8-phase clock driving.

  Next, the circuit configuration and operation of the auxiliary shift register circuit 201 will be described with reference to FIGS. FIG. 4A shows a circuit configuration of the auxiliary shift register circuit 201. The auxiliary shift register circuit 201 is composed of three Trs (MS1 to MS3) and one capacitor (C1). As control signals, a start signal ST (Gn-1), an input clock signal CK (CK / CKB), a voltage VGH is input as the source. That is, the auxiliary shift register circuit 201 has a voltage input terminal for inputting a VGH voltage (scanning voltage indicating a selected state), an output terminal connected to the output terminal of the shift register circuit 200 via a scanning line, and a clock signal CK ( CK / CKB) and a start terminal for inputting a start signal ST (Gn-1). Then, the auxiliary shift register circuit 201 uses the Tr (MS2) for supplying the clock signal CK (CK / CKB) input to the clock terminal to the output terminal and the start signal ST (Gn-1) input to the start terminal. Tr (MS1) for supplying the scanning voltage (VGH voltage) input to the voltage input terminal to the gate node of Tr (MS2), and Tr (MS2) by the clock signal CK (CK / CKB) input to the clock terminal Tr (MS3) for discharging the gate node to the output terminal, and a capacitor CS1 connected between the output terminal and the gate node of Tr (MS2).

  The circuit operation will be described with reference to FIGS. 4B shows an example of the auxiliary shift register circuit 201 on the first line, and FIG. 4C shows an example of the auxiliary shift register circuit 201 on the second line.

  First, in FIG. 4B, in the period T1, when the start signal ST (VST) is input, MS1 is turned on, and the internal node NS1 (gate signal of MS2) of the auxiliary shift register circuit 201 is changed from the VGL potential to the VGH potential. And MS2 is turned on. At this time, the capacitor CS1 is also charged. Next, by inputting a clock signal CK (CKB) that is output in a 1H cycle in the period T2, the clock signal CK is output from the MS2 to the scanning line Gn (G0). MS3 is also turned on in the same manner. At this time, since the scanning line Gn (G0) is at the VGH potential, the internal node NS1 becomes a potential of VGH × 2 due to the coupling of the capacitor CS1, and the gate voltage of the MS2 is normally set. A potential twice the time (VGH) is supplied, and the charge mobility of MS2 is higher than that in the normal state, and the convergence characteristics of the scanning signal are improved. Next, in the period T3, since the scanning line Gn (G0) is changed from the VGH potential to the VGL potential by the shift register circuit 200, the internal node NS1 is changed from the VGH × 2 potential to the VGH potential due to the coupling fluctuation of the capacitor CS1. To do. Next, in the period T4, MS3 is turned on by the clock signal CK (CKB). However, since the scanning line Gn (G0) holds the VGL potential by the shift register circuit 200, the internal node NS1 is changed from the VGH potential. Discharge to VGL potential.

  Next, in FIG. 4C, in the period T2, when the start signal ST (G0) is input, the MS1 is turned on, and the internal node NS1 (the gate signal of the MS2) of the auxiliary shift register circuit 201 is changed from the VGL potential to the VGH. It changes to a potential and MS2 is turned on. At this time, the capacitor CS1 is also charged. Next, by inputting a clock signal CK that is output in a 1H cycle in the T3 period, the clock signal CK is output from the MS2 to the scanning line Gn (G1). MS3 is also turned on in the same manner. At this time, since the scanning line Gn (G1) is at the VGH potential, the internal node NS1 becomes a potential of VGH × 2 due to the coupling of the capacitor CS1, and the gate voltage of the MS2 is normally set. A potential twice the time (VGH) is supplied, and the charge mobility of MS2 is higher than that in the normal state, and the convergence characteristics of the scanning signal are improved. Next, in the period T4, since the scanning line Gn (G1) is changed from the VGH potential to the VGL potential by the shift register circuit 200, the internal node NS1 is changed from the VGH × 2 potential to the VGH potential due to the coupling fluctuation of the capacitor CS1. To do. Next, in the T5 period, MS3 is turned on by the clock signal CK. However, since the scanning line Gn (G1) holds the VGL potential by the shift register circuit 200, the internal node NS1 changes from the VGH potential to the VGL potential. And discharge.

  As described above, in a high-definition and high-resolution display device, when the amount of scanning signal to the scanning line is fed, the conventional shift register circuit is used on one side, and the number of Trs and control signals is low on the other side. By supplying power on both sides with the auxiliary shift register circuit configured as described above, it is possible to improve the convergence characteristics of the scanning signal while narrowing the frame of the display device.

  In this embodiment, the eight-phase clock driving with the low power effect using eight clock signals (V1 to V8) has been described. However, the present invention is not limited to this, and the clock signal is changed according to the frame size of the display device. It may be increased or decreased.

  Further, in the auxiliary shift register circuit 201, when the channel width of the MS2 that supplies the clock signal to Gn is equal to or larger than the channel width of the M1 in the shift register circuit 200, the effect of improving the convergence characteristics of the scanning signal is increased. When smaller than M1 in the register circuit 200, the effect of improving the convergence characteristic of the scanning signal is also reduced.

  In the odd scan driving circuit 116, the shift register circuit 200 is arranged on the odd line, the auxiliary shift register circuit 201 is arranged on the even line, and in the even scan driving circuit 117, the shift register circuit is arranged on the even line. 200 is arranged, and the auxiliary shift register circuit 201 is arranged on the odd-numbered line. However, the present invention is not limited to this. In the odd-scan driving circuit 116, the auxiliary shift register circuit 201 is arranged on the odd-numbered line and the even-numbered line is arranged. The shift register circuit 200 may be disposed in the eye, and in the even scanning driver circuit 117, the auxiliary shift register circuit 201 may be disposed in the even line, and the shift register circuit 200 may be disposed in the odd line.

  Next, Embodiment 2 of the present invention will be described with reference to FIGS. In FIG. 4B, since the clock signal CK is input during the period T4, MS3 is turned on. Here, there is no problem when the charge mobility of MS3 is high, but when the charge mobility is low, the internal node NS1 has a certain amount of time until it is discharged from the VGH potential to the VGL potential (hereinafter referred to as transition time T). Will be applied. Therefore, during the transition time T, MS2 may be in a half-on state. When MS2 is in the half-on state, the clock signal CK is output to the scanning line Gn. Therefore, the VGH potential is the same as the scanning signal off period (VGL potential output), and the TFT in the pixel portion 115 is half-on. An unintended data voltage may be written to the source terminal, which may cause image quality degradation. Therefore, a reset function is added to the auxiliary shift register circuit.

  FIG. 5 shows circuit configurations of an odd-numbered scan line driving circuit 116 and an even-numbered scan line driving circuit 117 for explaining the second embodiment of the present invention. The odd scanning line driving circuit 116 and the even scanning line driving circuit 117 are constituted by a shift register circuit 200 and an auxiliary shift register circuit 500. The start signal ST and the clock signal CK input to the auxiliary shift register circuit 500 are the same as those of the auxiliary shift register circuit 201, but the configuration is such that the next-stage scanning signal is input as a reset signal as in the shift register circuit 200. . That is, the auxiliary shift register circuit 500 includes a reset terminal that inputs a reset signal RST (Gn + 1), a voltage input terminal that inputs a VGL voltage (non-scanning voltage indicating a non-selected state), and a reset signal that is input to the reset terminal. Tr (MS4) that discharges the gate node of Tr (MS2) to VGL voltage at RST (Gn + 1).

  Next, the circuit configuration and operation of the auxiliary shift register circuit 500 will be described with reference to FIGS. FIG. 6A shows a circuit configuration of the auxiliary shift register circuit 500, which includes four Trs (MS1 to MS4) and a capacitor CS1, and control signals include a start signal ST (Gn-1), a reset signal (Gn + 1), An input clock signal CK (CK / CKB) and VGL are input as a voltage source. The circuit operation will be described with reference to FIGS. 6B shows the auxiliary shift register circuit 500 for the first line, and FIG. 6C shows the auxiliary shift register circuit 500 for the second line as an example. First, in FIG. 6B, the period is the same as that of the auxiliary shift register circuit 201 in the period T1 to T2. In the T3 period, the reset signal RST (G1) is input, whereby the MS4 is turned on, and the potential of the internal node NS1 is forcibly discharged to VGL. Since the clock signal CK is at the VGL potential in the period T3, the clock signal CK is output to the scanning line Gn (G0) even during the transition time T from the VGH × 2 potential to the VGL potential at the internal node NS1. Absent. Next, in FIG. 6C, the auxiliary shift register circuit 201 is the same during the period T2 to T3. In the T4 period, the reset signal RST (G2) is input, whereby the MS4 is turned on, and the potential of the internal node NS1 is forcibly discharged to VGL. Since the clock signal CKB is at the VGL potential in the period T4, the clock signal CKB is output to the scanning line Gn (G1) even during the transition time T from the VGH × 2 potential to the VGL potential at the internal node NS1. Absent.

  As described above, by providing a reset function for forcibly changing the potential of the internal node NS1 in the auxiliary shift register circuit to VGL, the potential of the scanning signal holds the VGL potential during the scanning line off period. Is possible.

DESCRIPTION OF SYMBOLS 100 ... CPU, 101 ... Drive circuit, 102 ... System interface part, 103 ... Register part, 104 ... Memory control part, 105 ... Display memory part, 106 ... Timing generation 107: Latch circuit unit, 108 ... Data voltage generation unit, 109 ... Reference voltage generation unit, 110 ... Data voltage selection unit, 111 ... Operational amplifier unit, 112 ... Scanning line Control signal generator for drive circuit, 113 ... Common signal generator, 114 ... Display unit, 115 ... Pixel unit, 116 ... Drive circuit for odd scan lines, 117 ... For even scan lines Drive circuit, 200... Shift register circuit, 201... Auxiliary shift register circuit, 500.

Claims (6)

A plurality of scanning lines, a data line, a pixel portion arranged in a matrix, a common common electrode, and a plurality of scanning voltages indicating a selected state from both sides of the plurality of scanning lines in a line-sequential manner every scanning period. A data voltage corresponding to display data is applied to the data lines, and the common common electrode is applied to an active matrix display portion having a scanning line driving circuit composed of a shift register circuit and a plurality of auxiliary shift register circuits. In the display device, a common voltage corresponding to the polarity is applied, and the difference between the data voltage and the common voltage in the scanning line in the selected state is the applied voltage to the pixel portion.
The shift register circuit includes: a first voltage input terminal that inputs a non-scanning voltage indicating a non-selected state; a first output terminal that outputs a scanning signal to the scanning line of the display portion; and a first clock terminal; A first start terminal and a first reset terminal,
The auxiliary shift register circuit located on the opposite side of the display unit with respect to the shift register circuit includes a second voltage input terminal for inputting a scanning voltage indicating a selected state, and the first output of the shift register circuit. A display device comprising: a second output terminal connected to the terminal through a scanning line; a second clock terminal; and a second start terminal. The display device according to claim 1,
The auxiliary shift register circuit includes a first transistor that supplies a clock signal input to the second clock terminal to the second output terminal, and a start signal input to the second start terminal. A second transistor for supplying the scanning voltage input to the voltage input terminal of the second transistor to the gate node of the first transistor; and a gate signal of the first transistor by a clock signal input to the second clock terminal. A display device, comprising: a third transistor that discharges to the second output terminal; and a capacitor connected between the second output terminal and a gate node of the first transistor. The display device according to claim 1,
The display device, wherein the clock signal input to the second clock terminal of the auxiliary shift register circuit outputs the scanning voltage every other scanning period. The display device according to claim 1,
In the first line of the scanning line, a start signal generated by the display device driving device is input to the second start terminal of the auxiliary shift register circuit. A display device, wherein a scanning signal output from the second output terminal of the shift register circuit is input to the second start terminal of the auxiliary shift register circuit. The display device according to claim 1,
The auxiliary shift register circuit includes a second reset terminal, a third voltage input terminal for inputting a non-scanning voltage indicating a non-selected state, and a reset signal input to the second reset terminal. And a fourth transistor for discharging the gate node of the transistor to the non-scanning voltage. The display device according to claim 5,
The reset signal inputted to the second reset terminal of the auxiliary shift register circuit is inputted with a scanning signal outputted from the second output terminal of the auxiliary shift register circuit at the next stage. Display device.

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