JP2007241028A - Driving circuit of matrix display device and matrix display device with same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a driving circuit which can be laid out in a small space. <P>SOLUTION: Scanning signal transfer circuits 31_1L to 31_241L including first transistors 46b_1L to 4b6_242L which connect one-end sides of the respective scanning lines to clock signals CK1 and CK2 transferring scanning signals of the respective scanning lines and scanning signal transfer circuits 31_1R to 31_241R including second transistors 48b_1R to 48b_242R which connect other-end sides to low-level power sources Vgl of the respective scanning lines are arranged on both sides corresponding to both the ends of the respective scanning lines, one to one, so that the first transistors and second transistors are separately connected to both the ends of the respective scanning lines, one to one. The first and second transistors operate in pairs simultaneously based upon timings of the clock signals to scan the respective scanning lines. Further, an output signal exclusively for a transfer circuit output in scanning timing of each scanning line is used as at least one of input signals of the scanning signal transfer circuit based upon the timing of the clock signal. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention provides a driving circuit for a matrix display device in which a plurality of signal lines and a plurality of scanning lines are arranged in a matrix, and pixels are arranged at intersections of the signal lines and the scanning lines, and such driving The present invention relates to a matrix display device including a circuit.

  In recent years, matrix display devices such as active matrix liquid crystal display devices and organic EL display devices using thin film transistors (TFTs) have been developed.

  This matrix display device has a scanning line driving circuit (hereinafter referred to as a gate driver) that generates a scanning signal for sequentially scanning each row of the pixel matrix. The gate driver has an operating frequency lower than that of a signal line driver circuit (hereinafter referred to as a source driver) that supplies a video signal to each column of the matrix. It is also possible. At that time, polysilicon is often used as the thin film semiconductor layer, but a thin film that does not require an annealing step, such as amorphous silicon or ZnO, can also be used. However, in that case, since the mobility of the semiconductor layer is one to two orders of magnitude smaller than that of polysilicon, it is necessary to increase the gate width of each transistor constituting the gate driver and increase the driving force. However, if the gate width is too large, the area occupied by the gate driver increases, and area reduction (narrow frame), which is one of the merits of integrally forming the gate driver with the active elements in the pixel, cannot be achieved.

  As one solution to this problem of area increase, Patent Document 1 proposes a method in which gate drivers are arranged on both the left and right sides and the same signals (start signal, end signal, clock signal) are input to each. ing.

  FIG. 4A is a diagram showing a configuration of the liquid crystal display device disclosed in Patent Document 1. In FIG. That is, the liquid crystal display device includes a liquid crystal panel 10, a source driver 12, gate drivers 14 L and 14 R, a control circuit 16, and a drive power supply circuit 18. In the following description, for the sake of simplicity, the liquid crystal panel 10 will be described as a matrix type liquid crystal panel in which the pixel arrangement is a lattice.

  The liquid crystal panel 10 includes a plurality of signal lines 20 provided in the Y direction (vertical direction) and a plurality of scanning lines 22 provided in the X direction (horizontal direction). The number of signal lines 20 is M. The number of scanning lines 22 is N. The address of the signal line 20 is Y1 to YM, and the address of the scanning line 22 is X1 to XN.

  In such a lattice-like matrix type liquid crystal panel 10, signal lines 20 and scanning lines 22 are arranged in a matrix form, and pixels 24 are formed at intersections between the signal lines 20 and the scanning lines 22. A liquid crystal panel 10 shown in FIG. 4A is an example of a TFT type liquid crystal panel, and an element P at the intersection of the signal line 20 and the scanning line 22 represents a TFT that drives each pixel 24. A counter electrode 26 indicated by a broken line is an electrode for applying an operation reference voltage of the liquid crystal panel 10 of the TFT, and a terminal 28 is provided in a part thereof. The common signal voltage Vcom is applied to the counter electrode 26 from the drive power supply circuit 18 via the terminal 28.

  In the liquid crystal panel 10, the signal line 20 is driven by the source driver 12, and the scanning pulse is sequentially supplied to the scanning line 22 from both ends simultaneously by the gate driver 14L and the gate driver 14R.

  The control circuit 16 is a circuit that controls the source driver 12 and the gate drivers 14L and 14R based on an input image signal. The drive power supply circuit 18 is a circuit that supplies a drive voltage to the source driver 12 and the gate drivers 14L and 14R.

  FIG. 5A is a diagram illustrating a configuration example of a gate driver, and FIG. 5B is a diagram illustrating a configuration of each scanning signal transfer circuit in FIG. 5A. 6A is a diagram showing the signal holding circuit extracted from FIG. 5B, FIG. 6B is a circuit diagram of the signal holding circuit, and FIG. 6C is the signal holding circuit. It is a figure which shows the input-output waveform example of a circuit. 7A is a diagram showing the inverting circuit extracted from FIG. 5B. FIG. 7B is a circuit diagram of the inverting circuit, and FIG. 7C is an input of the inverting circuit. It is a figure which shows the example of an output waveform. 8A is a diagram illustrating the output circuit extracted from FIG. 5B. FIG. 8B is a circuit diagram of the output circuit, and FIG. 8C is an input diagram of the output circuit. It is a figure which shows the example of an output waveform. FIG. 9 is a diagram showing the configuration of the gate drivers 14L and 14R, and FIG. 10 is a diagram showing a timing chart for explaining the operation of the gate drivers 14L and 14R. Here, the number of scanning lines 22 is N = 242.

  That is, each of the gate drivers 14L and 14R is configured by connecting a plurality of, in this example, 242 scanning signal transfer circuits 30 (30_1 to 30_242) in series as shown in FIG. The scanning signal transfer circuit 30 is a shift register whose output signal is supplied to each of the 242 scanning lines 22. Here, each scanning signal transfer circuit 30 includes a clock signal input terminal CK, an input signal input terminal IN, a reset signal input terminal RST, and two output signal output terminals OUT (scanning signal) and OUTA (transfer circuit dedicated output signal). The output signal from the output signal output terminal OUT is supplied to the scanning line 22 of the corresponding line, and the output signal from the output signal output terminal OUTA is the input signal input terminal of the scanning signal transfer circuit 30 in the next stage. The signal is supplied to IN as an input signal. In other words, in the n-th scanning signal transfer circuit 30_n, the output signal OUTA_n-1 from the output signal output terminal OUTA of the scanning signal transfer circuit 30_n-1 at the previous stage (n-1 stage) is input to the input signal input terminal IN. The output signal OUTA_n + 1 from the output signal output terminal OUTA of the scanning signal transfer circuit 30_n + 1 in the subsequent stage (n + 1 stage) is input to the reset signal input terminal RST. However, a start signal ST for instructing the start of scanning is supplied from the control circuit 16 to the input signal input terminal IN of the first stage scanning signal transfer circuit 30_1. Further, an end signal END for instructing the end of scanning is supplied from the control circuit 16 to the reset signal input terminal RST of the scanning signal transfer circuit 30_242 in the 242nd stage as the final stage. The clock signal CK1 supplied to the clock signal input terminal CK of the odd-numbered scanning signal transfer circuit 30 and the clock signal CK2 supplied to the clock signal input terminal CK of the even-numbered scanning signal transfer circuit 30 are: The clock signal has a reverse phase relationship in which one is at a high level and the other is at a low level. Here, the high level (VDD) and the low level (VSS) of the signal are the same for each signal, and VDD−VSS = about 25V.

  As shown in FIG. 5B, each scanning signal transfer circuit 30 includes a signal holding circuit 32, an inverting circuit 34, and output circuits 36a and 36b.

  As shown in FIG. 6A, the signal holding circuit 32 receives the two signals IN and RST supplied to the input signal input terminal IN and the reset signal input terminal RST, and outputs an output signal A. It is. The specific circuit configuration of the signal holding circuit 32 includes two n-channel field effect (MOS) transistors 38 and 40 as shown in FIG. That is, the signal IN supplied to the input signal input terminal IN is supplied to the drain electrode of the MOS transistor 40 via the diode-connected MOS transistor 38. A signal RST supplied to the reset signal input terminal RST is supplied to the gate electrode of the MOS transistor 40, and a low level voltage Vgl of the scanning line 22 is applied from the control circuit 16 to the source electrode. Then, the output signal A is taken out from the drain electrode of the MOS transistor 40 which is a connection point between the two MOS transistors 38 and 40.

  In the signal holding circuit 32 having such a configuration, the MOS transistor 38 is turned on as the signal IN rises. At this time, if the signal RST supplied to the gate electrode of the MOS transistor 40 is at a low level, the MOS transistor 40 is in an OFF state. Therefore, in the output signal A taken out from the drain electrode of the MOS transistor 40, as shown in FIG. 6C, a high level signal by the signal IN appears through the MOS transistor 38 functioning as a diode (load). . When the signal IN becomes low level, the MOS transistor 38 is turned off. At this time, the output signal A taken out from the drain electrode of the MOS transistor 40 is in an electrically floating state, but may be considered to hold the previous level. In FIG. 6C, such a state is indicated by a broken line (the same applies to the diagrams showing other waveforms). Thereafter, when the signal RST becomes high level, the MOS transistor 40 is turned on. As a result, the output signal A extracted from the drain electrode of the MOS transistor 40 becomes the low level voltage Vgl. In this way, the signal holding circuit 32 changes the potential of the output signal A from the rising edge of the signal IN supplied to the input signal input terminal IN, as shown in FIG. Until the rising edge of the signal RST supplied to.

  Further, as shown in FIG. 7A, the inverting circuit 34 receives the output signal A of the signal holding circuit 32 and outputs an output signal A bar which is a reverse phase signal. A specific circuit configuration of the inverting circuit 34 is composed of two n-channel MOS transistors 42 and 44 as shown in FIG. That is, the MOS transistor 44 is diode-connected to the high-potential power supply VDD, and its drain and source electrodes are connected between the MOS transistor 42 that functions as a load and the low-potential power supply VSS as an operating voltage on the low-potential side. The output signal A is supplied to the gate electrode. The output signal A bar is taken out from the drain electrode of the MOS transistor 44.

  In the inverting circuit 34 having such a configuration, when the output signal A output from the signal holding circuit 32 is at a low level, the MOS transistor 44 is in an OFF state. Therefore, the output signal A bar taken out from the drain electrode of the MOS transistor 44 has a high level by the high potential power supply VDD via the MOS transistor 42 functioning as a diode (load) as shown in FIG. A signal appears. When the output signal A of the signal holding circuit 32 rises, the MOS transistor 44 is turned on accordingly. When the MOS transistor 44 is turned on, a current path is formed from the high potential power supply VDD to the low potential power supply VSS via the MOS transistors 42 and 44, and the potential of the drain electrode of the MOS transistor 44 becomes low, and the output signal A bar is low level. In this way, as shown in FIG. 7C, the inverting circuit 34 outputs an output signal A bar indicating the level obtained by inverting the output signal A output from the signal holding circuit 32 as the input signal. To do.

  Further, as shown in FIG. 8A, the output circuit 36a receives the output signal A of the signal holding circuit 32, the output signal A bar of the inverting circuit 34, and the clock signal CK, and outputs the output signal OUTA. Output. A specific circuit configuration of the output circuit 36a is a push-pull circuit composed of two n-channel type MOS transistors 46a and 48a, as shown in FIG. 8B. That is, the MOS transistors 46a and 48a are connected between the input terminal CK to which the clock signal CK is applied from the control circuit 16 and the power supply terminal to which the low level voltage Vgl of the scanning line 22 is applied from the control circuit 16 as well. Are connected in series so that the gate electrode of the MOS transistor 46a receives the output signal A of the signal holding circuit 32 and the gate electrode of the MOS transistor 48a receives the output signal A bar of the inverting circuit 34. It is connected to the. An output signal OUTA is output from the connection contact of both MOS transistors 46a and 48a.

  In the output circuit 36a having such a configuration, when the output signal A from the signal holding circuit 32 becomes high level, the MOS transistor 46a is turned on. At this time, since the output signal A bar from the inverting circuit 34 is at the low level, the MOS transistor 48a is turned off. Therefore, when the clock signal CK supplied to the MOS transistor 46a becomes high level, the signal level of the output signal OUTA also becomes high level. When the output signal A from the signal holding circuit 32 becomes low level in response to the reset signal input to the signal holding circuit 32, the output signal A bar from the inverting circuit 34 becomes a high level signal. Thus, the MOS transistor 46a is turned off, and the MOS transistor 48a is turned on. Therefore, the signal level of the output signal OUTA is also low. In this way, as shown in FIG. 8C, the output circuit 36a outputs the clock signal CK while the output signal A output from the signal holding circuit 32 is at the high level, and A is at the low level. During this period, the low level voltage Vgl is output.

  The output circuit 36b has the same configuration as the output circuit 36a. That is, as shown in FIG. 8A, the output circuit 36b receives the output signal A of the signal holding circuit 32, the output signal A of the inverting circuit 34, and the clock signal CK, and outputs the output signal OUT. Is output. A specific circuit configuration of the output circuit 36b is a push-pull circuit composed of two n-channel type MOS transistors 46b and 48b, as shown in FIG. 8B. That is, the MOS transistors 46b and 48b are connected between the input terminal CK to which the clock signal CK is applied from the control circuit 16 and the power supply terminal to which the low level voltage Vgl of the scanning line 22 is applied from the control circuit 16. Are connected in series, and the gate electrode of the MOS transistor 46b therein receives the output signal A of the signal holding circuit 32, and the gate electrode of the MOS transistor 48b receives the output signal A bar of the inverting circuit 34, respectively. It is connected to the. An output signal OUT is output from the connection contact of both MOS transistors 46b and 48b.

  In the output circuit 36b having such a configuration, when the output signal A from the signal holding circuit 32 becomes high level, the MOS transistor 46b is turned on. At this time, since the output signal A bar from the inverting circuit 34 is at a low level, the MOS transistor 48b is turned off. Therefore, when the clock signal CK supplied to the MOS transistor 46b becomes high level, the signal level of the output signal OUT also becomes high level. When the output signal A from the signal holding circuit 32 becomes a low level in response to the reset signal, the output signal A bar from the inverting circuit 34 becomes a high level signal, whereby the MOS transistor 46b is turned off. Thus, the MOS transistor 48b is turned on. Therefore, the signal level of the output signal OUT is also low. In this way, as shown in FIG. 8C, the output circuit 36b outputs the clock signal CK while the output signal A output from the signal holding circuit 32 is at the high level, and A is at the low level. During this period, the low level voltage Vgl is output.

  Thus, as a result, the single pulse signal input to the input signal input terminal IN of the signal holding circuit 32 is shifted by the clock signal CK from the scanning signal transfer circuit 30, and two signals are output at the timing. One is a signal supplied to the input signal input terminal IN of the scanning signal transfer circuit 30 in the next stage and the reset signal input terminal RST of the scanning signal transfer circuit 30 in the previous stage, and the other is a scanning signal of the scanning line 22.

  In this way, by separating the output signal dedicated to the transfer circuit (OUTA) and the scan signal (OUT) that actually drives the scan line, the transfer operation of the scan signal transfer circuit can be made more reliable.

  The MOS transistors 38 to 48 are all composed of, for example, an n-channel amorphous silicon TFT.

  The configuration of the gate drivers 14L and 14R by the scanning signal transfer circuit 30 having the above configuration is as shown in FIG. That is, the left side of the first scanning line 22_1 is connected to the signal holding circuit 32_1L, the inverting circuit 34_1L, and the scanning signal transfer circuit 30_1L including the output circuits 36a_1L and 36b_1L, and the right side is connected to the signal holding circuit 32_1R, the inverting circuit 34_1R, and Scanning signal transfer circuits 30a_1R and 30b_1L including the output circuit 36_1R are connected. A scanning signal transfer circuit 30_2L including a signal holding circuit 32_2L, an inverting circuit 34_2L, and output circuits 36a_2L and 36b_2L is connected to the left side of the second scanning line 22_2, and a signal holding circuit 32_2R, an inverting circuit 34_2R and an output circuit are connected to the right side. Scanning signal transfer circuits 30a_2R and 30b_2R composed of 36_2R are connected. Similarly, the scanning signal transfer circuits 30_nL and 30_nR are connected to both sides of the scanning line 22_n of each line, and the scanning signal transfer circuits 30_242L and 30_242R are connected to both sides of the scanning line 22_242 of the last 242nd line.

  In this case, in the inverting circuits 34_1L to 34_242L and 34_1R to 34_242R, the high level voltage Vgh of the scanning lines 22_1 to 22_242 applied from the control circuit 16 as the high potential power supply VDD is the same as the control circuit as the low potential power supply VSS. The low level voltage Vgl of the scanning lines 22_1 to 22_242 applied from 16 is used.

  FIG. 10 is a timing chart of input signals and output signals when the number of stages of the scanning signal transfer circuit 30 is 242. Here, one frame is, for example, 1/60 second.

  That is, the start signal ST supplied from the control circuit 16 to the signal holding circuits 32_1L and 32_1R of the first-stage scanning signal transfer circuits 30_1L and 30_1R is half of the clock signal CK1 from the start (write) timing of image display of one frame. High before clock. As a result, the signal that rises in the phase of the clock signal CK1 as described above from the output circuits 36b_1L and 36b_1R of the scanning signal transfer circuits 30_1L and 30_1R in the first stage as the clock signal CK1 rises is used as the output signal OUT_001. When the clock CK1 becomes high level, the high level output signal OUT_001 is supplied to the scanning line 22_1. Similarly, the signals rising at the phase of the clock signal CK1 as described above are output as the output signals OUTA_001L and OUTA_001R from the output circuits 36a_1L and 36a_1R of the scanning signal transfer circuits 30_1L and 30_1R in the first stage. When the clock CK1 becomes high level, the high level output signals OUTA_001L and OUTA_001R are supplied to the signal holding circuits 32_1L and 32_1R of the scanning signal transfer circuits 30_2L and 30_2R in the second stage.

  Thus, when a high level signal is supplied to the signal holding circuits 32_1L and 32_1R of the second-stage scanning signal transfer circuits 30_2L and 30_2R, the output circuits 36b_2L and 36b_2R of the second-stage scanning signal transfer circuits 30_2L and 30_2R A signal that rises in phase with the clock signal CK2 as described above is output as the output signal OUT_002, and when the clock CK2 becomes high level, the high-level output signal OUT_002 is supplied to the scanning line 22_2. It becomes. Similarly, the signals rising at the phase of the clock signal CK2 as described above are output as the output signals OUTA_002L and OUTA_002R from the output circuits 36a_2L and 36a_2R of the scanning signal transfer circuits 30_2L and 30_2R in the second stage. When the clock CK2 becomes high level, the high-level output signals OUTA_002L and OUTA_002R are supplied to the signal holding circuits 32_3L and 32_3R of the scanning signal transfer circuits 30_3L and 30_3R in the third stage. . Further, the high level output signals OUTA_002L and OUTA_002R are also supplied as reset signals RST to the reset signal input terminals RST of the signal holding circuits 32_1L and 32_1R of the first-stage scanning signal transfer circuits 30_1L and 30_1R. By this high level reset signal RST, as described above, the output as the output signal OUT_001 rising from the phase of the clock signal CK1 from the output circuits 36a_1L and 36a_1R of the scanning signal transfer circuits 30_1L and 30_1R in the first stage, And the outputs as the output signals OUTA_001L and OUTA_001R that rise from the phase of the clock signal CK1 from the output circuits 36b_1L and 36b_1R are respectively lowered. Accordingly, the output signals OUT_001, OUTA_001L, and OUTA_001R are at a low level.

  Similarly, the output signals OUT_n of the scanning signal transfer circuits 30_nL and 30_nR at the respective stages are supplied to the scanning lines 22_n at the respective stages, and the output signals OUTA_nL and OUTA_nR are transferred to the scanning signal transfer circuits 30_n + 1L and 30_n + 1R at the subsequent stages. In addition, the scanning signal transfer circuits 30_n-1L and 30_n-1R in the previous stage are supplied as the reset signal RST.

  However, in the scanning signal transfer circuits 30_242L and 30_242R in the final stage, the output signals OUTA_242L and OUTA_242R are only supplied as the reset signal RST to the scanning signal transfer circuits 30_241L and 30_241R in the previous stage. Then, at the timing when the output signals OUT_242, OUTA_242L, and OUTA_242R of the scanning signal transfer circuits 30_242L and 30_242R in the final stage are set to the low level, the end signal END is held by the control circuit 16 to hold the signals of the scanning signal transfer circuits 30_242L and 30_242R. The reset signals RST are supplied to the reset signal input terminals RST of the circuits 32_242L and 32_242R.

  In the case of the liquid crystal display device having such a configuration, if the wiring delay of the input signal is ignored, the left and right gate drivers 14L and 14R are electrically in parallel, so one gate driver configured with a double gate width is provided. The same electrical characteristics are obtained as on one side. Since it is often desirable for the frame of the display device to be symmetrical, such a double-sided drive is an effective method.

  Patent Document 1 also discloses that such double-sided parallel driving is applied to a liquid crystal display device using a passive matrix type liquid crystal panel.

  FIG. 4B is a diagram showing a configuration of a liquid crystal display device using a passive matrix type liquid crystal panel disclosed in Patent Document 1. In this case, the liquid crystal panel 10 includes a plurality of signal lines provided in the Y direction (vertical direction) and a plurality of scanning lines provided in the X direction (horizontal direction). In such a passive matrix type liquid crystal panel 10, the signal lines 20 and the scanning lines 22 are arranged in a matrix, and pixels 24 are formed at the intersections of the signal lines 20 and the scanning lines 22, respectively. The pixel 24 has a liquid crystal cell and a transparent pixel electrode, or a drive terminal including the liquid crystal cell and the transparent pixel electrode, and the capacity thereof is determined by the liquid crystal cell and the pixel electrode. Here, the capacity of the pixel 24 is referred to as a pixel capacity.

Also in a liquid crystal display device using such a passive matrix type liquid crystal panel, parallel driving on both sides by the left and right gate drivers 14L and 14R is an effective method.
JP-A-11-295696

  In the double side parallel drive as disclosed in Patent Document 1, there is a problem that the layout area increases.

  In other words, the occupied area of the circuit portion becomes larger when dispersed on both sides than when concentrated on one side. This is because the number of elements itself is doubled, so that the required free space is doubled. In other words, a circuit that performs both-side parallel driving apparently narrows the frame by using the space on both sides equally, but it simply reduces the area utilization efficiency when considered in terms of the layout area. When the actual layout area increases, the number of panels that can be cut out from the same size substrate decreases, which increases the cost.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a drive circuit for a matrix display device that can be laid out in a small space and a matrix display device including the drive circuit.

One aspect of the drive circuit of the matrix display device of the present invention is:
A scanning signal transfer for transferring a scanning signal of the scanning line in a matrix display device in which a plurality of signal lines and a plurality of scanning lines are arranged in a matrix and pixels are arranged at intersections of the signal lines and the scanning lines. A drive circuit comprising a circuit,
A first switching element connected to one end of each scanning line and selectively connected / disconnected to a clock signal for transferring a scanning signal of each scanning line;
A second switching element connected to the other end of each scanning line and selectively connected / disconnected to a low level power source of each scanning line;
Based on the timing of the clock signal, an output circuit that outputs a transfer circuit dedicated output signal that is output at the scanning timing of each scanning line;
Comprising
The first switching element and the second switching element are separately connected to both sides of each scanning line one by one,
Based on the timing of the clock signal input to the first switching element side, the first switching element and the second switching element operate as a set at the same time, so that each scanning line scans. And
The scanning signal transfer circuit is disposed on each side corresponding to both ends of each scanning line of the matrix display device,
The output signal dedicated to the transfer circuit also serves as at least one input signal of the scanning signal transfer circuit.

Also, one aspect of the matrix display device of the present invention is:
A display panel in which a plurality of signal lines and a plurality of scanning lines are arranged in a matrix, and pixels are arranged at intersections of the signal lines and the scanning lines;
A first switching element connected to one end of each scanning line and selectively connected / disconnected to a clock signal for transferring a scanning signal of each scanning line; and connected to the other end of each scanning line; A second switching element selectively connected / disconnected to / from a low-level power supply of the scanning line, and an output circuit for outputting a transfer circuit-dedicated output signal output at the scanning timing of each scanning line based on the timing of the clock signal And
The first switching element and the second switching element are separately connected to both sides of each scanning line one by one,
Based on the timing of the clock signal input to the first switching element side, the first switching element and the second switching element work together to scan each scanning line. Including a scanning signal transfer circuit,
The scanning signal transfer circuit is disposed on each side corresponding to both ends of each scanning line of the matrix display device,
The transfer circuit dedicated output signal also serves as at least one input signal of the scanning signal transfer circuit, and a drive circuit,
A control circuit for controlling the operation timing of the drive circuit;
It is characterized by comprising.

  According to the present invention, the number of switching elements (for example, transistors) is reduced as compared with the case of the conventional double-sided parallel drive, so that a denser, that is, layout with less free space is possible while maintaining the same driving force. The matrix display device driving circuit and the matrix display device including the same can be provided.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

  FIG. 1 is a schematic configuration diagram showing an overall configuration of a drive circuit of a matrix display device according to an embodiment of the present invention, and FIG. 2 is a diagram showing a configuration of gate drivers 15L and 15R in FIG. Here, a liquid crystal display device using a TFT active matrix type liquid crystal panel will be described as the matrix display device. FIG. 2 shows an example in which the number N of scanning lines 22 is N = 242.

  In FIG. 1 and FIG. 2, components common to the prior art shown in FIG. 9 are denoted by the same reference numerals and description thereof is simplified.

  That is, the drive circuit of the matrix display device according to the present embodiment has a plurality of signal lines and a plurality of scanning lines arranged in a matrix as shown in FIG. 1, and a pixel at each intersection of the signal lines and the scanning lines. Gate drivers 15L and 15R that generate scanning signals for sequentially scanning the scanning lines 22 of each row of the matrix are arranged on both sides of the liquid crystal panel 10 arranged. The gate drivers 15L and 15R are supplied with a start signal ST, an end signal END, a high level voltage Vgh of the scanning line 22 corresponding to the high potential power supply VDD, and a low potential power supply VSS from the control circuit 16 as shown in FIG. The corresponding low level voltage Vgl of the scanning line 22 and the clock signals CK1 and CK2 are from one gate driver (left gate driver 15R in this example) side to the other gate driver (right gate driver 15L in this example) side. It is supplied by being routed to.

  Specifically, as shown in FIG. 2, the left gate driver 15L includes 242 scanning signal transfer circuits 31_1L to 31_242L. Each scanning signal transfer circuit 31L includes a signal holding circuit 32, an inverting circuit 34, and an output. The circuits 36a and 37bL are configured. This is substantially the same as the prior art, except that the configuration of the output circuit 36b is an output circuit 37bL in this embodiment.

  That is, the output circuit 37b_1L of the scanning signal transfer circuit 31_1L at the first stage is composed of only one MOS transistor (first transistor) 46b_1L to which the output signal A of the signal holding circuit 32_1L is supplied to its gate electrode. Yes. Then, one of the source electrode and the drain electrode of the MOS transistor 46b_1L is supplied with a clock signal CK1 for transferring the scanning line 22_1, and an output signal (scanning signal) for scanning the scanning line 22_1 from the other drain electrode or source electrode. ) OUT_001 is configured to be taken out.

  Similarly, the output circuit 37b_2L of the scanning signal transfer circuit 31_2L at the second stage is composed of only one MOS transistor 46b_2L to which the output signal A of the signal holding circuit 32_2L is supplied to its gate electrode, and the source of the MOS transistor 46b_2L One of the electrodes and the drain electrode is supplied with a clock signal CK2 for transferring the scanning line 22_2, and an output signal OUT_002 for scanning the scanning line 22_2 is taken out from the other drain electrode or source electrode.

  Similarly, in the third to 242nd scanning signal transfer circuits 31L, each output circuit 37bL is composed of one MOS transistor 46bL, and the source of the MOS transistor 46bL of the odd-numbered scanning signal transfer circuit 31L. The clock signal CK1 is applied to one of the electrodes or the drain electrode, and the clock signal CK2 is applied to one of the source electrode or the drain electrode of the MOS transistor 46bL of the even-numbered scanning signal transfer circuit 31L.

  Further, output signals OUTA_001L to OUTA_241L taken out from connection points of the MOS transistors 46a_1L to 46a_241L and the MOS transistors 48a_1L to 48a_241L constituting the output circuits 36a_1L to 36a_241L of the first to 241st scanning signal transfer circuits 31_1L to 31_241L. The MOS transistors 46a_2L to 46a_242L in the second to 242nd scanning signal transfer circuits 31_2L to 31_241L are supplied to the signal holding circuits 32_2L to 32_242L of the second to 242th scanning signal transfer circuits 31_2L to 31_242L. Output signals OUTA_002L to OUTA_242L taken out from the connection points of the MOS transistors 48a_2L to 48a_242L are 1 Eyes to the 241-stage scanning signal transfer circuit 31_1L~31_241L signal holding circuit 32_1L~32_241L supplied as a reset signal RST to.

  On the other hand, the right gate driver 15R includes 242 scanning signal transfer circuits 31_1R to 31_242R, and each scanning signal transfer circuit 31R includes a signal holding circuit 32, an inverting circuit 34, and output circuits 36a and 37bR. This is substantially the same as the prior art, except that the configuration of the output circuit 36b is an output circuit 37bR in this embodiment.

  That is, the output circuit 37b_1R of the scanning signal transfer circuit 31_1R in the first stage is composed of only one MOS transistor (second transistor) 48b_1R to which the output signal A bar of the inverting circuit 34_1R is supplied to its gate electrode. Yes. One of the source electrode and the drain electrode of the MOS transistor 48b_1R is supplied with the low level voltage Vgl of the scanning line 22_1, and an output signal (scanning signal) for scanning the scanning line 22_1 from the other drain electrode or source electrode. OUT_001 is configured to be taken out.

  Similarly, the output circuit 37b_2R of the scanning signal transfer circuit 31_2R at the second stage is composed of only one MOS transistor 48b_2R to which the output signal A bar of the inverting circuit 34_2R is supplied to its gate electrode, and the source of the MOS transistor 48b_2R One of the electrode and the drain electrode is supplied with the low level voltage Vgl of the scanning line 22_2, and an output signal OUT_002 for scanning the scanning line 22_2 is taken out from the other drain electrode or source electrode.

  Similarly, in the scanning signal transfer circuits 31R in the third to 242nd stages, each output circuit 37bR is composed of one MOS transistor 48bR.

  The output signal OUTA taken out from the connection point of the two MOS transistors 46a and 48a constituting the output circuit 36a of the first to 241st scanning signal transfer circuit 31R is the second to 242th scanning signal. The output signal OUTA is supplied to the signal holding circuit 32 of the transfer circuit 31R and is taken out from the connection point of the two MOS transistors 46a and 48a constituting the output circuit 36a of the second to 242th scanning signal transfer circuit 31R. Is supplied as a reset signal RST to the signal holding circuit 32 of the scanning signal transfer circuit 31R in the first to 241st stages.

  Further, output signals OUTA_001R to OUTA_241R taken out from connection points of the MOS transistors 46a_1R to 46a_241R and the MOS transistors 48a_1R to 48a_241R constituting the output circuits 36a_1R to 36a_241R of the first to 241st scanning signal transfer circuits 31_1R to 31_241R. The MOS transistors 46a_2R to 46a_242R in the second to 242nd scanning signal transfer circuits 31_2R to 31_241R are supplied to the signal holding circuits 32_2R to 32_242R of the second to 242th scanning signal transfer circuits 31_2R to 31_242R. Output signals OUTA_002R to OUTA_242R taken out from the connection points of the MOS transistors 48a_2R to 48a_242R are 1 Eyes to the 241-stage scanning signal transfer circuit 31_1R~31_241R signal holding circuit 32_1R~32_241R supplied as a reset signal RST to.

  The clock signal CK1 is applied to one of the source electrode and the drain electrode of the MOS transistor 46a of the odd-numbered scanning signal transfer circuit 31R, and the source electrode or the drain electrode of the MOS transistor 46a of the even-numbered scanning signal transfer circuit 31R. On one side, a clock signal CK2 is applied.

  Therefore, based on the timing of the clock signals CK1 and CK2 input to the MOS transistors 46b_1L to 46b_242L constituting the output circuits 37b_1L to 37b_242L of the scanning signal transfer circuits 31_1L to 31_242L of the left gate driver 15L, the MOS transistors 46b_1L to 46b_242L Since the MOS transistors 48b_1R to 48b_242R constituting the output circuits 37b_1R to 37b_242R of the scanning signal transfer circuits 31_1R to 31_242R of the corresponding right gate driver 15R operate as a set, the scanning lines 22_1 to 22_242 are operated simultaneously. Scanned.

  In the drive circuit having such a configuration, the circuits (gate drivers 15L and 15R) arranged on both the left and right sides with the pixel matrix (liquid crystal panel 10) interposed therebetween do not operate independently, and the left and right sides are separated by the scanning lines 22. It operates only after being connected. In addition, the function as a gate driver is shared between right and left. That is, the left gate driver 15L acts so that the scanning line 22 has the same potential as the clock signals CK1 and CK2 in a predetermined period of each stage (a period in which the signal A is at a high level and the signal A bar is at a low level). In contrast, the right gate driver 15R acts to insulate between the scanning line 22 and the low level voltage Vgl. On the other hand, in other periods, the left gate driver 15L insulates the scanning line 22 from the clock signals CK1 and CK2, and the right gate driver 15R maintains the scanning line 22 at the low level voltage Vgl. Act on.

  At this time, in order to make the driving force as the gate driver equivalent to the case of the conventional both-side parallel driving as disclosed in Patent Document 1 described above, the MOS transistors 46b_1L to 46b_242L constituting the output circuits 37b_1L to 367_242L. In addition, the gate widths of the MOS transistors 48b_1R to 48b_242R constituting the output circuits 37b_1R to 37b_242R may be doubled as compared to those on one side in the case of parallel driving on both sides. Even if the total gate width is unchanged, the number of transistors is reduced compared to the case of conventional double-sided parallel drive, so a denser, that is, layout with less free space is possible while maintaining the same driving force. Become.

  Thus, according to the present embodiment, in each stage of the gate driver, the MOS transistor 46b in which one of the source electrode and the drain electrode is connected to the scanning line 22 and the other is connected to the clock signal input terminal CK, and the source electrode Alternatively, the MOS transistor 48b having one of the drain electrodes connected to the scanning line 22 and the other connected to the low level voltage Vgl is arranged separately on the left and right sides of the pixel matrix, so Compared to driving, the number of transistors is reduced, so that the layout area including necessary empty space can be reduced.

  Note that it is preferable to input an input signal from one side of the liquid crystal panel 10 and route it to the other side in consideration of restrictions on the number of terminals and minimizing the layout area. However, in that case, since the wiring has a resistance and a parasitic capacitance (capacitance mainly generated between the wiring electrode and the counter electrode 26), the clock signals CK1 and CK2 are delayed on the other side than on the one side. This difference occurs in each gate row. However, when the clock signals CK1 and CK2 are routed from the lower side to the upper side of the panel as shown in FIG. 1, the difference is greatest in the lowermost row.

  For this reason, in the conventional drive circuit as shown in FIG. 9, the timings of the output signals (scanning signals) of the left and right gate drivers 14L and 14R also differ. That is, there is a period in which one of the left and right gate drivers 14L and 14R outputs a high level and the other outputs a low level. Since the output signal output terminals OUT of both the gate drivers 14L and 14R are connected to the same scanning line 22, a current flows through the scanning line 22 during this period. This current is a current that is opposite to the current that the gate driver on the other side of the circuit on the other side has a large delay. That is, the gate drivers 14L and 14R are originally operated so that the potential of the scanning line 22 becomes the same potential as the clock signal CK at a predetermined output timing. If there is a timing difference as described above, The gate driver on the other side operates so that the clock signal (which should be an input) has the same potential as the scanning line 22 (which should be an output). Further, when viewed from the one side circuit with a small delay, the capacitive load is large at that moment. That is, not only the capacitance on the scanning line 22 but also the capacitance on the clock line becomes a load. Therefore, an extra current flows than usual.

  The extra transient current itself affects the rising and falling waveforms of the scanning signals from the gate drivers 14L and 14R, and shifts the optimum common signal voltage, for example, and causes display deterioration such as burn-in and flicker. Or, the deterioration of the element is promoted and the circuit life is shortened. In addition, even if the common signal voltage is adjusted so that the optimum common signal voltage fluctuates with time due to the above-described synergistic effect on the scanning signal and deterioration, that is, flicker does not occur, the flicker is still in use. Inconvenience such as starting to occur. Furthermore, the circuit deterioration due to this current occurs asymmetrically on the left and right, so there is a difference in display due to the deterioration, for example, there is a difference in the optimal common signal voltage on the right and left sides, and flicker cannot be deleted even if adjusted. Will also occur.

  Therefore, in the present embodiment, the output circuits 37b_1L to 37b_242L and 37b_1R to 37b_242R are configured as described above, and the clock signals CK1 and CK2 input to the left gate driver 15L as shown in FIG. Wiring is routed from the left gate driver 15L side to the right gate driver 15R side so that the delay is smaller than the clock signals CK1 and CK2 input to the gate driver 15R. That is, the clock signals CK1 and CK2 are routed so that the left clock delay for performing the insulating operation between the scanning line 22 and the clock signals CK1 and CK2 becomes small.

  With such a configuration, the conduction and insulation operation between the scanning line 22 and the clock signals CK1 and CK2 by the MOS transistors 46b_1L to 46b_242L of the output circuits 37b_1L to 37b_242L are the MOS transistors 48b_1R to 34B of the output circuits 37b_1R to 37b_242R. It is possible to reliably precede the conduction and insulation operation between the scanning line 22 and the low level voltage Vgl by 48b_242R. At this time, as shown in FIG. 3A, the clock signal CK is at the low level voltage Vgl in a period in which 46bL and 48bR are simultaneously conducted. Therefore, the occurrence of the abnormal transient current as described above can be prevented.

(On the contrary, when the wiring is routed from the right gate driver 15R side to the left gate driver 15L side and wired, the scanning line 22 and the clock signals CK1 and CK2 by the MOS transistors 46b_1L to 46b_242L of the output circuits 37b_1L to 37b_242L. Between the scanning line 22 and the low level voltage Vgl by the MOS transistors 48b_1R to 48b_242R of the output circuits 37b_1R to 37b_242R. As shown in FIG. 3B, the clock signal CK becomes the high level voltage Vgh during the period in which 46bL and 48bR are simultaneously turned on, so that an abnormal transient current is generated in this case.
In this way, by actively using the signal delay, the operations are surely generated in the preferred order, the abnormal transient current is not generated, the element deterioration is reduced, and flicker, burn-in, etc. caused by it It is possible to suppress display deterioration and fluctuations over time.

  Although the present invention has been described above based on the embodiments, the present invention is not limited to the above-described embodiments, and various modifications and applications are naturally possible within the scope of the gist of the present invention.

  For example, in the above embodiment, the liquid crystal display device using the TFT active matrix type liquid crystal panel is described as an example of the matrix display device to which the drive circuit according to the embodiment is applied. Needless to say, the present invention can also be applied to driving of scanning lines in a liquid crystal display device using a passive matrix type liquid crystal panel as disclosed in Patent Document 1 described above.

  The transistors 38, 40, 42, 44, 46a, 46b, 48a, and 48b constituting the scanning signal transfer circuit 31 are not limited to n-channel amorphous silicon TFTs, but are p-channel transistors. Further, a polysilicon TFT having the same conductivity, a ZnO TFT having the same conductivity, or the like may be used.

  Further, the left and right gate drivers 14L, 14R may be arranged in the opposite direction. However, in that case, the clock signals CK1 and CK2 are input from the right side and routed to the left side.

  For convenience of explanation, the description has been made on the left and right, but it goes without saying that in the case of a matrix configuration in which the scanning lines 22 extend in the vertical direction and the signal lines 20 extend in the horizontal direction, the gate drivers are arranged vertically. That is, the present invention can be applied to any configuration in which gate drivers are arranged on both sides of the scanning line 22.

It is a schematic block diagram which shows the whole structure of the drive circuit of the matrix display apparatus which concerns on one Embodiment of this invention. It is a figure which shows the structure of the gate driver of the both sides in FIG. FIG. 3A is a diagram illustrating a signal delay state when the clock signals CK1 and CK2 are routed from the left gate driver side to the right gate driver side (state in FIG. 1). FIG. 8 is a diagram illustrating a delay state of signals when the clock signals CK1 and CK2 are routed from the right gate driver side to the left gate driver side. 4A is a diagram illustrating a configuration of a liquid crystal display device using an active matrix type liquid crystal panel disclosed in Patent Document 1, and FIG. 4B is a passive matrix disclosed in Patent Document 1. It is a figure which shows the structure of the liquid crystal display device using a type liquid crystal panel. FIG. 5A is a diagram illustrating a configuration of the gate driver, and FIG. 5B is a diagram illustrating a configuration of each scanning signal transfer circuit in FIG. 5A. 6A is a diagram showing the signal holding circuit extracted from FIG. 5B, FIG. 6B is a circuit diagram of the signal holding circuit, and FIG. 6C is the signal holding circuit. It is a figure which shows the input-output waveform example of a circuit. 7A is a diagram illustrating the inverting circuit extracted from FIG. 5B, FIG. 7B is a circuit diagram of the inverting circuit, and FIG. 7C is an input diagram of the inverting circuit. It is a figure which shows the output waveform example. 8A is a diagram showing the output circuit extracted from FIG. 5B, FIG. 8B is a circuit diagram of the output circuit, and FIG. 8C is an input diagram of the output circuit. It is a figure which shows the example of an output waveform. It is a figure which shows the structure of the conventional gate driver of both sides. It is a figure which shows the timing chart for demonstrating operation | movement of a gate driver.

Explanation of symbols

    DESCRIPTION OF SYMBOLS 10 ... Liquid crystal panel, 12 ... Source driver, 14L, 14R, 15L, 15R ... Gate driver, 16 ... Control circuit, 18 ... Drive power supply circuit, 20 ... Signal line, 22, 22_1 to 22_242 ... Scanning line, 24 ... Pixel, 30_1L to 30_242L, 30_1R to 30_242R, 31_1L to 31_242L, 31_1R to 31_242R ... Scanning signal transfer circuit, 32_1L to 32_242L, 32_1R to 32_242R ... Signal holding circuit, 34_1L to 34_242L, 34_1R to 34_24_36_24_36_24_36L 36a_242R, 36b_1L to 36b_242L, 36b_1R to 36b_242R, 37b_1L to 37b_242L, 37b_1R to 37b_242R ... output times Road, 38-44, 46a_1L-46a_242L, 46a_1R-46a_242R, 46b_1L-46b_242L, 48a_1L-48a_242L, 48a_1R-48a_242R, 48b_1R-48b_242R ... MOS transistors.

Claims (8)

A scanning signal transfer for transferring a scanning signal of the scanning line in a matrix display device in which a plurality of signal lines and a plurality of scanning lines are arranged in a matrix and pixels are arranged at intersections of the signal lines and the scanning lines. A drive circuit comprising a circuit,
A first switching element connected to one end of each scanning line and selectively connected / disconnected to a clock signal for transferring a scanning signal of each scanning line;
A second switching element connected to the other end of each scanning line and selectively connected / disconnected to a low level power source of each scanning line;
Based on the timing of the clock signal, an output circuit that outputs a transfer circuit dedicated output signal that is output at the scanning timing of each scanning line;
Comprising
The first switching element and the second switching element are separately connected to both sides of each scanning line one by one,
Based on the timing of the clock signal input to the first switching element side, the first switching element and the second switching element operate as a set at the same time, so that each scanning line scans. And
The scanning signal transfer circuit is disposed on each side corresponding to both ends of each scanning line of the matrix display device,
The output signal dedicated to the transfer circuit also serves as at least one input signal of the scanning signal transfer circuit. Each of the scanning signal transfer circuits is supplied with the clock signal,
The clock signal input to the scanning signal transfer circuit side on the side where the first switching element is provided is the clock signal input to the scanning signal transfer circuit side on the side where the second switching element is provided The drive circuit of the matrix display device according to claim 1, wherein wiring is performed so that the delay is smaller than that of the matrix display device. The output signal dedicated to the transfer circuit on the first switching element side is the one on the side where the first switching element is provided in the scanning signal transfer circuit provided one by one on both sides of the scanning line of the next line. Supplied to the scanning signal transfer circuit;
The output signal dedicated to the transfer circuit on the second switching element side is the one on the side where the second switching element is provided in the scanning signal transfer circuit provided one by one on both sides of the scanning line of the next line. Supplied to the scanning signal transfer circuit;
The drive circuit of the matrix display device according to claim 1. The output signal dedicated to the transfer circuit on the side of the first switching element is the one on the side where the first switching element is provided in the scanning signal transfer circuit provided one by one on both sides of the scanning line of the previous line. Supplied to the scanning signal transfer circuit;
The output signal dedicated to the transfer circuit on the second switching element side is the one on the side where the second switching element is provided in the scanning signal transfer circuit provided one by one on both sides of the scanning line of the previous line. Supplied to the scanning signal transfer circuit;
The drive circuit of the matrix display device according to claim 1. The first switching element is a first transistor in which one of a source electrode and a drain electrode is connected to the clock signal, and the other of the source electrode and the drain electrode is connected to one end of each scanning line,
The second switching element is a second transistor in which one of a source electrode and a drain electrode is connected to the low-level power supply, and the other of the source electrode and the drain electrode is connected to the other end of each scanning line. The drive circuit of the matrix display device according to claim 1. A display panel in which a plurality of signal lines and a plurality of scanning lines are arranged in a matrix, and pixels are arranged at intersections of the signal lines and the scanning lines;
A first switching element connected to one end of each scanning line and selectively connected / disconnected to a clock signal for transferring a scanning signal of each scanning line; and connected to the other end of each scanning line; A second switching element selectively connected / disconnected to / from a low-level power supply of the scanning line, and an output circuit for outputting a transfer circuit-dedicated output signal output at the scanning timing of each scanning line based on the timing of the clock signal And
The first switching element and the second switching element are separately connected to both sides of each scanning line one by one,
Based on the timing of the clock signal input to the first switching element side, the first switching element and the second switching element work together to scan each scanning line. Including a scanning signal transfer circuit,
The scanning signal transfer circuit is disposed on each side corresponding to both ends of each scanning line of the matrix display device,
The transfer circuit dedicated output signal is a drive circuit that also serves as at least one input signal of the scanning signal transfer circuit;
A control circuit for controlling the operation timing of the drive circuit;
A matrix display device comprising: Each of the scanning signal transfer circuits is supplied with the clock signal,
The clock signal input to the scanning signal transfer circuit side on the side where the first switching element is provided is the clock signal input to the scanning signal transfer circuit side on the side where the second switching element is provided The matrix display device according to claim 6, wherein the matrix display device is wired so as to reduce delay. The first switching element is a first transistor in which one of a source electrode and a drain electrode is connected to the clock signal, and the other of the source electrode and the drain electrode is connected to one end of each scanning line,
The second switching element is a second transistor in which one of a source electrode and a drain electrode is connected to the low-level power supply, and the other of the source electrode and the drain electrode is connected to the other end of each scanning line. The matrix display device according to claim 6.

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