JP2006221694A - Shift register and flat panel display device using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a malfunction of a circuit, in a shift register, due to excessive off-leakage currents flowing through a transistor having a node of floating state. <P>SOLUTION: A sixth transistor is provided with a conductive path between an output terminal and a control electrode of a first transistor. Consequently, when a shift register operates, a potential difference between two terminals except the control electrode decreases when the sixth transistor T6 is in an "OFF" state, and an excessive off-leakage current is prevented from flowing from the sixth transistor T6 to the conductive path to the control electrode of the first transistor T1, which becomes a floating node n1, to normally control "ON/OFF" of the first transistor T1. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a shift register that operates in synchronization with a clock signal and a flat display device using the shift register.

  A flat display device typified by a liquid crystal display device is thin, lightweight, and has low power consumption, and is therefore used as a display device for various devices. Among them, an active matrix liquid crystal display device in which a transistor is arranged for each pixel is becoming widespread as a display device for a notebook personal computer or a portable information terminal. In recent years, a technology has been established for forming a thin film transistor made of polysilicon having a higher electron mobility in a relatively low temperature process than a transistor made of amorphous silicon used in a conventional liquid crystal display device. The transistor used can be downsized. As a result, the pixel substrate in which the thin film transistors are arranged at the intersections of the plurality of scanning lines and the plurality of signal lines and the driving circuit for driving the thin film transistors via the scanning lines and the signal lines are formed by the same manufacturing process. It can be formed integrally on the top.

The driving circuit of the flat panel display device includes a scanning line driving circuit that outputs pulses to a plurality of scanning lines and a signal line driving circuit that outputs pulses to a plurality of signal lines, and each driving circuit is electrically connected in a column. Each is provided with a plurality of connected shift registers. Each shift register has an input circuit, an output circuit, and a reset circuit, for example, as shown in Patent Document 1, and shifts the phase of a pulse input to the input circuit and outputs the result from the output circuit. The shift register may be configured using only one of a pMOS transistor and an nMOS transistor in order to shorten the manufacturing process and realize cost reduction.
JP 2003-346492 A

  However, in recent years, transistor size has been reduced due to progress in process technology, and off-leakage current that flows when the transistor is turned off has become a problem. In the conventional shift register as described above, the node of a specific transistor is operated in a floating state. In such a case, if an excessive off-leakage current flows through the transistor, the potential of the node rises and is connected to the next stage. It becomes impossible to normally control the on / off state of the transistor.

  The present invention has been made in view of the above, and an object of the present invention is to prevent malfunction of a circuit caused by an excessive off-leakage current flowing in a transistor having a node in a floating state in a shift register. .

  Another object of the present invention is to provide a flat display device using the shift register.

  A shift register according to a first aspect of the present invention includes a first transistor having a conductive path between a first clock terminal and an output terminal, and a second transistor having a conductive path between an output terminal and a first voltage electrode. An output circuit, a third transistor having a conductive path between the control electrode and the second voltage electrode of the first transistor and a conductive path to the input terminal, and a control electrode of the first voltage electrode and the second transistor An input circuit having a conductive path between and a fourth transistor having a conductive path to the input terminal, a fifth transistor having a conductive path between the second clock terminal and the control electrode of the second transistor, and an output terminal A reset circuit having a conductive path to the control electrode of the first transistor and a sixth transistor having a conductive path to the control electrode of the second transistor. To.

  In the present invention, “having a conductive path” represents a state where two elements are electrically connected regardless of whether the two elements are physically connected or not.

  In the present invention, since the sixth transistor has a conductive path between the output terminal and the control electrode of the first transistor, when the shift register is in operation, other than the control electrode in the off state of the sixth transistor. The potential difference between the two terminals is reduced, and an excessive off-leakage current flowing from the sixth transistor to the conductive path to the control electrode of the first transistor serving as a floating node can be suppressed.

  The flat display device according to the second aspect of the present invention includes a first transistor having a conductive path between the first clock terminal and the output terminal, and a second transistor having a conductive path between the output terminal and the first voltage electrode. An output circuit, a third transistor having a conductive path between the control electrode and the second voltage electrode of the first transistor and a conductive path to the input terminal, a control electrode of the first voltage electrode and the second transistor, An input circuit having a conductive path between and a fourth transistor having a conductive path to the input terminal, a fifth transistor having a conductive path between the second clock terminal and the control electrode of the second transistor, and an output terminal A reset circuit having a conductive path between the first transistor and the control electrode of the first transistor and a sixth transistor having a conductive path to the control electrode of the second transistor. A resistor is held between a first electrode substrate having a drive circuit connected in series, a second electrode substrate disposed opposite to the first electrode substrate, and the first electrode substrate and the second electrode substrate. And a display layer.

  In the present invention, since the shift register according to the first aspect of the present invention includes a plurality of drive circuits connected in series, the drive circuit stably supplies pulses to the scanning lines or signal lines. It becomes possible.

  A shift register according to a third aspect of the present invention includes a first transistor having a conductive path between a first clock terminal and an output terminal, and a second transistor having a conductive path between an output terminal and a first voltage electrode. And a sixth transistor having a conductive path between the output terminal and the control electrode of the first transistor and a conductive path to the control electrode of the second transistor.

  In the present invention, since the sixth transistor has a conductive path between the output terminal and the control electrode of the first transistor, when the shift register is in operation, other than the control electrode in the off state of the sixth transistor. The potential difference between the two terminals is reduced, and an excessive off-leakage current flowing from the sixth transistor to the conductive path to the control electrode of the first transistor serving as a floating node can be suppressed.

  According to the shift register of the present invention, it is possible to prevent a malfunction of a circuit due to an excessive off-leak current flowing in a transistor having a node in a floating state.

  Another effect of the present invention is to provide a flat display device using the shift register.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  As shown in the circuit diagram of FIG. 1, the flat display device according to the present embodiment includes a plurality of scanning lines G1, G2,... Gn (generically referred to as G) on the pixel portion 11 provided on the first electrode substrate 10. And a plurality of signal lines S1, S2,... Sm (generally referred to as S) are wired so as to cross each other, and a pixel is provided at each intersection between each scanning line G and each signal line S. Transistor 12 and pixel electrode 13 are arranged. As the pixel transistor 12, for example, a polysilicon thin film transistor is used. The gate of each pixel transistor 12 is connected to the scanning line G, the source is connected to the signal line S, and the drain is connected to the pixel electrode 13 and an auxiliary capacitor (not shown). A scanning line driving circuit 21 and a signal line driving circuit 31 are provided on the first electrode substrate 10 as driving circuits for the pixel transistors 12. The pixel unit 11, the scanning line driving circuit 21, and the signal line driving circuit 31 are integrally formed on the first electrode substrate 10 by the same manufacturing process.

  The scanning line driving circuit 21 includes a vertical shift register 22. The vertical shift register 22 outputs a signal obtained by shifting the phase of the vertical start signal (STV) synchronized with the vertical clock signal (CKV) by one stage with respect to the scanning lines G1 to Gn as a vertical scanning pulse. The output of the vertical scanning pulse is supplied to the corresponding scanning line G.

  The signal line drive circuit 31 includes a horizontal shift register 32, a video signal bus 33, and a plurality of analog switches 34 provided on each signal line S. The horizontal shift register 32 outputs a signal obtained by shifting the phase of the horizontal start signal (STH) synchronized with the horizontal clock signal (CKH) one by one with respect to the signal lines S1 to Sm as a horizontal scanning pulse to each analog switch 34. To do. The analog switch 34 samples the video signal (DATA) supplied to the video signal bus 33 according to the horizontal scanning pulse and outputs it to the signal line S.

  Further, as shown in the cross-sectional view of the flat display device of FIG. 2, in the pixel portion 11 of FIG. 1, the counter electrode 14 electrically opposed to the pixel electrode 13 connected to the drain of each pixel transistor 12 is It is formed on the surface of the second electrode substrate 16 disposed so as to face the first electrode substrate 10. A display layer 15 is held between the first electrode substrate 10 and the second electrode substrate 16, and the periphery of both electrode substrates is sealed with a sealing material 17. Here, the display layer 15 is a liquid crystal layer in a liquid crystal display device, for example.

  Next, the configuration of the shift register used for the vertical shift register 22 of the scanning line driving circuit 21 and the horizontal shift register 32 of the signal line driving circuit 31 in the flat display device will be described with reference to the circuit block diagram of FIG. . Here, for example, a three-phase shift register is used as the shift register.

  As shown in the figure, the three-phase shift register includes a plurality of shift registers SR1, SR2,... SRn (collectively referred to as SR) electrically connected in series, and clock signals C1, C2 to each shift register SR. , C3 (corresponding to CKV or CKH in FIG. 1), a clock line 36 for inputting any two clock signals, and an output line 37 for outputting an output signal. Shift registers SR1, SR2,... SRn correspond to the first stage, the second stage, and the nth stage, respectively.

  With such a configuration, a start signal STP (corresponding to STV or STH in FIG. 1) is input as an input signal to the shift register SR1, and each of the second to nth stage shift registers SR is supplied from the previous stage shift register. An output signal is input as an input signal. Each shift register SR sequentially outputs output signals obtained by shifting the phase of this input signal in synchronization with two clock signals.

  In this way, the vertical shift register 22 outputs the output signal from each shift register SR to each scanning line G as a vertical scanning pulse. On the other hand, the horizontal shift register 32 outputs the output signal from each shift register SR to each analog switch 34 as a horizontal scanning pulse.

[Comparative example]
Next, before describing the operation of the shift register constituting the three-phase shift register according to the present embodiment, the configuration and operation of the shift register will be described using a circuit diagram and a timing chart of a conventional shift register as a comparative example. In the actual operation, a problem relating to the off-leakage current of the transistor of the conventional shift register (hereinafter referred to as a shift register of the comparative example) will be specifically described.

  FIG. 7 is a circuit diagram of a shift register SR1 of a comparative example that constitutes a three-phase shift register. As shown in FIG. 7, the shift register SR1 includes an output circuit, an input circuit, and a reset circuit using six transistors. It is composed of a circuit. Here, as an example, all transistors are pMOS transistors. Since the other shift registers SR2 to SRn have the same configuration as the shift register SR1, the description thereof is omitted here.

  The output circuit includes a first transistor T1 having a conductive path between the first clock terminal 41 and the output terminal 44, and a second transistor T2 having a conductive path between the output terminal 44 and the first voltage electrode 46. Is done. Specifically, the drain of the first transistor T1 is electrically connected to the first clock terminal 41, and the source is electrically connected to the output terminal 44. The source of the second transistor T2 is electrically connected to the first voltage electrode 46, and the drain is electrically connected to the output terminal 44. The first clock signal C1 is input to the first clock terminal 41, and the high-level power supply voltage VDD is supplied to the first voltage electrode 46. Note that “having a conductive path” means that two elements are electrically connected regardless of whether or not the two elements are physically connected.

  The output circuit outputs the first clock signal C1 to the output terminal 44 when the first transistor T1 is on and the second transistor T2 is off, and the power circuit when the first transistor T1 is off and the second transistor T2 is on. The voltage VDD is output to the output terminal 44.

  The input circuit includes a third transistor T3 having a conductive path between the control electrode of the first transistor T1 and the second voltage electrode 47 and a conductive path to the input terminal 43, and the first voltage electrode 46 and the second transistor T2. The fourth transistor T4 has a conductive path to the control electrode and a conductive path to the input terminal 43.

  Specifically, the drain of the third transistor T3 is electrically connected to the second voltage electrode 47, the gate is electrically connected to the input terminal 43, and the source is electrically connected to the control electrode of the first transistor T1. Is done. The second voltage electrode 47 is supplied with the low level power supply voltage VSS. Further, the source of the fourth transistor T4 is electrically connected to the first voltage electrode 46, the drain is electrically connected to the control electrode of the second transistor, and the gate is electrically connected to the input terminal 43.

  The input circuit receives an input signal IN through the input terminal 43. Here, the conductive path to the control electrode of the first transistor T1 is represented as a node n1, and the conductive path to the control electrode of the second transistor T2 is represented as a node n2.

  The reset circuit includes a fifth transistor T5 having a conductive path between the second clock terminal 42 and the control electrode of the second transistor T2, and a conductive path between the first voltage electrode 46 and the control electrode of the first transistor T1. And a sixth transistor T6 having a conductive path to the control electrode of the second transistor T2.

  Specifically, the drain and gate of the fifth transistor T5 are electrically connected to the second clock terminal 42, and the source is electrically connected to the control electrode of the second transistor T2. The drain of the sixth transistor T6 is electrically connected to the control electrode of the first transistor T1, the gate is electrically connected to the control electrode of the second transistor T2, and the source is electrically connected to the first voltage electrode 46. Connected. The second clock signal C3 is input to the second clock terminal 42.

  The reset circuit turns on one of the first transistor T1 and the second transistor T2, and turns off the other.

  Next, the operation of the shift register SR1 of the comparative example will be described using the timing chart of FIG. This figure is a timing chart showing the relationship among the input signal IN, the clock signals C1 to C3, the nodes n1 to n2, and the output signal OUT in the shift register SR1 of FIG. The output signal OUT is obtained by shifting the phase of the input signal IN. Since the operations of the other shift registers SR2 to SRn are the same as the operation of the shift register SR1, the description thereof is omitted here.

  When the low-level input signal IN is input to the input terminal 43 at time t1, the third transistor T3 and the fourth transistor T4 are turned on. Since the second clock signal C3 is at a high level, the fifth transistor T5 is in an off state. At this time, the node n2 is supplied with the power supply voltage VDD from the fourth transistor T4 and becomes high level, and the second transistor T2 and the sixth transistor T6 are turned off. The node n1 is supplied with the power supply voltage VSS from the third transistor T3 and becomes low level. However, as the node n1 becomes low level, the third transistor T3 is turned off and finally the node n1 is in a floating state. At the same time, the first transistor T1 is turned on. As a result, since the first clock signal C1 having a high level is supplied from the first transistor T1 to the output terminal 44, the output signal OUT maintains a high level.

  When the potential of the input signal IN changes from the low level to the high level at time t2, the third transistor T3 and the fourth transistor T4 are turned off. When the fourth transistor T4 is turned off, the node n2 is in a floating state. However, since the fifth transistor T5 is turned off, the node n2 maintains a high level potential. As the potential of the node n2 is maintained at a high level, the sixth transistor T6 is maintained in an off state.

  At time t2, the potential of the input signal IN changes from the low level to the high level, and at the same time, the potential of the first clock signal C1 is inverted from the high level to the low level. Since the third transistor T3 and the sixth transistor T6 are off, the node n1 is in a floating state and has a potential lower than the low level (hereinafter referred to as LL level). This is because there is a parasitic capacitance between the gate and the source of the first transistor T1 or between the gate and the drain. Therefore, when the gate, that is, the node n1 is in a floating state, the potential variation between the drain and the source of the first transistor T1 is accompanied. This is because the potential of the node n1 varies. In this manner, a phenomenon in which the potential of a node in a floating state varies under the influence of potential variation in a connection destination transistor is referred to as a bootstrap, and the node at this time is referred to as a bootstrap node. Further, as indicated by (1) in FIG. 8, a high-level to LL-level voltage is applied between the source and drain of the sixth transistor T6 that is off at this time.

  As a result, the low-level first clock signal C1 is supplied from the first transistor T1 to the output terminal 44, so that the output signal OUT becomes low level. During this period, the node n1 is at the LL level and the node n2 is at the high level, which are in a floating state.

  At time t3, when the first clock signal C1 is at a high level and the potential of the second clock signal C3 is at a low level, the fifth transistor T5 is turned on. At this time, since the fourth transistor T4 is in an off state, the node n2 is at a low level. As a result, the second transistor T2 and the sixth transistor T6 are turned on, the node n1 becomes high level, and the first transistor T1 is turned off. The power supply voltage VDD is supplied to the output terminal 44 through the second transistor T2, and the potential of the output signal OUT becomes high level.

  After time t3, the input signal IN is fixed at a high level, so that the node n1 is fixed at a high level and the node n2 is fixed at a low level, the first transistor T1 is turned off, and the second transistor T2 is turned on. The output signal OUT is maintained at a high level.

  In this manner, the shift register SR1 outputs an output signal 44 that is an output signal OUT obtained by shifting the phase of the input signal IN input from the input terminal 43 in synchronization with the two clock signals C1 and C3.

  Next, a problem regarding the off-leakage current of the transistor included in the shift register of the comparative example will be specifically described.

  As shown in the timing chart of FIG. 8, since the potential of the node n1 in the floating state becomes the LL level by bootstrap in the period of time t2 to t3, the source of the sixth transistor T6 in the off state at this time The voltage applied between the drains increases from the high level to the LL level (the voltage indicated by (1) in FIG. 8).

  FIG. 9 is a timing chart in the actual operation of the shift register of the comparative example. As shown in FIG. 9, the off-leak current flowing from the sixth transistor T6 to the bootstrap node n1 in the floating state in the period from time t2 to t3. Increases in proportion to the voltage between the source and drain of the sixth transistor T6. As a result, the potential of the node n1 rises and eventually reaches a high level. In such a state, not only the first transistor is not turned on but also the bootstrap does not function normally, so the output signal OUT does not become a completely low level. As a result, there is a problem that the input to the next stage is not normally performed and the shift register malfunctions.

[Example]
The shift register according to the present embodiment (hereinafter referred to as the present shift register) solves the problems of the conventional shift register in the actual operation described in the comparative example. Hereinafter, the configuration and operation of the shift register will be specifically described with reference to a circuit diagram and a timing chart of the shift register.

  FIG. 4 is a circuit diagram of the shift register SR1 constituting the three-phase shift register in the present embodiment shown in FIG. In the figure, the shift register SR1 includes a first transistor T1 having a conductive path between the first clock terminal 41 and the output terminal 44, and a first transistor having a conductive path between the output terminal 44 and the first voltage electrode 46. An output circuit having two transistors T2, a third transistor T3 having a conductive path between the control electrode of the first transistor T1 and the second voltage electrode 47 and a conductive path to the input terminal 43, and a first voltage electrode 46. And an input circuit having a fourth transistor T4 having a conductive path between the second transistor T2 and the control electrode of the second transistor T2 and a conductive path to the input terminal 43, and a second clock terminal 42 and a control electrode of the second transistor T2 A fifth transistor T5 having a conductive path therebetween, a conductive path between the output terminal 44 and the control electrode of the first transistor T1, and the control of the second transistor T2. It has a reset circuit and a sixth transistor T6 having a conductive path to the electrode. Here, as an example, all transistors are pMOS transistors. The configuration of the shift registers SR2 to SRn is the same as that of the present shift register SR1, and the description thereof is omitted here.

  Hereinafter, a configuration of the output circuit, the input circuit, and the reset circuit included in the shift register SR1 will be specifically described.

  In the output circuit, the drain of the first transistor T1 is electrically connected to the first clock terminal 41, and the source is electrically connected to the output terminal 44. The source of the second transistor T 2 is electrically connected to the first voltage electrode 46, and the drain is electrically connected to the output terminal 44. The first clock signal C1 is input to the first clock terminal 41, and the high-level power supply voltage VDD is supplied to the first voltage electrode 46.

  The output circuit outputs the first clock signal C1 to the output terminal 44 when the first transistor T1 is on and the second transistor T2 is off, and the power circuit when the first transistor T1 is off and the second transistor T2 is on. The voltage VDD is output to the output terminal 44.

  In the input circuit, the drain of the third transistor T3 is electrically connected to the second voltage electrode 47, the gate is electrically connected to the input terminal 43, and the source is electrically connected to the control electrode of the first transistor T1. The The second voltage electrode 47 is supplied with the low level power supply voltage VSS. Further, the source of the fourth transistor T4 is electrically connected to the first voltage electrode 46, the drain is electrically connected to the control electrode of the second transistor, and the gate is electrically connected to the input terminal 43.

  The input circuit receives an input signal IN through the input terminal 43. Here, the conductive path to the control electrode of the first transistor T1 is represented as a node n1, and the conductive path to the control electrode of the second transistor T2 is represented as a node n2.

  In the reset circuit, the drain and gate of the fifth transistor T5 are electrically connected to the second clock terminal 42, and the source is electrically connected to the control electrode of the second transistor T2. The drain of the sixth transistor T6 is electrically connected to the control electrode of the first transistor T1, the gate is electrically connected to the control electrode of the second transistor T2, and the source is electrically connected to the output terminal 44. The The second clock signal C3 is input to the second clock terminal 42.

  The reset circuit turns on one of the first transistor T1 and the second transistor T2, and turns off the other.

  4 is different from the shift register SR1 of the comparative example in the shift register SR1 of FIG. 4 in that the source of the sixth transistor T6 is electrically connected to the output terminal 44 instead of the first voltage electrode 46. Is a point.

  Next, the operation of the shift register SR1 will be described with reference to the timing chart of FIG. This figure is a timing chart showing the relationship among the input signal IN, clock signals C1 to C3, nodes n1 to n2, and output signal OUT in the shift register SR1 of FIG. The output signal OUT is obtained by shifting the phase of the input signal IN. Since the operations of the shift registers SR2 to SRn are the same as the operation of the shift register SR1, the description thereof is omitted here.

  When the low-level input signal IN is input to the input terminal 43 at time t1, the third transistor T3 and the fourth transistor T4 are turned on. Since the second clock signal C3 is at a high level, the fifth transistor T5 is in an off state. At this time, the node n2 is supplied with the power supply voltage VDD from the fourth transistor T4 and becomes high level, and the second transistor T2 and the sixth transistor T6 are turned off. The node n1 is supplied with the power supply voltage VSS from the third transistor T3 and becomes low level. However, as the node n1 becomes low level, the third transistor T3 is turned off and finally the node n1 is in a floating state. At the same time, the first transistor T1 is turned on. As a result, since the first clock signal C1 having a high level is supplied from the first transistor T1 to the output terminal 44, the output signal OUT maintains a high level.

  When the potential of the input signal IN changes from the low level to the high level at time t2, the third transistor T3 and the fourth transistor T4 are turned off. When the fourth transistor T4 is turned off, the node n2 is in a floating state. However, since the fifth transistor T5 is turned off, the node n2 maintains a high level potential. By maintaining the potential of the node n2 at the high level, the sixth transistor T6 remains off.

  At time t2, the potential of the input signal IN changes from the low level to the high level, and at the same time, the potential of the first clock signal C1 is inverted from the high level to the low level. Since the third transistor T3 and the sixth transistor T6 are off, the node n1 is in a floating state, is affected by the bootstrap, and has a potential lower than the low level (hereinafter referred to as the LL level). As a result, the low-level first clock signal C1 is supplied from the first transistor T1 to the output terminal 44, so that the output signal OUT becomes low level.

  Since the output signal OUT is at the low level from time t2 to time t3, the source potential of the sixth transistor T6 connected to the output terminal 44 is at the low level, and the sixth transistor T6 connected to the node n1 has the source potential. Since the drain potential is at the LL level, the potential difference between the source and the drain of the sixth transistor T6 in the off state is from the low level to the LL level (voltage shown by (2) in FIG. 5). On the other hand, in the shift register circuit of the comparative example, the potential difference between the source and drain of the sixth transistor T6 was high level to LL level (voltage shown in (1) of FIGS. 5 and 8).

As described above, in this shift register, the voltage between the source and the drain of the sixth transistor T6 is smaller than that in the shift register circuit of the comparative example. Therefore, the off-leak current that increases in proportion to the voltage between the source and the drain of the transistor Can be suppressed.

  FIG. 6 is a timing chart in the actual operation of this shift register. In the figure, a case where an off-leakage current flows through the sixth transistor T6 in the off state and the potential of the node n1 rises from time t2 to time t3 is shown. In this way, even when an off-leakage current flows through the sixth transistor T6, the potential of the source of the sixth transistor T6 connected to the output terminal 44 (output signal OUT) is at a low level. The potential rises only to a low level (voltage shown by (3) in FIG. 6). Therefore, the first transistor T1 is not turned off, and as a result, the output voltage becomes a voltage increased by the threshold voltage of the first transistor T1 from the low level, and can be maintained at the low level. The shift register can operate normally.

  At time t3, when the first clock signal C1 is at a high level and the potential of the second clock signal C3 is at a low level, the fifth transistor T5 is turned on. At this time, since the fourth transistor T4 is in an off state, the node n2 is at a low level. As a result, the second transistor T2 and the sixth transistor T6 are turned on, and the power supply voltage VDD is supplied to the output terminal 44 (output signal OUT) through the second transistor T2. Since the output signal OUT is supplied to the node n1 through the sixth transistor T6, the node n1 becomes a high level, and the first transistor T1 is turned off.

  After time t3, the input signal IN is fixed at a high level, so that the node n1 is fixed at a high level and the node n2 is fixed at a low level, the first transistor T1 is turned off, and the second transistor T2 is turned on. The output signal OUT is maintained at a high level.

  Therefore, in the present embodiment, since the sixth transistor has a conductive path between the output terminal and the control electrode of the first transistor, the control in the OFF state of the sixth transistor T6 during the operation of the shift register. The potential difference between the two terminals other than the electrode is reduced, and an excessive off-leakage current flowing out from the sixth transistor T6 to the conductive path to the control electrode of the first transistor T1 serving as the floating node n1 can be suppressed. Off can be controlled normally.

  In the flat display device in this embodiment, since the shift register includes a plurality of drive circuits connected in series, the drive circuit stably supplies pulses to the scan lines or the signal lines. It becomes possible.

  In this embodiment mode, the shift register is mounted on both the vertical shift register of the scanning line driver circuit and the horizontal shift register of the signal line driver circuit. However, the present invention is not limited to this. It may be configured to be mounted on at least one of the vertical shift register of the driving circuit and the horizontal shift register of the signal line driving circuit.

  In the present embodiment, the shift register is described as using a three-phase clock signal and six transistors. However, the present invention is not limited to this, and the sixth transistor includes the output terminal and the first transistor. If the shift register is configured to have a conductive path to the control electrode, the same effects as in the present embodiment can be obtained.

  For example, an output having a first transistor T1 having a conductive path between the first clock terminal 41 and the output terminal 44 and a second transistor T2 having a conductive path between the output terminal 44 and the first voltage electrode 46. Circuit, a reset circuit having a sixth transistor T6 having a conductive path between the output terminal 44 and the control electrode of the first transistor T1 and a conductive path to the control electrode of the second transistor T2, and having an inverter function, A shift register may be configured by combining an input circuit capable of bringing the nodes n1 and n2 into a floating state when a two-clock signal and an input signal are input.

  In this embodiment, the present shift register is configured using only pMOS transistors, but the present invention is not limited to this. This shift register may be configured using only nMOS transistors instead of pMOS transistors. In this case, an effect similar to that of the present embodiment can be obtained by using the inverted potential of each signal as compared with the case where a pMOS transistor is used.

  In this embodiment, as an example of application of the present shift register to a flat display device, a liquid crystal layer corresponding to a display layer is held between a first electrode substrate and a second electrode substrate that are arranged to face each other. In the flat display device, the configuration in which the drive circuit in which the shift registers are connected in a plurality of columns is arranged on the first substrate has been described, but the present invention is not limited to this. For example, the present shift register can be similarly applied to a flat display device having a structure in which an organic EL corresponding to a display layer is held between a first electrode substrate and a second electrode substrate which are arranged to face each other.

1 is a circuit diagram illustrating a schematic configuration of a flat display device according to an embodiment. FIG. It is sectional drawing which shows the structure of the said flat display apparatus. It is a circuit block diagram which shows the structure of the 3 phase shift register of the drive circuit in the said flat display apparatus. It is a circuit diagram of this shift register which comprises the said 3 phase shift register. It is a timing chart of this shift register. 4 is a timing chart in actual operation of the present shift register. It is a circuit diagram of the shift register of a comparative example. 6 is a timing chart of a shift register of a comparative example. It is a timing chart in the actual operation | movement of the shift register of a comparative example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... 1st electrode substrate 11 ... Pixel part
12 ... Pixel transistor
13: Pixel electrode
14 ... Counter electrode
15 ... Display layer
16 ... Second electrode substrate
17 ... Sealing material 21 ... Scan line drive circuit
22: Vertical shift register
31 ... Signal line drive circuit
32. Horizontal shift register
33 ... Video signal bus 34 ... Analog switch
36 ... clock line
37 ... Output line
41 ... 1st clock terminal
42 ... Second clock terminal
43 ... Input terminal
44 ... Output terminal 46 ... First voltage electrode
47. Second voltage electrodes G1 to Gn Scanning lines S1 to Sn Signal lines
T1 to T6 ... Transistors SR1 to SRn ... Shift register VDD ... High-level power supply voltage VSS ... Low-level power supply voltage

Claims (3)

An output circuit having a first transistor having a conductive path between the first clock terminal and the output terminal, and a second transistor having a conductive path between the output terminal and the first voltage electrode;
A third transistor having a conductive path between the control electrode of the first transistor and the second voltage electrode and a conductive path to the input terminal; and a conductive property between the first voltage electrode and the control electrode of the second transistor. An input circuit having a path and a fourth transistor having a conductive path to the input terminal;
A fifth transistor having a conductive path between a second clock terminal and the control electrode of the second transistor; a conductive path between the output terminal and the control electrode of the first transistor; and a control electrode of the second transistor. A reset circuit having a sixth transistor with a conductive path to
A shift register comprising: An output circuit having a first transistor having a conductive path between a first clock terminal and an output terminal; and a second transistor having a conductive path between the output terminal and the first voltage electrode; and the first transistor. A third transistor having a conductive path between the control electrode and the second voltage electrode and a conductive path to the input terminal, a conductive path between the first voltage electrode and the control electrode of the second transistor, and the input An input circuit having a fourth transistor having a conductive path to a terminal; a fifth transistor having a conductive path between a second clock terminal and a control electrode of the second transistor; the output terminal; and the first transistor. A reset circuit having a conductive path to the control electrode of the second transistor and a sixth transistor having a conductive path to the control electrode of the second transistor. A first electrode substrate having a drive circuit Torejisuta is connected in cascade,
A second electrode substrate disposed opposite the first electrode substrate;
A display layer held between the first electrode substrate and the second electrode substrate;
A flat display device comprising: A first transistor having a conductive path between the first clock terminal and the output terminal; a second transistor having a conductive path between the output terminal and the first voltage electrode;
A sixth transistor having a conductive path between the output terminal and the control electrode of the first transistor and a conductive path to the control electrode of the second transistor;
A shift register comprising:

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